veriwell: remove unnecessary distname declaration (it's already the default)
--- trunk/dports/science/veriwell/Portfile 2008-08-31 23:46:18 UTC (rev 39700)
+++ trunk/dports/science/veriwell/Portfile 2008-08-31 23:48:41 UTC (rev 39701)
@@ -18,7 +18,6 @@
platforms darwin
master_sites sourceforge
checksums md5 1c1c6fb05009172d2677e34f0e511a37
-distname ${name}-${version}
depends_lib port:help2man
# The following prevent conflicts with other Verilog simulators