[Xquartz-changes] mesa: Changes to '11.1'
Jeremy Huddleston
jeremyhu at freedesktop.org
Wed Jan 20 16:36:05 PST 2016
New branch '11.1' available with the following commits:
commit c147589d79a48ceca14ea9f86a793e132e66e1de
Author: Arlie Davis <arlied at google.com>
Date: Thu Sep 17 15:19:24 2015 -0700
mesa: Reduce libGL.so binary size by about 15%
Ok, here's v2 of the change, with the suggested edits.
From 5f393faa058f453408dfc640eecae3fe6335dfed Mon Sep 17 00:00:00 2001
From: Arlie Davis <arlied at google.com>
Date: Tue, 15 Sep 2015 09:58:34 -0700
Subject: [PATCH] This patch significantly reduces the size of the libGL.so
binary. It does not change the (externally visible) behavior of libGL.so at
all.
gl_gentable.py generates a function, _glapi_create_table_from_handle.
This function allocates a large dispatch table, consisting of 1300 or so
function pointers, and fills this dispatch table by doing symbol lookups
on a given shared library. Previously, gl_gentable.py would generate a
single, very large _glapi_create_table_from_handle function, with a short
cluster of lines for each entry point (function). The idiom it generates
was a NULL check, a call to snprintf, a call to dlsym / GetProcAddress,
and then a store into the dispatch table. Since this function processes
a large number of entry points, this code is duplicated many times over.
We can encode the same information much more compactly, by using a lookup
table. The previous total size of _glapi_create_table_from_handle on x64
was 125848 bytes. By using a lookup table, the size of
_glapi_create_table_from_handle (and the related lookup tables) is reduced
to 10840 bytes. In other words, this enormous function is reduced by 91%.
The size of the entire libGL.so binary (measured when stripped) itself drops
by 15%.
So the purpose of this change is to reduce the binary size, which frees up
disk space, memory, etc.
(cherry picked from commit 2a2c8fa7d480d83dac73b0e4e89c79a3777309b6)
commit a2f2c38a550f97423d44ffc0ce6fa3aee470068a
Author: Jon TURNEY <jon.turney at dronecode.org.uk>
Date: Mon May 12 16:30:26 2014 +0100
applegl: Provide requirements of _SET_DrawBuffers
_SET_DrawBuffers requires driDispatchRemapTable, so we need to link with libmesa
for remap.c. libmesa requires the C++ linker.
Also need to arrange to call _mesa_init_remap_table() to initialize the remap
table.
XXX: There has to be a better way fixing this.
Signed-off-by: Jon TURNEY <jon.turney at dronecode.org.uk>
(cherry picked from commit 9800301a312ac06e0ce0af20e5817ee1e44ed4a5)
commit d99f49955f4b5f611964a45312a40bec08d86a0e
Author: Jon TURNEY <jon.turney at dronecode.org.uk>
Date: Sun May 11 14:40:07 2014 +0100
darwin: Suppress type conversion warnings for GLhandleARB
On darwin, GLhandleARB is defined as a void *, not the unsigned int it is on
linux.
For the moment, apply a cast to supress the warning
Possibly this is safe, as for the mesa software renderer the shader program
handle is not a real pointer, but a integer handle
Probably this is not the right thing to do, and we should pay closer attention
to how the GLhandlerARB type is used.
main/shader_query.cpp:49:7: error: no matching function for call to '_mesa_lookup_shader_program_err'
_mesa_lookup_shader_program_err(ctx, program, "glBindAttribLocation");
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../../src/mesa/main/shaderobj.h:81:1: note: candidate function not viable: cannot convert argument of incomplete type 'GLhandleARB' (aka 'void *') to 'GLuint' (aka 'unsigned int')
_mesa_lookup_shader_program_err(struct gl_context *ctx, GLuint name,
^
main/shader_query.cpp:111:13: error: no matching function for call to '_mesa_lookup_shader_program_err'
shProg = _mesa_lookup_shader_program_err(ctx, program, "glGetActiveAttrib");
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../../src/mesa/main/shaderobj.h:81:1: note: candidate function not viable: cannot convert argument of incomplete type 'GLhandleARB' (aka 'void *') to 'GLuint' (aka 'unsigned int')
_mesa_lookup_shader_program_err(struct gl_context *ctx, GLuint name,
^
main/shader_query.cpp:218:7: error: no matching function for call to '_mesa_lookup_shader_program_err'
_mesa_lookup_shader_program_err(ctx, program, "glGetAttribLocation");
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../../src/mesa/main/shaderobj.h:81:1: note: candidate function not viable: cannot convert argument of incomplete type 'GLhandleARB' (aka 'void *') to 'GLuint' (aka 'unsigned int')
_mesa_lookup_shader_program_err(struct gl_context *ctx, GLuint name,
Signed-off-by: Jon TURNEY <jon.turney at dronecode.org.uk>
(cherry picked from commit 24eefbd4ca271f22400549dd44ccd409263089e1)
commit 92f69b77daf44a15b01eb0148c3c12ef723c223f
Author: Jeremy Huddleston Sequoia <jeremyhu at apple.com>
Date: Wed Feb 11 12:32:56 2015 -0800
glext.h: Add missing include of stddef.h for ptrdiff_t
Signed-off-by: Jeremy Huddleston Sequoia <jeremyhu at apple.com>
(cherry picked from commit c07669e721c99206fe67dd0c0f8b592b2975b685)
commit 4b2d9f29e9b75cbbeb76ccf753a256e11f07ee1a
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Wed Jan 13 15:23:53 2016 +0200
docs: add sha256 checksums for 11.1.1
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
commit 330aa44a0da7548000a6b2fc2bb580e9c8e733cc
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Wed Jan 13 12:11:33 2016 +0200
docs: add release notes for 11.1.1
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
commit e429500dd16df6b2cb611fbb25e4cd528083f85f
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Wed Jan 13 12:00:19 2016 +0200
Update version to 11.1.1
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
commit bf00b36c9df72758ce8a89399d5575d0725da315
Author: Sarah Sharp <sarah.a.sharp at linux.intel.com>
Date: Mon Sep 21 14:22:53 2015 -0700
mesa: Add KBL PCI IDs and platform information.
Add PCI IDs for the Intel Kabylake platforms. The IDs are taken
directly from the Linux kernel patches, which are under review:
http://lists.freedesktop.org/archives/intel-gfx/2015-October/078967.html
http://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=kbl-upstream-v2
The Kabylake PCI IDs taken from the kernel are rearranged to be in order
of GT type, then PCI ID.
Please note that if this patch is backported, the following fixes will
need to be added before this patch:
commit 28ed1e08e8ba98e "i965/skl: Remove early platform support"
commit c1e38ad37042b0e "i965/skl: Use larger URB size where available."
Thanks to Ben for fixing a bug around setting urb.size, and being
patient with my questions about what the various fields mean.
Signed-off-by: Sarah Sharp <sarah.a.sharp at linux.intel.com>
Suggested-by: Ben Widawsky <benjamin.widawsky at intel.com>
Tested-by: Rodrigo Vivi <rodrigo.vivi at intel.com> (KBL-GT2)
Cc: "11.1" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 39c41be50d9474dde4c0dcf23a546d14b212e80a)
commit fab2039588be1e5f6bbd53d8b1422776e213494a
Author: Brian Paul <brianp at vmware.com>
Date: Tue Jan 5 17:10:12 2016 -0700
st/mesa: check state->mesa in early return check in st_validate_state()
We were checking the dirty->st flags but not the dirty->mesa flags.
When we took the early return, we didn't clear the dirty->mesa flags
so the next time we called st_validate_state() we'd often flush the
glBitmap cache. And since st_validate_state() is called from
st_Bitmap(), it meant we flushed the bitmap cache for every glBitmap()
call.
This change seems to recover most of the performance loss observed
with the ipers demo on llvmpipe since commit commit 36c93a6fae27561.
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: José Fonseca <jfonseca at vmware.com>
(cherry picked from commit c28d72a3473ad0127c82c1244b6688dcc184e85e)
commit 536c8cbcd3326fc7207f8a2c166c380135924589
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Jan 5 05:09:46 2016 -0800
nir: Add a lower_fdiv option, turn fdiv into fmul/frcp.
The nir_opt_algebraic rule
(('fadd', ('flog2', a), ('fneg', ('flog2', b))), ('flog2', ('fdiv', a, b))),
can produce new fdiv operations, which need to be lowered on i965,
as we don't actually implement fdiv. (Normally, we handle this in
GLSL IR's lower_instructions pass, but in the above case we introduce
an fdiv after that point. So, make NIR do it for us.)
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Cc: mesa-stable at lists.freedesktop.org
(cherry picked from commit 7295f4fcc2b2dd1bc6a8d1d834774b8152a029cf)
commit 978480d69f0b40ae45766bbc65c4a6c5bb805b98
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Jan 4 11:26:27 2016 -0500
nvc0: scale up inter_bo size so that it's 16M for a 4K video
Experimentally, 4M causes corruption and slowness, try to ramp it up
with size instead.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit b16c9be4a5561bd825176a228c300331f989e837)
commit c2be35d30907fc110df8de93b8fb344a7968c7b3
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Jan 4 11:16:45 2016 -0500
nv50,nvc0: fix crash when increasing bsp bo size for h264
H264 doesn't have a bitplane bo. We just need a device reference, so use
the one from the client.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit b5f2f7073f047b4e4128cf05af8dddf356f9b48c)
commit df47b1e07844f6a8a9dc9b71868b92c18648e3b7
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Dec 6 13:36:57 2015 +0100
st/mesa: fix GLSL uniform updates for glBitmap & glDrawPixels (v2)
Spotted by luck. The GLSL uniform storage is only associated once
in LinkShader and can't be reallocated afterwards, because that would
break the association.
v2: don't remove st_upload_constants calls, clarify why they're needed
Cc: 11.0 11.1 <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 36c93a6fae275614b6004ec5ab085774d527e1bc)
commit bb3581ca3d60366f5e3621e62f5300f4f0c127c4
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Dec 6 13:31:25 2015 +0100
program: add _mesa_reserve_parameter_storage
The next commit will use this.
Reviewed-by: Brian Paul <brianp at vmware.com>
Cc: 11.0 11.1 <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 294ed5cd13e878ec43126a2070343d6d99ef5669)
commit 132131af6b78a887dac606ccf640bb901359d289
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Dec 31 20:33:15 2015 -0500
nv50,nvc0: make sure there's pushbuf space and that we ref the bo early
First off, we can't flush in the middle of a command. Secondly
requesting the extra push space might cause a flush to happen. If that
flush happens, we'd have to do the PUSH_REFN again. So instead do
PUSH_REFN after the push space request. This helps avoid rare crashes
with supertuxkart in libdrm due to assertion failures.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit c1d14c6817e3fa9a1c04f9b6c51b4ca601637843)
[Emil Velikov: resolve trivial conflict]
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Conflicts:
src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c
commit f4977656c1d4732022946f4e3642fa128979e60d
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Dec 30 02:53:08 2015 -0800
nvc0: Set winding order regardless of domain.
Quads need to respect winding order, too - not just triangles.
Fixes rendering in GFXBench 4.0's tessellation benchmark.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 65d3f85eb3efb326a826c2db0225340d5421a389)
commit b2352d758591cac76ddc66f7640522da76dee5d1
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Dec 30 02:33:00 2015 -0800
glsl: Fix varying struct locations when varying packing is disabled.
varying_matches::record tries to compute the number of components in
each varying, which varying_matches::assign_locations uses to assign
locations. With varying packing, it uses glsl_type::component_slots()
to come up with a reasonable value.
Without varying packing, it fell back to an open-coded computation
that didn't bother to handle structs at all. I believe we can simply
use 4 * glsl_type::count_attribute_slots(false), which already handles
these cases correctly.
Partially fixes rendering in GFXBench 4.0's tessellation benchmark.
(NVE0 is almost right after this, but i965 is still mostly garbage.)
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Timothy Arceri <timothy.arceri at collabora.com>
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 7cdc2b9ca0ab60b282416b975a2ac6d7abcd42ad)
[Emil Velikov: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
Conflicts:
src/glsl/link_varyings.cpp
commit 6c69561068b92b8f6285645798a9b9769bc50cf4
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Oct 12 13:47:40 2015 +1000
glsl: only update doubles inputs for vertex inputs.
This doesn't apply to other stages. This is only
used in the mesa/st code, which needs further fixes.
Reviewed-by: Timothy Arceri <timothy.arceri at collabora.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
(cherry picked from commit 1fc39dae22843d6faf3ec43eab90c7d06f9f6f7b)
commit 343fc2c3a33a4967fcc75bf1cc5b3baffba8fa5d
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Dec 9 16:06:48 2015 +1000
glsl: fix count_attribute_slots to allow for different 64-bit handling
So vertex shader input attributes are handled different than internal
varyings between shader stages, dvec3 and dvec4 only count as
one slot for vertex attributes, but for internal varyings, they
count as 2.
This patch comments all the uses of this API to clarify what we
pass in, except one which needs further investigation
Signed-off-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Timothy Arceri <timothy.arceri at collabora.com>
(cherry picked from commit 5dc22cadb5ed4a7cf8c7d1cbaf7296c27e567e0f)
commit 703ad597483c3bb6e26aa2e173382f7f7a129534
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Dec 9 16:06:46 2015 +1000
glsl/fp64: add helper for dual slot double detection.
The old function didn't work for matrices, and we need this
in other places to fix some other problems, so move to a helper
in glsl type and fix the one user so far.
A dual slot double is one that has 3 or 4 components in it's
base type.
Signed-off-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Oded Gabbay <oded.gabbay at gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri at collabora.com>
(cherry picked from commit d97b060e6f305ce4ad050881944404b920c86edf)
commit 7aab081f9804ad87a54472aa51b2f89de478025b
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Dec 9 16:06:45 2015 +1000
glsl: pass stage into mark function
Don't use a bool here, as for some 64-bit fixes we need
the stage.
Signed-off-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Oded Gabbay <oded.gabbay at gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri at collabora.com>
(cherry picked from commit 9fbcd8e8475e249c7f76b6d63b3a48b8684cb1ff)
commit 73844f6edf904bf6cc1c3ae95329349454a29d6e
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Dec 28 14:20:28 2015 -0800
drirc: Disable ARB_blend_func_extended for Heaven 4.0/Valley 1.0.
Unigine Heaven 4.0 and Valley 1.0 use dual color blending but don't
specify which fragment shader output is which, so there's at best a
50/50 chance of us guessing it correctly. This is invalid.
Unigine fixed this in 4.1 and 1.1 versions over a year and a half ago,
but hasn't actually released them for whatever reason. So, add the
workaround back so that it works for most people.
Fixes Heaven 4.0/Valley 1.0 rendering on Ivybridge. For whatever
reason, Broadwell worked. 4.1 and 1.1 have always worked.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92233
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Cc: mesa-stable at lists.freedesktop.org
(cherry picked from commit 4acf71c89b5ef5e2fe8c1a3d7ecf6031e191463c)
commit 1415b6b0aebd37f9d472a2c24b9ce603023d0475
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Tue Dec 29 15:05:34 2015 -0500
nv50/ir: float(s32 & 0xff) = float(u8), not s8
Make sure to make conversion unsigned when we're ANDing the high bits
away. Fixes corruption in dolphin.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 724134f68322087ef88bc590febd0011167ae367)
commit e468d4b1d69bd8cd290bb5d8fbef72ae28428a6e
Author: Grazvydas Ignotas <notasas at gmail.com>
Date: Tue Dec 22 04:12:07 2015 +0200
r600: fix constant buffer size programming
When buffer size is less than 16, zero ends up being programmed as
size, which prevents the hardware from fetching the correct values.
Fix it by combining shift and align so that the value is always
rounded up.
Cc: "11.1 11.0 10.6" <mesa-stable at lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92229
Signed-off-by: Grazvydas Ignotas <notasas at gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
(cherry picked from commit da0e216e069bd064199ed04b52de6fb23d810806)
commit b95dc1a5c8fb7ff9698c86529cccf43378ccdf3f
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Dec 27 20:44:01 2015 -0500
nvc0: don't forget to reset VTX_TMP bufctx slot after blit completion
Also release the scratch allocation if any.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 109c348284843054f708f4403260739b7db18275)
commit a8a7af68e8d471f69ed84d3106a41697e94d67c2
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: Fri Dec 18 23:25:16 2015 -0500
gallium/radeon: fix regression in a number of driver queries
This rather silly mistake was introduced by commit 01910676.
Cc: "11.1" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
(cherry picked from commit ea8c0b16ec222786c32bf6fc735613c25b28a6ca)
commit 56318a9899ee116eb9a0c38eff95d33c473457fb
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Dec 19 15:29:14 2015 -0500
glx/dri3: a drawable might not be bound at wait time
A trace of Alien Isolation hit this on nouveau.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer at amd.com>
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit f7b71451231c75c36771e8b7b0d78f05e0d50f65)
commit 28680b36e89826df0f7c30c71d05de0a2102f5db
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Dec 18 02:48:34 2015 -0800
ralloc: Fix ralloc_adopt() to the old context's last child's parent.
I was cleverly using one iteration to obtain a pointer to the last item
in ralloc's singly list child list, while also setting parents.
Unfortunately, I forgot to set the parent on that last item.
Cc: "11.1 11.0 10.6" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
(cherry picked from commit 14193e4643370db92210710f2ef152c693d6c4ff)
commit 96e931fea1b2511c5f8c85e09f491dc52aeec386
Author: Eric Anholt <eric at anholt.net>
Date: Fri Dec 18 11:41:38 2015 -0800
vc4: Keep sample mask writes from being reordered after TLB writes
Fixes a regression I noticed after introducing scheduling on the QIR.
Cc: "11.1" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 960f48809ffebca14af27ce9e87eabc04dfe9b84)
commit 48b580d1cc9d49f3ff3479bda34df723da3c7fdd
Author: Rob Herring <robh at kernel.org>
Date: Thu Dec 17 09:42:40 2015 -0600
freedreno/ir3: fix 32-bit builds with pointer-to-int-cast error enabled
Android builds with -Werror=pointer-to-int-cast causing an error on 32-bit
builds.
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Rob Herring <robh at kernel.org>
Signed-off-by: Rob Clark <robclark at freedesktop.org>
(cherry picked from commit b201a6ed9f6001ceaa1fc2eaf8a409b044ec97a3)
commit d4d2315d65fe3132747200cbfee48471562c8504
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: Mon Dec 14 16:10:31 2015 -0500
gallium/radeon: only dispose locally created target machine in radeon_llvm_compile
Unify the cleanup paths of the function rather than duplicating code.
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
(cherry picked from commit 0a6a17b9d72c57f0840d91756924632fee91f2c2)
commit ca30800dfdfa6806c95e5033d5ec366dc3ff127d
Author: Miklós Máté <mtmkls at gmail.com>
Date: Wed Dec 16 00:05:34 2015 +0100
mesa: Don't leak ATIfs instructions in DeleteFragmentShader
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 7279453da5c847d8f63f7e1f9e30ac2b03e6b3e9)
commit 04f01a844a7f087da3e8edf2a8e1ec8693d0b4b8
Author: Oded Gabbay <oded.gabbay at gmail.com>
Date: Tue Dec 15 12:05:22 2015 +0200
configura.ac: fix test for SSE4.1 assembler support
This patch modifies the SSE4.1 test in configure.ac to use a global
variable to initialize vector variables. In addition, we now return the
value of the computation instead of 0.
This is done so gcc 4.9 (and lower) won't optimize the SSE4.1 assembly
instructions (when using -O1 and higher), because then the configure test
might incorrectly pass even though the assembler doesn't support the
SSE4.1 instructions (the test will pass because the compiler does support the intrinsics).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91806
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Oded Gabbay <oded.gabbay at gmail.com>
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
(cherry picked from commit 6e44bbe0f5496b1aea2b4a29adae7990b62fda33)
commit 6bb88aa04b072a52898841fecae3736c8c21e83d
Author: Jonathan Gray <jsg at jsg.id.au>
Date: Sun Dec 6 16:11:05 2015 +1100
configure: check for python2.7 for PYTHON2
Check for a 'python2.7' binary, 'python' and 'python2' are not
provided by the OpenBSD python 2.7.x packages.
Signed-off-by: Jonathan Gray <jsg at jsg.id.au>
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
(cherry picked from commit 4ef44bb484cbc0336d4fdcb8edce889ed1283732)
commit a1843802f879477dbfaa9079a1a6b6ae4bccc485
Author: Jonathan Gray <jsg at jsg.id.au>
Date: Wed Dec 9 16:55:01 2015 +1100
configure.ac: use pkg-config for libelf
Use PKG_CHECK_MODULES to get the flags to link libelf
v2: keep AC_CHECK_LIB as a fallback for elfutils provided
libelf that doesn't install a pkg-config file.
Signed-off-by: Jonathan Gray <jsg at jsg.id.au>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
Tested-by: Michel Dänzer <michel.daenzer at amd.com>
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
(cherry picked from commit 7f585a6a98d0553ec0ba48e18b1d9bac1256881a)
commit 259734ae3fd947709f1c286687c51d5b7c409edb
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Wed Dec 16 22:54:30 2015 +0100
nv50: free memory allocated by the prog which reads MP perf counters
This fixes a memory leak introduced in 6a9c151
("nv50: add compute-related MP perf counters on G84+")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "11.1" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 695ae816da2fd9739eac769820bee8b7b4a87d95)
commit 10ec6685d04d5657c0e8f44c832859f2dba3950c
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Wed Dec 16 22:44:17 2015 +0100
nv50,nvc0: free memory allocated by performance metrics
The destroy_query() helper was actually never called. This fixes
a memory leak while monitoring performance metrics.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Acked-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "11.1" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit aeee7f2a4dc7ceddace91ef5e91790483f4597e0)
commit 89d585357aafe9b8643a6041645533e3325479b7
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Wed Dec 16 21:47:27 2015 +0100
nvc0: free memory allocated by the prog which reads MP perf counters
This fixes a long time ago memory leak (even before all my query
related changes).
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 9aca60bfb07d87d82aff943a23cfa693e2712528)
commit bdf289e7fbc030651394cecc3bae43565380d591
Author: Neil Roberts <neil at linux.intel.com>
Date: Tue Dec 8 16:35:57 2015 +0000
i965: Fix crash when calling glViewport with no surface bound
If EGL_KHR_surfaceless_context is used then glViewport can be called
with NULL for the draw and read surfaces. This was previously causing
a crash because the i965 driver tries to use this point to invalidate
the surfaces and it was derferencing the NULL pointer.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93257
Cc: Nanley Chery <nanley.g.chery at intel.com>
Cc: "11.1" <mesa-stable at lists.freedesktop.org>
Tested-by: Nanley Chery <nanley.g.chery at intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>
(cherry picked from commit 8c5310da9d1cbf2272f72d3ed4264544456a4683)
commit ab0b96a939b8eb48f203b8726ca5440a593716da
Author: Eric Anholt <eric at anholt.net>
Date: Fri Dec 11 19:06:09 2015 -0800
vc4: Warn instead of abort()ing on exec ioctl failures.
It's really harsh to abort() the X Server because of a momentary failure
(particularly -ENOMEM). I don't see a way to pass an -ENOMEM up the stack
from here, but we can at least log to stderr before proceeding on.
Cc: "11.1" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 02bcb443ee39cec1b61e5ba3e466471f3668f536)
commit d4474a96df7194250eeb071dcd7f91e1e7e4fcca
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Thu Dec 3 12:22:23 2015 -0800
meta/generate_mipmap: Work-around GLES 1.x problem with GL_DRAW_FRAMEBUFFER
GL_DRAW_FRAMEBUFFER does not exist in OpenGL ES 1.x, and since
_mesa_meta_begin hasn't been called yet, we have to work-around API
difficulties. The whole reason that GL_DRAW_FRAMEBUFFER is used instead
of GL_FRAMEBUFFER is that the read framebuffer may be different. This
is moot in OpenGL ES 1.x.
I have another patch series that would also fix this (by removing the
calls to _mesa_BindFramebuffer and friends), but it's not quite ready
yet... and I think it may be a bit heavy for some stable branches.
Consider this a stop-gap fix.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93215
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
(cherry picked from commit 96dc732ed81f48d8bbc7aa6fb4d9c2833b691189)
commit 66e0a26b56d80921e886195e4be550b8d033d7e9
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Dec 13 03:23:13 2015 -0500
glsl: assign varying locations to tess shaders when doing SSO
GRID Autosport uses SSO shaders. When a tessellation evaluation shader
is passed through this, it triggers assertion failures down the line
with unassigned varying locations. Make sure to do this when the first
shader in the pipeline is not a vertex shader.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Timothy Arceri <timothy.arceri at collabora.com>
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit eca8f38dcffb700fdfe413a707d524e6a84bd453)
commit 242146977f494b545f552634034b24ac3c408392
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Fri Dec 18 12:25:53 2015 +0000
cherry-ignore: don't pick a specific i965 formats patch
commit 839793680f9 "MESA_FORMAT_B8G8R8X8_SRGB for RGB visuals" causes a
handfull of regressions, some of which listed in fdo#92759.
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
commit a98bc4999794efff42b01730732458a7a37ed2a4
Author: Neil Roberts <neil at linux.intel.com>
Date: Fri Dec 11 12:32:17 2015 +0000
i965: Add B8G8R8X8_SRGB to the alpha format override
brw_init_surface_formats overrides the render format for RGBX formats
which aren't supported for rendering so that they internally use RGBA
instead. However, B8G8R8X8_SRGB was missing so it wasn't marked as a
renderable format. This patch just adds it.
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
Cc: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
(cherry picked from commit 43f4be5f06b7a96b96a3a7b43f5112139a1f423a)
commit 0193dc6a427e20e4ccbad153f676b241ca299167
Author: Neil Roberts <neil at linux.intel.com>
Date: Fri Dec 11 12:32:16 2015 +0000
i965: Add MESA_FORMAT_B8G8R8X8_SRGB to brw_format_for_mesa_format
This will be used in a subsequent patch as the format for RGB visuals.
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
Cc: Ilia Mirkin <imirkin at alum.mit.edu>
Suggested-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
(cherry picked from commit c769efda939e06338d41e1046a5f954c690951d5)
commit 55d9c80d21d3791bd31a51ee048668fcafb2df88
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Dec 10 18:19:44 2015 -0500
gk104/ir: simplify and fool-proof texbar algorithm
With the current algorithm, we only look at tex uses. However there's a
write-after-write hazard where we might decide to, on some path, not use
a texture's output at all, but instead to write a different value to
that register. However without the barrier, the texture might complete
later and overwrite that value.
This fixes Unreal Elemental demo on GK110/GK208, flightgear on GK10x,
and likely other random-looking failures.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "11.1" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 7752bbc44e78e982de3cd4c34862adc38a338234)
commit 070dbfa8106ff8263ac547517f084b25a182b1a4
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Dec 10 12:18:51 2015 -0500
nv50/ir: can't have predication and immediates
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 6aca7fecb7f7b6c67cf0315e781060a8d1d4b704)
commit ceb00fb1b9aefeca8ef36631786d343c0612ca83
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Dec 9 20:26:21 2015 +0100
gallium/radeon: fix Hyper-Z hangs by programming PA_SC_MODE_CNTL_1 correctly
This is the recommended setting according to hw people and it makes Hyper-Z
stable. Just the two magic states.
This fixes Evergreen, Cayman, SI, CI, VI (using the Cayman code).
Cc: 11.0 11.1 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
(cherry picked from commit d3c08309abd17b6e0d466b677af57e3cc74b0e00)
commit 408fcfedee96c1e5e1f096ee4188767134122d7e
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Dec 4 21:24:21 2015 +0100
radeonsi: apply the streamout workaround to Fiji as well
Cc: 11.0 11.1 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
(cherry picked from commit 787ada6bf65a58b1bab5a30be86698e9b7b0797e)
commit f9dd8468b152c2b0c373f00fa32869b49a3666b3
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Dec 9 22:14:32 2015 +0100
radeonsi: don't call of u_prims_for_vertices for patches and rectangles
Both caused a crash due to a division by zero in that function.
This is an alternative fix.
Cc: 11.0 11.1 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
(cherry picked from commit 0f9519b938d78ac55e8e5fdad5727a79baf18d42)
commit 2b526fc2d975accf6598656c225077b6d7c75464
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Dec 10 13:19:45 2015 +0100
r600g: write all MRTs only if there is exactly one output (fixes a hang)
This fixes a hang in
piglit/arb_blend_func_extended-fbo-extended-blend-pattern_gles2 on REDWOOD.
Cc: 11.0 11.1 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
(cherry picked from commit b5b87c4ed1dfd58aec8905e0514c9ba92ba83e1d)
commit 4974996545225037f9497d88467ba0f976f07d60
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Dec 10 13:15:50 2015 +0100
tgsi/scan: add flag colors_written
This is a prerequisite for the following r600g fix.
Cc: 11.0 11.1 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
(cherry picked from commit eb4813a9524e1a61f46bf45150adb1bd78564863)
commit a1ca42a9ee317541fd7b1941573b4fb4cb6aba8a
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Fri Jan 8 11:50:23 2016 +0200
cherry-ignore: drop the "re-enable" DCC on Stoney
As per Marek's request of the mesa-stable ML.
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
commit fce9699bcad9c2d001af3855be0409a81e9ae7f2
Author: Dave Airlie <airlied at redhat.com>
Date: Thu Dec 10 11:44:34 2015 +1000
mesa/shader: return correct attribute location for double matrix arrays
If we have a dmat2[4], then dmat2[0] is at 17, dmat2[1] at 19,
dmat2[2] at 21 etc. The old code was returning 17,18,19.
I think this code is also wrong for float matricies as well.
There is now a piglit for the float case.
This partly fixes:
GL41-CTS.vertex_attrib_64bit.limits_test
[airlied: update with Tapani suggestion to clean it up].
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Timothy Arceri <timothy.arceri at collabora.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
(cherry picked from commit 18ad641c3b2e926b8b3e2bd1df31fa739624cbe4)
commit 86100d4ca9b42ac044bd97ba7b24c23f0b53a762
Author: Patrick Rudolph <siro at das-labor.org>
Date: Thu Dec 10 19:50:38 2015 +0100
gallium/util: return correct number of bound vertex buffers
In case a state tracker unbinds every slot by a seperate
pipe->set_vertex_buffers() call, starting from slot zero, the number
of bound buffers would not reach zero at all.
The current algorithm does not account for pre-existing holes in the
buffer list.
Unbinding all buffers at once or starting at the top-most slot results
in correct behaviour.
Calculating the correct number of bound buffers fixes a NULL pointer
dereference in nvc0_validate_vertex_buffers_shared().
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93004
Signed-off-by: Patrick Rudolph <siro at das-labor.org>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 79bff488bc23b8615cc37069b6c5914c56be835f)
commit c054b2dd3393d64fa7168d719c6e9c7db1fd60fd
Author: Dave Airlie <airlied at redhat.com>
Date: Thu Dec 10 10:36:42 2015 +1000
mesa/varray: set double arrays to non-normalised.
Doesn't have any effect in practice I don't think, but
CTS reads back using GetVertexAttrib.
This fixes: GL41-CTS.vertex_attrib_64bit.get_vertex_attrib
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
(cherry picked from commit 21abaad8fe7b5bf78737b9cf009548f41e4777b9)
commit 47fa06c839e647a0eb0236daec5f96e4a2441ed1
Author: Patrick Rudolph <siro at das-labor.org>
Date: Sun Dec 6 10:11:59 2015 +0100
nv50,nvc0: fix use-after-free when vertex buffers are unbound
Always reset the vertex bufctx to make sure there's no pointer to
an already freed pipe_resource left after unbinding buffers.
Fixes use after free crash in nvc0_bufctx_fence().
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93004
Signed-off-by: Patrick Rudolph <siro at das-labor.org>
[imirkin: simplify nvc0 fix, apply to nv50]
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 432a798cf5c7fab18a3e32d4073840df7d0d37cb)
commit 525f3c2c28cd083b37e1f6a27f503af1c4781141
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Tue Dec 15 14:59:56 2015 +0000
docs: add sha256 checksums for 11.0.1
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
commit 5a616125acf0ac043d2d44b7a8e804739d55014e
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Mon Dec 14 23:02:50 2015 +0000
docs: Update 11.1.0 release notes
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
commit a8b2698494de564390473fae83ed4c2afb658cb5
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Mon Dec 14 12:20:18 2015 +0000
Update version to 11.1.0(final)
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
commit 7753691f1a3b147c71b606ee482b96ed4a0e7ebd
Author: Francisco Jerez <currojerez at riseup.net>
Date: Fri Sep 4 15:30:41 2015 +0300
i965: Resolve color and flush for all active shader images in intel_update_state().
Fixes arb_shader_image_load_store/execution/load-from-cleared-image.shader_test.
Couldn't reproduce any significant FPS regression in CPU-bound
benchmarks from the Finnish benchmarking system on neither VLV nor BSW
after 30 runs with 95% confidence level.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92849
Cc: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Jason Ekstrand <jason.ekstrand at intel.com>
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
Tested-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
(cherry picked from commit 595c8180714da1d97be445b9a66affa1dfea39f6)
commit ce914d941d1d5c70f1278b15bdcf7035ce36159f
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Dec 9 17:02:38 2015 +1000
radeonsi: handle loading doubles as geometry shader inputs.
This adds the double code to the geometry shader input handling.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied at redhat.com>
(cherry picked from commit e307cfa7d9a6c4c44be9d0fb50a113024646029e)
commit 300f807649e3d441f7d3e67c7ce687a0b18dfb57
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Dec 9 17:02:01 2015 +1000
radeonsi: handle doubles in lds load path.
This handles loading doubles from LDS properly.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
Cc: "11.0 11.1" <mesa-stable at lists.fedoraproject.org>
Signed-off-by: Dave Airlie <airlied at redhat.com>
(cherry picked from commit 8c9e40ac22ce5a60753172a8f95a120d84a3ec4c)
commit 61a275b789b6009e2dabbb2e6585b3f18e9cd7e6
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Dec 7 05:38:00 2015 +0000
r600: handle geometry dynamic input array index
This fixes:
glsl-1.50/execution/geometry/dynamic_input_array_index.shader_test
my profanity.
We need to load the AR register with the value from the index reg
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied at redhat.com>
(cherry picked from commit cce3864046be104933fd4f1bb7a4b36092ff4925)
commit 0f3892ed9da970b9c4d1052a6a878f5d4199fe52
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Dec 7 03:49:59 2015 +0000
r600g: fix geom shader input indirect indexing.
This fixes:
gs-input-array-vec4-index-rd
The others run out of gprs unfortunately.
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied at redhat.com>
(cherry picked from commit 38542921c785efb37bae88db409d278990684fa4)
commit 3d942ee4e5726e539bbfccb0e475c40c26273dd0
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Nov 30 15:34:14 2015 +1000
r600/shader: add utility functions to do single slot arithmatic
These utilities are to be used to do things like integer adds and
multiplies to be used in calculating the LDS offsets etc.
It handles CAYMAN MULLO differences as well.
Signed-off-by: Dave Airlie <airlied at redhat.com>
(cherry picked from commit 0696ebc899d3aa125ae85b757c5fba137617ecaa)
commit efdf841238f63a616daaa1499098841d31b911f2
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Nov 30 14:23:00 2015 +1000
r600/shader: split address get out to a function.
This will be used in the tess shaders.
Reviewed-by: Oded Gabbay <oded.gabbay at gmail.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
(cherry picked from commit 4d64459a92a4c1a64fb7051fd1320c14c1854dcb)
commit 5913a8c9ecf05ad7ee38cb1fe0358048731cc78c
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Dec 7 01:36:21 2015 +0000
r600g: fix outputing to non-0 buffers for stream 0.
This fixes:
arb_transform_feedback3-ext_interleaved_two_bufs_gs
arb_transform_feedback3-ext_interleaved_two_bufs_gs_max
transform-feedback-builtins
If we are only emitting one ring, then emit all output
buffers on it.
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied at redhat.com>
(cherry picked from commit e97ac006d77ccbc87a56e46e2f75da6511c9b9e5)
[Emil Velikov: squash trivial conflicts]
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Conflicts:
src/gallium/drivers/r600/r600_shader.c
commit 3c9e76fc24189e1af3c43e913610a78d280bbbd9
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Tue Dec 8 21:01:15 2015 -0500
nv50/ir: fix cutoff for using r63 vs r127 when replacing zero
The only effect here is a space savings - 822 programs in shader-db
affected with the following overall change:
total bytes used in shared programs : 44154976 -> 44139880 (-0.03%)
Fixes: 641eda0c (nv50/ir: r63 is only 0 if we are using less than 63 registers)
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit f920f8eb026d39c0adb547a90399e76b8351fec6)
commit 67b1e7b94739d7a48a1256853862f97d8a9a711e
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Dec 7 14:18:38 2015 -0800
glsl: Relax qualifier ordering restriction in ES 3.1.
... and allow the "binding" qualifier in ES 3.1 as well.
GLSL ES 3.1 incorporates only a few features from the extension
ARB_shading_language_420pack: the relaxed qualifier ordering
requirements and the binding qualifier.
Cc: "11.1" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
(cherry picked from commit eca846e7ae3721c900ad78db300bbc66b08a3cc3)
commit 0586c5844fb01d8b8df99a7f189e7ad55490659a
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Dec 7 14:11:01 2015 -0800
glsl: Use has_420pack().
These features would not have been enabled with #version 420 otherwise.
Cc: "11.1" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
(cherry picked from commit 79da7220db645ade2903af238603c32d551ed5c4)
commit 7d226ee279b956d762e9a865c1cc5e08f94169a7
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Dec 7 11:14:56 2015 -0800
glsl: Allow binding of image variables with 420pack.
This interaction was missed in the addition of ARB_image_load_store.
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93266
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
(cherry picked from commit c200e606f7348a6d75e4cf72fb538f5d78d67649)
commit 36ff210d0e0b587db3a889719842627707cceff0
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Nov 10 21:07:45 2015 -0800
i965/nir: Remove unused indirect handling
The one and only place where the FS backend allows reladdr is on uniforms.
For locals, inputs, and outputs, we lower it away before the backend ever
sees it. This commit gets rid of the dead indirect handling code.
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
(cherry picked from commit 22c273de2b97743587310f7bbf66767191bde866)
commit 017f4755fd5631f8ce304c9aabe9fd8cedc0b030
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Dec 4 18:33:51 2015 -0800
i965/state: Get rid of dword_pitch arguments to buffer functions
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
(cherry picked from commit abb569ca18db159ae3e4c4b51d01e5a8b3215e04)
commit 61cb4db868138a6cb26438c38873b8fd98f00326
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Nov 2 11:33:12 2015 -0800
i965/vec4: Use a stride of 1 and byte offsets for UBOs
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92909
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
(cherry picked from commit 05bdc21f84edc200a0b0a695b79d12f25cc00645)
commit 34785fb7b9fcfb4a608891e7c27e0a1596089ecb
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Sat Oct 31 16:52:29 2015 -0700
i965/fs: Use a stride of 1 and byte offsets for UBOs
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
(cherry picked from commit 13ad8d03f201a4d09bf7ab9078b00807d61dfada)
commit 22d6bf50781a42880cae42513c31dabd51d791fa
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Nov 23 16:01:44 2015 -0800
i965/vec4: Use byte offsets for UBO pulls on Sandy Bridge
Previously, the VS_OPCODE_PULL_CONSTANT_LOAD opcode operated on
vec4-aligned byte offsets on Iron Lake and below and worked in terms of
vec4 offsets on Sandy Bridge. On Ivy Bridge, we add a new *LOAD_GEN7
variant which works in terms of vec4s. We're about to change the GEN7
version to work in terms of bytes, so this is a nice unification.
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
(cherry picked from commit e3e70698c3cfa7e9acccd6eddfb37516c45d5ac2)
commit 9908d196999bcdff73f29fbb3ab6ebf6b4da4ae9
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: Mon Dec 7 15:16:24 2015 -0500
radeonsi: last_gfx_fence is a winsys fence
Cc: "11.1" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
(cherry picked from commit d5a5dbd71f0e8756494809025ba2119efdf26373)
commit a500109aad1c1d0645b741ebd0ca81b0b2033ef6
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Dec 7 17:40:36 2015 -0500
gk110/ir: fix imad sat/hi flag emission for immediate args
According to nvdisasm both the immediate and non-imm cases use the same
bits. Both of these flags are quite rarely set though.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 1d708aacb7631833b0f04e704481854428f60ba3)
commit 0e78a6770948cbf79140a9b3471727963e31328f
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Dec 7 16:14:53 2015 -0500
gk104/ir: sampler doesn't matter for txf
We actually leave the sampler unset for OP_TXF, which caused the GK104+
logic to treat some texel fetches as indirect. While this works, it's
incredibly wasteful. This only happened when the texture was > 0 (since
sampler remained == 0).
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 63b850403c90f33c295d3ad6be4ad749d4ea6274)
commit 4bb16d712a3b281eb5e7f1c18f110935288daaee
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Dec 4 20:35:08 2015 +0100
radeonsi: disable DCC on Stoney
Cc: 11.1 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
(cherry picked from commit 32f05fadbbdf2a3fb60055e610bbbdcd82dd3ce5)
commit 950e9886d01cd76d4ed5d1854609d27b8e459266
Author: Christian König <christian.koenig at amd.com>
Date: Mon Nov 23 15:21:19 2015 +0100
st/va: disable MPEG4 by default v2
The workarounds are too hacky to enable them by default
and otherwise MPEG4 doesn't work reliably.
v2: add docs/envvars.html, CC stable and fix typos
Signed-off-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com> (v1)
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu> (v1)
Cc: "11.1.0" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit a2c5200a4b3e04a6284dac7de87bc34957b01fa3)
commit dff89432d826275e340713eb11127a174bde8e0f
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Dec 7 13:26:51 2015 -0500
gk110/ir: fix imul hi emission with limm arg
The elemental demo hits this case.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit db072d20867426958153279575dfdc2049b5f595)
commit 499d409a20136d66b265b96d19eba5c1bc7fc5f4
Author: Timothy Arceri <timothy.arceri at collabora.com>
Date: Sun Dec 6 15:17:15 2015 +1100
mesa: move pipeline input/output validation inside _mesa_validate_program_pipeline()
This allows validation to be done on rendering calls also.
Fixes 3 dEQP-GLES31.functional.separate tests.
Cc: "11.1" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Cc: Kenneth Graunke <kenneth at whitecape.org>
(cherry picked from commit 4dd096d74178e66334089fb0ed01cbf2d6117fac)
commit a16f5195ef750118688d6c7b4863516e10f8b43f
Author: Timothy Arceri <timothy.arceri at collabora.com>
Date: Thu Nov 26 21:32:48 2015 +1100
glsl: don't generate extra errors in ValidateProgramPipeline
From Section 11.1.3.11 (Validation) of the GLES 3.1 spec:
"An INVALID_OPERATION error is generated by any command that trans-
fers vertices to the GL or launches compute work if the current set
of active program objects cannot be executed, for reasons including:"
It then goes on to list the rules we validate in the
_mesa_validate_program_pipeline() function.
For ValidateProgramPipeline the only mention of generating an error is:
"An INVALID_OPERATION error is generated if pipeline is not a name re-
turned from a previous call to GenProgramPipelines or if such a name has
since been deleted by DeleteProgramPipelines,"
Which we handle separately.
This fixes:
ES31-CTS.sepshaderobjs.PipelineApi
No regressions on the eEQP 3.1 tests.
Cc: Gregory Hainaut <gregory.hainaut at gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
(cherry picked from commit c3ec12ec3c1ddbc72e50df1f5632fe0547a89f7e)
Nominated-by: Emil Velikov <emil.velikov at collabora.com>
commit f65b79008987e662f2bb6218cdd251643650db12
Author: Timothy Arceri <timothy.arceri at collabora.com>
Date: Sun Dec 6 14:30:44 2015 +1100
glsl: re-validate program pipeline after sampler change
Cc: "11.1" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Cc: Kenneth Graunke <kenneth at whitecape.org>
https://bugs.freedesktop.org/show_bug.cgi?id=93180
(cherry picked from commit da1a01361b0b4b9c727aa9a5a2ebe270a6fa81b7)
commit aa19234943bb254f79f3d3582d3f1fcda2f5b5d6
Author: Gregory Hainaut <gregory.hainaut at gmail.com>
Date: Sun Oct 25 15:01:37 2015 +0100
glsl: don't sort varying in separate shader mode
This fixes an issue where the addition of the FLAT qualifier in
varying_matches::record() can break the expected varying order.
It also avoids a future issue with the relaxing of interpolation
qualifier matching constraints in GLSL 4.50.
V2: (by Timothy Arceri)
* reworked comment slightly
Signed-off-by: Gregory Hainaut <gregory.hainaut at gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri at collabora.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
(cherry picked from commit 2ab9cd0c4dcefb3e63266cadc1e06079e67c3962)
Nominated-by: Timothy Arceri <timothy.arceri at collabora.com>
commit 66f216d8ceda75ed0a47512a69af5f8d94ea0172
Author: Gregory Hainaut <gregory.hainaut at gmail.com>
Date: Sun Oct 25 15:01:35 2015 +0100
glsl: don't dead code remove SSO varyings marked as active
GL_ARB_separate_shader_objects allow matching by name variable or block
interface. Input varyings can't be removed because it is will impact the
location assignment.
This fixes the bug 79783 and likely any application that uses
GL_ARB_separate_shader_objects extension.
V2 (by Timothy Arceri):
* simplify now that builtins are not set as always active
Signed-off-by: Gregory Hainaut <gregory.hainaut at gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri at collabora.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
https://bugs.freedesktop.org/show_bug.cgi?id=79783
(cherry picked from commit 8117f46f496fb31339fc97a2501d5b3325a1fefb)
Nominated-by: Timothy Arceri <timothy.arceri at collabora.com>
commit 4d34038ae5a01c723a2d63f1b8f9f846637dd645
Author: Gregory Hainaut <gregory.hainaut at gmail.com>
Date: Sun Oct 25 15:01:34 2015 +0100
glsl: add always_active_io attribute to ir_variable
The value will be set in separate-shader program when an input/output
must remains active. e.g. when deadcode removal isn't allowed because
it will create interface location/name-matching mismatch.
v3:
* Rename the attribute
* Use ir_variable directly instead of ir_variable_refcount_visitor
* Move the foreach IR code in the linker file
v4:
* Fix variable name in assert
v5 (by Timothy Arceri):
* Rename functions and reword comments
* Don't set always active on builtins
Signed-off-by: Gregory Hainaut <gregory.hainaut at gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri at collabora.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
(cherry picked from commit 618612f867ed8140409796535314d9b9ed58440b)
Nominated-by: Timothy Arceri <timothy.arceri at collabora.com>
commit 781a68555db22588f0e9817671885a3fb7c7c66f
Author: Timothy Arceri <timothy.arceri at collabora.com>
Date: Sat Nov 21 11:08:36 2015 +1100
glsl: copy how_declared when lowering interface blocks
Cc: Gregory Hainaut <gregory.hainaut at gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
(cherry picked from commit 76c09c1792ff1209bd34e1ae0e17b9c4929a892f)
commit e0b11bcc877025a6578ab612c69262a5d3d4258a
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Oct 27 23:10:51 2015 +0100
radeonsi: fix occlusion queries on Fiji
Tested.
(cherry picked from commit bfc14796b077444011c81f544ceec5d8592c5c77)
commit 359679cb339f47d28673b04271b2aa17355f02b1
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Nov 24 21:25:53 2015 -0800
i965: Pass brw_context pointer, not gl_context pointer.
Fixes a warning introduced by commit dcadd855.
(cherry picked from commit f1b7fefd4e7e3872cc0d43901b7ec643e1d115f9)
commit fcf6091521af3310a13a91918fec2290fadbdfdc
Author: Marta Lofstedt <marta.lofstedt at intel.com>
Date: Fri Nov 27 15:31:05 2015 +0100
gles2: Update gl2ext.h to revision: 32120
This is needed to be able to implement the accepted OES
extensions.
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Marta Lofstedt <marta.lofstedt at linux.intel.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
(cherry picked from commit 1d5b88e33b07bc26d612720e6cb197a6917ba75f)
commit aa5082b135b81eaebbf60827cea06da512427892
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Dec 12 18:10:25 2015 +0000
Revert "cherry-ignore: ignore unneeded header update"
This reverts commit 79f3aaca4f03e8efec4c75907fe9b80cfcefefdf.
The commit (header update) was not needed for the 11.0 branch as opposed
to this one (11.1)
commit 1df00e17d35a00f2d9ebf66f988426034aabf8b6
Author: Eric Anholt <eric at anholt.net>
Date: Thu Dec 10 22:02:30 2015 -0800
vc4: When doing algebraic optimization into a MOV, use the right MOV.
If there were src unpacks, changing to the integer MOV instead of float
(for example) would change the unpack operation.
(cherry picked from commit e3efc4b02334897e0103f8cf926f376159ca1293)
commit ad3df9d168a589052ec8d501d590ba521fb4ef98
Author: Eric Anholt <eric at anholt.net>
Date: Thu Dec 10 22:23:10 2015 -0800
vc4: Fix handling of src packs on in qir_follow_movs().
The caller isn't going to expect it from a return, so it would probably
get misinterpreted. If the caller had an unpack in its reg, that's fine,
but don't lose track of it.
(cherry picked from commit 2591beef890015538bed005a79414274a7497b2f)
commit e4cf550501cb10a6fcfb63acd11c853f41ff9f6b
Author: Eric Anholt <eric at anholt.net>
Date: Thu Dec 10 21:51:03 2015 -0800
vc4: Add missing progress note in opt_algebraic.
(cherry picked from commit b70a2f4d81940ef103c95ee51f2a84391a076ac0)
commit ecf2885d7f6b015127c8e2a73818fc7aa37903d3
Author: Eric Anholt <eric at anholt.net>
Date: Tue Dec 8 17:18:37 2015 -0800
vc4: Fix handling of sample_mask output.
I apparently broke this in a late refactor, in such a way that I decided
its tests were some of those interminable ones that I should just
blacklist from my testing. As a result, the refactors related to it were
totally wrong.
(cherry picked from commit 53b2523c6ed8202ba44596bee7ec7ba8420c4e92)
commit fc59ca406488ce1a4a760b015545b5612ebcee1c
Author: Eric Anholt <eric at anholt.net>
Date: Sat Jun 20 15:21:40 2015 -0700
vc4: Enable MSAA.
We still have several failures in the newly enabled tests in simulation:
sRGB downsampling is done as if it was just linear, stencil blits are not
supported on MSAA either, and derivatives are still not supported
(breaking some MSAA simulation shaders). So, other than sRGB downsampling
quality, things seem to be in good shape.
(cherry picked from commit f61ceeb3fd368cec18b13416a65a35fc233d7799)
commit 396fbdc721340615f288cd049e1997b550d1a611
Author: Eric Anholt <eric at anholt.net>
Date: Sun Nov 22 14:31:51 2015 -0800
vc4: Add support for mapping of MSAA resources.
The pipe_transfer_map API requires that we do an implicit
downsample/upsample and return a mapping of that.
(cherry picked from commit fc4a1bfb88d065afb9eda9a888b91d8c0fa72dcd)
commit 50ac2100df2aa8dff25532a740149f5f4af9e3f2
Author: Eric Anholt <eric at anholt.net>
Date: Tue Jun 23 09:50:36 2015 -0700
vc4: Add support for texel fetches from MSAA resources.
This is the core of ARB_texture_multisample. Most of the piglit tests for
GL_ARB_texture_multisample require GL 3.0, but exposing support for this
lets us use the gallium blitter for multisample resolves. We can
sometimes multisample resolve using just the RCL, but that requires that
the blit is 1:1, unflipped, and aligned to tile boundaries.
(cherry picked from commit 6b4dfd53ae9b4f86cda0377a4d67b79e9faf7cc8)
commit 08cf0f85295701bab0377fa890667e4328d28502
Author: Eric Anholt <eric at anholt.net>
Date: Tue Jun 23 13:11:55 2015 -0700
vc4: Add support for multisample framebuffer operations.
This includes GL_SAMPLE_COVERAGE, GL_SAMPLE_ALPHA_TO_ONE, and
GL_SAMPLE_ALPHA_TO_COVAGE.
I haven't implemented a dithering function yet, and gallium doesn't give
me a good chance to do so for GL_SAMPLE_COVERAGE.
(cherry picked from commit a97b40dca4949b5b8b3320e76768e54f430c9e78)
commit ba51596b1d55146595335a5b0e5c696e06b2ff26
Author: Eric Anholt <eric at anholt.net>
Date: Fri Nov 20 20:25:46 2015 -0800
vc4: Add a workaround for HW-2905, and additional failure I saw with MSAA.
I only stumbled on this while experimenting due to reading about HW-2905.
I don't know if the EZ disable in the Z-clear is actually necessary, but
go with it for now.
(cherry picked from commit edc3305de7d749338ad88a949cedfc290a796fe5)
commit 3d13bb88511087193030f669e041cd3fe9e75360
Author: Eric Anholt <eric at anholt.net>
Date: Mon Jun 22 13:12:27 2015 -0700
vc4: Add support for drawing in MSAA.
(cherry picked from commit edfd4d853a0d26bc0cde811de7b20116db7e66fc)
commit 3bf2c6b96a236f697f7a1b263805211fb777fe0c
Author: Eric Anholt <eric at anholt.net>
Date: Sat Jun 20 15:30:04 2015 -0700
vc4: Add kernel RCL support for MSAA rendering.
(cherry picked from commit e7c8ad0a6c8ba263f29b7c3c5120bc6beabeba7b)
commit 5ab1bb4becb90649244535ab396b1659a68c0f56
Author: Eric Anholt <eric at anholt.net>
Date: Mon Jun 22 11:37:32 2015 -0700
vc4: Rename color_ms_write to color_write.
I was thinking this was the only MSAA resolve thing, so it should be noted
separately, but actually load/store general also do MSAA resolve.
(cherry picked from commit 568d3a8e32109200cc12549d18118b7660be628b)
commit c5ca18ec2fb1ce5b5bfbe94543e4244815092d76
Author: Eric Anholt <eric at anholt.net>
Date: Mon Dec 7 15:18:59 2015 -0800
vc4: Allow RCL blits to the edge of the surface.
The recent unaligned fix successfully prevented RCL blits that weren't
aligned inside of the surface, but we also want to be able to do RCL blits
for the whole surface when the width or height of the surface aren't
aligned (we don't care what renders inside of the padding).
(cherry picked from commit bf92017ace970104b24219fad0ce5b51bc4509b5)
commit f6cca7a0c91ba1a99271160b9b4c7f22d012a334
Author: Eric Anholt <eric at anholt.net>
Date: Mon Dec 7 20:24:12 2015 -0800
vc4: Fix check for tile RCL blits with mismatched y.
This was a typo in 3a508a0d94d020d9cd95f8882e9393d83ffac377 that didn't
show up in testcases at that moment.
(cherry picked from commit 2792d118f17f92b1908e3f0fc735087bb7ea4c38)
commit ae649bf1ad329472ef6a82e492f5cc384c062078
Author: Eric Anholt <eric at anholt.net>
Date: Mon Dec 7 12:24:46 2015 -0800
vc4: Fix compiler warning from size_t change.
I missed this when bringing over the kernel changes.
(cherry picked from commit 1529f138fff59bdb857d5f7da0ee2537521d5044)
commit 132303cfe432ae1c813a0927e6c4455b8cc41d0f
Author: Eric Anholt <eric at anholt.net>
Date: Fri Dec 4 13:41:50 2015 -0800
vc4: Fix accidental scissoring when scissor is disabled.
Even if the rasterizer has scissor disabled, we'll have whatever
vc4->scissor bounds were last set when someone set up a scissor, so we
shouldn't clip to them in that case.
Fixes piglit fbo-blit-rect, and a lot of MSAA tests once they're enabled.
(cherry picked from commit a4eff86f4afb6618aff488e9da5600e33d97a9c3)
commit 9df243119463b4c1da9b95b44d0e444f19bb892b
Author: Eric Anholt <eric at anholt.net>
Date: Fri Dec 4 13:15:01 2015 -0800
vc4: Disable RCL blitting when scissors are enabled.
We could potentially handle scissored blits when they're tile aligned, but
it doesn't seem worth it. If you're doing a scissored blit, you're
probably a testcase.
Fixes piglit's fbo-scissor-blit fbo
(cherry picked from commit d16d666776ee12659145f08bd35566dd2cc0f925)
commit dd409e2a414d82fe2dc0605b1e0634afa6dcc6ea
Author: Eric Anholt <eric at anholt.net>
Date: Sat Dec 5 12:25:25 2015 -0800
vc4: Bring over cleanups from submitting to the kernel.
(cherry picked from commit 0afe83078d10e0d376f7c3e2515ab2682fec0eb1)
commit 38c770ec29d937cbb05f5a164efb2691199d40f7
Author: Eric Anholt <eric at anholt.net>
Date: Sun Aug 9 14:16:30 2015 -0700
vc4: Add debug dumping of MSAA surfaces.
(cherry picked from commit a69ac4e89c1c3edc33eb4e9361229a3f25de3ee6)
commit d8450616d9eb681876ba58bc9d1831b96467aaa1
Author: Eric Anholt <eric at anholt.net>
Date: Mon Jun 22 17:41:08 2015 -0700
vc4: Add support for laying out MSAA resources.
For MSAA, we store full resolution tile buffer contents, which have their
own tiling format. Since they're full resolution buffers, we have to
align their size to full tiles.
(cherry picked from commit 3c3b1184eb57951c8a40258c9214a1aece1602e6)
commit c9fe9e4b42014556f36af01d9720184b667b7a48
Author: Eric Anholt <eric at anholt.net>
Date: Fri Nov 20 17:18:03 2015 -0800
vc4: Add support for storing sample mask.
From the API perspective, writing 1 bits can't turn on pixels that were
off, so we AND it with the sample mask from the payload.
(cherry picked from commit 74c4b3b80cc4246fd1eb503d97edb3d293eef5de)
commit 693e93832105f186cff4095da1214c214e6e2954
Author: Eric Anholt <eric at anholt.net>
Date: Sat Nov 21 19:26:54 2015 -0800
vc4: Fix up tile alignment checks for blitting using just an RCL.
We were checking that the blit started at 0 and was 1:1, but not that it
went to the full width of the surface, or that the width was aligned to a
tile. We then told it to blit to the full width/height of the surface,
causing contents to be stomped in a bunch of MSAA tests that happen to
include half-screen-width blits to 0,0.
(cherry picked from commit 3a508a0d94d020d9cd95f8882e9393d83ffac377)
commit 7a0661839b936f75fac2d4f78b473605d7c6e20a
Author: Eric Anholt <eric at anholt.net>
Date: Fri Nov 20 17:11:18 2015 -0800
vc4: Add support for loading sample mask.
(cherry picked from commit a664233042e1ad343184a0c237c3bd7ac5010779)
commit 4c234d183ba2b3f87d3ebf4415ace4362d203202
Author: Eric Anholt <eric at anholt.net>
Date: Fri Nov 20 20:42:12 2015 -0800
vc4: Use nir_channel() to simplify all of our nir_swizzle() cases.
(cherry picked from commit 4cff16bc3a84569da05e672c8226931678aa62c0)
commit b37189523e2edfe7f31e598218770dc640a39afa
Author: Eric Anholt <eric at anholt.net>
Date: Fri Nov 20 18:52:58 2015 -0800
vc4: Fix point size lookup.
I think I may have regressed this in the NIR conversion. TGSI-to-NIR is
putting the PSIZ in the .x channel, not .w, so we were grabbing some
garbage for point size, which ended up meaning just not drawing points.
Fixes glean pointAtten and pointsprite.
(cherry picked from commit 81544f231ad6eba1c7eb8b89273c59eb53a25879)
commit 20db46c227fad1ccc23287d3c008d0ca24b49d5a
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Mon Dec 7 13:50:15 2015 +0000
Update version to 11.1.0-rc3
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
commit b2a5efb56f612123fbaf9a10e63abf712e397807
Author: Michel Dänzer <michel.daenzer at amd.com>
Date: Thu Nov 19 11:30:21 2015 +0900
radeon/llvm: Use llvm.AMDIL.exp intrinsic again for now
llvm.exp2.f32 doesn't work in some cases yet.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92709
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
(cherry picked from commit d09463193608009fa42e046b1fc144435d3533f6)
commit 38c645b60a49899e58edce4a2b47ed19b25c3b08
Author: Connor Abbott <connor.w.abbott at intel.com>
Date: Mon Aug 3 14:38:12 2015 -0700
i965: fix 64-bit immediates in brw_inst(_set)_bits
If we tried to get/set something that was exactly 64 bits, we would
try to do (1 << 64) - 1 to calculate the mask which doesn't give us all
1's like we want.
v2 (Iago)
- Replace ~0 by ~0ull
- Removed unnecessary parenthesis
v3 (Kristian)
- Avoid the conditional
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
(cherry picked from commit b1a83b5d1b677faf650a41cd2c152b4d1cd18f84)
Squashed with commit
i965: Use ull immediates in brw_inst_bits
This fixes a regression introduced in b1a83b5d1 that caused basically all
shaders to fail to compile on 32-bit platforms.
Reported-by: Mark Janes <mark.a.janes at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
(cherry picked from commit 9d703de85a7bdd6ae767aedd7690cb82794cb90a)
Nominated-by: Ian Romanick <ian.d.romanick at intel.com>
commit 2dff4c6fa76acf3c415ee406faa1005f301b09fb
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Nov 26 00:36:17 2015 +0000
mesa: rework the meaning of gl_debug_message::length
Currently it stores strlen(buf) whenever the user originally provided a
negative value for length.
Although I've not seen any explicit text in the spec, CTS requires that
the very same length (be that negative value or not) is returned back on
Pop.
So let's push down the length < 0 checks, tweak the meaning of
gl_debug_message::length and fix GetDebugMessageLog to add and count the
null terminators, as required by the spec.
v2: return correct total length in GetDebugMessageLog
v3: rebase (drop _mesa_shader_debug hunk).
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri at collabora.com>
(cherry picked from commit 5a23f6bd8d8d26e0e75801df44cc228f15f9768e)
commit d81ddb3ed8e180b08e0905c7f3b1f9ce72b9dccf
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Nov 26 00:36:16 2015 +0000
mesa: errors: validate the length of null terminated string
We're about to rework the meaning of gl_debug_message::length to only
store the user provided data. Thus we should add an explicit validation
for null terminated strings.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri at collabora.com>
(cherry picked from commit 622186fbdf47e4c77aadba3e38567636ecbcccf5)
commit c25c1dbf512cec97c480e26e2030d9120d83ea76
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Nov 26 00:36:15 2015 +0000
mesa: accept TYPE_PUSH/POP_GROUP with glDebugMessageInsert
These new (relative to ARB_debug_output) tokens, have been explicitly
separated from the existing ones in the spec text. With the reference
to glDebugMessageInsert was dropped.
At the same time, further down the spec says:
"The value of <type> must be one of the values from Table 5.4"
... and these two are listed in Table 5.4.
The GL 4.3 and GLES 3.2 do not give any hints on the former
'definition', plus CTS requires that the tokens are valid values for
glDebugMessageInsert.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri at collabora.com>
(cherry picked from commit 66fea8bd9662c8fc62d87cafce89adc27e3172a2)
commit bed982c4b75e4521d33e3798bec1bda7c78f204c
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Nov 26 00:36:14 2015 +0000
mesa: add SEVERITY_NOTIFICATION to default state
As per the spec quote:
"All messages are initially enabled unless their assigned severity
is DEBUG_SEVERITY_LOW"
We already had MEDIUM and HIGH set, let's toggle NOTIFICATION as well.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri at collabora.com>
(cherry picked from commit 53be28107b44200a59c678c5d2234efeb48d0b35)
commit dcaf3989d12602799b3d50d6068fe926509c911d
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Nov 26 00:36:13 2015 +0000
mesa: return the correct value for GroupStackDepth
We already have one group (the default) as specified in the spec. So
lets return its size, rather than the index of the current group.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri at collabora.com>
(cherry picked from commit 078dd6a0b4135b5181eea538473fe53a9bc61223)
commit 996a4958da7ae97efff4335cae857143d5119404
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Nov 26 00:36:12 2015 +0000
mesa: rename GroupStackDepth to CurrentGroup
The variable is used as the actual index, rather than the size of the
group stack - rename it to reflect that.
Suggested-by: Ilia Mirkin <imirkin at alum.mit.edu>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri at collabora.com>
(cherry picked from commit f39954bf7cf09199a1cccb71e0e858c0b2054c6d)
commit 0cf5a8159f9821425dbc63315545fbf52436e911
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Nov 26 00:36:11 2015 +0000
mesa: do not enable KHR_debug for ES 1.0
The extension requires (cough implements) GetPointervKHR (alias of
GetPointerv) which in itself is available for ES 1.1 enabled mesa.
Anyone willing to fish around and implement it for ES 1.0 is more than
welcome to revert this commit. Until then lets restrict things.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93048
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri at collabora.com>
(cherry picked from commit 1ca735701bb4d66c95d2ab64c0d838608f7c3f96)
commit 6cc9a53d84fba33a3557826f6fc9b34d67c44069
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Nov 26 00:36:10 2015 +0000
glapi: add GetPointervKHR to the ES dispatch
The KHR_debug extension implements this.
Strictly speaking it could be used with ES 1.0, although as the original
function is available on ES 1.1, I'm inclined to lift the KHR_debug
requirement to ES 1.1.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93048
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri at collabora.com>
(cherry picked from commit f53f9eb8d495a318bc8e6fd758df4ba4074599ef)
Squashed with commit
mesa/tests: add KHR_debug GLES glGetPointervKHR entry points
Should have been part of commit f53f9eb8d49 "glapi: add GetPointervKHR
to the ES dispatch".
v2: comment out the ES1.1 symbol and use the same description (pattern)
as elsewhere (Matt)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93235
Fixes: f53f9eb8d49 "glapi: add GetPointervKHR to the ES dispatch".
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Tested-by: Vinson Lee <vlee at freedesktop.org> (v1)
Tested-by: Michel Dänzer <michel.daenzer at amd.com>
(cherry picked from commit 1074e38fbbc89a06c74f036622cbe2778bee993a)
commit 0a51e77fa1e858c0593579f2052d70bb1602e167
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Nov 27 13:12:59 2015 +0000
mesa: remove len argument from _mesa_shader_debug()
There was only a single user which was using strlen(buf).
As this function is not user facing (i.e. we don't need to feed back
original length via a callback), we can simplify things.
Suggested-by: Timothy Arceri <timothy.arceri at collabora.com>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri at collabora.com>
(cherry picked from commit d37ebed470c6c37abfc6fe42079bff027ff58e9d)
commit ca6d0a3dbe3f875ee2098fcdd634a1f30d85c921
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Dec 3 22:37:22 2015 -0500
nv50/ir: avoid looking at uninitialized srcMods entries
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 2b98914fe01f1c7b2de8a096c8923b3ab0a69578)
commit 4ae9142f8ba30da1e892f0d29a287dca0ed5a840
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Dec 3 14:04:06 2015 -0500
nv50/ir: fix DCE to not generate 96-bit loads
A situation where there's a 128-bit load where the last component gets
DCE'd causes a 96-bit load to be generated, which no GPU can actually
emit. Avoid generating such instructions by scaling back to 64-bit on
the first load when splitting.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 49692f86a1b77fac4634d2a3f0502ec7451c3435)
commit aff9f8a6f7b6cf19a0ba4260dddf9cef77c02cc2
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Dec 3 23:50:00 2015 +0100
radeonsi: fix Fiji for LLVM <= 3.7
Cc: 11.0 11.1 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
(cherry picked from commit dd27825c8cf0e7b55ebaa139e299f275943d22f6)
commit b0b163c82a74a9910172784ccf59d7343fec3583
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Tue Dec 1 10:42:21 2015 -0800
mesa/version: Update gl_extensions::Version during version override
Commit a16ffb743ced9fde80b2485dfc2d86ae74e86f25, which introduced
gl_extensions::Version, updates the field when the context version
is computed and when entering/exiting meta. Update this field when
the version is overridden as well.
Cc: "11.1" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
Reviewed-by: Marta Lofstedt <marta.lofstedt at intel.com>
(cherry picked from commit 808e75279618d887daeee8ab2025e39c863234ac)
commit f70574c835c39f4df9fbabe631442e8f919fd50f
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Wed Dec 2 13:21:37 2015 +0200
i965: use _Shader to get fragment program when updating surface state
Atomic counters and Images were using ctx::Shader that does not take in
to account program pipeline changes, ctx::_Shader must be used for SSO to
work. Commit c0347705 already changed ubo's to use this.
Fixes failures seen with following Piglit test:
arb_separate_shader_object-atomic-counter
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 231db5869c2c0f32608f39100bffff569da21bea)
commit 26dff8a7bb013d1c24b2bef9bbdff7aedd887242
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Dec 2 20:02:12 2015 -0500
nv50/ir: don't forget to mark flagsDef on cvt in txb lowering
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 101e315cc167b0b00319aa70f64c49470e2525f8)
commit ea21336d1561a3acac02bbfa8170063654e82a0f
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Dec 2 20:24:33 2015 -0500
nv50/ir: fix instruction permutation logic
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 06055121e6386bc74e4558a86ef690eae9556482)
commit 7f6e9c5f59cd424b3bcdd3e8edd9600e3097c927
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Dec 2 20:10:54 2015 -0500
nv50/ir: the mad source might not have a defining instruction
For example if it's $r63 (aka 0), there won't be a definition.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 11fcf46590129abfa2ca2117a320e8a8052761e4)
commit 0828391a3466b382814c03fd4ea70428d3a6800c
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Dec 2 00:38:21 2015 -0500
nv50/ir: deal with loops with no breaks
For example if there are only returns, the break bb will not end up part
of the CFG. However there will have been a prebreak already emitted for
it, and when hitting the RET that comes after, we will try to insert the
current (i.e. break) BB into the graph even though it will be
unreachable. This makes the SSA code sad.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit adcc547bfbef362067bb3b4e3aee75b287bc6189)
commit 75b6f14ab8ddb45a617797a36ee47f39931fd741
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Tue Dec 1 20:35:19 2015 -0500
nvc0/ir: fold postfactor into immediate
SM20-SM50 can't emit a post-factor in the presence of a long immediate.
Make sure to fold it in.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit ff61ac48387d3f42ede50a572c11f404f4cd3abb)
commit 69df6ac27287bdc47d843da6dbd9bdbc6cb6a6fa
Author: Roland Scheidegger <sroland at vmware.com>
Date: Tue Dec 1 20:06:59 2015 +0100
mesa: fix VIEWPORT_INDEX_PROVOKING_VERTEX and LAYER_PROVOKING_VERTEX queries
These are implementation-dependent queries, but so far we just returned the
value of whatever the current provoking vertex convention was set to, which
was clearly wrong.
Just make this a variable in the context constants like for other things
which are implementation dependent (I assume all drivers will want to set
this to the same value for both queries), and set it to GL_UNDEFINED_VERTEX
which is correct for everybody (and drivers can override it).
Reviewed-by: Brian Paul <brianp at vmware.com>
CC: <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 09f74e6ef45859a3b595e2932e2be3e7d7ab6ca0)
commit 0f53b2010cebb570c473777c6cec78b835595c0d
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Feb 24 14:10:20 2015 +1000
r600: SMX returns CONTEXT_DONE early workaround
streamout, gs rings bug on certain r600s, requires a wait idle
before each surface sync.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Cc: "10.6 11.0 11.1" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied at redhat.com>
(cherry picked from commit af4013d26b3203a794ae34fe0c98139bc1058273)
commit 67be605b96612b9944142f002f9d80b6703c797a
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Feb 23 20:14:31 2015 +0000
r600: do SQ flush ES ring rolling workaround
Need to insert a SQ_NON_EVENT when ever geometry
shaders are enabled.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Cc: "10.6 11.0 11.1" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied at redhat.com>
(cherry picked from commit b63944e8b9177d231b3789bf84ea9e67b9629905)
commit be20f1d7c1f76746cedb146ee56d995c30310f6a
Author: Tom Stellard <thomas.stellard at amd.com>
Date: Sat Nov 28 02:40:24 2015 +0000
clover: Handle NULL devices returned by pipe_loader_probe() v2
When probing for devices, clover will call pipe_loader_probe() twice.
The first time to retrieve the number of devices, and then second time
to retrieve the device structures.
We currently assume that the return value of both calls will be the
same, but this will not be the case if a device happens to disappear
between the two calls.
When a device disappears, the pipe_loader_probe() will add a NULL
device to the device list, so we need to handle this.
v2:
- Keep range for loop
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
Acked-by: Emil Velikov <emil.l.velikov at gmail.com>
CC: <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 9adbb9e7134fdc40766710592e81cbc9c09c7aaa)
commit 15344c978bccec869ca66c24e0406a75f93d87c8
Author: Jonathan Gray <jsg at jsg.id.au>
Date: Mon Nov 23 14:22:24 2015 +1100
automake: fix some occurrences of hardcoded -ldl and -lpthread
Correct some occurrences of -ldl and -lpthread to use
$(DLOPEN_LIBS) and $(PTHREAD_LIBS) respectively.
Signed-off-by: Jonathan Gray <jsg at jsg.id.au>
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit 99cd60083518ad4465e3e29996168e8fa8a89fbb)
commit f1bb27acc545cfdaec442f4434d7351d506cd375
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Feb 24 14:09:40 2015 +1000
r600: workaround empty geom shader.
We need to emit at least one cut/emit in every
geometry shader, the easiest workaround it to
stick a single CUT at the top of each geom shader.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Cc: "10.6 11.0 11.1" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied at redhat.com>
(cherry picked from commit 4f347225752b48f3dc5a59a6be71fe78616252a7)
commit dd37db0c80f907323fdbd6098d90044236f14410
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Feb 24 16:30:05 2015 +1000
r600: rv670 use at least 16es/gs threads
This is specified in the docs for rv670 to work properly.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Cc: "10.6 11.0 11.1" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied at redhat.com>
(cherry picked from commit 04efcc6c7adfda75b425f443588f0faab453ba3a)
commit 8e3fbb90a9eea5c1076f759aaa5dbbfbc1d5636e
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Feb 18 23:51:19 2015 +0000
r600: geometry shader gsvs itemsize workaround
On some chips the GSVS itemsize needs to be aligned to a cacheline size.
This only applies to some of the r600 family chips.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Cc: "10.6 11.0 11.1" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied at redhat.com>
(cherry picked from commit 8168dfdd4e63457bd8a9ef04a5d49a1f2e202ab8)
commit 79f3aaca4f03e8efec4c75907fe9b80cfcefefdf
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Fri Dec 4 16:35:05 2015 +0000
cherry-ignore: ignore unneeded header update
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
commit f9a2bd212a18545864ddfea9a1bf288ba26f0e9e
Author: Julien Isorce <j.isorce at samsung.com>
Date: Fri Nov 27 08:55:55 2015 +0000
vl/buffers: fixes vl_video_buffer_formats for RGBX
Fixes: 42a5e143a8d "vl/buffers: add RGBX and BGRX to the supported formats"
Cc: mesa-stable at lists.freedesktop.org
Signed-off-by: Julien Isorce <j.isorce at samsung.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit 10c14919c82b0fd209500d3ecd5a8bbb2653a5a1)
commit aefd6769e87ba84b900db0daeaa814c83f2e6043
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Sun Nov 29 23:25:51 2015 +0000
Update version to 11.1.0-rc2
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
commit 82a363b851d897dacdbe53597652dc6bc613ecde
Author: Neil Roberts <neil at linux.intel.com>
Date: Wed Nov 4 15:52:06 2015 +0100
i965: Handle lum, intensity and missing components in the fast clear
It looks like the sampler hardware doesn't take into account the
surface format when sampling a cleared color after a fast clear has
been done. So for example if you clear a GL_RED surface to 1,1,1,1
then the sampling instructions will return 1,1,1,1 instead of 1,0,0,1.
This patch makes it override the color that is programmed in the
surface state in order to swizzle for luminance and intensity as well
as overriding the missing components.
Fixes the ext_framebuffer_multisample-fast-clear Piglit test.
v2: Handle luminance and intensity formats
Reviewed-by: Ben Widawsky <benjamin.widawsky at intel.com>
(cherry picked from commit 2010de4015c96f241e81012b395cb4254091f0bb)
commit b3183c81c431382a029c0ea450209843a9d6a9ca
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Wed Oct 28 14:50:58 2015 -0700
mesa/teximage: Fix S3TC regression due to ASTC interaction
A prior, literal reading of the ASTC spec led to the prohibition
of some compressed formats being used against the targets:
TEXTURE_CUBE_MAP_ARRAY and TEXTURE_3D. Since the spec does not specify
interactions with other extensions for specific compressed textures,
remove such interactions.
Fixes the following Piglit tests on Gen9:
piglit.spec.arb_direct_state_access.getcompressedtextureimage
piglit.spec.arb_get_texture_sub_image.arb_get_texture_sub_image-getcompressed
piglit.spec.arb_texture_cube_map_array.fbo-generatemipmap-cubemap array s3tc_dxt1
piglit.spec.ext_texture_compression_s3tc.getteximage-targets cube_array s3tc
v2. Don't interact with other specific compressed formats (Ian).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91927
Suggested-by: Neil Roberts <neil at linux.intel.com>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
(cherry picked from commit d1212abf505a468c9947a66dbf2d59acb4616e42)
commit f5e508649db5c046e506d817e158ddff6b3828b1
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Fri Nov 20 16:15:04 2015 -0800
mesa/extensions: Enable overriding permanently enabled extensions
Provide the ability to prevent any permanently enabled extension
from appearing in the string returned by glGetString[i]().
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
Tested-by: Brian Paul <brianp at vmware.com>
(cherry picked from commit 21d43fe51ab5bcbc89ad5c61a51d3517c4243298)
commit 31546c0e8f0c0b696b1341add618cfe472ad6293
Author: Leo Liu <leo.liu at amd.com>
Date: Fri Nov 20 12:07:52 2015 -0500
radeon/vce: disable Stoney VCE for 11.0
Signed-off-by: Leo Liu <leo.liu at amd.com>
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
commit 6b149bedc3b44ff9ec34f42a16ab42e6a201d9bf
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Nov 23 20:26:59 2015 +0000
auxiliary/vl/dri: fd management cleanups
Analogous to previous commit, minus the extra dup. We are the one
opening the device thus we can directly use the fd.
Spotted by Coverity (CID 1339867, 1339877)
Cc: mesa-stable at lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit 5d294d9fa3dcdf8453d97f35e2c799efa887cbcc)
commit 7a4ba7bfad064a7046b8a425f94a9887b1fc9088
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Nov 23 20:26:58 2015 +0000
auxiliary/vl/drm: fd management cleanups
Analogous to previous commit.
Spotted by Coverity (CID 1339868)
Cc: mesa-stable at lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit 151290c1548052fa4e4d625ba99ad63919467e96)
commit ef6769f18f16c11ff1fa7cb50a8713b8cbaf3a12
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Nov 23 20:26:57 2015 +0000
st/xa: fd management cleanups
Analogous to previous commit.
Spotted by Coverity (CID 1339866)
Cc: mesa-stable at lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit fe71059388ebb797255d5d5f7191f300343c6e3c)
commit a71db1c46e12583cd2ecca9ad5258d8a1f4a2a03
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Nov 23 20:26:56 2015 +0000
st/dri: fd management cleanups
Add some checks if the original/dup'd fd is valid and ensure that we
don't leak it on error. The former is implicitly handled within the
pipe_loader, although let's make things explicit and check beforehand.
Spotted by Coverity (CID 1339865)
Cc: mesa-stable at lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit d90ba57c08dc51579c92224c7eedfc9f88f47853)
commit 88cd21fefb99d08201a7fd1c96d76fffd2e46dd8
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Nov 23 20:26:55 2015 +0000
pipe-loader: check if winsys.name is non-null prior to strcmp
In theory this wouldn't be an issue, as we'll find the correct name and
break out of the loop before we hit the sentinel.
Let's fix this and avoid issues in the future.
Spotted by Coverity (CID 1339869, 1339870, 1339871)
Cc: mesa-stable at lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit 5f92906b876d5463efba3ffb19c1de0dcb3c755f)
commit 97d4954f3f699c64ecdf2ad03bc0af9595d5bbe1
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Nov 26 10:32:57 2015 -0500
mesa: support GL_RED/GL_RG in ES2 contexts when driver support exists
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93126
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Eduardo Lima Mitev <elima at igalia.com>
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 0396eaaf80c5d7955d7926c4e448f006c7682d2e)
commit 3d525c86506feb80597a180675c66754809dfcf8
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: Sat Nov 28 00:02:26 2015 +0100
radeon: only suspend queries on flush if they haven't been suspended yet
Non-timer queries are suspended during blits. When the blits end, the queries
are resumed, but this resume operation itself might run out of CS space and
trigger a flush. When this happens, we must prevent a duplicate suspend during
preflush suspend, and we must also prevent a duplicate resume when the CS flush
returns back to the original resume operation.
This fixes a regression that was introduced by:
commit 8a125afa6e88a3eeddba8c7fdc1a75c9b99d5489
Author: Nicolai Hähnle <nhaehnle at gmail.com>
Date: Wed Nov 18 18:40:22 2015 +0100
radeon: ensure that timing/profiling queries are suspended on flush
The queries_suspended_for_flush flag is redundant because suspended queries
are not removed from their respective linked list.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reported-by: Axel Davy <axel.davy at ens.fr>
Cc: "11.1" <mesa-stable at lists.freedesktop.org>
Tested-by: Axel Davy <axel.davy at ens.fr>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
(cherry picked from commit 9e5e702cfb380af461062c96d974027da8d5f17a)
commit 9b9fff6830e4f3b46f5ada810f10740f9fab8f84
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Nov 23 15:28:55 2015 +0000
targets: use the non-inline sw helpers
Previously (with the inline ones) things were embedded into the
pipe-loader, which means that we cannot control/select what we want in
each target.
That also meant that at runtime we ended up with the empty
sw_screen_create() as the GALLIUM_SOFTPIPE/LLVMPIPE were not set.
v2: Cover all the targets, not just dri.
Cc: "11.1" <mesa-stable at lists.freedesktop.org>
Cc: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: Edward O'Callaghan <edward.ocallaghan at koparo.com>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Tested-by: Oded Gabbay <oded.gabbay at gmail.com>
Tested-by: Nick Sarnie <commendsarnex at gmail.com>
(cherry picked from commit 59cfb21d4670559d49a721df766073d9d288b51a)
Squashed with commit
targets/xvmc: use the non-inline sw helpers
This was missed in commit 59cfb21d ("targets: use the non-inline sw
helpers").
Fixes build failure:
CXXLD libXvMCgallium.la
../../../../src/gallium/auxiliary/pipe-loader/.libs/libpipe_loader_static.a(libpipe_loader_static_la-pipe_loader_sw.o):(.data.rel.ro+0x0): undefined reference to `sw_screen_create'
collect2: error: ld returned 1 exit status
Makefile:756: recipe for target 'libXvMCgallium.la' failed
make[3]: *** [libXvMCgallium.la] Error 1
Trivial.
(cherry picked from commit 22d2dda03be32d23bc8e9f5823a4f2469737ddbe)
commit 3d09bede300084484d87689148147ed17145c09c
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Nov 23 11:26:39 2015 +0000
target-hepers: add non inline sw helpers
Feeling rather dirty copying the inline ones, yet we need the inline
ones for swrast only targets like libgl-xlib, osmesa.
Cc: "11.1" <mesa-stable at lists.freedesktop.org>
Cc: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: Edward O'Callaghan <edward.ocallaghan at koparo.com>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Tested-by: Oded Gabbay <oded.gabbay at gmail.com>
Tested-by: Nick Sarnie <commendsarnex at gmail.com>
(cherry picked from commit fbc6447c3d06d85a862df67aadb68333e2ea2431)
commit aad5c7d1ca66c58e1f4ac173e8587872489f9c09
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Nov 23 21:37:51 2015 +0000
pipe-loader: fix off-by one error
With earlier commit we've dropped the manual iteration over the fixed
size array and prepemtively set the variable storing the size, that is
to be returned. Yet we forgot to adjust the comparison, as before we
were comparing the index, now we're comparing the size.
Fixes: ff9cd8a67ca "pipe-loader: directly use
pipe_loader_sw_probe_null() at probe time"
Cc: mesa-stable at lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93091
Reported-by: Tom Stellard <thomas.stellard at amd.com>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Tested-by: Tom Stellard <thomas.stellard at amd.com>
Tested-by: Dieter Nützel <Dieter at nuetzel-hh.de>
(cherry picked from commit f6235171882d18d0b4d11a3d564c6aa3b22af9d1)
commit 323161333cd9e871e77d27813b6ac6722903d8dc
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Nov 24 21:33:01 2015 -0800
i965: Fix scalar vertex shader struct outputs.
While we correctly set output[] for composite varyings, we set completely
bogus values for output_components[], making emit_urb_writes() output
zeros instead of the actual values.
Unfortunately, our simple approach goes out the window, and we need to
recurse into structs to get the proper value of vector_elements for each
field.
Together with the previous patch, this fixes rendering in an upcoming
game from Feral Interactive.
v2: Use pointers instead of pass-by-mutable-reference (Jason, Matt).
Cc: "11.1 11.0" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
(cherry picked from commit 3810c1561401aba336765d64d1a5a3e44eb58eb3)
commit 80febef0add665fd7ca396a0b0c6ce48fe39157d
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 19 20:03:25 2015 -0800
i965: Fix fragment shader struct inputs.
Apparently we have literally no support for FS varying struct inputs.
This is somewhat surprising, given that we've had tests for that very
feature that have been passing for a long time.
Normally, varying packing splits up structures for us, so we don't see
them in the backend. However, with SSO, varying packing isn't around
to save us, and we get actual structs that we have to handle.
This patch changes fs_visitor::emit_general_interpolation() to work
recursively, properly handling nested structs/arrays/and so on.
(It's easier to read with diff -b, as indentation changes.)
When using the vec4 VS backend, this fixes rendering in an upcoming
game from Feral Interactive. (The scalar VS backend requires additional
bug fixes in the next patch.)
v2: Use pointers instead of pass-by-mutable-reference (Jason, Matt).
Cc: "11.1 11.0" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
(cherry picked from commit 3e9003e9cf55265ab1fb6522dc5cbb2f455ea1f9)
commit cf705849072c5a467884b0ce89503fdf8f0f2749
Author: Tom Stellard <thomas.stellard at amd.com>
Date: Mon Nov 16 20:00:12 2015 +0000
radeonsi/compute: Use the compiler's COMPUTE_PGM_RSRC* register values
The compiler has more information and is able to optimize the bits
it sets in these registers.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
CC: <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 89851a296536b89364fe6104d13330975788f960)
commit 96e1bf879116bb1ec646cec66eca8d1943c5a524
Author: Tom Stellard <thomas.stellard at amd.com>
Date: Mon Nov 16 19:58:32 2015 +0000
radeonsi: Rename si_shader::ls_rsrc{1,2} to si_shader::rsrc{1,2}
In the future, these will be used by other shaders types.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
(cherry picked from commit 95e051091676584fd7bfba9d0316c3747bf17f35)
commit 34521c2840d59a414b314c7861436e41d13ee9ac
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Nov 24 08:58:49 2015 -0800
docs: add missed i965 feature to relnotes
Trivial. GL_ARB_fragment_layer_viewport support was added in 8c902a58
by Ken.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Cc: "11.1" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 9b41489cb5ae7ef9157e8e6b42f3621a871c75a3)
commit 6a710900025c2ee07700077dc43af04fa2ac8386
Author: Timothy Arceri <timothy.arceri at collabora.com>
Date: Tue Nov 24 11:44:13 2015 +1100
glsl: implement recent spec update to SSO validation
Enables 200+ dEQP SSO tests to proceed past validation,
and fixes a ES31-CTS.sepshaderobjs.PipelineApi subtest.
V2: split out change that reverts a previous patch into its own commit,
move variable declaration to top of function, and fix some formatting
all suggested by Ian.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Cc: "11.1" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 2571a768d6cacfbc7e434dfc2b6d01bdf5be21a6)
commit 88fd679706c6014cf0d044105e02bec94edf679e
Author: Timothy Arceri <timothy.arceri at collabora.com>
Date: Tue Nov 24 11:50:22 2015 +1100
Revert "mesa: return initial value for VALIDATE_STATUS if pipe not bound"
This reverts commit ba02f7a3b6a0e4314753a8e5080db61241563f9c.
The commit checked whether the pipeline was currently bound instead
of checking whether it had ever been bound. The previous setting
of Validated during object creation makes this unnecessary. The
real problem was that Validated was not properly set to false
elsewhere in the code. This is fixed by a later patch.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Cc: "11.1" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 3c4aa7aff2a976e94c2b6b7bf273edd617080ca3)
commit bb7a1ee11f818a279a0859fcd6bb6e361d21b5bf
Author: Boyuan Zhang <boyuan.zhang at amd.com>
Date: Thu Nov 12 18:01:16 2015 -0500
radeon/uvd: uv pitch separation for stoney
v2: set the behaviour default for future ASICs.
Signed-off-by: Boyuan Zhang <boyuan.zhang at amd.com>
Reviewed-by: Leo Liu <leo.liu at amd.com>
Cc: mesa-stable at lists.freedesktop.org
(cherry picked from commit f55f134a033a61d67c2a71bbe57f85eb3484eec1)
commit 7a41162b45fedff82d56b21c3eed533af5367bbf
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Nov 11 12:33:38 2015 +1000
texgetimage: consolidate 1D array handling code.
This should fix the getteximage-depth test that currently asserts.
I was hitting problem with virgl as well in this area.
This moves the 1D array handling code to a single place.
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Ben Skeggs <bskeggs at redhat.com>
Cc: "10.6 11.0 11.1" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied at redhat.com>
(cherry picked from commit 237bcdbab529237a120e225c63f567934a955523)
commit 5e853a4f013a0f72f52697e92b2347ce39f31527
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Nov 23 12:31:59 2015 -0500
docs: add missed freedreno features to relnotes
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "11.1" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit e4c1221d367405debdb010b249c633355a3eafe9)
commit 2e073938d039436515f1de6c8abc6cc5839374f0
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Nov 22 14:03:29 2015 -0500
freedreno/a4xx: use a factor of 32767 for snorm8 blending
It appears that the hardware wants the integer to be scaled the same way
that the hardware representation is. snorm16 uses one of the float
factors, so this is only relevant for snorm8.
This fixes a number of subcases of
bin/fbo-blending-formats GL_EXT_texture_snorm
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org
(cherry picked from commit 81b16350fa2e7c1b47d976be12d2313283f22e24)
commit 30e1c390b3ce927132848d93778cb5c240642be4
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sun Nov 22 22:05:01 2015 +0000
configure.ac: default to disabled dri3 when --disable-dri is set
Not too long ago, the dri3 code was living in src/glx, which in itself
was guarded by HAVE_DRI_GLX. As the name suggests we didn't dive into
the folder when dri was disabled, thus we missed that dri3 does not
consider/honour --enable-dri.
Cc: mesa-stable at lists.freedesktop.org
Fixes: 6bd9ba7d074 "loader: Add dri3 helper"
Cc: Pali Rohár <pali.rohar at gmail.com>
Reported-by: Pali Rohár <pali.rohar at gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit b89d1b2ccf16c0bee3708560b69e99b6dbb212f0)
commit 72e51e5dfa22a0e966d60df43aceb09c68f1da2f
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sun Nov 22 22:05:00 2015 +0000
loader: unconditionally add AM_CPPFLAGS to libloader_la_CPPFLAGS
It seems that due to the conditional autotools is getting confused and
forgetting to add AM_CPPFLAGS when building libloader (when
HAVE_DRICOMMON is not set).
Cc: mesa-stable at lists.freedesktop.org
Fixes: 5a79e0a8e37 "automake: loader: rework the CPPFLAGS"
Reported-by: Pali Rohár <pali.rohar at gmail.com>
Tested-by: Pali Rohár <pali.rohar at gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
(cherry picked from commit b9b0a1f58e41ba4027a16300393835dc8c632f50)
commit 902378d6c8b1be54cb8ebccea59d8687690c373b
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Nov 21 19:43:09 2015 +0000
pipe-loader: link against libloader regardless of libdrm presence
Whether or not the loader has libdrm support is up-to it. Anyone using
the loader should just include it whenever they depend on it.
Cc: mesa-stable at lists.freedesktop.org
Fixes: 0f39f9cb7ad "pipe-loader: add a dummy 'static' pipe-loader"
Reported-by: Jon TURNEY <jon.turney at dronecode.org.uk>
Tested-by: Jon TURNEY <jon.turney at dronecode.org.uk>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit 8a6d4765880a2c9000970b2b6e584291090b1dc3)
commit f6f127b597611c9a30a2e8f7c10859b56de08b9c
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Apr 18 15:00:45 2015 -0400
nv50/ir: fix (un)spilling of 3-wide results
There is no 96-bit load/store operations, so we have to split it up
into a 32-bit parts, with a split/merge around it.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90348
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 4deb118d06e96731f3481daa72c201d7258bfbbb)
commit a2f2329cdd7d82b79fb49d9fe73d090bc5f86dab
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Nov 22 21:08:16 2015 -0500
nv50,nvc0: properly handle buffer storage invalidation on dsa buffer
In case that the buffer has no bind at all, assume it can be a regular
buffer. This can happen on buffers created through the ARB_dsa
interfaces.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit ad5f6b03e793b9390e3b9f3eca68bd43f9d809eb)
commit 642b66291cee9c411b963a26824b15074f63f9a4
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Nov 22 20:58:56 2015 -0500
nouveau: use the buffer usage to determine placement when no binding
With ARB_direct_state_access, buffers can be created without any binding
hints at all. We still need to allocate these buffers to VRAM or GART,
as we don't have logic down the line to place them into GPU-mappable
space. Ideally we'd be able to shift these things around based on usage.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92438
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 079f713754a9e5d7802b655d54320bd37f24fbfa)
commit 06c3ed8d219f3099062691c3dbf13b0c8d293301
Author: Eric Anholt <eric at anholt.net>
Date: Sat Nov 21 12:52:48 2015 -0800
vc4: Take precedence over ilo when in simulator mode.
They're exclusive at build time, but the ilo entry is always present, so
we'd try to use it and fail out.
v2: Add comment in the code, from Emil.
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit 1b62a4e885267c374dbbe5d5bb2c36515eee6a95)
commit cfbb08168a2302b4a0a6124592cb939fb40c4ea4
Author: Eric Anholt <eric at anholt.net>
Date: Sat Nov 21 13:07:42 2015 -0800
vc4: Just put USE_VC4_SIMULATOR in DEFINES.
In the pipe-loader reworks, it was missed in one of the new directories it
was used.
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit a39eac80fd491abb990b0b77dd5e4adc5b9c53e1)
commit 43b0b8a9a30ed520a9c21805d953a88616bed4eb
Author: Igor Gnatenko <i.gnatenko.brain at gmail.com>
Date: Sun Nov 22 10:12:09 2015 +0100
virgl: pipe_virgl_create_screen is not static
Cc: mesa-stable at lists.freedesktop.org
Fixes: 17d3a5f8579 "target-helpers: add a non-inline drm_helper.h"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93063
Signed-off-by: Igor Gnatenko <i.gnatenko.brain at gmail.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit 05eed0eca71f8c35f315b3b0d7de30f3ff1878b4)
commit 85b6f905e10a14d15465cd167a04966cc5a0d6cb
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Nov 21 01:27:01 2015 -0500
freedreno/a4xx: disable blending and alphatest for integer rt0
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org
(cherry picked from commit 22aeb0c5684cec11fd8cb4a159b10edbcfe8d6ec)
commit 6a6326dcd46545c6885e0b3b3ec5c4e94a9e4dad
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Nov 21 00:02:36 2015 -0500
freedreno/a4xx: fix independent blend
This fixes the ext_draw_buffers2 and arb_draw_buffers_blend tests.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org
(cherry picked from commit 4c170d9e1d5b4e3e642b0241fd1e33948e60df9b)
commit 17a64701cb0287e3c9c56e6beaf5117f6479b615
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Nov 20 21:34:20 2015 -0500
freedreno/a4xx: fix 3d texture setup
Same fix as on a3xx - set the second (tiny) layer size bitfield to the
smallest level's size so that the hw knows not to minify beyond that.
This fixes texelFetch sampler3D piglits.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org
(cherry picked from commit 740eb63aa78a48bae5248b72f023d725ed82d1b3)
commit cb4f6e2a307643e41acdb16cab756e51373f03f4
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Nov 20 21:20:00 2015 -0500
freedreno/a4xx: only align slices in non-layer_first textures
When layer is the container, slices are tightly packed inside of each
layer. We don't need any additional alignment. On a3xx, each slice
contains all the layers, so having alignment makes sense.
This fixes a whole slew of array-related piglits, including texelFetch
and tex-miplevel-selection varieties.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org
(cherry picked from commit ecb0dcd34c9bb31b240a213cd17c236b224cd290)
commit 8c564f03767ca06a8516feccef88f9da2b90418c
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Nov 9 11:15:04 2015 -0800
meta: Don't save or restore the active client texture
This setting is only used by glTexCoordPointer and related glEnable
calls. Since the preceeding commits removed all of those, it is not
necessary to save, reset to default, or restore this state.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
(cherry picked from commit 47b3a0d23504de43ce2dc028e84037f7cd89bd89)
commit 3d2bf5a5f52a83ac9330403e2abec3dff33ee224
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Thu Nov 5 14:48:58 2015 -0800
meta: Don't save or restore the VBO binding
Nothing left in meta does anything with the VBO binding, so we don't
need to save or restore it. The VAO binding is still modified.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
(cherry picked from commit c63f9c735dfbd572b671f739ba5df0c2ad9a388a)
commit d1b7a1f5afdd39ca939b86bb0bc54c7400dd56a4
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Nov 9 13:11:02 2015 -0800
meta/TexSubImage: Don't pollute the buffer object namespace
tl;dr: For many types of GL object, we can *NEVER* use the Gen function.
In OpenGL ES (all versions!) and OpenGL compatibility profile,
applications don't have to call Gen functions. The GL spec is very
clear about how you can mix-and-match generated names and non-generated
names: you can use any name you want for a particular object type until
you call the Gen function for that object type.
Here's the problem scenario:
- Application calls a meta function that generates a name. The first
Gen will probably return 1.
- Application decides to use the same name for an object of the same
type without calling Gen. Many demo programs use names 1, 2, 3,
etc. without calling Gen.
- Application calls the meta function again, and the meta function
replaces the data. The application's data is lost, and the app
fails. Have fun debugging that.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92363
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
(cherry picked from commit 58aa56d40bfc6ba54ad9172bf219d18eeb615a80)
commit 9c2a7cfbbf5233baec5cf8d621ae9b749583fc95
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Thu Nov 5 14:44:26 2015 -0800
meta: Don't pollute the buffer object namespace in _mesa_meta_DrawTex
tl;dr: For many types of GL object, we can *NEVER* use the Gen function.
In OpenGL ES (all versions!) and OpenGL compatibility profile,
applications don't have to call Gen functions. The GL spec is very
clear about how you can mix-and-match generated names and non-generated
names: you can use any name you want for a particular object type until
you call the Gen function for that object type.
Here's the problem scenario:
- Application calls a meta function that generates a name. The first
Gen will probably return 1.
- Application decides to use the same name for an object of the same
type without calling Gen. Many demo programs use names 1, 2, 3,
etc. without calling Gen.
- Application calls the meta function again, and the meta function
replaces the data. The application's data is lost, and the app
fails. Have fun debugging that.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92363
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
(cherry picked from commit 76cfe2bc4436186fd585be96c4f402c1b1c79bdf)
commit 089fa07dee42fdbe3c94bdc799eeeee9a3f5a899
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Thu Nov 5 14:42:07 2015 -0800
meta: Use internal functions for buffer object and VAO access in _mesa_meta_DrawTex
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
(cherry picked from commit a222d4cbc3de49857aebbdf727e53c273abcc6c1)
commit 7ebc8c36a0dd5ed523c4858f1f3ef4ecc5883aeb
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Thu Nov 5 14:31:23 2015 -0800
meta: Track VBO using gl_buffer_object instead of GL API object handle in _mesa_meta_DrawTex
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
(cherry picked from commit b8a7369fb7e5773892d01fcb1140fe6569ee27eb)
commit 79468fac69974bd94fe2bda0882ca97c83abfd41
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Thu Nov 5 14:16:31 2015 -0800
meta: Partially convert _mesa_meta_DrawTex to DSA
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
(cherry picked from commit d5225ee5d92f00958c54b425fe829c811149e889)
commit 756e323f2c84c8839908bec7393b73b4283c8a7d
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Nov 3 17:41:16 2015 -0800
meta: Don't pollute the buffer object namespace in _mesa_meta_setup_vertex_objects
tl;dr: For many types of GL object, we can *NEVER* use the Gen function.
In OpenGL ES (all versions!) and OpenGL compatibility profile,
applications don't have to call Gen functions. The GL spec is very
clear about how you can mix-and-match generated names and non-generated
names: you can use any name you want for a particular object type until
you call the Gen function for that object type.
Here's the problem scenario:
- Application calls a meta function that generates a name. The first
Gen will probably return 1.
- Application decides to use the same name for an object of the same
type without calling Gen. Many demo programs use names 1, 2, 3,
etc. without calling Gen.
- Application calls the meta function again, and the meta function
replaces the data. The application's data is lost, and the app
fails. Have fun debugging that.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92363
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
(cherry picked from commit 37d11b13ce1db2ad867ff5433cb31bcd1d93c7bf)
commit 507732ea3d7c63367897cdb5f48260ba14fcb82c
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Nov 3 16:47:22 2015 -0800
meta: Use internal functions for buffer object and VAO access
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
(cherry picked from commit b1b73a42c8f245d5bf6bbed04071b2c6519b2fb4)
commit 01909c1f29a369f1b39af7da458afd72a59fd7b0
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Nov 3 15:55:14 2015 -0800
meta: Use DSA functions for VBOs in _mesa_meta_setup_vertex_objects
The fixed-function attribute paths don't get the DSA treatment because
there are no DSA entry-points for fixed-function attributes. These
could have been added, but this is a temporary patch intended to make
later patches easier to review.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
(cherry picked from commit 52921f8e089abbc6871060fc50f90b62aaf1e11b)
commit 76b155c9cd125be5a1f8c8eb85cd0d0578cc7fb2
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Nov 3 15:37:40 2015 -0800
meta: Track VBO using gl_buffer_object instead of GL API object handle
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
(cherry picked from commit 1035e00a815f0babddac0c6c43d01fd34f7e8a94)
commit 4a5c29d877c8a89a0a53ba6ba8c864c8cdf70a02
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Nov 2 20:11:02 2015 -0800
meta: Don't leave the VBO bound after _mesa_meta_setup_vertex_objects
Meta currently does this, but future changes will make this impossible.
Explicitly do it as a step in the patch series now to catch any possible
kinks.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
(cherry picked from commit 3b5a7d450dea9bfadf1d72338f4418c87340805b)
commit bf3f0b9e9b56e48e52ccd6e25d5f792adf4313ea
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Nov 2 19:10:08 2015 -0800
i965: Use _mesa_NamedBufferSubData for users of _mesa_meta_setup_vertex_objects
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
(cherry picked from commit ed0bd6573b6ce83471e73d009dbab5220f9e80c0)
commit e097324fee3d3cf12a752d6c27c8a093ef0f3a88
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Nov 2 18:36:34 2015 -0800
meta: Use _mesa_NamedBufferData and _mesa_NamedBufferSubData for users of _mesa_meta_setup_vertex_objects
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
(cherry picked from commit 7f2f3000716d994d94c53f4a0c8a211fb00a46a4)
commit aa607c69af724a75763a14258a6ce2ec5c770171
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Nov 2 18:33:54 2015 -0800
meta: Use DSA functions for PBO in create_texture_for_pbo
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
(cherry picked from commit 89a61afdd7346d6e36caccc4d6f2a2607dc4a1f6)
commit 72470a9c37c889ec636d147992fe256b9aa083c1
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Nov 2 17:04:41 2015 -0800
i965: Don't pollute the buffer object namespace in brw_meta_fast_clear
tl;dr: For many types of GL object, we can *NEVER* use the Gen function.
In OpenGL ES (all versions!) and OpenGL compatibility profile,
applications don't have to call Gen functions. The GL spec is very
clear about how you can mix-and-match generated names and non-generated
names: you can use any name you want for a particular object type until
you call the Gen function for that object type.
Here's the problem scenario:
- Application calls a meta function that generates a name. The first
Gen will probably return 1.
- Application decides to use the same name for an object of the same
type without calling Gen. Many demo programs use names 1, 2, 3,
etc. without calling Gen.
- Application calls the meta function again, and the meta function
replaces the data. The application's data is lost, and the app
fails. Have fun debugging that.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92363
Reviewed-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
(cherry picked from commit 4e6b9c11fc545cc570ea0042af93e61bfb525d34)
commit de299e1e2e27826e002ece9325adc9132a3789ad
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Nov 2 14:49:03 2015 -0800
i965: Use internal functions for buffer object access
Instead of going through the GL API implementation functions, use the
lower-level functions. This means that we have to keep track of a
pointer to the gl_buffer_object and the gl_vertex_array_object.
This has two advantages. First, it avoids a bunch of CPU overhead in
looking up objects and validing API parameters. Second, and much more
importantly, it will allow us to stop calling _mesa_GenBuffers /
_mesa_CreateBuffers and pollute the buffer namespace (next patch).
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
(cherry picked from commit e62799bd4e7b7525995e465a4bdcf6df0b0a69a0)
commit ded66b145158ce15a86d1f00db115e39bfc7737a
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Nov 2 14:31:56 2015 -0800
i965: Use DSA functions for VBOs in brw_meta_fast_clear
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
(cherry picked from commit 1c5423d3a074d50138e5ad7945024f9cf4d063ec)
commit b7b4104a7fd6a206f1efbde8712e59952ba7776c
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Nov 2 12:41:28 2015 -0800
i965: Pass brw_context instead of gl_context to brw_draw_rectlist
Future patches will use the brw_context instead. Keeping this
non-functional change separate should make the function changes easier
to review.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
(cherry picked from commit dcadd855f14b0d3dcce04a16afdfed2d7159d4a8)
commit 236fb067a538991567fb48d679ee0a5bb2d6cd2e
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Nov 3 16:16:00 2015 -0800
mesa: Refactor enable_vertex_array_attrib to make _mesa_enable_vertex_array_attrib
Pulls the parts of enable_vertex_array_attrib that aren't just parameter
validation out into a function that can be called from other parts of
Mesa (e.g., meta).
_mesa_enable_vertex_array_attrib can also be used to enable
fixed-function arrays.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
(cherry picked from commit 4a644f1caadc6b3e26b5f0ac60ac855152e38e59)
commit 2d9093fdf0b9761c0e1f27de2b994f2e8e20e3b5
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Nov 3 16:09:22 2015 -0800
mesa: Refactor update_array_format to make _mesa_update_array_format_public
Pulls the parts of update_array_format that aren't just parameter
validation out into a function that can be called from other parts of
Mesa (e.g., meta).
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
(cherry picked from commit a336fcd36a4743c1ea6f8549cb31b48277359717)
commit d757c0421531ed04653f9b5be46665518c9693d5
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Nov 2 12:40:32 2015 -0800
mesa: Make bind_vertex_buffer avilable outside varray.c
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
(cherry picked from commit 8fae494df2813bfa38f1aabd6c9b3c1ba3a5e4ef)
commit f9339359d5dc64aff818627dce2e0fd9eef543a7
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Sat Nov 21 13:00:25 2015 +0000
Update version to 11.1.0-rc1
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
commit 623f64efc1630fa6c287d4de107430835f9a5fa3
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Oct 16 20:34:52 2015 +0100
util: use RTLD_LOCAL with util_dl_open()
Otherwise we risk things blowing up due to conflicting symbols.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Rob Clark <robclark at freedesktop.org>
commit 8943a562e26091b13295af734f3034077fc825e1
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Oct 15 19:29:00 2015 +0100
targets/nine: remove unused static functions
Dead code since commit 8f50614910c40366d94964fe2c5da5772aff2f96
Cc: Axel Davy <axel.davy at ens.fr>
Cc: Tiziano Bacocco <tizbac2 at gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Rob Clark <robclark at freedesktop.org>
commit 42dde5aa24f4aed176baefb9b72c4184026196ed
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Oct 14 16:52:07 2015 +0100
targets/nine: add note about messy header inclusion order
Cc: Axel Davy <axel.davy at ens.fr>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Rob Clark <robclark at freedesktop.org>
commit 09422507817d21e989004bc93e7447f37cffc9ab
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Oct 14 16:49:59 2015 +0100
targets/nine: add note about fd owndership
v2:
- move autotools hunk into correct patch
- correct the note based on Axel's feedback
Cc: Axel Davy <axel.davy at ens.fr>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Rob Clark <robclark at freedesktop.org>
commit f8a1665542d2bee829ab0c1bbde533f32d983e96
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Oct 14 15:37:03 2015 +0100
auxiliary/vl: Don't close the drm fd on failure
Ported from an identically named commit in st/xa
commit 35cf3831d71770211f29da6608313dc1f6213d7b
Author: Thomas Hellstrom <thellstrom at vmware.com>
Date: Thu Jul 3 02:07:36 2014 -0700
st/xa: Don't close the drm fd on failure v2
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Rob Clark <robclark at freedesktop.org>
commit e43a771dfa5b99899a4a09cdd2989afc25eef17c
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Oct 15 00:46:26 2015 +0100
st/dri: NULL check the pscreen earlier
We delay the null check only to jump through hoops to work around that.
Check early to make our lives easier.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Rob Clark <robclark at freedesktop.org>
commit 13bccee87d6344ec7932b42de3fe3a2d10d30d96
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Oct 15 00:45:13 2015 +0100
st/dri: Don't close the drm fd on failure
Ported from an identically named commit in st/xa
commit 35cf3831d71770211f29da6608313dc1f6213d7b
Author: Thomas Hellstrom <thellstrom at vmware.com>
Date: Thu Jul 3 02:07:36 2014 -0700
st/xa: Don't close the drm fd on failure v2
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Rob Clark <robclark at freedesktop.org>
commit b7f5c2ee48a8e386a891996ca83eb56fdc21229e
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Nov 19 19:47:02 2015 +0000
target-helpers: remove inline_drm_helper.h
As of earlier all the targets use the non inline version. Don't forget
to remove the function prototypes/declarations.
v2: rebase on top of virgl support.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Rob Clark <robclark at freedesktop.org>
commit dddedbec0ed6a7791a92e40689b564999ca9b7eb
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Oct 14 16:47:04 2015 +0100
{st,targets}/nine: use static/dynamic pipe-loader
Analogous to previous commits.
v2: add the missing winsys libs linkage
Cc: Axel Davy <axel.davy at ens.fr>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Rob Clark <robclark at freedesktop.org>
commit 611ef64ed5ddb3c8bd95c2e0dc2f0959218bf516
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Oct 15 00:43:52 2015 +0100
{st,targets}/xa: use static/dynamic pipe-loader
Analogous to previous commits.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Rob Clark <robclark at freedesktop.org>
commit 1eb6e8a23cc29081105336dc2a1cbf6bb4c2603d
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Nov 20 18:02:12 2015 +0000
{auxiliary,targets}/vl: use static/dynamic pipe-loader
Analogous to previous commit.
v2: rebase on top of vl_winsys_drm.c addition
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Rob Clark <robclark at freedesktop.org>
commit 23fb11455b415238fb9e378fa0ab51f4b6cefd7a
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Oct 14 23:48:15 2015 +0100
{st,targets}/dri: use static/dynamic pipe-loader
Covert DRI to use only the pipe-loader interface.
With drisw_create_screen and kms_swrast_create_screen replaced by their
pipe-loader equivalent, we can now drop them.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Rob Clark <robclark at freedesktop.org>
commit c4d337146ad1b880834214510f773f10d9ea6556
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Oct 14 23:44:17 2015 +0100
pipe-loader: add preliminary Android support
Add a 'static' pipe-loader build, which will be used with follow-up
commits.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Chih-Wei Huang <cwhuang at linux.org.tw>
Acked-by: Rob Clark <robclark at freedesktop.org>
commit 234b03cc2378fbb4375fc2635fe3eeab85840d38
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Oct 14 23:32:58 2015 +0100
pipe-loader: add preliminary scons support
Add a 'static' pipe-loader build, which will be used with follow-up
commits.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Rob Clark <robclark at freedesktop.org>
commit 7999e6ddba38016964cbc33b98b4658e900bcd3c
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Oct 14 18:11:11 2015 +0100
pipe-loader: don't mix code and variable declarations
We cannot use this C99 feature here quite yet, as the code needs to be
build with MSVC prior to 2013.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Rob Clark <robclark at freedesktop.org>
commit 17d3a5f8579cf103ffd7002052c700ffe9819152
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sun Oct 11 13:50:56 2015 +0100
target-helpers: add a non-inline drm_helper.h
Unlike the inline ones, here we'd want to have an extern definition of
the functions. This is required as with follow-up commits, we'll
gradually start using the static pipe-loader, with the latter needing
the symbols.
These are direct copy from the inline version.
v2:
- rebase on top of virgl support
- add "driver missing" printfs (Nicolai)
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Rob Clark <robclark at freedesktop.org>
commit af031deed6ab4d6236b896507e8afcf9d6fd3173
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Oct 7 17:37:37 2015 +0100
target-helpers: move the DRI specifics to the target
Rather than having all targets include the file, with only some defining
the relevant guard macro, just move things where they are used.
v2: rebase on top of virgl support.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Rob Clark <robclark at freedesktop.org>
commit 950e06a29bd664af0cb454fc2f35f8cc4153e7f1
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Oct 17 21:14:09 2015 +0100
automake: remove no longer needed HAVE_LOADER_GALLIUM conditional
As of last few commits we have a static and dynamic pipe-loader. Either
of which will be used with (almost) all targets..
We can look into allowing the user to select which way the targets are
built, be that 'static for all' or 'per target' in follow up commits.
After which we can look into building only the static or dynamic
version, although building both shouldn't cause any issues.
Hack/workaround alert:
Control the standalone pipe-drivers via HAVE_CLOVER. Will need to be
fixed as the targets are converted/configure knobs are in.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Rob Clark <robclark at freedesktop.org>
commit be78f73b37caa5c9bc8dec9390d0c397bbff8729
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Nov 20 17:19:54 2015 +0000
pipe-loader: wire up the 'static' sw pipe-loader
Analogous to previous commit with a small catch.
As the sw inline helpers are mere wrappers, and the screen <> winsys
split is more prominent (with the latter not being part of the final
pipe-driver), things will just work.
v2: rebase on top of earlier 'consolitate teardown' changes
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Rob Clark <robclark at freedesktop.org>
commit 1b589207dee10abbe946dd7c3955ad153c5c5881
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Oct 14 14:56:21 2015 +0100
pipe-loader: wire up the 'static' drm pipe-loader
Add a list of driver descriptors and select one from the list, during
probe time.
As we'll need to have all the driver pipe_foo_screen_create() functions
provided externally (i.e. from another static lib) we need a separate
(non-inline) drm_helper, which contains the function declarations.
v2: rebase on top of virgl support.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Rob Clark <robclark at freedesktop.org>
commit 0f39f9cb7ad8e93cfad95043724143ed097de966
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Tue Oct 13 18:07:11 2015 +0100
pipe-loader: add a dummy 'static' pipe-loader
It is to be used in contrast of the dynamic one. The state-tracker does
not need to know if the pipe-driver is built into the final blob or
a separate object. This will allow us to move the logic to the final
step (in target) where the appropriate pipe-loader will be chosen.
Cc: Tom Stellard <thomas.stellard at amd.com>
Cc: Francisco Jerez <currojerez at riseup.net>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Rob Clark <robclark at freedesktop.org>
commit ad12027d8f8ff37ffe14ce17f9d79466b6ffeb32
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Oct 17 22:06:17 2015 +0100
gallium: rename libpipe_loader to libpipe_loader_dynamic
With the next commits we'll introduce a 'static' version, which will
essentially load the statically linked-in pipe-drivers, rather than the
standalone pipe-$foo.so ones.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Rob Clark <robclark at freedesktop.org>
commit 3ca12ee976e44a1126775a8e801889d42dd06980
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Oct 17 21:51:45 2015 +0100
pipe-loader: dlopen/dlsym the pipe-driver at probe time
Rather than giving false hopes that things might work, just check at
probe time. This allows us to remove the duplication and consolidate
the code wrt the upcomming static pipe-loader.
Cc: Tom Stellard <thomas.stellard at amd.com>
Cc: Francisco Jerez <currojerez at riseup.net>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Rob Clark <robclark at freedesktop.org>
commit e465de5a51dbb1af50da1a44353867adc45d57c7
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Oct 14 21:35:50 2015 +0100
pipe-loader: annotate the ops as const data
Already defined as such in struct pipe_loader_device::ops.
Cc: Tom Stellard <thomas.stellard at amd.com>
Cc: Francisco Jerez <currojerez at riseup.net>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Rob Clark <robclark at freedesktop.org>
commit 46991ab9aac99c5ba55b735396f32447e75a6320
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Oct 17 20:53:16 2015 +0100
pipe-loader: teardown the winsys, if create_screen fails
i.e. plug some (hard to hit) memory leaks.
v2: fix rebase fallout - really teardown the winsys (Brian)
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Rob Clark <robclark at freedesktop.org>
commit d54ca54faa2a6dde3c4d2125fd41d10dfcf2f91e
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Oct 17 21:51:24 2015 +0100
pipe-loader: rework the sw backend
Move the winsys into the pipe-target, similar to the hardware
pipe-driver.
v2:
- move int declaration outside of loop (Brian)
- fold the teardown into a goto + separate function.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Rob Clark <robclark at freedesktop.org>
commit f58a6f7be3efa6a13d7ac321f304de2703870def
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Oct 17 23:23:49 2015 +0100
gallium: keep the libdrm link alongside libkmsdri.la
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Rob Clark <robclark at freedesktop.org>
commit ff9cd8a67cabe4a7bbfec941666a216617f18103
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Oct 14 21:31:24 2015 +0100
pipe-loader: directly use pipe_loader_sw_probe_null() at probe time
Due to the nature of the other sw winsys' we cannot use them during the
generic probe stage. As such there is little point in keeping the
abstraction layer.
Cc: Tom Stellard <thomas.stellard at amd.com>
Cc: Francisco Jerez <currojerez at riseup.net>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Rob Clark <robclark at freedesktop.org>
commit 4e3c06a501cbba8cc463c3c244d6cb838e3be782
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Oct 14 19:35:51 2015 +0100
pipe-loader: add pipe_loader_sw_probe_init_common() helper
Allows us to fold the duplication in pipe_loader_sw_probe_*().
Cc: Tom Stellard <thomas.stellard at amd.com>
Cc: Francisco Jerez <currojerez at riseup.net>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Rob Clark <robclark at freedesktop.org>
commit 6d68d714c0ef6afa9666b6ed5f45bf998024805f
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Oct 14 16:16:52 2015 +0100
gallium/tests: remove unneeded include paths
The tests don't (and shouldn't) need to have anything driver and/or
winsys specific.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Rob Clark <robclark at freedesktop.org>
commit 74d41a32bc179425e866f8afa33a222488ea7760
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Oct 14 16:37:37 2015 +0100
gallium: remove library_path argument from pipe_loader_create_screen()
Currently the location is determined at configure/build time and
consistently copied across gallium. Just remove the extra argument, and
use PIPE_SEARCH_DIR where appropriate.
This will allow us to remove the duplication in the *configuration and
*screen_create APIs by moving util_dl_get_proc_address() and friends to
probe time.
v2: rebase on top of vl_winsys_drm.c addition
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Rob Clark <robclark at freedesktop.org>
commit cbc4d9730a7c48744fe7ac62d55b40a80e8fc2e2
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Oct 14 14:52:37 2015 +0100
targets/nine: remove the custom pipe-driver path management
Since the up-streaming of nine, the static target was used by default.
The dynamic pipe-drivers being available only via manual tweak of
configure.ac.
As we'll be removing the library_path argument from the pipe-loader with
follow-up commits, we can remove D3D9_DRIVERS_PATH/D3D9_DRIVERS_DIR.
Everyone doing local hacking on nine, or wishing to have a env override
can bring them back within the pipe-loader.
Cc: Axel Davy <axel.davy at ens.fr>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Rob Clark <robclark at freedesktop.org>
commit 149454bb13aba2815e1a577073e5a834507cbb4c
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Oct 14 16:26:53 2015 +0100
pipe-loader: remove HAVE_DRM_LOADER_GALLIUM and HAVE_PIPE_LOADER_DRM
... in favour of HAVE_LIBDRM. After all we solely want to build the code
when the latter is available.
In the not too distant future we will remove the libudev/sysfs
dependency and simplify configure.ac even further.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Rob Clark <robclark at freedesktop.org>
commit 33f1db1eb412382d2bd6552369e6f63bad52ca8d
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Oct 14 16:24:55 2015 +0100
pipe-loader: add pipe_loader_sw_probe_kms() implementation
Will be used as a counterpart for target-helpers'
kms_swrast_create_screen().
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Rob Clark <robclark at freedesktop.org>
commit be430726e2586e1c9932953325b45e0e6a39f301
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sun Oct 11 11:53:45 2015 +0100
configure: use HAVE_DRISW_KMS when handling kms swrast
Using HAVE_DRI2 to manage it seems counter-intuitive.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Rob Clark <robclark at freedesktop.org>
commit f9c9471b768593d61c486f7a9c0dac52e22fff65
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Tue Oct 6 23:04:22 2015 +0100
targets/nine: use the existing sw_screen_wrap() over our custom version
Cc: Axel Davy <axel.davy at ens.fr>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Rob Clark <robclark at freedesktop.org>
commit 6bcd5f0d02fff2db0c330af7d139d7a60b59e0e2
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Oct 14 16:23:50 2015 +0100
automake: use GALLIUM_PIPE_LOADER_DEFINES only where applicable
As of last commit we no longer need the defines in order to have the
function prototypes.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Rob Clark <robclark at freedesktop.org>
commit b7875ca4939bc5db145b463b7a9a1ea0f9fbccb8
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Oct 14 16:20:32 2015 +0100
pipe-loader: remove HAVE_PIPE_LOADER_foo function prototype guards
They serve little to no purpose, as we don't need any additional
dependencies (headers and/or symbols). On the other hand dropping them
will allow us to use GALLIUM_PIPE_LOADER_DEFINES in only one single
place - the pipe-loader.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Rob Clark <robclark at freedesktop.org>
commit c751d33a2082a44bddb23ee90225be4db0da587f
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Tue Oct 6 22:25:47 2015 +0100
gallium/trace: remove useless NULL check from trace_screen_create()
Currently every target makes sure that the screen is non-null prior to
using the debug (trace including) wrappers. If that no longer holds true
we want to know and fix this ASAP rather than silently bailing out.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Rob Clark <robclark at freedesktop.org>
commit e762a46a074c2e95c0d4bf1765cb16044c1d0d9e
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Oct 7 18:05:04 2015 +0100
configure: remove obsolete _CLIENT comment
The referenced variable(s) have been removed with commit abc20120e4a
(automake: pipe-loader: remove the 'client' pipe-loader)
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Rob Clark <robclark at freedesktop.org>
commit 1a18457a52b22651a282ea0f94e6f7fc5e07ad22
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Sat Nov 21 12:42:48 2015 +0000
docs: add news item and link release notes for 11.0.6
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
commit da2cb8a2eeca83b7f95978798ab77807a1c97aa2
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Sat Nov 21 12:40:06 2015 +0000
docs: add sha256 checksums for 11.0.6
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
(cherry picked from commit 2555e000fc1771dd231207247b5d9dfec4600fe8)
commit 380aec170331598f4098d6670baf67666535b264
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Sat Nov 21 11:38:20 2015 +0000
docs: add release notes for 11.0.6
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
(cherry picked from commit 04fd3a6f629b5098cc2a4da1f2392678349ecf56)
commit d8c26969d5ea585bf53d6efdc5ba2c634b84a2a6
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Nov 20 20:40:45 2015 -0500
freedreno/a4xx: add missing formats to enable ARB_vertex_type_2_10_10_10_rev
Same as commit 84d087aea but for a4xx. The RE'd enums had the same issue
too.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit f6986a81c93de9796e2c805ef831bb110109ed23
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Nov 4 14:38:27 2015 -0800
i965: Test that nonrepresentable floats cannot be converted to VF.
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit f450030f66036e560be87067c0a0cef33cd7b5ed
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Nov 4 14:31:59 2015 -0800
i965: Use ldexpf() in VF float test set up.
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 0684aed8abc51308945ead050d2452b522937c0a
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu Nov 19 21:48:47 2015 -0800
i965/vec4: Initialize nir_inputs with src_reg().
nir_locals, nir_ssa_values, and nir_system_values are all dst_reg (not
that that makes a whole lot of sense to me), and only nir_inputs is a
src_reg.
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit c875e3cdd21811ad6669160d59fa39a4526ef872
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Nov 13 17:51:12 2015 -0800
i965/fs: Add support for gl_HelperInvocation system value.
In most cases (when the negate is copy propagated and the MOV removed),
this is two instructions on Gen >= 8 and only two instructions on
earlier platforms -- and it doesn't use the flag register.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 4b15281295791278b3cd63baccb528742de1d21f
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Nov 16 09:29:01 2015 -0800
i965: Add brw_imm_uv().
commit ce11d4f3695506bd00b319b6ebbfcb9168eb3b84
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Nov 16 09:28:02 2015 -0800
i965: Don't bother setting regioning on immediates.
The region fields are unioned with the immediate storage.
commit c28b574170706d4f9625e7ffa72c87862aa1ca31
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Nov 13 17:50:27 2015 -0800
nir: Add support for gl_HelperInvocation system value.
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit fe29330406f8ea277b2c02f9c6dd2da78796ea84
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Nov 20 18:34:03 2015 -0500
freedreno/a4xx: use hardware RGTC texture samplers
a4xx hardware has real support for RGTC so there's no need to fake it
like we do on a3xx. Undo the hacks, and keep track of an "internal
format" of a resource, which on a3xx will be different, triggering the
transfer-time conversions to take place.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 39fa5c8419076f6ec84de0252905617feb70f279
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Nov 20 17:43:11 2015 -0500
freedreno/a4xx: hook up RGB565 format
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 3b77826cc19d7a6a7e5cc6af6552d0ba89ec2922
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Nov 20 13:27:49 2015 -0500
freedreno/a4xx: logic op handling
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit e1319dcdd6c63ce289a75cd06ac20355d48f01d7
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Nov 20 10:40:59 2015 -0500
freedreno/a4xx: add 16-bit unorm/snorm format texturing/rendering
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit ff9450ecd1f7635f8917e3177f0ef18eb8f9f49b
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Nov 20 18:11:26 2015 -0500
freedreno/a4xx: point regid to "red" even for alpha-only rb formats
Looks like a4xx hw does this in a more standard way and we don't need to
hack around it like we do on a3xx. Fixes GL_ALPHA formats in
fbo-blending-formats, fbo-colormask-formats, and fbo-alphatest-formats.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org
commit 4fd24caf92fc995e4a730181e0f179a7f2218e60
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Nov 20 16:51:07 2015 -0500
ttn: add TEX2 support
This fixes CubeArrayShadow tests (where the shadow comes in via a second
arg to the TEX2 instruction).
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Rob Clark <robdclark at gmail.com>
Cc: mesa-stable at lists.freedesktop.org
commit c1babbd85c4069d9d9b319d5ca95a614039ba609
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Nov 20 17:04:05 2015 -0500
freedreno: always set all border colors
Instead of playing the guessing game as to which texture format reads
from which border color encoding type, just write both of them always.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit ec106e9f621cc1f8b3c1ee55aafa69d5ad159276
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Nov 20 13:45:18 2015 -0500
freedreno/a4xx: fix dst_alpha blend for RGBX render targets
There are not native RGBX render formats, so we must manually force
dst_alpha to be one, same as for a3xx.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 5bda3d0958967b88e739302a480499d1428a0b2a
Author: Nicolai Hähnle <nhaehnle at gmail.com>
Date: Fri Nov 20 12:58:55 2015 +0100
radeon: re-prepare query buffers on begin_query for predicate queries
The point of prepare_buffer is to ensure that the query buffer contains valid
initial data for conditional rendering: as long as the buffer is initialized
correctly, the GPU is able to tell whether query results have been written
already (and wait or fall back to unconditional rendering if desired).
This means prepare_buffer needs to be called again when a buffer is reused.
Conversely, for queries that cannot be used for conditional rendering
(notably pipeline statistics), we can re-use buffers immediately, and they
do not need to be initialized.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Tested-by: Andy Furniss <adf.lists at gmail.com>
commit 6f4fe8e76ada4cd04f20d37825d7763fcc2b62ae
Author: Nicolai Hähnle <nhaehnle at gmail.com>
Date: Fri Nov 20 11:46:26 2015 +0100
radeon: reset query buffers for PIPE_QUERY_TIMESTAMP
Since begin_query is not called for this query type, we need to reset the
query buffer state in end_query instead.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93015
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Tested-by: Andy Furniss <adf.lists at gmail.com>
Tested-by: Mathias Tillman <master.homer at gmail.com>
commit 47fae842d01331af5acc56ff8db37c09ceca791f
Author: Brian Paul <brianp at vmware.com>
Date: Fri Nov 20 10:19:16 2015 -0700
mesa: update some old-style (K&R?) function pointer calls
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 1def5ef95863f704ab5d1bd3bef3a31a6e461b60
Author: Brian Paul <brianp at vmware.com>
Date: Fri Nov 20 14:05:55 2015 -0700
docs: mention GL 3.3 support for VMware driver in Mesa 11.1 relnotes
Signed-off-by: Brian Paul <brianp at vmware.com>
commit 527466d9a12e81f3bade04c5ff0258a003b48f34
Author: Brian Paul <brianp at vmware.com>
Date: Thu Nov 19 10:39:49 2015 -0700
svga: add num-bytes-uploaded HUD query
To graph the number of bytes uploaded to GPU per frame (vertex buffer data,
constant buffer data, texture data, etc).
Reviewed-by: José Fonseca <jfonseca at vmware.com>
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
commit e96d7a1489c1e4ddd66fc5c88c0fc603e1483e32
Author: Brian Paul <brianp at vmware.com>
Date: Thu Nov 19 10:39:09 2015 -0700
svga: add some sanity check assertions in svga_buffer_transfer_map()
Make sure y and z values of buffers are as expected.
Reviewed-by: José Fonseca <jfonseca at vmware.com>
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
commit b109cd3c276e476143ae85fd48d5e43e904291dd
Author: Timothy Arceri <timothy.arceri at collabora.com>
Date: Thu Nov 5 22:17:36 2015 +1100
docs: mark compile-time constant expressions as done
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
commit f7af69c350977f03c6648bdb0b21851933cb98ad
Author: Timothy Arceri <timothy.arceri at collabora.com>
Date: Mon Nov 9 09:34:40 2015 +1100
glsl: add subroutine index qualifier support
ARB_explicit_uniform_location allows the index for subroutine functions
to be explicitly set in the shader.
This patch reduces the restriction on the index qualifier in
validate_layout_qualifiers() to allow it to be applied to subroutines
and adds the new subroutine qualifier validation to ast_function::hir().
ast_fully_specified_type::has_qualifiers() is updated to allow the
index qualifier on subroutine functions when explicit uniform locations
is available.
A new check is added to ast_type_qualifier::merge_qualifier() to stop
multiple function qualifiers from being defied, before this patch this
would cause a segfault.
Finally a new variable is added to ir_function_signature to store the
index. This value is validated and the non explicit values assigned in
link_assign_subroutine_types().
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 02d2ab23786a0f4ef635914801da97faf577197a
Author: Timothy Arceri <timothy.arceri at collabora.com>
Date: Sat Nov 14 15:13:28 2015 +1100
glsl: add support for complie-time constant expressions
This patch replaces the old interger constant qualifiers with either
the new ast_layout_expression type if the qualifier requires merging
or ast_expression if the qualifier can't have mulitple declarations
or if all but the newest qualifier is simply ignored.
We also update the process_qualifier_constant() helper to be
similar to the one in the ast_layout_expression class, but in
this case it will be used to process the ast_expression qualifiers.
Global shader layout qualifier validation is moved out of the parser
in this change as we now need to evaluate any constant expression
before doing the validation.
V2: Fix minimum value check for vertices (Emil)
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
commit 0954b813a3a356b5836f4169783b8c8c58ff2158
Author: Timothy Arceri <timothy.arceri at collabora.com>
Date: Mon Nov 9 07:48:46 2015 +1100
glsl: add new type for compile time constants
In this patch we introduce a new ast type for holding the new
compile-time constant expressions. The main reason for this is that
we can no longer do merging of layout qualifiers before they have been
converted into GLSL IR so we need to store them to be proccessed later.
The new type has two helper functions:
- process_qualifier_constant()
Used to merge and then evaluate qualifier expressions
- merge_qualifier()
Simply appends a qualifier to a list to be merged later by
process_qualifier_constant()
In order to avoid cascading error messages the process_qualifier_constant()
helpers return a bool
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
commit 4196af4ce7cdb0217a7cc6e196b1a788d32c5b6f
Author: Timothy Arceri <timothy.arceri at collabora.com>
Date: Sat Nov 14 14:05:30 2015 +1100
glsl: call set_shader_inout_layout() earlier
This will allow us to add error checking to this function
in a later patch, if we don't move it the error messages
will go missing.
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
commit e74fe2a844e301e8774f2c7e6b142956cc980d4a
Author: Timothy Arceri <timothy.arceri at collabora.com>
Date: Sun Nov 15 00:42:44 2015 +1100
glsl: replace binding layout min boundary check
Use new helper that will in a later patch allow for
compile time constants.
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
commit 64710db66461e5ccfaf7667971bc5e513b9ce547
Author: Timothy Arceri <timothy.arceri at collabora.com>
Date: Sun Nov 15 00:55:29 2015 +1100
glsl: encapsulate binding validation and setting
This change moves the binding layout handing code into an apply
function to be consistent with other helper functions in the ast
code, and to encapsulate the code so that when we introduce
compile time constants the code will be much cleaner.
One small downside is for unnamed interface blocks we will now
be revalidating the binding for each member its applied to.
However this seems a small sacrifice in order to have code which
is readable.
We also remove the incorrect comment in the named interface code
about propagating bindings to members which seems to have been
copied from the unnamed interface code.
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
commit db3c36aedfa2e92c2cf1c17a096c1b5e7cd51c42
Author: Timothy Arceri <timothy.arceri at collabora.com>
Date: Sat Nov 14 14:32:38 2015 +1100
glsl: move stream layout max validation
This validation is moved later so we can validate the
max value when compile time constant support is added in a
later patch.
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
commit 17e224e8ec9c190fb856a60a22d8e19b8f20837e
Author: Timothy Arceri <timothy.arceri at collabora.com>
Date: Fri Nov 13 18:47:55 2015 +1100
glsl: move stream layout qualifier validation
We are moving this out of the parser in preparation for compile
time constant support.
The reason a validation function is used rather than an apply
function like what is used with bindings is because glsl allows
streams to be defined on members of blocks even though they must
match the stream thats associated with the current block, this
means we need access to the value after validation to do this
comparision.
V2: Fix typo in comment (Emil)
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
commit efa34e4a1d09c6f140fba7ff339a989ea079e212
Author: Timothy Arceri <timothy.arceri at collabora.com>
Date: Sat Nov 14 13:09:46 2015 +1100
glsl: replace index layout min boundary check
Use new helper that will in a later patch allow for
compile time constants.
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
commit 1d87d6f9ca543631b2bc30ac8d82b6a23159fb55
Author: Timothy Arceri <timothy.arceri at collabora.com>
Date: Fri Nov 13 15:16:20 2015 +1100
glsl: remove duplicate validation for index layout qualifier
The minimum value for index is validated in apply_explicit_location()
and we want to remove validation from the parser so we can add
compile time constant support.
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
commit d1f23545a1416ffa476a3685e39380701cbfc4fd
Author: Timothy Arceri <timothy.arceri at collabora.com>
Date: Fri Nov 13 15:10:57 2015 +1100
glsl: move location layout qualifier validation
We are moving this out of the parser in preparation for compile
time constant support.
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
commit de8f0c9ab99ac6140f6560e776a42a22eeff6721
Author: Timothy Arceri <timothy.arceri at collabora.com>
Date: Sat Nov 14 12:22:49 2015 +1100
glsl: add process_qualifier_constant() helper
For now this just validates that a qualifier is inside its
minimum boundary, in a later patch we will expand it to
evaluate compile time constants.
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
commit f57285c8fc8c3128fc07a59bc0d56645f7e0ef18
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Tue Nov 10 01:08:28 2015 +0100
docs: mark GL_AMD_performance_monitor for nv50
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Acked-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit aede8ca9a79cafa7d019a16d38e6ee6bfc557100
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Tue Nov 10 01:40:00 2015 +0100
nv50: expose two groups of compute-related MP perf counters
This turns on GL_AMD_performance_monitor.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Acked-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 0288f92e7b0ce5f0d821f2d0ddef522a23776ecb
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Tue Oct 13 20:50:27 2015 -0700
i965/gen9: Support fast clears for 32b float
SKL supports the ability to do fast clears and resolves of 32b RGBA as both
integer and floats. This patch only enables float color clears because we
haven't yet enabled integer color clears, (HW support for that was added in
BDW).
v2: Remove LUMINANCE16F and INTENSITY16F special cases since they are now
handled by Neil's patch to disable MSAA fast clears.
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Neil Roberts <neil at linux.intel.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit 7c690da29c9eb78f1f61c0aed6582065b8ff9775
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Tue Oct 13 20:50:24 2015 -0700
Revert "i965/gen9: Enable rep clears on gen9"
This reverts commit 8a0c85b25853decb4a110b6d36d79c4f095d437b.
It's not a strict revert because I don't want to bring back the gen < 9 check at
this point in time.
Reviewed-by: Neil Roberts <neil at linux.intel.com>
commit f838e53c70e387232f89bd235bcee582894dc257
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Tue Oct 13 20:50:23 2015 -0700
Revert "i965/gen9: Disable MCS for 1x color surfaces"
This reverts commit dcd59a9e322edeea74187bcad65a8e56c0bfaaa2.
Reviewed-by: Neil Roberts <neil at linux.intel.com>
commit c4edc048c6f6877461a9d9dc07142640f380f340
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Tue Oct 13 20:50:22 2015 -0700
i965/meta/gen9: Individually fast clear color attachments
The impetus for this patch comes from a seemingly benign statement within the
spec (quoted within the patch).
It is very important for clearing multiple color buffer attachments and can be
observed in the following piglit tests:
spec/arb_framebuffer_object/fbo-drawbuffers-none glclear
spec/ext_framebuffer_multisample/blit-multiple-render-targets 0
v2: Doing the framebuffer binding only once (Chad)
Directly use the renderbuffers from the mt (Chad)
v3: Patch from Neil whose feedback I originally missed.
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Chad Versace <chad.versace at intel.com>
Reviewed-by: Neil Roberts <neil at linux.intel.com>
commit 6fa1130cd21926cdd4ae86aa12ee3f5c0bb5ba33
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Tue Oct 13 20:50:21 2015 -0700
i965/skl: skip fast clears for certain surface formats
Some of the information originally in this commit message is now in the patch
before this.
SKL adds compressible render targets and as a result mutates some of the
programming for fast clears and resolves. There is a new internal surface type
called the CCS. The old AUX_MCS bit becomes AUX_CCS_D. "Auxiliary Surfaces For
Sampled Tiled Resource".
The formats which are supported are defined in the table titled "Render Target
Surface Types [SKL+]". There is no PRM yet to reference. The previously
implemented helper function already does the right thing provided the table is
correct.
v2: Use better English in commit message (Matt)
s/compressable/compressible/ (Matt)
Don't compare bools to true (Matt)
Use the helper function and don't increase the context size - this is mostly
implemented in the patch just before this (Chad, Neil)
Remove an "invalid" assert (Chad)
Fix assertion to check num_samples > 1, instead of num_samples (Chad)
v3:
Use Matt's code as Requested-by: Chad. I didn't even look at it since Chad said
he was fine with that, and presumably Matt is fine with it.
v4: Use better quote from spec (Topi)
Cc: Chad Versace <chad.versace at intel.com>
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 9d94eeb8a42bc78ebd9bb249eff61618d54f92e4
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Tue Nov 10 12:16:54 2015 -0800
i965: Add lossless compression to surface format table
Background: Prior to Skylake and since Ivybridge Intel hardware has had the
ability to use a MCS (Multisample Control Surface) as auxiliary data in
"compression" operations on the surface. This reduces memory bandwidth. This
hardware was either used for MSAA compression, or fast clear operations. On
Gen8, a similar mechanism exists to allow the hiz buffer to be sampled from, and
therefore this feature is sometimes referred to more generally as "AUX buffers".
Skylake adds the ability to have the display engine directly source compressed
surfaces on top of the ability to sample from them. Inference dictates that
enabling this display features adds a restriction to the formats which could
actually be compressed. This is backed up by a blurb in the AUX_CCS_D section
from the RENDER_SURFACE_STATE: "In addition, if the surface is bound to the
sampling engine, Surface Format must be supported for Render Target Compression
for surfaces bound to the sampling engine." The current set of surfaces seems
to be a subset as compared to previous gens (see the next patch). Also, if I had
to guess I would guess that future gens add support for more surface formats. To
make handling this a bit easier to read, and more future proof, the support for
this is moved into the surface formats table.
Along with the modifications to the table, a helper function is also provided to
determine if a surface is CCS_E compatible. Because fast clears are currently
disabled on SKL, we can plumb the helper all the way through here, and not
actually have anything break.
v2:
- rename ccs to ccs_e; Requested-by: Chad
- rename lossless_compression to lossless_compression Requested-by: Chad
- change meaning of brw_losslessly_compressible_format Requested-by: Chad
- related changes to the code to reflect this.
- remove excess ccs (Chad)
v3:
- Commit message changes (Topi)
- Const some things which could be const (Topi)
Requested-by: Chad Versace <chad.versace at intel.com>
Requested-by: Neil Roberts <neil at linux.intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky at intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit d23aa634e0d45bbeda0f48033cc42656259ce0ef
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Tue Apr 14 14:57:51 2015 -0700
i965/skl: Add fast color clear infrastructure
Patch was originally called:
i965/skl: Enable fast color clears on SKL
Skylake introduces some differences in the way that fast clears are programmed
and in the restrictions for using fast clears. Since some of these are
non-obvious, and fast clears are currently disabled globally, we can enable the
simple stuff here and leave the weirder stuff and separately reviewable work.
Based on a patch originally from Kristian.
Note that within this patch the change in scaling factors could be achieved with
this hunk instead. I've opted to keep things more like how the docs describe it
however.
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -150,9 +150,13 @@ intel_get_non_msrt_mcs_alignment(struct brw_context *brw,
/* In release builds, fall through */
case I915_TILING_Y:
*width_px = 32 / mt->cpp;
- *height = 4;
+ if (brw->gen >= 9)
+ *height = 2;
+ else
+ *height = 4;
v2: Add braces for the multiline (Matt + Chad)
Comment updates (requested by Chad)
Modified commit message
Commit message from Chad explaining the MCS height change (Chad)
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Neil Roberts <neil at linux.intel.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit 2f7d2fd9979ce111af9c3a79b967d4efc029ab60
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Fri Nov 20 11:36:41 2015 -0800
docs: Add GL_EXT_shader_samples_identical to the release notes
Trivial
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
commit 8762570cc5382730afda9954c53dead5a56f398a
Author: Leo Liu <leo.liu at amd.com>
Date: Tue Nov 10 13:34:17 2015 -0500
radeon/vce: disable two pipe mode for stoney
Only one encoding pipe available for Stoney
Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
commit 99d92de5d0af8b926db20d4b2aecbe37b58c758c
Author: Leo Liu <leo.liu at amd.com>
Date: Tue Nov 3 13:33:03 2015 -0500
radeon/vce: add new firmware interface support
Add new interface to create and encode
Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
commit 8fdb54879963892cd9c3d0ca09172f2b3533043f
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Nov 20 15:12:56 2015 +0000
egl: don't forget to ship platform_x11_dri3.h into the tarball
Should have been a part of f35198badeb
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit ae6d6941f6656494adafb025475f83e02c6dd684
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Nov 20 14:59:27 2015 +0000
glsl: move builtin_type_macros.h into the correct list
Commit b9b40ef9b76 moved the file, but forgot to update the reference in
the makefile. Thus the out of tree build was busted :\
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit c45b4257c26b93043508e55c6a1aeb3a8b14eee9
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Nov 20 15:15:18 2015 +0000
automake: use static llvm for make distcheck
With llvm 3.7 semi-dropping the autoconf build, we rely on their cmake
build. With the latter of which annoyingly using another (busted?)
SONAME.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 0743e14aeef8f91bdd1fbd05f615458cf2b01d41
Author: Brian Paul <brianp at vmware.com>
Date: Fri Nov 20 09:34:11 2015 -0700
mesa: remove unused var in _mesa_PushDebugGroup()
Trivial.
commit 108013b8e5c593f9039335010672466ef6ac6010
Author: Brian Paul <brianp at vmware.com>
Date: Thu Nov 19 12:41:28 2015 -0700
mesa: whitespaces fixes in _mesa_one_time_init_extension_overrides()
Trivial.
commit 8a125afa6e88a3eeddba8c7fdc1a75c9b99d5489
Author: Nicolai Hähnle <nhaehnle at gmail.com>
Date: Wed Nov 18 18:40:22 2015 +0100
radeon: ensure that timing/profiling queries are suspended on flush
The queries_suspended_for_flush flag is redundant because suspended queries
are not removed from their respective linked list.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 6a14a39fab805b1471101afc6d6d1d843b5f16ec
Author: Nicolai Hähnle <nhaehnle at gmail.com>
Date: Thu Nov 12 15:09:21 2015 +0100
st/mesa: add support for batch driver queries to perfmon
v2 + v3: forgot null-pointer checks (spotted by Samuel Pitoiset)
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Tested-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
commit 424a614ff1105dcb5195178cb8f04ac46b8c0d8a
Author: Nicolai Hähnle <nhaehnle at gmail.com>
Date: Tue Nov 10 17:04:32 2015 +0100
gallium/hud: add support for batch queries
v2 + v3: be more defensive about allocations
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Tested-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
commit d61d4df02e568d314c4e763ba9b5bdd57aef98c5
Author: Nicolai Hähnle <nhaehnle at gmail.com>
Date: Tue Nov 10 14:06:59 2015 +0100
gallium: add the concept of batch queries
Some drivers (in particular radeon[si], but also freedreno judging from
a quick grep) may want to expose performance counters that cannot be
individually enabled or disabled.
Allow such drivers to mark driver-specific queries as requiring a new
type of batch query object that is used to start and stop a list of queries
simultaneously.
v3: adjust recently added nv50 queries
v2: documentation for create_batch_query
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Tested-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
commit c235300bfc3547d418f9a66555a5ee93a15666f9
Author: Nicolai Hähnle <nhaehnle at gmail.com>
Date: Thu Nov 12 12:30:23 2015 +0100
st/mesa: maintain active perfmon counters in an array
It is easy enough to pre-determine the required size, and arrays are
generally better behaved especially when they get large.
v2: make sure init_perf_monitor returns true when no counters are active
(spotted by Samuel Pitoiset)
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Tested-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
commit afa6121b4ef2d249004cff0bb40237c71c61946d
Author: Nicolai Hähnle <nhaehnle at gmail.com>
Date: Thu Nov 12 12:02:44 2015 +0100
st/mesa: use BITSET_FOREACH_SET to loop through active perfmon counters
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Tested-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
commit 0aea83dc4ad8826648be7b400553083e0aeac004
Author: Nicolai Hähnle <nhaehnle at gmail.com>
Date: Thu Nov 12 11:53:22 2015 +0100
st/mesa: store mapping from perfmon counter to query type
Previously, when a performance monitor was initialized, an inner loop through
all driver queries with string comparisons for each enabled performance
monitor counter was used. This hurts when a driver exposes lots of queries.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Tested-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
commit 4e1339691d3e04eb7e90d33ab5900ce1a40e628f
Author: Nicolai Hähnle <nhaehnle at gmail.com>
Date: Fri Nov 6 14:19:54 2015 +0100
st/mesa: map semantic driver query types to underlying type
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Tested-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
commit 050db20d37307b30b05abca368e865f15daf728c
Author: Nicolai Hähnle <nhaehnle at gmail.com>
Date: Tue Nov 10 14:41:52 2015 +0100
gallium/hud: remove unused field in query_info
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Tested-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
commit ddf27a3dd062c78ff49a69a1396be4de9c1b5d37
Author: Nicolai Hähnle <nhaehnle at gmail.com>
Date: Tue Nov 10 13:35:01 2015 +0100
gallium: remove pipe_driver_query_group_info field type
This was only used to implement an unnecessarily restrictive interpretation
of the spec of AMD_performance_monitor. The spec says
A performance monitor consists of a number of hardware and software
counters that can be sampled by the GPU and reported back to the
application.
I guess one could take this as a requirement that counters _must_ be sampled
by the GPU, but then why are they called _software_ counters? Besides,
there's not much reason _not_ to expose all counters that are available,
and this simplifies the code.
v3: add a missing change in the nouveau driver (thanks Samuel Pitoiset)
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Tested-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
commit 24dc0316b4d7b29e055f220b23cab7daf4698c0c
Author: Roland Scheidegger <sroland at vmware.com>
Date: Fri Nov 20 04:49:23 2015 +0100
gallivm: use sampler index 0 for texel fetches
texel fetches don't use any samplers. Previously we just set the same
number for both texture and sampler unit (as per "ordinary" gl style
sampling where the numbers are always the same) however this would trigger
some assertions checking that the sampler index isn't over PIPE_MAX_SAMPLERS
limit elsewhere with d3d10, so just set to 0.
(Fixing the assertion instead isn't really an option, the sampler isn't
really used but might still pass an out-of-bound pointer around and even
copy some things from it.)
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 9a93da4e83ee332367a0d6aa601cbcd7f59321b2
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Nov 19 19:17:04 2015 -0500
freedreno/a4xx: add BPTC support
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 8a94ba5e0cb738c6b1a817ea54afc5816d2bb596
Author: François Tigeot <ftigeot at wolfpond.org>
Date: Tue Nov 17 18:54:01 2015 +0100
xmlconfig: Add support for DragonFly
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 480ba46bcb44169cefb46a978c24e3f77d144df2
Author: Mauro Rossi <issor.oruam at gmail.com>
Date: Sat Nov 7 01:23:46 2015 +0100
android: export the path of glsl nir headers
The change is necessary to avoid building errors in glsl and i965
modules due to missing glsl_types.h header
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit b8547a50631649bf19fc29cb339bdb3992537607
Author: Boyan Ding <boyan.j.ding at gmail.com>
Date: Fri Nov 20 11:11:19 2015 +0000
mesa: re-enable KHR_debug for ES contexts
With the earlier issues resolved we can expose the extension.
Signed-off-by: Boyan Ding <boyan.j.ding at gmail.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit ab7294668cb245fbe8c925be6fd6f0242bdd6a0f
Author: Boyan Ding <boyan.j.ding at gmail.com>
Date: Sun Nov 8 17:56:40 2015 +0800
main: Don't restrict several KHR_debug enum to desktop GL
In preparation for supporting GL_KHR_debug in OpenGL ES
v2: add a missing hunk in _mesa_IsEnabled (Emil)
Signed-off-by: Boyan Ding <boyan.j.ding at gmail.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit af272368547600e1db87d4dd5d718e41ea9db6c0
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Nov 5 20:22:25 2015 +0000
mesa: use the correct string for the ES GL_KHR_debug functions
As defined in the spec
when implemented in an OpenGL ES context, all entry points defined
by this extension must have a "KHR" suffix.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 9108a785a0fc6bb47ca577d2e2bdcf3728fead43
Author: Gregory Hainaut <gregory.hainaut at gmail.com>
Date: Sun Oct 25 15:01:36 2015 +0100
glsl: avoid linker and user varying location to overlap
Current behavior on the interface matching:
layout (location = 0) out0; // Assigned to VARYING_SLOT_VAR0 by user
out1; // Assigned to VARYING_SLOT_VAR0 by the linker
New behavior on the interface matching:
layout (location = 0) out0; // Assigned to VARYING_SLOT_VAR0 by user
out1; // Assigned to VARYING_SLOT_VAR1 by the linker
v4:
* Fix variable name in assert
Signed-off-by: Gregory Hainaut <gregory.hainaut at gmail.com>
Reviewed-by: Timothy Arceri <timothy.arceri at collabora.com>
commit 3afb253e9ba5ea44cf7be34cc2c3e0e358d169d0
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Nov 6 23:39:01 2015 +0000
auxiliary/vl/dri2: coding style fixes
Rewrap long(ish) lines, add space between struct foo and *.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
commit b31f092bfb48118e671d0705c21b1c6f6f3bef84
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Nov 9 11:25:59 2015 +0000
auxiliary/vl/dri2: hide internal functions
Analogous to previous commit. While we're here prefix all functions
identically -> vl_dri2_foo
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
commit 4533c022f41ebcaa91f2c22c04824d647c8c9fec
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Nov 9 11:24:35 2015 +0000
auxiliary/vl/drm: hide internal functions
As of last commit everyone is using the vl_screen dispatch, thus we can
hide this function from the headers and make it static.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
commit abbfda60d8b5ff870c75073cd408551c25c6a0b5
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Nov 6 23:12:13 2015 +0000
st/vdpau: use the vl_screen dispatch
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
commit 4307155127fbd682d04fd23ce4aa80e7da2cb203
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Nov 6 23:02:14 2015 +0000
st/xvmc: use the vl_screen dispatch
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
commit 422356ed2f05ef0f5bcdac13899a529df5497357
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Nov 9 11:23:37 2015 +0000
st/va: use the vl_screen dispatch
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
commit 9eb109f4d3b3b145c544eb69ac21cb69e0a5e2be
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Nov 6 22:45:38 2015 +0000
st/omx: use the vl_screen dispatch
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
commit 32094979f70a5f532eb27eb41df4a0eadd2fd1a1
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Nov 6 22:40:34 2015 +0000
auxiliary/vl/dri2: setup the dispatch
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
commit 6150d8d4bd64151522615c417f1fe51bff1cdd5f
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Nov 9 11:34:48 2015 +0000
auxiliary/vl/drm: use a label for the error path
... just like every other place in gallium.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
commit d03d9ecafa6548c30e22e26b14bf552472a9f231
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Nov 9 11:18:14 2015 +0000
auxiliary/vl/drm: setup the dispatch
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
commit 6b152ee7b6121f661cdcfdfafa547457dc27b921
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Nov 6 22:34:01 2015 +0000
auxiliary/vl: add dispatch table
As mentioned previously, it will allow us to use different vl backend in
a generic way from either video state-tracker.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
commit 2bd9116b8249fdb1711335711f8daef5f68752a6
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Nov 9 11:17:07 2015 +0000
auxiliary/vl: rename vl_screen_create to vl_dri2_screen_create
In a preparation of having proper multi-platform/backend handling in VL.
With follow up commits we'll introduce a dispatch within vl_screen
similar to the one in pipe_screen. This way any VL state-tracker can
operate seamlessly, considering the backend/platform is properly setup.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
commit c31218cdb342482064345d78ada691521c367446
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Nov 9 11:14:56 2015 +0000
st/va: trivial cleanup
Drop the temporary variable and fold the two conditional.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
commit a8f45e0161c13fbda6f3b846219a3eb1d44b25de
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Nov 9 11:03:01 2015 +0000
st/omx: straighten get/put_screen
The current code is busted in a number of ways.
- initially checks for omx_display (rather than omx_screen), which may
or may not be around.
- blindly feeds the empty env variable string to loader_open_device()
- reads the env variable every time get_screen is called
- the latter manifests into memory leaks, and other issues as one sets
the variable between two get_screen calls.
Additionally it cleans up a couple of extra bits
- drops unneeded set/check of omx_display.
- make the teardown (put_screen) order was not symmetrical to the setup
(get_screen)
v2: Drop the "is empty string" check (Leo)
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Leo Liu <leo.liu at amd.com>
commit 7157085140a502a182ff0e23d30bd8e421212c42
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Thu Nov 19 15:36:03 2015 +0000
automake: loader: don't create an empty dri3 helper
Seems that creating an empty one does not fair too well with MacOSX's
ar. Considering that all the users of the helper include it only when
needed, let's reshuffle the makefile.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92985
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
Tested-by: Vinson Lee <vlee at freedesktop.org>
Tested-by: Kai Wasserbäch <kai at dev.carbon-project.org>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 115f1798525899c23249b09aa63113f84328186d
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Thu Nov 19 15:34:20 2015 +0000
automake: loader: honour the XCB_DRI3 cflags
Without this the compilation will fail, as the headers are installed in
a non-default location.
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
Tested-by: Kai Wasserbäch <kai at dev.carbon-project.org>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 166314dd8829c80f1df5a3b7070b6c86cccf1b9e
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Thu Nov 19 15:50:50 2015 +0000
automake: egl: add symbols test
Should help us catch issues where we expose any extra symbols by
mistake. Just like the ones fixes with previous commit.
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
Tested-by: Kai Wasserbäch <kai at dev.carbon-project.org>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit 5a79e0a8e37ea10cfa6fc39f4fbe315f9620fe52
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Thu Nov 19 15:31:06 2015 +0000
automake: loader: rework the CPPFLAGS
Rather than duplicating things, just use the generic AM_CPPFLAGS. This
has the fortunate side-effect of adding VISIBILITY_CFLAGS for the dri3
helper. The latter of which was erroneously exposing some internal
symbols.
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
Reported-by: Kai Wasserbäch <kai at dev.carbon-project.org>
Tested-by: Kai Wasserbäch <kai at dev.carbon-project.org>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 99840eb983f74cd447546f7205c8c9f505ef82c8
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Nov 17 17:57:08 2015 -0800
i965: Enable EXT_shader_samples_identical
On the vec4 backend, textureSamplesIdentical() will always return
false. There are currently no test cases for the vec4 backend, so we
don't have much confidence in any implementation. We also don't think
anyone is likely to miss it.
v2: Handle immediate value for MCS smarter. Rebase on changes to
nir_texop_sampels_identical (missing second parameter). Suggested by
Jason.
v3: Add Neil's code to handle 16x MSAA in the FS. Also rebase on top of
f9a9ba5e. Stub out the vec4 implementation.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Signed-off-by: Neil Roberts <neil at linux.intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com> [v2]
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz> [v2]
commit 84b6c64efc52948da8db89b8d92d5e744e6cfc95
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Nov 17 19:31:39 2015 -0800
i965/vec4: Handle nir_tex_src_ms_index more like the scalar
v2: Rebase on top of f9a9ba5e.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit 457bb290efc162ea3c7c51a820ab7cf88a4efb8d
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Nov 17 17:09:09 2015 -0800
nir: Add nir_texop_samples_identical opcode
This is the NIR analog to GLSL IR ir_samples_identical.
v2: Don't add the second nir_tex_src_ms_index parameter. Suggested by
Ken and Jason.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit 06c56f443aa1850b2651df3636c42a8740cff847
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Nov 17 16:59:40 2015 -0800
glsl: Add textureSamplesIdenticalEXT built-in functions
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit 8343583557fbbf0e04ce8e834a71f00b219232ce
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Nov 17 16:54:31 2015 -0800
glsl: Add ir_samples_identical opcode
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit ef54434c52385bea59d47dbfcedc6845f33fb231
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Nov 17 15:36:15 2015 -0800
glsl: Extension tracking for EXT_shader_samples_indentical
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit ff59700d29bb5db0010c3f7508336bf66a03d11f
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Nov 17 15:32:10 2015 -0800
mesa: Extension tracking for EXT_shader_samples_indentical
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit b1b9f68d4cc29130d0cb6219b02e13c67c0c7f10
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Nov 17 15:26:27 2015 -0800
Import current draft of EXT_shader_samples_identical spec
v2: Add Neil to the list of contributors. I meant to do that before,
but Matt reminded me.
v3: Fix typos noticed by Nicolai.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit acca6c65d3c793885b343aad17cbdbad7fbe1830
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Nov 5 10:23:48 2015 -0500
nir: add nir_ssa_for_alu_src()
Using something like:
numer = nir_ssa_for_src(bld, alu->src[0].src,
nir_ssa_alu_instr_src_components(alu, 0));
for alu src's with swizzle, like:
vec1 ssa_10 = intrinsic load_uniform () () (0, 0)
vec2 ssa_11 = intrinsic load_uniform () () (1, 0)
vec2 ssa_2 = udiv ssa_10.xx, ssa_11
ends up turning into something like:
vec1 ssa_10 = intrinsic load_uniform () () (0, 0)
vec2 ssa_11 = intrinsic load_uniform () () (1, 0)
vec2 ssa_13 = imov ssa_10
...
because nir_ssa_for_src() ignore's the original nir_alu_src's swizzle.
Instead for alu instructions, nir_src_for_alu_src() should be used to
ensure the original alu src's swizzle doesn't get lost in translation:
vec1 ssa_10 = intrinsic load_uniform () () (0, 0)
vec2 ssa_11 = intrinsic load_uniform () () (1, 0)
vec2 ssa_13 = imov ssa_10.xx
...
v2: check for abs/neg, and re-use existing nir_alu_src
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit c73f40c4731235153e29222eee8e12241166094a
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Nov 4 16:10:52 2015 -0500
nir: fix missing increments of num_inputs/num_outputs
Note: not quite perfect, we should use type_size vfunc (in
compiler_options or nir_shader?) to determine how much we
increment num_inputs/outputs/uniforms. But we don't have
that yet, so let's at least fix things for the existing
users of these passes.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Acked-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit fec9367deb51003ccb74aca796e759502cfedfeb
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Nov 4 10:05:32 2015 -0500
nir/print: show # of uniforms/inputs/outputs
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 01e94d8d5d32d0debf35533180bf4633a139dd63
Author: Rob Clark <robclark at freedesktop.org>
Date: Mon Oct 26 13:29:45 2015 -0400
nir/print: show shader name/label if set
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 006e4f070f08ff1e1731863940bc51de9e97b865
Author: Rob Clark <robdclark at gmail.com>
Date: Mon Oct 19 11:57:51 2015 -0400
nir: add nir_var_all enum
Otherwise, passing -1 gets you:
error: invalid conversion from 'int' to 'nir_variable_mode' [-fpermissive]
Signed-off-by: Rob Clark <robdclark at gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 769b3ab6c5111f50502f9df0e8930c8d13f475c7
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Nov 19 01:37:14 2015 -0500
freedreno/a4xx: fix 5_5_5_1 texture sampler format
This fixes teximage-colors, fbo-generatemipmap-formats, and probably
others (in relation to the RGB5 formats, others still fail).
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org
commit a05e5491c367cdb7db93a2cc47a839329b90e513
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Nov 19 00:32:39 2015 -0500
freedreno/a4xx: add depth clamp and halfz clip
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit b17a405609156dc554d2d7c148c02e24bfdecaca
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Nov 19 00:06:46 2015 -0500
freedreno/a4xx: allow seamless cubemap filtering to be enabled per-texture
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 0a4462ad6ee921ed805ad51e330b819b95ee90d6
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Nov 18 23:54:25 2015 -0500
freedreno/a4xx: support lod_bias
The lower layers assume that we support this, and it's been core since
GL 1.4. This fixes a slew of piglit tests, especially around
tex-miplevel-selection.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org
commit 0cfc1304bece9cbc17a39b009956b2830c6fd2f5
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Thu Nov 19 09:51:03 2015 +0100
nv50: allow using inline vertex data submit when gl_VertexID is used
The hardware can actually generates vertexid when vertices come from
a client-side buffer like when glDrawElements is used.
This doesn't fix (or break) any piglit tests but it improves the
previous attempt of Ilia (c830d19 "nv50: avoid using inline vertex
data submit when gl_VertexID is used")
The only disadvantage is that only works on G84+, but we don't really
care of that weird and old NV50 chipset.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 9e40a621c177d595ffd1cf094246219e7067d768
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Thu Nov 19 09:51:02 2015 +0100
nv50: add NV84_3D macro
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit a5b3115f0a9ede775b332b1a669de570668e871c
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Nov 2 12:25:24 2015 -0800
i965: Drop IMM fs_reg/src_reg -> brw_reg conversions.
The previous two commits make this unnecessary.
Reviewed-by: Emil Velikov <emil.velikov at collabora.co.uk>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit f9a9ba5eac2f1934bd7fecc92cd309f22411164b
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Nov 2 12:12:44 2015 -0800
i965/vec4: Replace src_reg(imm) constructors with brw_imm_*().
Cuts 1.5k of .text.
Reviewed-by: Emil Velikov <emil.velikov at collabora.co.uk>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 9b978046eb1d1657060365e8dcde4aad41b50af9
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Nov 2 11:28:35 2015 -0800
i965/fs: Use brw_imm_uw().
W/UW immediates are 16-bits, but those 16-bits must be replicated
in the high 16-bits of the 32-bit field.
Remove the useless W/UW immediate saturating code, since we'll now be
using the appropriate immediate (and W/UW immediates in the IR can now
no longer be larger than 16-bits).
Reviewed-by: Emil Velikov <emil.velikov at collabora.co.uk>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 3ccc41ecfc5e9345a1c291748d8840984f7413ae
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Nov 2 11:26:16 2015 -0800
i965/fs: Replace fs_reg(imm) constructors with brw_imm_*().
Cuts 10k of .text, of which only 776 bytes are the fs_reg constructor
implementations themselves.
text data bss dec hex filename
5204535 214112 27784 5446431 531b1f i965_dri.so before
5193977 214112 27784 5435873 52f1e1 i965_dri.so after
Reviewed-by: Emil Velikov <emil.velikov at collabora.co.uk>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit c15a407eb49d3b26bdbf039816636adb184c276a
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Nov 2 10:29:45 2015 -0800
i965: Make brw_imm_vf4() take 8-bit restricted floats.
This partially reverts commit bbf8239f92ecd79431dfa41402e1c85318e7267f.
I didn't like that commit to begin with -- computing things at compile
time is fine -- but for purposes of verifying that the resulting values
are correct, looking up 0x00 and 0x30 in a table is a lot better than
evaluating a recursive function.
Anyway, by making brw_imm_vf4() take the actual 8-bit restricted floats
directly (instead of only integral values that would be converted to
restricted float), we can use this function as a replacement for the
vector float src_reg/fs_reg constructors.
brw_float_to_vf() is not currently an inline function, so it will not be
evaluated at compile time. I'll address that in a follow-up patch.
Reviewed-by: Emil Velikov <emil.velikov at collabora.co.uk>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit e8c5ef3ecaafae0ad6c300019c489401a9af714c
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Wed Nov 18 15:01:44 2015 -0800
mesa: Add test for sorted extension table
Enable developers to know if the table's alphabetical sorting
is maintained or lost.
v2: Move "*" next to pointer name (Matt)
Include extensions_table.h instead of extensions.h (Ian)
Remove extra " *" in comment (Ian)
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit f030227f4643ae7e832545dfa3c3db472e00ab65
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Wed Nov 18 15:01:43 2015 -0800
mesa/extensions: Sort the extension table alphabetically
Make it easier to determine where to add new extensions.
Performed with the vim sort command.
v2: Insert newline after last #define (Matt)
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit bcda79676a7a51e433f0f044f43b61405ebcc9e5
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Nov 19 12:25:53 2015 -0500
docs: GL3.1 for a3xx and a4xx
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 0ec218d167a2e5cef993ba7863608c7b40f4d649
Author: Ryan Houdek <Sonicadvance1 at gmail.com>
Date: Thu Nov 5 11:07:08 2015 -0600
mesa: enable EXT_blend_func_extended if the driver supports the ARB version
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit f7c23f225f37f96bf711ccc6b2a6315b64582b81
Author: Ryan Houdek <Sonicadvance1 at gmail.com>
Date: Thu Nov 5 11:05:58 2015 -0600
mesa: allow MAX_DUAL_SOURCE_DRAW_BUFFERS to be available to ES
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 4b549f0d8ce425e96f57f4014edcfe7bac36920c
Author: Ryan Houdek <Sonicadvance1 at gmail.com>
Date: Thu Nov 5 11:05:17 2015 -0600
mesa: enable usage of blend_func_extended blend factors in GLES2
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 33ddc8e865e67f3dabcd1b598f4e978be6c7be6f
Author: Ryan Houdek <Sonicadvance1 at gmail.com>
Date: Thu Nov 5 11:03:44 2015 -0600
glsl: add a parse check to check for the index layout qualifier
This can only be used if EXT_blend_func_extended is enabled
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit ef9e6d1ec8389f800d22c0dd091efb30f189fa45
Author: Ryan Houdek <Sonicadvance1 at gmail.com>
Date: Thu Nov 5 20:44:03 2015 -0600
glsl: add GL_EXT_blend_func_extended preprocessor define
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 1d1d02f2ac69475da112a6aadfa7c161b13ff4da
Author: Ryan Houdek <Sonicadvance1 at gmail.com>
Date: Thu Nov 5 10:59:32 2015 -0600
glsl: add support for EXT_blend_func_extended builtins
gl_MaxDualSourceDrawBuffersEXT - Maximum dual-source draw buffers supported
For ESSL 1.0, it provides two builtins since you can't have user-defined
color output variables:
gl_SecondaryFragColorEXT
gl_SecondaryFragDataEXT[MaxDSDrawBuffers]
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit ceecb0876f1479661e561520c7e3561fd051720a
Author: Ryan Houdek <Sonicadvance1 at gmail.com>
Date: Thu Nov 5 10:53:40 2015 -0600
glsl: add EXT_blend_func_extended parser enables
This adds a state for the maximum dual source draw variables available
and the variable for determining if the extension has been enabled
in the program shaders.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 625414f78c4ece1c5b24a31afad2efa4ea504933
Author: Ryan Houdek <Sonicadvance1 at gmail.com>
Date: Thu Nov 5 10:52:35 2015 -0600
glapi: add EXT_blend_func_extended XML definitions
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 15f8dc7b234fa79c9dca69b0b49afead463293e3
Author: Brian Paul <brianp at vmware.com>
Date: Wed Nov 18 09:25:48 2015 -0700
os: check for GALLIUM_PROCESS_NAME to override os_get_process_name()
Useful for debugging and for glretrace.
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
Reviewed-by: José Fonseca <jfonseca at vmware.com>
commit f1ba0a5ea0faf331be9fa28fd6d43a3ff061b735
Author: Connor Abbott <connor.w.abbott at intel.com>
Date: Fri Aug 14 11:58:45 2015 -0700
glsl: fix ir_constant::equals() for doubles
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
commit 84ed3819a42042757a32cae4260c26c4fb3b673c
Author: Connor Abbott <connor.w.abbott at intel.com>
Date: Fri Aug 14 11:58:07 2015 -0700
glsl: fix isinf() for doubles
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
commit 7820b2c071ec974d824c9b6dc3a0dd0ad1b77444
Author: Connor Abbott <connor.w.abbott at intel.com>
Date: Tue Aug 4 14:04:34 2015 -0700
nir: fix constant folding of bfi
Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
commit 1cfffb95ebf49a8342d4799e68ecc0009300cb2f
Author: Brian Paul <brianp at vmware.com>
Date: Wed Nov 18 17:08:39 2015 -0700
hud: fix Windows build break
Protect signal-related code with PIPE_OS_UNIX test.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 2f554761536bbfd0d8ec22e807c18bd6df0f22b8
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Nov 17 18:35:00 2015 -0800
glsl: Fix off-by-one error in array size check assertion
Apparently, this has been a bug since 2010 (c30f6e5d).
Also use ARRAY_SIZE instead of open coding it.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Cc: mesa-stable at lists.freedesktop.org
commit 0aded03046a5dd73bedece767dea8559463a7a57
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Nov 17 15:27:59 2015 -0800
mesa: Don't expose GL_EXT_shader_integer_mix in GLES 1.x
There are no shaders, so it doesn't even make sense to expose the
extension.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Cc: Nanley Chery <nanley.g.chery at intel.com>
commit 37c2cfa6bc6743e2b9d30cf119353d5e2e4bb063
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Nov 17 16:58:02 2015 -0800
glsl: Silence unused parameter warnings
builtin_functions.cpp:5289:52: warning: unused parameter 'num_arguments' [-Wunused-parameter]
unsigned num_arguments,
^
builtin_functions.cpp:5290:52: warning: unused parameter 'flags' [-Wunused-parameter]
unsigned flags)
^
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit c82498c4daf1cfdee065011a10ee4345ae67ef3b
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Nov 17 16:25:06 2015 -0800
glsl: Silence ignored qualifier warning
I think the intention was to mark the "this" parameter as const, but
const goes on the other end to do that.
In file included from glsl_symbol_table.cpp:26:0:
ast.h:339:35: warning: type qualifiers ignored on function return type [-Wignored-qualifiers]
const bool is_single_dimension()
^
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Timothy Arceri <timothy.arceri at collabora.com>
commit fc19a0d2e422ea8e45bc5440a91f858f5f345884
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Nov 7 18:58:59 2015 -0800
i965: Allow indirect GS input indexing in the scalar backend.
This allows arbitrary non-constant indices on GS input arrays,
both for the vertex index, and any array offsets beyond that.
All indirects are handled via the pull model. We could potentially
handle indirect addressing of pushed data as well, but it would add
additional code complexity, and we usually have to pull inputs anyway
due to the sheer volume of input data. Plus, marking pushed inputs
as live due to indirect addressing could exacerbate register pressure
problems pretty badly. We'd need to be careful.
v2: Use updated MOV_INDIRECT opcode.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 09d610796c03ae5a238b999ace5ccc2d3effd700
Author: Jimmy Berry <jimmy at boombatower.com>
Date: Tue Nov 3 23:24:47 2015 -0600
gallium/hud: document GALLIUM_HUD_PERIOD in envvars.html.
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit 56a1c10bb8cc957caa9ebc3723b4692a522a02f5
Author: Jimmy Berry <jimmy at boombatower.com>
Date: Mon Nov 9 23:20:37 2015 -0600
gallium/hud: control visibility at startup and runtime.
- env GALLIUM_HUD_VISIBLE: control default visibility
- env GALLIUM_HUD_SIGNAL_TOGGLE: toggle visibility via signal
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit 0bee3acc2a303b4cbbac0f6f54ffc8be79bc7470
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Nov 16 11:48:05 2015 -0800
i965/nir: Add hooks for testing nir_shader_clone
This commit adds code for testing nir_shader_clone by running it after each
and every optimization pass and throwing away the old shader. Testing
nir_shader_clone is hidden behind a new INTEL_CLONE_NIR environment
variable.
Reviewed-by: Rob Clark <robclark at freedesktop.org>
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
commit 9fbd390dd4b60746c2ce60fb20c61c45c0e8a022
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Nov 11 08:31:29 2015 -0800
nir: Add support for cloning shaders
This commit is heavily based on one by Rob Clark <robdclark at gmail.com> but
reworked to re-use nir_create functions and do less hashing.
Signed-off-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Rob Clark <robclark at freedesktop.org>
commit 9ff71b649b4b3808a9e17ce69743c6037fd6603c
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Nov 3 00:31:22 2015 -0800
i965/nir: Validate that NIR passes call nir_metadata_preserve().
Failing to call nir_metadata_preserve() can have nasty consequences:
some pass breaks dominance information, but leaves it marked as valid,
causing some subsequent pass to go haywire and probably crash.
This pass adds a simple validation mechanism to ensure passes handle
this properly. We add a new bogus metadata flag that isn't used for
anything in particular, set it before each pass, and ensure it *isn't*
still set after the pass. nir_metadata_preserve will reset the flag,
so correct passes will work, and bad passes will assert fail.
(I would have made these functions static inline, but nir.h is included
in C++, so we can't bit-or enums without lots of casting...)
Thanks to Dylan Baker for the idea.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 7bc097899924f40140981567c7bb52297dd801f2
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Nov 3 00:31:15 2015 -0800
i965/nir: Add OPT() and OPT_V() macros for invoking NIR passes.
OPT() is the normal macro for passes that return booleans, while OPT_V()
is a variant that works for passes that don't properly report progress.
(Such passes should be fixed to return a boolean, eventually.)
These macros take care of calling nir_validate_shader() and setting
progress appropriately. In the future, it would be easy to add shader
dumping similar to INTEL_DEBUG=optimizer by extending the macro.
v2 (Jason Ekstrand):
- Fix an unused variable warning
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit d27ae2cf8cd548fe822ae9bcf11ead1dadfed744
Author: Rob Clark <robclark at freedesktop.org>
Date: Fri Nov 6 11:35:21 2015 -0500
nir: add array length field
This will simplify things somewhat in clone.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 624ec66653e2ce0abc6f4021111cf067b70741c1
Author: Rob Clark <robclark at freedesktop.org>
Date: Fri Nov 6 11:35:20 2015 -0500
nir: remove nir_variable::max_ifc_array_access
No users.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 4671c13852f3bb6341e4a6d4030948399e711e56
Author: Rob Clark <robclark at freedesktop.org>
Date: Tue Nov 17 12:35:09 2015 -0500
freedreno/a4xx: add fake RGTC support (required for GL3)
The a4xx bits corresponding to 'freedreno/a3xx: add fake RGTC support
(required for GL3)'
TODO some more r/e.. maybe we get lucky and hw supports some of this
directly? For now this will help us enable gl3.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 2379cc9fe03911133037616fd1d3576c5acc3a96
Author: Rob Clark <robclark at freedesktop.org>
Date: Tue Nov 17 11:42:53 2015 -0500
freedreno/a4xx: add compressed texture formats
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit fadd39442b2892821cdd4923ea511da881bfd02a
Author: Rob Clark <robclark at freedesktop.org>
Date: Tue Nov 17 11:42:34 2015 -0500
freedreno: update generated headers
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 4607b2b9b64e5486e636d300d89ee3712e2f7550
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Nov 8 00:28:34 2015 -0500
freedreno: expose GLSL 140 and fake MSAA for GL3.0/3.1 support
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 9c409c8df3db09c2922a8f9a0376ee91b2a6837c
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Sep 17 01:43:36 2015 -0400
freedreno/a3xx: fix texture buffers, enable offsets
The main issue is that the current logic looked into cso->u.tex, which
is the wrong side of the union to look into for texture buffers. While I
was at it, it was easy enough to add the logic to handle offsets
(first_element).
- reduce texture buffer size limit (determined experimentally)
- don't look at first/last levels, instead look at first/last element
- include the first element offset
- set offset alignment to 16 (determined experimentally)
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit d69e557f2a2c39888d83c7b52244412ee2a5594e
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Nov 7 23:20:31 2015 -0500
freedreno: add support for conditional rendering, required for GL3.0
A smarter implementation would make it possible to attach this to emit
state for the BY_REGION versions to avoid breaking the tiling. But this
is a start.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 059da344ec17853bb503a7e4afa229c2e2a98c83
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Nov 7 22:13:16 2015 -0500
freedreno/a3xx: add fake RGTC support (required for GL3)
Also throw in LATC while we're at it (same exact format). This could be
made more efficient by keeping a shadow compressed texture to use for
returning at map time. However... it's not worth it for now...
presumably compressed textures are not updated often.
Lastly fix up Z32S8 transfers to non-0 layers.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 84d087aea29821a029aeefe76386d487e72d7287
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Nov 7 19:32:32 2015 -0500
freedreno/a3xx: add missing formats to enable ARB_vertex_type_2_10_10_10_rev
The previously RE'd formats were from an ES driver implementing
OES_vertex_type_10_10_10_2 and thus backwards. A future change could add
the 2_10_10_10 support.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 8106fec74c4d8548974fcf64e052a6bac07e926f
Author: Rob Clark <robclark at freedesktop.org>
Date: Mon Nov 16 15:07:29 2015 -0500
freedreno/a3xx+a4xx: fix for stk binning pass hang
We'd end up in a state where shader uses no inputs, yet num_elements is
greater than zero. Triggered by a TF vertex shader which did:
gl_Position = vec4(0.0, 0.0, 0.0, 0.0);
resulting in a binning pass variant with no inputs.
Includes equiv fix in a4xx, even though we don't have binning-pass
enabled yet on a4xx.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit b24c9a8aeef6fbad06d7982aee8bdb55679289f3
Author: Rob Clark <robclark at freedesktop.org>
Date: Mon Nov 16 14:58:50 2015 -0500
freedreno/a3xx+a4xx: fix GL_POINTS lockup w/ GLES
point_size_per_vertex is always TRUE for GLES, causing us to configure
the hw as if gl_PointSize was written, even if it was not. Which makes
for grumpy hw.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit b40e144a665142957a7ae027238e61fd01a27ebc
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Nov 8 13:43:07 2015 -0500
nir: fix typo in idiv lowering, causing large-udiv-udiv failures
In nv50, and in the python script that Rob circulated, we do:
bld.mkCmp(OP_SET, CC_GE, TYPE_U32, (s = bld.getSSA()), TYPE_U32, m, b);
Do the same in the nir div lowering pass. This fixes the large-udiv-udiv
piglit tests on freedreno.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 4581f8428e0e1d2f6787d0765823c7883bd2cfcd
Author: Oded Gabbay <oded.gabbay at gmail.com>
Date: Tue Nov 17 16:16:46 2015 +0200
llvmpipe: disable VSX in ppc due to LLVM PPC bug
This patch disables the use of VSX instructions, as they cause some
piglit tests to fail
For more details, see: https://llvm.org/bugs/show_bug.cgi?id=25503#c7
With this patch, ppc64le reaches parity with x86-64 as far as piglit test
suite is concerned.
v2:
- Added check that we have at least LLVM 3.4
- Added the LLVM bug URL as a comment in the code
v3:
- Only disable VSX if Altivec is supported, because if Altivec support
is missing, then VSX support doesn't exist anyway.
- Change original patch description.
Signed-off-by: Oded Gabbay <oded.gabbay at gmail.com>
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit 8e68113c1a78c48f26e820f4beb2dda9e4b99f32
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Nov 18 14:23:35 2015 -0500
nvc0/ir: actually emit AFETCH on kepler
Looks like this was forgotten in the commit which added the AFETCH
logic.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org
commit 2631bfd62c899dfa2a7095685c4f6874d5e9704d
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Nov 17 14:56:32 2015 -0800
nir: Store the size of the TCS output patch in nir_shader_info.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit b196f1fff31f1528afa84590926c2935d9b0c255
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Nov 11 19:24:01 2015 -0800
i965: Add enums for 3DSTATE_TE field values.
3DSTATE_TE has partitioning, output topology, and domain fields,
each of which has several enumerated values. We'll also need to
switch on the domain, so enums (rather than #defines) seem like a
natural fit.
I chose to put these in brw_compiler.h because they'll be stored
in struct brw_tes_prog_data, which will live there.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 72e232374eda780a5dcd374b55d203d0e2a6d02b
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Fri Nov 13 16:09:37 2015 -0800
meta/generate_mipmap: Don't leak the framebuffer object
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
commit 1a48326a84e3a5df0c3e6c2c3bd59992df5097ab
Author: Brian Paul <brianp at vmware.com>
Date: Mon Nov 16 10:41:20 2015 -0700
svga: use more VGPU10 formats
We always want to prefer the VGPU10 formats over the VGPU9 ones when
we have VGPU10 support.
Original patch by Jose and updated by Brian.
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
Reviewed-by: José Fonseca <jfonseca at vmware.com>
commit 1a90e3e1e3ee70504f2ce57462fb592b448269be
Author: Brian Paul <brianp at vmware.com>
Date: Mon Nov 16 10:31:46 2015 -0700
svga: add/use new svga_sampler_format() function
This is important for the case of sampling from a depth texture. In
that case, we need to sample the texture as if it were a single-channel
color texture. For other/color formats, we can use the format as-is.
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
Reviewed-by: José Fonseca <jfonseca at vmware.com>
commit 27ce75ed12c814b0d4b96c32f6e89ba308910e26
Author: Nicolai Hähnle <nhaehnle at gmail.com>
Date: Fri Nov 13 00:38:36 2015 +0100
radeon: count cs dwords separately for query begin and end
This will be important for perfcounter queries.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit ffd01b7781eebd207c16a9df5ea2858f6f5be544
Author: Nicolai Hähnle <nhaehnle at gmail.com>
Date: Wed Nov 18 12:06:58 2015 +0100
radeon: expose r600_query_hw functions for reuse
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
[Fixed a rebase conflict and re-tested before pushing.]
commit 50f0f938e3a577647fdfb6bdbb4ad3da252aa791
Author: Nicolai Hähnle <nhaehnle at gmail.com>
Date: Fri Nov 13 00:27:34 2015 +0100
radeon: implement r600_query_hw_get_result via function pointers
We will need the clear_result override for the batch query implementation.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit c207c55fc08a1bf3dd40e79b3aaec34afbee2e55
Author: Nicolai Hähnle <nhaehnle at gmail.com>
Date: Wed Nov 18 12:05:11 2015 +0100
radeon: split hw query buffer handling from cs emit
The idea here is that driver queries implemented outside of common code
will use the same query buffer handling with different logic for starting
and stopping the corresponding counters.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
[Fixed a rebase conflict and re-tested before pushing.]
commit 1d10b3d01e8af58f3c14bf39af8b592860ab36aa
Author: Nicolai Hähnle <nhaehnle at gmail.com>
Date: Wed Nov 18 11:59:21 2015 +0100
radeon: convert hardware queries to the new style
Move r600_query and r600_query_hw into the header because we will want to
reuse the buffer handling and suspend/resume logic outside of the common
radeon code.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
[Fixed a rebase conflict and re-tested before pushing.]
commit 019106760d16a7badf2d3a7034b4281b6cf2c27f
Author: Nicolai Hähnle <nhaehnle at gmail.com>
Date: Wed Nov 18 11:55:09 2015 +0100
radeon: convert software queries to the new style
Software queries are all queries that do not require suspend/resume
and explicit handling of result buffers.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
[Fixed a rebase conflict and re-tested before pushing.]
commit 829a9808a98f5b53576c6c8bc5da53182d58e1e8
Author: Nicolai Hähnle <nhaehnle at gmail.com>
Date: Wed Nov 18 11:40:00 2015 +0100
radeon: add query handler function pointers
The goal here is to be able to move the implementation details of hardware-
specific queries (in particular, performance counters) out of the common code.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
[Fixed a rebase conflict and re-tested before pushing.]
commit 50cab4788d664769ffc8547d8e759e92d14cf5e6
Author: Nicolai Hähnle <nhaehnle at gmail.com>
Date: Thu Nov 12 22:04:50 2015 +0100
radeon: move R600_QUERY_* constants into a new query header file
More query-related structures will have to be moved into their own
header file to support hardware-specific performance counters.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit c56e83e518cf5aa852c746f49023256e2c092ae2
Author: Nicolai Hähnle <nhaehnle at gmail.com>
Date: Tue Nov 10 20:42:02 2015 +0100
radeon: cleanup driver query list
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit e117e74baf0e0482fd4c3c2fa412e7168889d286
Author: Nicolai Hähnle <nhaehnle at gmail.com>
Date: Fri Nov 6 12:52:51 2015 +0100
radeon: move get_driver_query_info to r600_query.c
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 5dfb4dbc0583d2593e36f7eb27c77b81680db848
Author: Neil Roberts <neil at linux.intel.com>
Date: Mon Nov 16 14:03:11 2015 +0100
i965: Prevent fast clears for MSRTs on SKL
There are currently a bunch of formats that behave strangely when
sampling the cleared color from the MCS buffer on SKL. They seem to
mostly be formats that don't have an alpha component, although it's
not all of them, and we haven't yet found anything in the specs which
would explain this. For now to be on the safe side this patch just
prevents fast clears for MSRTs on SKL altogether so that when fast
clears are eventually enabled it will only be for single-sampled
surfaces. The assumption is that clears are probably more likely to be
used in single-sampled applications anyway so we can at least get them
working and we can enable MSRTs later once we understand the problem
better.
This patch should have no functional effect other than perhaps
receiving fewer perf_debug messages on SKL+.
v2: Improve the commit message to avoid saying the patch disables fast
clears because it will be merged before fast clears are enabled
for any surfaces so it doesn't actually disable anything.
Reviewed-by: Ben Widawsky <benjamin.widawsky at intel.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit dd05ffebfcb5d2e7ca44def1907aa2fbadd5e19d
Author: Eric Anholt <eric at anholt.net>
Date: Wed Nov 11 17:09:40 2015 -0800
vc4: Don't bother lowering uniforms when the same value is used twice.
DEQP likes to do math on uniforms, and the "fmaxabs dst, uni, uni" to get
the absolute value would get lowered. The lowering doesn't bother to try
to restrict the lifetime of the lowered uniforms, so we'd end up register
allocation failng due to this on 5 of the tests (More tests still fail in
RA, which look like we'll need to reduce lowered uniform lifetimes to
fix).
No changes on shader-db, though fewer extra MOVs are generated on even
glxgears (MOVs pair well enough that it ends up being the same instruction
count).
commit dffe7260cd5f9c70df4b817c26a4268ddad2475c
Author: Eric Anholt <eric at anholt.net>
Date: Mon Nov 16 20:45:46 2015 -0800
vc4: Fix uniform reordering to support reading the same uniform twice.
This does actually happen in the wild (particularly fabs of a uniform), so
we'd like to support it.
commit d18d1ba5877c234a2cf4e3e834df27f03c7b6a11
Author: Eric Anholt <eric at anholt.net>
Date: Wed Nov 11 16:50:29 2015 -0800
vc4: Fix documentation on vc4_qir_lower_uniforms.c.
commit a4bf28178f064082d3b818d2cd48abf9075cc459
Author: Eric Anholt <eric at anholt.net>
Date: Tue Nov 10 15:37:47 2015 -0800
vc4: Add support for nir_op_uge, using the carry bit on QPU_A_SUB.
It looks like nir_lower_idiv is going to use it soon, so add support.
With Ilia's change, this fixes one case in fs-op-div-large-uint-uint (with
GL 3.0 forced on).
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
commit 27b1d344384ef89faf6d321bf4625d08ba6ff3bf
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Nov 17 16:31:14 2015 -0800
i965: Fix PIPE_CONTOL typo.
PIPE_CONTOL!!!
commit c531d409274328c9713221f33f1d24e0f4877451
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Mon Nov 16 17:23:01 2015 -0800
i965: Add assertion for src_stencil payload size
This helps address a coverity warning and prevents future questions about this
code.
Reported-by: Coverity (via Ilia)
Cc: Ilia Mirkin <imirkin at alum.mit.edu>
Signed-off-by: Ben Widawsky <benjamin.widawsky at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 2bec154b479c0135c9be54bf15fc817b2be12dce
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Oct 28 16:26:15 2015 -0700
i965: Implement ARB_pipeline_statistics_query tessellation counters.
We basically just need to uncomment Ben's code.
v2: Fix obvious bugs caught by Ben.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Ben Widawsky <benjamin.widawsky at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit d4fbf11b583d76cbb362fb04334f791cc486b583
Author: Timothy Arceri <timothy.arceri at collabora.com>
Date: Fri Nov 13 15:43:13 2015 +1100
glsl: rename location layout helper
Change name from validate -> apply to more accurately describe what
the function does.
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit 03bbddd139fc3e543cb3aedf64236808ca20eeca
Author: Timothy Arceri <timothy.arceri at collabora.com>
Date: Fri Nov 13 11:41:52 2015 +1100
glsl: don't validate binding when its not needed
Checking that the flag has been set is all the validation thats
needed here.
Also not calling the binding validation function will make things
much simpler when adding compile time constant support as we
won't need to resolve the binding value.
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
commit 4f4ca6b90ac33ad84bc469f58df1682e93ab3733
Author: Timothy Arceri <timothy.arceri at collabora.com>
Date: Fri Nov 13 11:28:20 2015 +1100
glsl: remove temp variable to make code easier to read
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
commit a01b8c7e774aec651302fc8177b937c915daf1e7
Author: Timothy Arceri <timothy.arceri at collabora.com>
Date: Fri Nov 13 11:21:42 2015 +1100
glsl: cleanup and fix validate matrix function for arrays
Previously if the member was an array of matrices then a
warning message would be incorrectly given.
Also the struct case could never be met so it has been removed.
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
commit f8b5cc827e2fcbd64424495eac31e5d3d3f0567c
Author: Timothy Arceri <timothy.arceri at collabora.com>
Date: Fri Nov 13 10:49:48 2015 +1100
glsl: use better location in struct and block error messages
Previously we only gave the location for some members and never
gave the variable location. In those cases we were just giving
the location of the struct/block.
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
commit c54865db784ec26406aa98ebe67d86568ab9fc96
Author: Timothy Arceri <timothy.arceri at collabora.com>
Date: Fri Nov 13 10:27:00 2015 +1100
glsl: only do type and qualifier validation once per declaration
For struct and block members previously we were doing it for
every variable declaration.
So for example
struct S {
atomic_uint x, y, z;
};
Would previously generate three error messages when one is sufficient.
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
commit 14d343b0247e8ce826b43c4cb0f9e8c94102167e
Author: Timothy Arceri <timothy.arceri at collabora.com>
Date: Fri Nov 13 09:49:31 2015 +1100
glsl: rename function that processes struct and iface members
As of the previous commit this function handles only struct/iface
members.
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
commit 8cf795dc7c874a9062a27fc393066e7bdae94501
Author: Timothy Arceri <timothy.arceri at collabora.com>
Date: Fri Nov 13 09:45:36 2015 +1100
glsl: move block validation outside function that validates members
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
commit 649803742dd96ea6702c6ef16c35c36e6d4fd676
Author: Timothy Arceri <timothy.arceri at collabora.com>
Date: Thu Nov 12 17:43:52 2015 +1100
glsl: move ast layout qualifier handling code into its own function
We now also only apply these rules to variables rather than also
trying to apply them to function params.
V2: move code for handling stream layout qualifier
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
commit 5b596f38785a11ad429e30b2237de2c8c59a451f
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Nov 10 01:53:33 2015 -0800
i965: Add INTEL_DEBUG=shader_time support for tessellation shaders.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit df87cb837f995827072056d361207fd9fce514f2
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Jul 25 19:28:59 2015 -0700
i965: Add INTEL_DEBUG=tcs,tes and hs,ds flags for tessellation shaders.
Even though both tessellation shader stages must be used together, I
still think it makes sense to add separate debug flags for each stage.
It makes it possible to read the TCS/HS, rule out problems, then read
the TES/DS separately, without sifting through as much printed text.
I decided to add both the GL names (tcs/tes) and hardware names (hs/ds)
so they can be used interchangeably.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit e9b0fa496ca3d8645ff528b0b44c76ebfa76b534
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Nov 10 18:06:07 2015 -0800
i965: Add more MAX_*_URB_ENTRY_SIZE_BYTES #defines.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
commit 874a1ed813c62af245524df6f6d55c1d64e0781d
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Nov 17 01:37:27 2015 -0800
i965: Add missing stdio.h include to brw_compiler.h.
This is needed for the FILE * type in brw_print_vue_map().
Apparently, all files that include brw_compiler.h already pick this up
via some include chain, so this isn't actually a build fix. However,
I have patches which introduce new consumers of brw_compiler.h that
fail to build because of the missing #include.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 4518eea065df5c6877b996738ed425c292e3b144
Author: Martin Peres <martin.peres at linux.intel.com>
Date: Fri Oct 30 17:16:35 2015 +0200
egl: make it clear which platform x11 backend is being used (dri2 or 3)
Signed-off-by: Martin Peres <martin.peres at linux.intel.com>
Reviewed-by: Boyan Ding <boyan.j.ding at gmail.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Emil Velikov <emil.velikov at collabora.co.uk>
commit fcdc798515a74d12e4f1f848ac8b8bacce928855
Author: Boyan Ding <boyan.j.ding at gmail.com>
Date: Tue Jul 21 23:44:02 2015 +0800
egl/x11_dri3: Implement EGL_KHR_image_pixmap
v2: from Martin Peres
- Replace a tab with spaces
v3: from Martin Peres
- disable EGL_KHR_image_pixmap when is_different_gpu is set (Axel Davy)
Signed-off-by: Boyan Ding <boyan.j.ding at gmail.com>
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Emil Velikov <emil.velikov at collabora.co.uk>
commit bd6131a8d1e1cf0e6eb5494b50607a4ccb21e1f9
Author: Boyan Ding <boyan.j.ding at gmail.com>
Date: Tue Jul 21 23:44:01 2015 +0800
loader/dri3: Expose function to create __DRIimage from pixmap
Used to support EGL_KHR_image_pixmap.
Signed-off-by: Boyan Ding <boyan.j.ding at gmail.com>
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Emil Velikov <emil.velikov at collabora.co.uk>
commit f35198badeb956a8f435727d805a47c7e42610d0
Author: Boyan Ding <boyan.j.ding at gmail.com>
Date: Tue Jul 21 23:44:00 2015 +0800
egl/x11: Implement dri3 support with loader's dri3 helper
v2: From Martin Peres
- Tell we are compiling the dri3 backend in configure.ac
- Update the Makefile.am
- get rid of the LIBDRM_HAS_RENDERNODE_SUPPORT macro
- fix some warnings related to EGLuint64KHR to int64_t conversions
- use dri2_get_dri_config to get the __DRIconfig instead of open-coding it
- replace the occasional tabs with spaces
v3: From Martin Peres
- fix and indent problem (Matt Turner)
- drop the authenticate function, use NULL in the vtable instead (Emil)
- drop some useless includes (Emil Velikov)
- mandate libdrm (Emil Velikov)
- link to xcb-dri3 (Kristian Høgsberg)
- convert to the new loader interface for drwable (Kristian)
- remove some dead code after the dropping of some vfuncs (Kristian)
- add a comment on the topic of rendering to the frontbuffer
v4: From Martin Peres
- do not expose the preserved swap behavior (Acked by Eric Anholt)
Signed-off-by: Boyan Ding <boyan.j.ding at gmail.com>
Signed-off-by: Martin Peres <martin.peres at linux.intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Emil Velikov <emil.velikov at collabora.co.uk>
commit a25df5457121d40fef86929d4c10d8058a4d5c72
Author: Boyan Ding <boyan.j.ding at gmail.com>
Date: Tue Jul 21 23:43:59 2015 +0800
egl_dri2: Add a function to let platform code return dri drawable from _EGLSurface
dri3 for EGL will use different struct other than dri2_egl_surface for
an EGL surface, the common code only uses __DRIdrawable from that
struct, so instead of converting _EGLSurface to dri2_egl_surface, let
the platform code return the __DRIdrawable by its own (although the
current platforms use the same function).
v2: From Martin Peres
- convert to the new drawable interface (Kristian)
Signed-off-by: Boyan Ding <boyan.j.ding at gmail.com>
Signed-off-by: Martin Peres <martin.peres at linux.intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Emil Velikov <emil.velikov at collabora.co.uk>
commit fdacbc439edc1d26865a99524d1a9efc9edb4c0d
Author: Boyan Ding <boyan.j.ding at gmail.com>
Date: Tue Jul 21 23:43:55 2015 +0800
glx/dri3: Convert to use dri3 helper in loader library
v2: From Martin Peres
- convert to the new drawable interface
- delete dead code after the dropping of some vfuncs
- delete the width and height attributes since they are found in the helper
Signed-off-by: Boyan Ding <boyan.j.ding at gmail.com>
Signed-off-by: Martin Peres <martin.peres at linux.intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Emil Velikov <emil.velikov at collabora.co.uk>
commit 6bd9ba7d07490059024d16ba32fafa1c5bb239ee
Author: Boyan Ding <boyan.j.ding at gmail.com>
Date: Tue Jul 21 23:43:54 2015 +0800
loader: Add dri3 helper
v2: From Martin Peres
- Try to fit in the 80-col limit as much as possible
v3: From Martin Peres
- introduce loader_dri3_helper.la to avoid dragging the xcb dep everywhere (Kristian & Emil)
- get rid of the width, height, dri_screen and is_different_gpu vfuncs (Kristian)
- replace the create/destroy functions with init/fini for dri3 drawables
- prefix static functions with dri3_ and exported ones with loader_dri3 (Emil)
- keep the function definition consistent (Emil)
Signed-off-by: Boyan Ding <boyan.j.ding at gmail.com>
Signed-off-by: Martin Peres <martin.peres at linux.intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Emil Velikov <emil.velikov at collabora.co.uk>
commit 252b143e9e8ca0b98143c237f14cb0b548ffd510
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Tue Nov 17 09:49:43 2015 +0100
i965: Return the correct value type from brw_compile_gs()
brw_compile_gs() should return a pointer to unsigned, but it is returning the
bool 'false' at some point, hence annoying us with a compiler warning:
In function 'const unsigned int* brw::brw_compile_gs(const brw_compiler*,
void*, void*, const brw_gs_prog_key*, brw_gs_prog_data*, const nir_shader*,
gl_shader_program*, int, unsigned int*, char**)':
brw_vec4_gs_visitor.cpp:776:14: warning: converting 'false' to pointer type
'const unsigned int*' [-Wconversion-null]
return false;
^
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit dfa60e7057ef8e5b07c49c7ba22fbddaa75e848b
Author: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Date: Mon Nov 16 12:35:13 2015 +0100
glsl: copy each field's precision information in glsl_types's structure constructor
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 688b58c40c2fdf99c94706d02511293d30fe2430
Author: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Date: Mon Nov 16 12:02:41 2015 +0100
glsl: copy each field's precision information from the old gl_PerVertex interface block
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit cfe32cfa8ed0cb2b41be8e63ddab9f68f2cc63de
Author: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Date: Mon Nov 16 12:01:37 2015 +0100
glsl: copy each field's precision information when generating varying variables
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 91eefe850531adf7e1ed527e4b5bcb4a1f8c5d63
Author: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Date: Mon Nov 16 11:59:18 2015 +0100
glsl: initialize data.precision value in ir_variable constructor
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 58954e4daa5e874771e1a33320a4009249f2429a
Author: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Date: Mon Nov 16 11:43:20 2015 +0100
glsl/nir: initialize precision field in glsl_struct_field constructor
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit a96afaced8d4498e3f24ff1e201b4569fd03d55d
Author: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Date: Mon Nov 16 10:23:42 2015 +0100
nir: reduce memory footprint of glsl_struct_field's precision
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit f4f30ad730b7dafaadafda63344012203543894c
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Mon Nov 16 08:43:12 2015 +0200
mesa: do runtime validation of precision varyings only on ES
Precision qualifier should be ignored on desktop OpenGL.
v2: include spec quote (Samuel)
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit 023fd58fd685135bfb4ee401ac9bd1c3a3988e02
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Mon Nov 16 08:44:18 2015 +0200
glsl: initialize precision when adding per vertex record fields
Fixes issues with tessellation builtin variables since precision was
introduced to IR with commit f84bc57d7dc02fceb805803131426c791eadeff9.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 292df1940126f267418e656b9ec33eb3f06667b8
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Nov 13 14:55:50 2015 -0800
i965: Set MaxCombinedUniformBlocks properly.
Up until now, we've been letting core Mesa initialize it to 36 for us
(which is presumably BRW_MAX_UBO (12) * (VS+GS+FS stages -> 3)).
With compute and tessellation, we need to increase this.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 5ee5dfddeafde2e2b89f86d2a59769a61ce5d6b2
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 12 13:46:16 2015 -0800
i965: Clean up context constant initialization code.
This was getting pretty out of hand, and with compute partially in place
and tessellation on the way, it was only going to get worse.
This patch makes a "stage exists?" predicate and a "number of stages"
count and uses them to clean up a lot of calculations. We can just
loop over shader stages and set things for the ones that exist. For
combined counts, we can just multiply by the number of stages.
It also tries to organize a little bit.
We should probably use _mesa_has_geometry_shaders/tessellation/compute
here, but we can't because ctx->Version isn't initialized yet. Perhaps
that could be fixed in the future.
No change in "glxinfo -l" on Broadwell.
v2: Drop stray compute shader hunk. Mark stage_exists as const.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 44d6c0c805d2911cc5dfe853e5bc5a505f87775f
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 12 13:32:13 2015 -0800
i965: Convert scalar_* flags to a scalar_stage array.
I was going to add scalar_tcs and scalar_tes flags, and then thought
better of it and decided to convert this to an array. Simpler.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit a2611ffe4b5f1852c59301f086b988233a1c62f3
Author: Roland Scheidegger <sroland at vmware.com>
Date: Tue Nov 17 01:04:05 2015 +0100
r200: fix bgrx8/xrgb8 blits
Since 779cabfc7d022de8b7b9bc7fdac0caffa8646c51 the same txformat table entries
are used for "normal" texturing as well as for blits. However, I forgot to put
in an entry for the bgrx8 (le) and xrgb8 (be) formats - the normal texturing
path can't hit them because the radeon tex format chooser will never chose
them, but we get that format from the dri buffers (at least I assume we got
it from there).
This is untested but essentially addressing the same bug as for radeon.
(I don't think that the second entry per le/be table is actually necessary,
but shouldn't hurt...)
Tested-by: Ian Romanick <ian.d.romanick at intel.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
commit 983614dbede7b94cba1bad9f3e8627fc5e14bb91
Author: Roland Scheidegger <sroland at vmware.com>
Date: Thu Nov 12 19:33:14 2015 +0100
radeon: fix bgrx8/xrgb8 blits
Since d21320f6258b2e1780a15c1ca718963d8a15ca18 the same txformat table entries
are used for "normal" texturing as well as for blits. However, I forgot to put
in an entry for the bgrx8 (le) and xrgb8 (be) formats - the normal texturing
path can't hit them because the radeon tex format chooser will never chose
them, but we get that format from the dri buffers (at least I assume we got
it from there). This caused lots of piglit regressions (and probably lots of
trouble outside piglit too).
This fixes bug https://bugs.freedesktop.org/show_bug.cgi?id=92900.
Tested-by: Ian Romanick <ian.d.romanick at intel.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
commit c40a88b6c5a698e5297957e28cccf2ce23820caa
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Fri Nov 13 11:58:41 2015 -0800
meta/generate_mipmap: Only modify the draw framebuffer binding in fallback_required
Previously GL_FRAMEBUFFER was used. However, if GL_EXT_framebuffer_blit
is supported (note: it is supported by every Mesa driver), this is
*sometimes* an alias for GL_DRAW_FRAMEBUFFER (getters) and *sometimes*
an alias for *both* GL_DRAW_FRAMEBUFFER and GL_READ_FRAMEBUFFER
(setters). As a result, the code saved one binding but modified both.
If the bindings were different, the GL_READ_FRAMEBUFFER would be
incorrect on exit.
Fixes the piglit fbo-generatemipmap-versus-READ_FRAMEBUFFER test.
Ideally this function would use DSA functions and not modify the binding
at all. However, that would be a much more intrusive change because
_mesa_meta_bind_fbo_image would also need to be modified.
_mesa_meta_bind_fbo_image has a lot of callers. Much of this code is
about to get a major rework due to bug #92363, so I don't think it
matters too much. In fact, I discovered this bug while working on the
other bug. Le bon temps!
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
commit d564b5b58e8955f807e330364ff534ce57c99d8c
Author: Matt Turner <mattst88 at gmail.com>
Date: Sat Nov 14 17:47:33 2015 -0800
nir/glsl: Fix copy-n-paste mistakes from commit 213f864.
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 00f554abba8c0f3b65af94365c15109c3b858486
Author: Alex Deucher <alexander.deucher at amd.com>
Date: Fri Nov 13 13:00:30 2015 -0500
radeonsi: enable optimal raster config setting for fiji (v2)
Requires proper kernel tiling configuration so check the tiling
config registers.
v2: send the right version of the patch
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
Cc: mesa-stable at lists.freedesktop.org
commit 5b37d8b50cfc9a390f8320557a332a3c75b91953
Author: Alex Deucher <alexander.deucher at amd.com>
Date: Fri Nov 13 16:21:09 2015 -0500
radeonsi: use proper GRBM_GFX_INDEX offset for CI+
The offset is different on CI and newer.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
commit 2ca018cb65e1001e890f3dccbe65f757ed8da3f8
Author: Neil Roberts <neil at linux.intel.com>
Date: Mon Nov 16 14:35:46 2015 +0100
docs: Add 16x MSAA on i965 to the release notes
Signed-off-by: Neil Roberts <neil at linux.intel.com>
commit 1780a562bcb996828509c5e8912305751bee6144
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Mon Nov 16 10:49:14 2015 +0000
nv50: add missing header into the sources list
Otherwise it won't end up in the tarball.
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
commit 40c2acef5cfe28f4ac371203bd70bfc7a222ba26
Author: Juan A. Suarez Romero <jasuarez at igalia.com>
Date: Fri Nov 6 12:23:17 2015 +0000
nir/glsl_to_nir: use _mesa_fls() to compute num_textures
Replace the current loop by a direct call to _mesa_fls() function.
It also fixes an implicit bug in the current code where num_textures
seems to be one value less than it should be when sh->Program->SamplersUsed > 0.
For instance, num_textures is 0 instead of 1 when
sh->Program->SamplersUsed is 1.
Signed-off-by: Juan A. Suarez Romero <jasuarez at igalia.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 3f34afa0aad2a9bcfc0e5469a9675eca11ea7649
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Fri Nov 13 09:03:55 2015 +0100
nir/copy_propagate: do not copy-propagate MOV srcs with source modifiers
If a source operand in a MOV has source modifiers, then we cannot
copy-propagate it from the parent instruction and remove the MOV.
v2: remove the check for source modifiers from is_move() (Jason)
v3: Put the check for source modifiers back into is_move() since
this function is called from copy_prop_alu_src(). Add source
modifiers checks to is_vec() instead.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit ff17b3ccf4f8d9f989cc975cd0e11716ff48bc1d
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Nov 14 20:14:07 2015 -0500
nv50,nvc0: disable render condition around clear_* functions
Only the regular "clear" call is supposed to respect the render
condition. The rest should ignore it.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit d2f089ba17c6b17823fc3d244e15c0a18108d5ce
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Nov 7 18:58:34 2015 -0800
i965: Introduce a MOV_INDIRECT opcode.
The geometry and tessellation control shader stages both read from
multiple URB entries (one per vertex). The thread payload contains
several URB handles which reference these separate memory segments.
In GLSL, these inputs are represented as per-vertex arrays; the
outermost array index selects which vertex's inputs to read. This
array index does not necessarily need to be constant.
To handle that, we need to use indirect addressing on GRFs to select
which of the thread payload registers has the appropriate URB handle.
(This is before we can even think about applying the pull model!)
This patch introduces a new opcode which performs a MOV from a
source using VxH indirect addressing (which allows each of the 8
SIMD channels to select distinct data.)
Based on a patch by Jason Ekstrand.
v2: Rename from INDIRECT_THREAD_PAYLOAD_MOV to MOV_INDIRECT; make it
a bit more generic. Use regs_read() instead of hacking up the
register allocator. (Suggested by Jason Ekstrand.)
v3: Fix regs_read() to be more accurate for small unaligned regions.
Also rebase on Matt's work.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com> [v3]
Reviewed-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com> [v1]
commit 848fa3101d5077b1aecfb0886c69a7d0dd7f75bc
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Thu Nov 12 00:59:00 2015 +0100
nv50: add support for performance metrics on G84+
Currently only one metric is exposed but more will be added later.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Tested-by: Pierre Moreau <pierre.morrow at free.fr>
Acked-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 6a9c151dbb87a10b6d51c451a5a277d646d08857
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Tue Nov 10 01:27:15 2015 +0100
nv50: add compute-related MP perf counters on G84+
These compute-related MP performance counters have been reverse
engineered using CUPTI which is part of NVIDIA CUDA.
As for nvc0, we use a compute kernel to read out those performance
counters, and the command stream to configure them. Note that Tesla
only exposes 4 MP performance counters, while Fermi has 8.
Only G84+ is supported because G80 is an old and weird card.
Tested on G84, G96, G200, MCP79 and GT218 with glxgears, glxspheres64,
xonotic-glx, heaven and valley.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Tested-by: Pierre Moreau <pierre.morrow at free.fr>
Acked-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit ff72440b40211326eda118232fabd53965410afd
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Wed Oct 14 21:42:41 2015 +0200
nv50: implement a basic compute support
This adds the ability to launch simple compute kernels like the one I
will use to read out MP performance counters in the upcoming patch.
This compute support is based on the work of Francisco Jerez (aka curro)
that he did as part of his EVoC project in 2011/2012 to get OpenCL
working on Tesla. His original work can be found here:
https://github.com/curro/mesa/commits/nv50-compute
I did some improvements on the original code, like fixing using both 3D
and COMPUTE simultaneously, improving global buffers binding, and making
the code closer to what nvc0 already does. This compute support has been
tested by Pierre Moreau and myself with some compute kernels. This is a
step towards OpenCL.
Speaking about this, it seems like compute programs overlap fragment
programs when they are used both. To fix this, we need to re-validate
fragment programs when binding compute programs and vice versa.
Note that, textures, samplers and surfaces still need to be implemented.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Tested-by: Pierre Moreau <pierre.morrow at free.fr>
Acked-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 7167a058baa2b524e31e51d8924fe5d0ea661b70
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Sat Nov 14 22:57:59 2015 +0100
nv50: free interpolation parameters in nv50_program_destroy()
As for nvc0, we need to free memory allocated by interpolation
parameters. This fixes a memory leak spotted by valgrind.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 69271bba068c21a07b0698bf579becc20767b158
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Sat Nov 14 17:20:09 2015 +0100
nvc0: reduce the number of GPR used when reading MP perf counters
No need to allocate more GPR than used in the compute kernel which
reads MP performance counters on Fermi.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
commit f94e1d97381ec787c2abbbcd5265252596217e33
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Nov 14 10:28:55 2015 -0500
nouveau: don't expose HEVC decoding support
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org
commit 3a0fef0005eca63c6f8067d55145b8e884221cfa
Author: Vinson Lee <vlee at freedesktop.org>
Date: Mon Nov 2 01:23:59 2015 -0800
nir: Silence GCC maybe-uninitialized warnings.
nir/nir_control_flow.c: In function ‘split_block_cursor.isra.11’:
nir/nir_control_flow.c:460:15: warning: ‘after’ may be used uninitialized in this function [-Wmaybe-uninitialized]
*_after = after;
^
nir/nir_control_flow.c:458:16: warning: ‘before’ may be used uninitialized in this function [-Wmaybe-uninitialized]
*_before = before;
^
Signed-off-by: Vinson Lee <vlee at freedesktop.org>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 5480bbd90ea288877b6e56d4860feb8f97bcba80
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Nov 7 01:37:33 2015 -0800
i965: Add a SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT opcode.
We need to use per-slot offsets when there's non-uniform indexing,
as each SIMD channel could have a different index. We want to use
them for any non-constant index (even if uniform), as it lives in
the message header instead of the descriptor, allowing us to set
offsets in GRFs rather than immediates.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
commit 511de1a80cedc0add386dad79cce56dd68d2f611
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 12 13:02:05 2015 -0800
glsl: Allow implicit int -> uint conversions for the % operator.
GLSL 4.00 and GL_ARB_gpu_shader5 introduced a new int -> uint implicit
conversion rule and updated the rules for modulus to use them. (In
earlier languages, none of the implicit conversion rules did anything
relevant, so there was no point in applying them.)
This allows expressions such as:
int foo;
uint bar;
uint mod = foo % bar;
Cc: mesa-stable at lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit a4ba476c30ebcb99694c6167ac9b8af9414cb656
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Nov 10 00:48:33 2015 -0800
i965: Print input/output VUE maps on INTEL_DEBUG=vs, gs.
I've been carrying around a patch to do this for the last few months,
and it's been exceedingly useful for debugging GS and tessellation
problems. I've caught lots of bugs by inspecting the interface
expectations of two adjacent stages.
It's not that much spam, so I figure we may as well just print it.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit f88c175a29bb287d41ef90343eb6670525475a06
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Nov 11 22:37:53 2015 -0800
i965: Make convert_attr_sources_to_hw_regs handle stride == 0.
This makes expressions like component(fs_reg(ATTR, n), 7) get a proper
<0,1,0> region instead of the invalid <0,8,0>.
Nobody uses this today, but I plan to.
v2: Rebase on Matt's changes; simplify.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com> [v1]
commit 26f9469a46585f64b24fb1037aaae7c757a5e6e1
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Nov 7 22:35:33 2015 -0800
nir: Add helpers for getting input/output intrinsic sources.
With the many variants of IO intrinsics, particular sources are often in
different locations. It's convenient to say "give me the indirect
offset" or "give me the vertex index" and have it just work, without
having to think about exactly which kind of intrinsic you have.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit d12bde0944d1d69401ef1d854aa0ab92b5a6af54
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Oct 19 11:28:15 2015 -0700
nir: Don't lower TCS outputs to temporaries.
We'd like to shadow these when possible, but the current code doesn't
work properly for TCS outputs. For now, disable it.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 134728fdaef9d2a5d072d25b31437ac0fecd9076
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Oct 19 11:44:28 2015 -0700
nir: Allow outputs reads and add the relevant intrinsics.
Normally, we rely on nir_lower_outputs_to_temporaries to create shadow
variables for outputs, buffering the results and writing them all out
at the end of the program. However, this is infeasible for tessellation
control shader outputs.
Tessellation control shaders can generate multiple output vertices, and
write per-vertex outputs. These are arrays indexed by the vertex
number; each thread only writes one element, but can read any other
element - including those being concurrently written by other threads.
The barrier() intrinsic synchronizes between threads.
Even if we tried to shadow every output element (which is of dubious
value), we'd have to read updated values in at barrier() time, which
means we need to allow output reads.
Most stages should continue using nir_lower_outputs_to_temporaries(),
but in theory drivers could choose not to if they really wanted.
v2: Rebase to accomodate Jason's review feedback.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit c51d7d5fe3425b0b1cb551f47979a1e41f1f73d8
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Oct 2 00:11:01 2015 -0700
nir/lower_io: Introduce nir_store_per_vertex_output intrinsics.
Similar to nir_load_per_vertex_input, but for outputs. This is not
useful in geometry shaders, but will be useful in tessellation shaders.
v2: Change stage_uses_per_vertex_outputs() to is_per_vertex_output(),
taking a nir_variable (requested by Jason Ekstrand).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 0df452cd0d9da031d2ef29853d39112fdf8e1d46
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Sep 30 17:17:35 2015 -0700
nir/lower_io: Use load_per_vertex_input intrinsics for TCS and TES.
Tessellation control shader inputs are an array indexed by the vertex
number, like geometry shader inputs. There aren't per-patch TCS inputs.
Tessellation evaluation shaders have both per-vertex and per-patch
inputs. Per-vertex inputs get the new intrinsics; per-patch inputs
continue to use the ordinary load_input intrinsics, as they already
work like we want them to.
v2: Change stage_uses_per_vertex_inputs into is_per_vertex_input(),
which takes a variable (requested by Jason Ekstrand).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 1cb49eedb52c387caf6a0035e5baad29bb55e3ff
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Nov 2 14:29:42 2015 -0800
i965: Silence unused parameter warnings in get_buffer_rect
brw_meta_fast_clear.c: In function 'get_buffer_rect':
brw_meta_fast_clear.c:318:37: warning: unused parameter 'brw' [-Wunused-parameter]
get_buffer_rect(struct brw_context *brw, struct gl_framebuffer *fb,
^
brw_meta_fast_clear.c:319:44: warning: unused parameter 'irb' [-Wunused-parameter]
struct intel_renderbuffer *irb, struct rect *rect)
^
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 758f12fd98dea9a9682becf2d496bd38ef3959e5
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Nov 10 12:36:58 2015 -0800
meta/generate_mipmap: Don't leak the sampler object
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 7a879e422bcdaf89bde286de6c7b9db5c34f7fc3
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Nov 13 12:16:48 2015 -0800
i965: Remove unneeded #includes.
Some of these are no longer needed since all the backends switched to
NIR.
commit 386759b02dac1382072cecef4d6520a0770f995e
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Nov 13 12:13:14 2015 -0800
i965: Silence warning.
intel_asm_annotation.c: In function ‘annotation_insert_error’:
intel_asm_annotation.c:214:18:
warning: ‘ann’ may be used uninitialized in this function
[-Wmaybe-uninitialized]
ann->error = ralloc_strdup(annotation->mem_ctx, error);
^
I initially tried changing the type of ann_count to unsigned (is
currently int), since that in addition to the check that it's non-zero
at the beginning of the function seems sufficient to prove that it must
be greater than zero. Unfortunately that wasn't sufficient.
commit 8b145d6a3de381a568d8001131e48257611a542a
Author: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
Date: Fri Nov 13 13:36:43 2015 +0200
i965: Don't write beyond allocated memory.
Reviewed-by: Eduardo Lima Mitev <elima at igalia.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
commit 0eb3db117b56b081ee2674cc8940c193ffc3c41b
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Nov 2 10:23:12 2015 -0800
i965: Use BRW_MRF_COMPR4 macro in more places.
Reviewed-by: Emil Velikov <emil.velikov at collabora.co.uk>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 49b3215d7076db8b9afe8998b01ef250795b5892
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Oct 26 18:41:27 2015 -0700
i965: Combine register file field.
The first four values (2-bits) are hardware values, and VGRF, ATTR, and
UNIFORM remain values used in the IR.
Reviewed-by: Emil Velikov <emil.velikov at collabora.co.uk>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit b3315a6f56fb93f2884168cbf9358b2606641db5
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Oct 26 17:52:57 2015 -0700
i965: Replace HW_REG with ARF/FIXED_GRF.
HW_REGs are (were!) kind of awful. If the file was HW_REG, you had to
look at different fields for type, abs, negate, writemask, swizzle, and
a second file. They also caused annoying problems like immediate sources
being considered scheduling barriers (commit 6148e94e2) and other such
nonsense.
Instead use ARF/FIXED_GRF/MRF for fixed registers in those files.
After a sufficient amount of time has passed since "GRF" was used, we
can rename FIXED_GRF -> GRF, but doing so now would make rebasing awful.
Reviewed-by: Emil Velikov <emil.velikov at collabora.co.uk>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 4b0fbebf024e564c195f3ce94e1ce43a3d6442ea
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Nov 2 00:25:04 2015 +0000
i965/fs: Set stride correctly for immediates in fs_reg(brw_reg).
The fs_reg() constructors for immediates set stride to 0, except for
vector-immediates, which set stride to 1. This patch makes the fs_reg
constructor that takes a brw_reg do likewise, so that stride is set
correctly for cases such as fs_reg(brw_imm_v(...)).
The generator asserts that this is true (and presumably it's useful in
some optimization passes?) and the VF fs_reg constructors did this (by
virtue of the fact that it doesn't override what init() does).
In the next commit, calling this constructor with brw_imm_* will generate
an IMM file register rather than a HW_REG, making this change necessary
to avoid breakage with existing uses of brw_imm_v().
Reviewed-by: Emil Velikov <emil.velikov at collabora.co.uk>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit b99e1fd547035be9a6da5ee1b78b8a853c2ef3e0
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Nov 2 00:22:29 2015 +0000
i965/fs: Handle type-V immediates in brw_reg_from_fs_reg().
We use brw_imm_v() to produce type-V immediates, which generates a
brw_reg with fs_reg's .file set to HW_REG. The next commit will rid us
of HW_REGs, so we need to handle BRW_REGISTER_TYPE_V in the IMM case.
Reviewed-by: Emil Velikov <emil.velikov at collabora.co.uk>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit b163aa01487ab5f9b22c48b7badc5d65999c4985
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Oct 26 17:09:25 2015 -0700
i965: Rename GRF to VGRF.
The 2-bit hardware register file field is ARF, GRF, MRF, IMM.
Rename GRF to VGRF (virtual GRF) so that we can reuse the GRF name to
mean an assigned general purpose register.
Reviewed-by: Emil Velikov <emil.velikov at collabora.co.uk>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 5a23b31c75556fa0fe9ca53db481bbec18c2baba
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu Oct 29 22:04:22 2015 -0700
i965: Move BAD_FILE from the beginning of enum register_file.
I'm going to begin using brw_reg's file field in backend_reg and its
derivatives, and in order to keep the hardware value for ARF as 0, we
have to do something different.
Reviewed-by: Emil Velikov <emil.velikov at collabora.co.uk>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit dba309fc14d1ca99251c8f8115d2a26ac86f14f6
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Oct 30 13:53:38 2015 -0700
i965: Initialize registers.
The test (file == BAD_FILE) works on registers for which the constructor
has not run because BAD_FILE is zero. The next commit will move
BAD_FILE in the enum so that it's no longer zero.
In the case of this->outputs, the constructor was being run implicitly,
and we were unnecessarily memsetting is to zero.
Reviewed-by: Emil Velikov <emil.velikov at collabora.co.uk>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 7638e75cf99263c1ee8e31c6cc5a319feec2c943
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Oct 26 04:35:14 2015 -0700
i965: Use brw_reg's nr field to store register number.
In addition to combining another field, we get replace silliness like
"reg.reg" with something that actually makes sense, "reg.nr"; and no one
will ever wonder again why dst.reg isn't a dst_reg.
Moving the now 16-bit nr field to a 16-bit boundary decreases code size
by about 3k.
Reviewed-by: Emil Velikov <emil.velikov at collabora.co.uk>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 3048053908310eaf082058e5be34ae902e1fc02c
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Oct 26 04:04:16 2015 -0700
i965: Unwrap some lines.
Reviewed-by: Emil Velikov <emil.velikov at collabora.co.uk>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 58fa9d47b536403c4e3ca5d6a2495691338388fd
Author: Matt Turner <mattst88 at gmail.com>
Date: Sun Oct 25 21:14:56 2015 -0700
i965/vec4: Remove swizzle/writemask fields from src/dst_reg.
Also allows us to handle HW_REGs in the swizzle() and writemask()
functions.
Reviewed-by: Emil Velikov <emil.velikov at collabora.co.uk>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 94b1031703b1b5759436fe215323727cffce5f86
Author: Matt Turner <mattst88 at gmail.com>
Date: Sat Oct 24 15:29:03 2015 -0700
i965: Remove fixed_hw_reg field from backend_reg.
Since backend_reg now inherits brw_reg, we can use it in place of the
fixed_hw_reg field.
Reviewed-by: Emil Velikov <emil.velikov at collabora.co.uk>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 1392e45bfb396ccbfa5bb0c6063522e0550988d3
Author: Matt Turner <mattst88 at gmail.com>
Date: Sat Oct 24 14:55:57 2015 -0700
i965: Use immediate storage in inherited brw_reg.
Reviewed-by: Emil Velikov <emil.velikov at collabora.co.uk>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit d74dd703f80ff40047ad8360e66ffd70b80f7230
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Oct 23 13:11:44 2015 -0700
i965: Add and use enum brw_reg_file.
Reviewed-by: Emil Velikov <emil.velikov at collabora.co.uk>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 977df90d6538ae35a5463a6b098ba974d3f0143e
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Oct 23 12:17:03 2015 -0700
i965: Reorganize brw_reg fields.
Put fields that are meaningless with an immediate in the same storage
with the immediate. This leaves fields type, file, nr, subnr in the
first dword where there's now extra room for expansion.
Reviewed-by: Emil Velikov <emil.velikov at collabora.co.uk>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit e42fb0c2a687cdcd6af2a590f6f5e24f64cfff3b
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu Oct 22 19:41:30 2015 -0700
i965: Make 'dw1' and 'bits' unnamed structures in brw_reg.
Generated by
sed -i -e 's/\.bits\././g' *.c *.h *.cpp
sed -i -e 's/dw1\.//g' *.c *.h *.cpp
and then reverting changes to comments in gen7_blorp.cpp and
brw_fs_generator.cpp.
There wasn't any utility offered by forcing the programmer to list these
to access their fields. Removing them will reduce churn in future
commits.
This is C11 (and gcc has apparently supported it for sometime
"compatibility with other compilers")
See https://gcc.gnu.org/onlinedocs/gcc/Unnamed-Fields.html
Reviewed-by: Emil Velikov <emil.velikov at collabora.co.uk>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 182f137521f9c81f89a473ca5a411e6a7c531e19
Author: Matt Turner <mattst88 at gmail.com>
Date: Sat Oct 24 15:04:23 2015 -0700
i965: Delete type field from backend_reg.
Switching from an implicitly-sized type field to field with an explicit
bit width is safe because we have fewer than 2^4 types, and gcc will
warn if you attempt to set a value that will not fit.
Reviewed-by: Emil Velikov <emil.velikov at collabora.co.uk>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 433df2e03c9a066bb2975bed28b57d6e2edf0aa9
Author: Matt Turner <mattst88 at gmail.com>
Date: Sat Oct 24 14:35:33 2015 -0700
i965: Delete abs/negate fields from backend_reg.
Instead use the ones provided by brw_reg. Also allows us to handle
HW_REGs in the negate() functions.
Reviewed-by: Emil Velikov <emil.velikov at collabora.co.uk>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit c7ed5d1d1ca5d0e537cd5eb2cc8d4cae7ae73564
Author: Matt Turner <mattst88 at gmail.com>
Date: Sat Oct 24 14:32:03 2015 -0700
i965: Make backend_reg inherit from brw_reg.
Some fields (file, type, abs, negate) in brw_reg are shadowed by
backend_reg.
Reviewed-by: Emil Velikov <emil.velikov at collabora.co.uk>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 88f349c4e100acd5dd3e7137496444907a175c39
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu Nov 12 16:02:22 2015 -0800
i965/fs: Replace nested ternary with if ladder.
Since the types of the expression were
bool ? src_reg : (bool ? brw_reg : brw_reg)
the result of the second (nested) ternary would be implicitly
converted to a src_reg by the src_reg(struct brw_reg) constructor. I.e.,
bool ? src_reg : src_reg(bool ? brw_reg : brw_reg)
In the next patch, I make backend_reg (the parent of src_reg) inherit
from brw_reg, which changes this expression to return brw_reg, which
throws away any fields that exist in the classes derived from brw_reg.
I.e.,
src_reg(bool ? brw_reg(src_reg) : bool ? brw_reg : brw_reg)
Generally this code was gross, and wasn't actually shorter or easier to
read than an if ladder.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit 3694d58e6c4a39bd84e8aef0d8e67c3ae9447f33
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Oct 15 23:41:35 2015 +0200
radeonsi: remove dead code after ES-GS linkage change
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit d79a3449a70b35a7fd38e7b4e17cafcbc28dda0d
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Oct 15 23:29:00 2015 +0200
radeonsi: link ES-GS just like LS-HS
This reduces the shader key for ES.
Use a fixed attrib location based on (semantic name, index).
The ESGS item size is determined by the physical index of the highest ES
output, so it's almost always larger than before, but I think that
shouldn't matter as long as the ESGS ring buffer is large enough.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit b1c5f3faa9d7a227150b677469df1a5832236541
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Nov 8 13:34:44 2015 +0100
radeonsi: calculate optimal GS ring sizes to fix GS hangs on Tonga
I discovered that increasing the ESGS ring size fixes GS hangs on Tonga,
so let's do it properly.
There is now a separate init_config_gs_rings state that is not immutable,
because GS rings are resized when needed.
This also saves some memory. Most apps won't need more than 1MB
per ring per shader engine.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
commit 2f5d911ba2b0d477bce80e4dd3ae4d9748c6f784
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Nov 8 12:15:54 2015 +0100
radeonsi: rename si_update_gs_rings
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
commit 4acd856088c31ab7ebbfbe5010db1fbcca72845c
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Nov 8 12:12:46 2015 +0100
radeonsi: calculate ESGS_RING_ITEMSIZE in create_shader
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
commit a0cf58996197d99cc7d743b76be977cc2359dca9
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Nov 8 12:05:39 2015 +0100
radeonsi: move maximum gs stream calculation into create_shader
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
commit 3ab0c49f04e5039655ddc8b81cac325709b154fe
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Nov 8 11:49:33 2015 +0100
radeonsi: clean up small duplication in si_shader_gs
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
commit eb0d3e8a90df3f6a39a3ffc911a335554fc8cd98
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Nov 7 16:30:01 2015 +0100
gallium/radeon: shorten render_cond variable names
and ..._cond -> ..._invert
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
commit 70c40cc9899c1e895004c3e25c4f763af44cd17d
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Nov 7 16:24:47 2015 +0100
gallium/radeon: remove predicate_drawing flag
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
commit 12596cfd4cea4cff2bc067876d5ff25c54cdc874
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Nov 7 15:39:39 2015 +0100
gallium/radeon: atomize render condition (SET_PREDICATION)
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
commit 35219076227e83ad2a406942c8b009337a4746d8
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Nov 7 15:00:55 2015 +0100
gallium/radeon: simplify restoring render condition after flush
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
commit 600e212d87017db613b8068decfeab3e4bf86deb
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Nov 7 14:55:23 2015 +0100
gallium/radeon: don't use PREDICATION_OP_CLEAR
Not setting the predication bit is sufficient.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
commit 6eff5415e46fb43619b543368fa427334d267a71
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Nov 7 14:45:58 2015 +0100
gallium/radeon: simplify disabling render condition for u_blitter
just disable it by not setting the predication bit
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
commit 8dd1ee6ff30fd481dd33de93e5d613d11331c1f6
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Nov 7 14:36:38 2015 +0100
r600g: don't set predication on non-draw packets
This has no effect.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
commit 6cc8f6c6a72b1aab7bb506deb220e04ae50d8c2b
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Nov 7 14:00:30 2015 +0100
gallium/radeon: inline the r600_rings structure
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
commit 3d963abc81789870d86257956a8fc24f7c6b661b
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Nov 7 12:22:56 2015 +0100
radeonsi: prevent recursion in si_context_gfx_flush
The recursion can only occur if you modify need_cs_space to always flush.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
commit 8569f9a87ec8d1bea3946476d5cc0be2a58ea149
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Nov 7 13:43:18 2015 +0100
gallium/radeon: remove the IB flushing flag
Not needed anymore. A similar flag will be introduced in the next commit,
which will be private in radeonsi.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
commit 81d412e02ce7db644774202b175f1f24b1f262c7
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Nov 7 13:31:03 2015 +0100
gallium/radeon: move GFX/DMA flushing from add_to_buffer_list to need_cs_space
need_cs_space isn't invoked so often and is called before all commands too.
This is a lot cleaner. The code in radeon_add_to_buffer_list always seemed
dodgy to me.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
commit c6012a6650c894e57dba51f8e336f134aad13d61
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Nov 6 21:11:16 2015 +0100
radeonsi: rename cache flushing flags once more
KCACHE, TC L1 and TC L2 are renamed to:
- SMEM L1
- VMEM L1
- GLOBAL L2
You can easily tell what they are used for now.
Shaders must deal with coherency issues between both L1s manually,
e.g. by setting GLC=1 or by using s_dcache_*.
BOTH_ICACHE_KCACHE was an unused definition.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
commit 10130ccd8ca9e28e417268f4e5681b5c25398516
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Nov 7 12:07:31 2015 +0100
radeonsi: set the DISABLE_WR_CONFIRM flag on CI-VI as well
I missed this in commit c3e527f93d4281ad6e2ca165eaf6ff588e4faefa
radeonsi: only enable write confirmation on the last CP DMA packet
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
commit 40912dd91e96376517fb41bb4dc228b45fd1a01c
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Nov 5 23:56:38 2015 +0100
radeonsi: initialize SX_PS_DOWNCONVERT to 0 on Stoney
otherwise the SX or CB blocks can go bananas
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
Cc: mesa-stable at lists.freedesktop.org
commit f7757100f22f0d22eb8c9f232915b9d9a28cc781
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Nov 3 19:35:46 2015 +0100
radeonsi: add glClearBufferSubData acceleration
8-bit and 16-bit clears which are not aligned to dwords are done in software.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
commit 19773f98055ec6976b5f5c2d0d83245f96206ec4
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Nov 6 23:16:11 2015 +0100
radeonsi: add SI_SAVE_FRAGMENT_STATE blitter flag
Buffer clears via transform feedback won't set this.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
commit 19a9c1ecc7e2aee621b784cf452674373ec8499f
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Nov 6 23:41:15 2015 +0100
gallium/u_blitter: add support for multi-dword clear values in clear_buffer
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
commit e15c5c7a069a8dd8e0ad97f0f405a85f0f52d9f4
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Nov 6 23:42:49 2015 +0100
radeonsi: fix a future crash in emit_cb_target_mask
This can't crash currently, but it would crash if clear_buffer
from u_blitter were used with a clean context.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
commit 65d0c558d5dfa0d10f3f169dd5af65ccc69e1899
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Nov 6 23:06:47 2015 +0100
radeonsi: fix unaligned clear_buffer fallback
This is unreachable currently, but it will be used by unaligned 8-bit and
16-bit fills.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
commit 7f1e34e6c80b4cc59822eaf0c1731cab46befa46
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Nov 5 12:24:20 2015 +0100
r600g: fix clear_buffer fallback with offset != 0
Discovered by luck. This code path hasn't been exercised since transform
feedback was implemented.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
commit 01526136badbc611b7dafa5a99934e7e8cf527e8
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Nov 7 19:31:55 2015 +0100
gallium/radeon: fix PIPE_QUERY_GPU_FINISHED
Broken by the addition of r600_multi_fence
in 3b37155a68acc351cba86a1fa142bd0de2192d4c
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89014
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 40663864d2ee46afe246c15f5c4e6e380bb81720
Author: Brian Paul <brianp at vmware.com>
Date: Fri Nov 13 08:02:05 2015 -0700
mesa: minor comment fix in blend.c
commit 5a5efbf804eb848553b85f498bf4c4340d748c3d
Author: Brian Paul <brianp at vmware.com>
Date: Fri Nov 13 08:01:29 2015 -0700
docs: add link to Coverity on developer utilities page
Signed-off-by: Brian Paul <brianp at vmware.com>
commit 00046393f80f2a13b21fce647f35e1a979f41d7d
Author: Brian Paul <brianp at vmware.com>
Date: Fri Nov 13 07:59:42 2015 -0700
docs: update VMware driver instructions
Use a LIBDIR variable, set per-platform.
Update the Mesa configuration flags.
Run update-initramfs or dracut, update /etc/modules
Signed-off-by: Brian Paul <brianp at vmware.com>
commit d1314de293e9e4a63c35f094c3893aaaed8580b4
Author: Daniel Stone <daniels at collabora.com>
Date: Sat Nov 7 18:25:31 2015 +0000
egl/wayland: Ignore rects from SwapBuffersWithDamage
eglSwapBuffersWithDamage accepts damage-region rectangles to hint the
compositor that it only needs to redraw certain areas, which was passed
through the wl_surface_damage request, as designed.
Wayland also offers a buffer transformation interface, e.g. to allow
users to render pre-rotated buffers. Unfortunately, there is no way to
query buffer transforms, and the damage region was provided in surface,
rather than buffer, co-ordinate space.
Users could in theory account for this themselves, but EGL also requires
co-ordinates to be passed in GL/mathematical co-ordinate space, with an
inversion to Wayland's natural/scanout co-ordinate space, so
transformations other than a 180-degree rotation will fail as EGL
attempts to subtract the region from (its view of the) surface height.
Pending creation and acceptance of a wl_surface.buffer_damage request,
which will accept co-ordinates in buffer co-ordinate space, pessimise to
always sending full-surface damage.
bce64c6c provides the explanation for why we send maximum-range damage,
rather than the full size of the surface: in the presence of buffer
transformations, full-surface damage may not actually cover the entire
surface.
Signed-off-by: Daniel Stone <daniels at collabora.com>
Reviewed-by: Pekka Paalanen <pekka.paalanen at collabora.co.uk>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit a29d922c1a19ecebb7c274f31248b00086cb4733
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Fri Nov 13 08:51:06 2015 +0100
Revert "nir/copy_propagate: do not copy-propagate MOV srcs with source modifiers"
The change proposed in the review leads to piglit regressions because
is_move() is used in other places and relies on the checks for source
modifiers to be there.
Revert this until we agree on a better solution.
commit 5f004fd1970338c9a1db51b421ae0f6f687661d9
Author: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Date: Thu Nov 12 16:14:07 2015 +0100
glsl: fix 'shared' layout qualifier related regressions
Commit 8b28b35 added 'shared' as a keyword for compute shaders
but it broke the existing 'shared' layout qualifier support for
uniform and shader storage blocks.
This patch fixes 578 dEQP-GLES31.functional.ssbo.* tests.
v2:
- Move SHARED to interface_block_layout_qualifier (Timothy)
- Don't remove "shared" case insensitive check (Timothy)
- Remove the clearing of shared_storage flag (Timothy)
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Reviewed-by: Timothy Arceri <timothy.arceri at collabora.com>
commit 8610cd6b8c71b92a8e68603c030961e36faa0ef4
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Fri Nov 6 12:08:49 2015 +0100
nir/copy_propagate: do not copy-propagate MOV srcs with source modifiers
If a source operand in a MOV has source modifiers, then we cannot
copy-propagate it from the parent instruction and remove the MOV.
v2: remove the check for source source modifiers from is_move() (Jason)
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 5f43e074d4a4e74b1238a5687da5d38e53ad4596
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Nov 12 21:52:37 2015 -0800
nir/vars_to_ssa: Delete dead output set code
This was a remnant of an early attempt to handle output reads in
vars_to_ssa. That attempt was abandon a long time ago but these few lines
were aparently left in the pass and managed to evade review.
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 226ba889a0f820b9f4b1132e379620d2688c96e7
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Nov 12 18:10:22 2015 -0800
nir/vars_to_ssa: Rework copy set handling in lower_copies_to_load_store
Previously, we walked through a given deref_node's copies and, after
lowering the copy away, removed it from both the source and destination
copy sets. This commit changes this to only remove it from the other
node's copy set (not the one we're lowering). At the end of the loop, we
just throw away the copy set for the node we're lowering since that node no
longer has any copies. This has two advantages:
1) It's more efficient because we're doing potentially half as many set
search operations.
2) It now properly handles copies from a node to itself. Perviously, it
would delete the copy from the set when processing the destinatioon and
then assert-fail when we couldn't find it for the source.
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92588
Reviewed-by: Timothy Arceri <timothy.arceri at collabora.com>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 4bbf2ac06e71102a65b4d0427a0ba630a3c2477c
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Nov 10 14:13:47 2015 -0800
nir/validate: Allow subroutine types for the tails of derefs
The shader-subroutine code creates uniforms of type SUBROUTINE for
subroutines that are then read as integers in the backends. If we ever
want to do any optimizations on these, we'll need to come up with a better
plan where they are actual scalars or something, but this works for now.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92859
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 79f68306d23bfb48ef645c4bded8ee7b74d2d661
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Fri Oct 16 10:14:39 2015 -0700
mesa: Replace gl_extensions::EXT_texture3D with ::dummy_true
Mesa unconditionally sets this driver flag to true in
_mesa_init_extensions(). There is therefore no need for
the driver to communicate support for this extension.
Replace the driver capability flag with ::dummy_true.
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit 2de2e1702b4fab73b1f577fa4a21b7bd0a7040dd
Author: Brian Paul <brianp at vmware.com>
Date: Thu Nov 12 15:59:21 2015 -0700
mesa: fix MSVC build break in extensions.h
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 39f51ec96f00f601b9c4d4e321dacb3af9dc866f
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Sep 14 16:23:29 2015 -0400
nvc0/ir: add support for TGSI_SEMANTIC_HELPER_INVOCATION
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit e3d9dbe3046c4fd10c6b4c66d8016e908ea7c140
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Sep 14 16:23:04 2015 -0400
gallium: add support for gl_HelperInvocation semantic
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Glenn Kennard <glenn.kennard at gmail.com>
commit 20748318c5b870fc27f699637041e67a67321f5f
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Sep 14 16:13:43 2015 -0400
glsl: add gl_HelperInvocation system value
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit b52cb9ec6ab3b74f754ccf8472b9db2b6d8c3333
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Wed Nov 11 22:02:06 2015 -0800
glsl: Correctly handle vector extract on function parameter
This commit accidentally used a '==' when '=' was intended.
commit 96b22fb080894ba1840af2372f28a46cc0f40c76
Author: Kristian Høgsberg Kristensen <krh at bitplanet.net>
Date: Wed Nov 4 14:58:54 2015 -0800
glsl: Use array deref for access to vector components
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit a16ffb743ced9fde80b2485dfc2d86ae74e86f25
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Thu Oct 15 12:34:43 2015 -0700
mesa: In helpers, only check driver capability for meta
Make API context and version checks done by the helper functions pass
unconditionally while meta is in progress. This transparently makes
extension checks solely dependent on struct gl_extensions while in meta.
v2: Use an 8-bit data type instead of a GLuint
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit 5645770742d21b0a2ae0fe3ecce135933cd9b4fc
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Mon Oct 26 15:22:24 2015 -0700
mesa/extensions: Prefix global struct and extension type
Rename the following types and variables:
* struct extension -> struct mesa_extension,
like the mesa_format type.
* extension_table -> _mesa_extension_table,
like the _mesa_extension_override_{enables,disables} structs.
Suggested-by: Marek Olšák <marek.olsak at amd.com>
Suggested-by: Chad Versace <chad.versace at intel.com>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit ab129a44ae3a7515eb4642c068299673c890fb73
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Thu Sep 17 15:49:40 2015 -0700
mesa: Generate a helper function for each extension
Generate functions which determine if an extension is supported in the
current context. Initially, enums were going to be explicitly used with
_mesa_extension_supported(). The idea to embed the function and enums
into generated helper functions was suggested by Kristian Høgsberg.
For performance, the function body no longer uses
_mesa_extension_supported() and, as suggested by Chad Versace, the
functions are also declared static inline.
v2: Place function qualifiers on separate line (Chad)
v3: Move function curly brace to new line (Chad)
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit eda15abd84af575d3bde432e2163e30d743a7c87
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Mon Sep 21 11:23:33 2015 -0700
mesa/extensions: Replace extension::api_set with ::version
The api_set field has no users outside of _mesa_extension_supported().
Remove it and allow the version field to take its place.
The brunt of the transformation was performed with the following vim commands:
s/\(GL [^,]\+\),\s*\d*,\s*\d*\(,\s*\d*\)\(,\s*\d*\)/\1, GLL, GLC\2\3/g
s/\(GLL [^,]\+\)\,\s*\d*/\1, GLL/g
s/\(GLC [^,]\+\)\(,\s*\d*\),\s*\d*\(,\s*\d*\)\(,\s*\d*\)/\1\2, GLC\3\4/g
s/\( ES1[^,]*\)\(,\s*\(\w\|\d\)\+\)\(,\s*\(\w\|\d\)\+\),\s*\d*/\1\2\4, ES1/g
s/\( ES2[^,]*\)\(,\s*\(\w\|\d\)\+\)\(,\s*\(\w\|\d\)\+\)\(,\s*\(\w\|\d\)\+\),\s*\d*/\1\2\4\6, ES2/g
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit a82bc779af37334ebc874d38951324f5f0b651cd
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Tue Sep 8 12:41:18 2015 -0700
mesa/extensions: Use _mesa_extension_supported()
Replace open-coded checks for extension support with
_mesa_extension_supported().
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit f6a818e76d09633c37057703ba1796ecd5678317
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Wed Sep 2 11:53:16 2015 -0700
mesa/extensions: Create _mesa_extension_supported()
Create a function which determines if an extension is supported in the
current context.
v2: Use common variable names (Emil)
Insert new line between variables and return statement (Chad)
Rename api_set variable to api_bit (Chad)
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit f47df8f729abfda177120a1437197372fd19b83f
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Tue Sep 8 12:25:56 2015 -0700
mesa/extensions: Add extension::version
Enable limiting advertised extension support by context version with
finer granularity. This new field is currently unused and is set to
0 everywhere. When it is used, a value of 0 will indicate that the
extension is supported for any version of a context.
v2: Use uint*t type for version and note the expected values (Emil)
Use an 8-bit data type
Reformat macro for better readability (Chad)
v3: Note preparatory nature of commit (Chad)
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit 8bd82a91c05804260041b572b1a5d812cb58ae96
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Wed Sep 16 11:27:38 2015 -0700
mesa/extensions: Move entries entries to separate file
With this infrastructure set in place, we can now reuse the entries to
generate useful code.
v2: Add the new file into Makefile.sources (Emil)
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit c0b568f3db7968bde2b6c6e887522f2c208188cf
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Wed Sep 2 11:26:57 2015 -0700
mesa/extensions: Wrap array entries in macros
Now that we're using macros, remove the redundant text from each entry.
Remove comments between the entries to make editing easier and separate
the sections with blank lines. Structure the EXT macros in a way that
helps reviewers verify that no meaning has been altered.
v2: Indent the entries (Chad)
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit e5af09f9ba4a2bca256d7cd1087187fd8efe7f00
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Fri Sep 11 09:59:32 2015 -0700
mesa/extensions: Remove array sentinel
Simplify future updates to the extension struct array by removing
the sentinel.
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit 74e48e95441e5735a03934243abb1051875e053a
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Jun 29 15:59:37 2015 -0700
i965: Check instructions appear only on supported hardware.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 0b45d47f71f57f685ce1a12a3dcd4fdb63c160b4
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Jun 29 14:08:51 2015 -0700
i965: Add initial assembly validation pass.
Initially just checks that sources are non-NULL, which would have
alerted us to the problem fixed by commit 6c846dc5.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 34ed45557e9b8a834af2816e774165a0ee7acdd2
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Oct 21 15:23:10 2015 -0700
i965: Add annotation_insert_error() and support for printing errors.
Will allow annotations to contain error messages (indicating an
instruction violates a rule for instance) that are printed after the
disassembly of the block.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit a280e83d71bb046098ed5380cb053318f9e8cf8e
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Oct 7 21:04:48 2015 -0700
i965: Combine assembly annotations if possible.
Often annotations are identical between sets of consecutive
instructions. We can perhaps avoid some memory allocations by reusing
the previous annotation.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 93e371c140cb1aa438ce3c1a9946811d92032897
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Jun 29 14:05:27 2015 -0700
i965: Set annotation_info's mem_ctx.
It was being memset to 0 previously.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 9ab45b4df91fadcbbec62828265644d7463b78bb
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu Oct 15 11:38:43 2015 -0700
i965: Don't consider control flow instructions to have sources.
And why did IFF have a destination?
I suspect that once upon a time the disassembler used this information
to know which fields to find the jump targets in. The jump targets have
moved, so the disassembler has to know how to handle these
per-generation anyway.
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 0865e743c18cb7ba65962d794be8387d6edc0b8a
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Jun 29 14:03:55 2015 -0700
i965: Fill out instruction list.
Add some instructions: illegal, movi, sends, sendsc.
Remove some instructions with reused opcodes: msave, mrestore, push,
pop, goto. I did have some gross code for disassembling opcodes
per-generation, but there's very little meaningful overlap so it's
probably not needed.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 238877207eda2d7513cb0d2b415f8fc7ac821d0e
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Jun 29 15:05:19 2015 -0700
ralloc: Set *start in ralloc_vasprintf_rewrite_tail() if str is NULL.
We were leaving it undefined, even though we were writing a string to
*str.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 903050694bd42b658145b96e501c803c3c21127e
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu Oct 8 14:19:10 2015 -0700
i965: Consolidate is_3src() functions.
Otherwise I'll have to add another later in this series.
commit 3e74038280319cf02c55f3879d95d7c1aec210fe
Author: Brian Paul <brianp at vmware.com>
Date: Tue Nov 10 14:49:17 2015 -0700
st/wgl: add a comment about recursive locking in stw_make_current()
Reviewed-by: Sinclair Yeh <syeh at vmware.com>
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
commit f45b644e11127e07fe909f418d1c0e2ca3285743
Author: Brian Paul <brianp at vmware.com>
Date: Tue Nov 10 14:49:01 2015 -0700
st/wgl: add a lock assertion in stw_framebuffer_from_hwnd_locked()
Reviewed-by: Sinclair Yeh <syeh at vmware.com>
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
commit a1c9feafd592d13f8215e7a535c68a03fd84849e
Author: José Fonseca <jfonseca at vmware.com>
Date: Tue Nov 10 14:41:30 2015 -0700
st/wgl: add some mutex checking code
This would have caught the locking bug that was fixed in the earlier
"st/wgl: fix locking issue in stw_st_framebuffer_present_locked()"
patch.
v2: minor coding style changes by Brian.
Reviewed-by: Sinclair Yeh <syeh at vmware.com>
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
commit 166769fe4bf4042ecb2a54ee5c7b23e3b0cd471d
Author: Brian Paul <brianp at vmware.com>
Date: Tue Nov 10 14:51:26 2015 -0700
st/wgl: rename stw_framebuffer_release() to stw_framebuffer_unlock()
To match the new stw_framebuffer_lock() function.
Reviewed-by: Sinclair Yeh <syeh at vmware.com>
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
commit dabc423ed0f946bc32268a42dc8fee12a1cd0b0a
Author: Brian Paul <brianp at vmware.com>
Date: Tue Nov 10 14:38:25 2015 -0700
st/wgl: reimplement stw_framebuffer::mutex with CRITICAL_SECTION
v2: update comments on the stw_framebuffer::mutex field regarding locking
order.
Reviewed-by: Sinclair Yeh <syeh at vmware.com>
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
commit f71508ae793aaea999d3aa5bdd5f4cf157f016c6
Author: Brian Paul <brianp at vmware.com>
Date: Tue Nov 10 14:34:51 2015 -0700
st/wgl: include u_debug.h
To get declaration for debug_printf() directly instead of getting it
indirectly through os_thread.h
Reviewed-by: Sinclair Yeh <syeh at vmware.com>
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
commit fce68832c5e06a046b69fbad1e1424aaec6fc0b2
Author: Brian Paul <brianp at vmware.com>
Date: Tue Nov 10 14:24:18 2015 -0700
st/wgl: reimplement stw_device::fb_mutex with CRITICAL_SECTION
Reviewed-by: Sinclair Yeh <syeh at vmware.com>
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
commit fa30de7643ca6c70ac2661684b22f7b220a40b0b
Author: Brian Paul <brianp at vmware.com>
Date: Tue Nov 10 14:10:45 2015 -0700
st/wgl: re-implement stw_device::ctx_mutex with CRITICAL_SECTION
This is Windows-only code so we can use the native Win32 functions for
critical sections. This will also allow us to (cleanly) add some mutex
check/debug code in subsequent patches.
Reviewed-by: Sinclair Yeh <syeh at vmware.com>
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
commit a02385cd691df9dd35844a727350db72b17f586b
Author: Brian Paul <brianp at vmware.com>
Date: Thu Nov 12 09:06:25 2015 -0700
gallium/hud: add cpu graph support for Windows
We support "cpu" but not "cpu#" because there's no good way of querying
per-cpu usage. Also, the cpu usage is for the process, not the whole
system.
Original code cobbled together by Brian and then fixed/polished by Jose.
Signed-off-by: Brian Paul <brianp at vmware.com>
commit f2fe6072617fd77f1abe213ff8fd2c233908b63d
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Mon Nov 2 13:36:19 2015 +0200
glsl: set matrix_stride for non matrices with atomic counter buffers
Patch sets matrix_stride as 0 for non matrix uniforms that are in a
atomic counter buffer. Matrix stride calculation for actual matrix
uniforms is done during link_assign_uniform_locations.
From ARB_program_interface_query specification:
GL_MATRIX_STRIDE:
"For active variables not declared as a matrix or array of matrices,
zero is written to <params>. For active variables not backed by a
buffer object, -1 is written to <params>, regardless of the variable
type."
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Marta Lofstedt <marta.lofstedt at intel.com>
commit 7e6dac11866d264c21a108b9623114943d6e88ec
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Thu Nov 5 12:52:26 2015 +0200
mesa: validate precision of varyings during ValidateProgramPipeline
Fixes following failing ES3.1 CTS tests:
ES31-CTS.sepshaderobjs.InterfacePrecisionMatchingFloat
ES31-CTS.sepshaderobjs.InterfacePrecisionMatchingInt
ES31-CTS.sepshaderobjs.InterfacePrecisionMatchingUInt
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 5bd122cad9d16596f89260f3b115cd0fb72cb886
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Thu Nov 5 12:23:17 2015 +0200
glsl: do not lose precision information when packing varyings
This information will be used by cross stage validation of varyings
for pipeline objects.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit f84bc57d7dc02fceb805803131426c791eadeff9
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Tue Nov 10 08:22:07 2015 +0200
glsl: Add precision information to ir_variable
We will need this later on when we implement proper support for
precision qualifiers in the drivers and also to do link time checks for
uniforms as indicated by the spec.
This patch also adds compile-time checks for variables without precision
information (currently, Mesa only checks that a default precision is set
for floats in fragment shaders).
As indicated by Ian, the addition of the precision information to
ir_variable has been done using a bitfield and pahole to identify an
available hole so that memory requirements for ir_variable stay the
same.
v2 (Ian):
- Avoid if-ladders by defining arrays of supported sampler names and
indexing
into them with type->sampler_array + 2 * type->sampler_shadow
- Make the code that selects the precision qualifier to use an utility
function
- Fix a typo
v3 (Tapani):
- rebased
- squashed in "Precision qualifiers are not allowed on structs"
- fixed select_gles_precision for sampler arrays
- fixed precision_qualifier_allowed for arrays of structs
v4 (Tapani):
- add atomic_uint handling
- do not allow precision qualifier on images
(issues reported by Marta)
v5 (Tapani):
- support precision qualifier on image types
v6 (Tapani):
- set precision qualifier on interface block members
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit 9a00e1a69deba6ffc4c21fdaa77de4a3d74717ba
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Thu Nov 5 08:18:46 2015 +0200
glsl: Move the definition of precision_qualifier_allowed
We will need this to build later patches
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit e6629d814f9a860b3a5390684be06370b270be14
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Thu Feb 26 12:15:18 2015 +0100
glsl: Add user-defined default precision qualifiers to the symbol table
Notice that the spec requires that a default precision has been set for every
type used by a shader that can use a precision qualifier and does not have a
predefined precision, however, at the moment, Mesa only checks this for floats
in the fragment shader. This is probably because the GLSL ES 1.0 specs mentions
this case specifically, but GLSL ES 3.0 clarifies that the same applies to
other types:
"The fragment language has no default precision qualifier for floating point
types. Hence for float, floating point vector and matrix variable
declarations, either the declaration must include a precision qualifier or
the default float precision must have been previously declared. Similarly,
there is no default precision qualifier for the following sampler types in
either the vertex or fragment language:
sampler3D;
samplerCubeShadow;
sampler2DShadow;
sampler2DArray;
sampler2DArrayShadow;
isampler2D;
isampler3D;
isamplerCube;
isampler2DArray;
usampler2D;
usampler3D;
usamplerCube;
usampler2DArray;"
we will fix this in a later patch.
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit e3082fb2732c2af836875201b8d7f49e864c8e4e
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Thu Feb 26 12:15:17 2015 +0100
glsl: Add default precision qualifiers to the symbol table
The GLSL ES spec specifies default precision qualifiers for certain types,
so populate the symbol table with these.
Notice that the desktop GLSL spec also indicates defaults for some types
but this is not really useful since precision qualifiers are completely
ignored in desktop GLSL.
v2: simplify and add samplerExternalOES, specified by
OES_EGL_image_external (Tapani)
v3: add atomic_uint (reported missing by Marta)
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit d6a61673543deeebac773801cbd717b7a342626e
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Thu Feb 26 12:15:16 2015 +0100
glsl: Add API to put default precision qualifiers in the symbol table
These have scoping rules that match the ones defined for other things such
as variables, so we want them in the symbol table.
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit d4fdb84f80dd3dbad2b71ea6e877f24dc625aa2a
Author: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Date: Tue Nov 10 13:45:21 2015 +0100
i965/fs/nir: fix the number of register written by FS_OPCODE_GET_BUFFER_SIZE
FS_OPCODE_GET_BUFFER_SIZE is calculated with a resinfo's sampler message.
This patch adjusts the number of registers written by the opcode
following what the PRM spec says about the number of registers written
by the SIMD8 and SIMD16's writeback messages for sampler messages.
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 55314c5be4cbf933ab7fbd20f6aa49207e04c946
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Fri Nov 6 18:12:27 2015 -0800
i965/skl/gt4: Fix URB programming restriction.
The comment in the code details the restriction. Thanks to Ken for having a very
helpful conversation with me, and spotting the blurb in the link I sent him :P.
There are still stability problems for me on GT4, but this definitely helps with
some of the failures.
v2: Comment fixes
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit c4182bb9b0897b4a4ac4f06b54fc7f6a2ddeb105
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Nov 9 12:39:05 2015 -0500
nv50,nvc0: add ARB_clear_texture support
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit ae39b0fda81ce592b8c965b715469650d35e5fef
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Tue Mar 4 21:51:55 2014 -0500
st/mesa: implement ARB_clear_texture
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 3695b253f908b58290d69e2d770209abf0c6beee
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Nov 9 13:27:07 2015 -0500
gallium: add PIPE_CAP_CLEAR_TEXTURE and clear_texture prototype
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 725fcdfbb11ff4c4399d58e08403e4e0064a8c5e
Author: Timothy Arceri <timothy.arceri at collabora.com>
Date: Wed Oct 28 07:42:49 2015 +1100
glsl: add helper to check for enhanced layouts support
Reviewed-by: Emil Velikov <emil.velikov at collabora.co.uk>
commit 82e4f22d1ec65269328bbd472261d6a8e0689558
Author: Timothy Arceri <timothy.arceri at collabora.com>
Date: Mon Oct 5 00:01:45 2015 +1100
mesa: add ARB_enhanced_layouts
Reviewed-by: Emil Velikov <emil.velikov at collabora.co.uk>
commit df8af7d75155845d12d5a14a3a5ca644f07cb3b1
Author: Dave Airlie <airlied at redhat.com>
Date: Thu Nov 12 08:34:18 2015 +1000
r600: initialised PGM_RESOURCES_2 for ES/GS
This fixes the corruption on rendering that we are seeing in
certain geometry shaders.
Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=91780
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Tested / Reviewed-by: Glenn Kennard <glenn.kennard at gmail.com>
Cc: "10.6" "11.0" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 918bda23dda36004c95f6441328ecc892e068886
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Nov 4 23:05:07 2015 -0800
i965: Split nir_emit_intrinsic by stage with a general fallback.
Many intrinsics only apply to a particular stage (such as discard).
In other cases, we may want to interpret them differently based on
the stage (such as load_primitive_id or load_input).
The current method isn't that pretty - we handle all intrinsics in
one giant function. Sometimes we assert on stage, sometimes we forget.
Different behaviors are handled via if-ladders based on stage.
This commit introduces new nir_emit_<stage>_intrinsic() functions,
and makes nir_emit_instr() call those. In turn, those fall back to
the generic nir_emit_intrinsic() function for cases they don't want
to handle specially.
This makes it clear which intrinsics only exist in one stage, and makes
it easy to handle inputs/outputs differently for various stages.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 912babba7bf1abd3caa49f6372d581ae1afe7e84
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Nov 8 04:46:38 2015 -0500
mesa/copyimage: allow width/height to not be multiples of block
For compressed textures, the image size is not necessarily a multiple of
the block size (e.g. the last mip levels). Section 18.3.2 (Copying
Between Images) of the OpenGL 4.5 Core Profile spec says:
An INVALID_VALUE error is generated if the dimensions of either
subregion exceeds the boundaries of the corresponding image
object, or if the image format is compressed and the dimensions of
the subregion fail to meet the alignment constraints of the
format.
and Section 8.7 (Compressed Texture Images) says:
An INVALID_OPERATION error is generated if any of the following
conditions occurs:
* width is not a multiple of four, and width + xoffset is not
equal to the value of TEXTURE_WIDTH.
* height is not a multiple of four, and height + yoffset is not
equal to the value of TEXTURE_HEIGHT.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92860
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Cc: mesa-stable at lists.freedesktop.org
commit 80890eb0d322483fb13558afddc4feae5210f996
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Aug 19 22:15:33 2015 -0700
i965/brw_reg: Add a brw_VxH_indirect helper
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 68993f77cd9db5b9cb77fe3e7d1c451cf9bd6538
Author: Brian Paul <brianp at vmware.com>
Date: Tue Nov 10 17:03:37 2015 -0700
mesa: remove old comments in arrayobj.c
commit 9870a5c6c9664d34432ba551ab9dce6ae79beaa4
Author: Brian Paul <brianp at vmware.com>
Date: Mon Nov 9 17:25:22 2015 -0700
st/wgl: clarify code in stw_framebuffer_from_hwnd_locked()
Just a minor code change to make it obvious that NULL is returned when
we don't find the given HWND.
Reviewed-by: Sinclair Yeh <syeh at vmware.com>
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
Reviewed-by: José Fonseca <jfonseca at vmware.com>
commit 004ed6f4a9eb50d7a5e79040b036beff63a3440b
Author: Brian Paul <brianp at vmware.com>
Date: Mon Nov 9 17:35:55 2015 -0700
st/wgl: improve some function comments
In particular, explain when stw_framebuffer objects are
locked/unlocked/etc.
Reviewed-by: Sinclair Yeh <syeh at vmware.com>
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
Reviewed-by: José Fonseca <jfonseca at vmware.com>
commit b93cb6c1dc6e87fe2528c46ec1c30c6a2a628587
Author: Brian Paul <brianp at vmware.com>
Date: Mon Nov 9 17:19:35 2015 -0700
st/wgl: whitespace/formatting fixes
commit eb812921ac3a9b43e2cdd5dc65db34ba3fe9189b
Author: Brian Paul <brianp at vmware.com>
Date: Mon Nov 9 14:51:56 2015 -0700
st/wgl: fix locking issue in stw_st_framebuffer_present_locked()
When stw_st_framebuffer_present_locked() is called, the
stw_framebuffer's mutex will already be locked. Normally, the
stw_framebuffer_present_locked() function calls
stw_framebuffer_release() to unlock the mutex when it's done. But if
for some reason the 'resource' pointer in
stw_st_framebuffer_present_locked() is null, we'd return without
unlocking the stw_framebuffer. This fixes that to avoid potential
deadlocks.
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
commit e42a29531ae3d5dedb72011da2947357dfa8715b
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Nov 9 23:55:58 2015 -0800
i965: Print force_writemask_all in dump_instructions().
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit ecb5e0a9861679846a5dbae2a8511b0e624f8f6e
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Nov 25 02:59:28 2014 -0800
i965: Combine BRW_NEW_*_BINDING_TABLE dirty bits.
A while back, we moved to directly emitting the Gen7+ state when
constructing the binding tables. These flags are only used on
Gen4-6, which emit all the binding table pointers at once.
We gain nothing by having separate flags, so combine them.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit a2987ff57f08325f6e1dedae578bd6251a22b2b4
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Jul 24 21:15:35 2015 -0700
i965: Map GL_PATCHES to 3DPRIM_PATCHLIST_n.
Inspired by a patch by Fabian Bieler.
Fabian defined a _3DPRIM_PATCHLIST_0 macro (which isn't actually a valid
topology type); I instead chose to make a macro that takes an argument.
He also took the number of patch vertices from _mesa_prim (which was set
to ctx->TessCtrlProgram.patch_vertices) - I chose to use it directly to
avoid the need for the VBO patch.
v2: Change macro to 0x20 + (n - 1) instead of 0x1F + n to better match
the documentation (suggested by Ian).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit cbb7d90e5784b1e44c1801f74c3088638940442d
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Wed Nov 11 11:18:27 2015 +0000
docs: add news item and link release notes for 11.0.5
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
commit 6435d8ac5a54b6c09b4a8ba5aa83225acee132c0
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Wed Nov 11 11:10:30 2015 +0000
docs: add sha256 checksums for 11.0.5
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
(cherry picked from commit 66c949d0a19b1e601243be22b6506528b866388b)
commit 07948b03fbcbe9a36c8251ed209cac7f2508ef30
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Wed Nov 11 10:05:57 2015 +0000
docs: add release notes for 11.0.5
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
(cherry picked from commit ee57c22141c42d9b511a7dfa5971c4428cd1c6e7)
commit 3f45d29fe435266b137e8007acebcda498690b27
Author: Glenn Kennard <glenn.kennard at gmail.com>
Date: Sat Oct 17 16:53:28 2015 +0200
r600g: Pass conservative depth parameters to hw
Supported on R700 and up.
Signed-off-by: Glenn Kennard <glenn.kennard at gmail.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit b3e793f2db0e294c2b18e030a45c6253f20a16a6
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Nov 11 09:05:50 2015 +1000
Revert "r600g: Pass conservative depth parameters to hw"
This reverts commit a1fc78911e9a6439db94d6ae91d5672c76e5fb1c.
I pushed the wrong patch.
commit c878d61124397706072e0f7f5a694a8bf644cc91
Author: Glenn Kennard <glenn.kennard at gmail.com>
Date: Fri Oct 16 01:53:47 2015 +0200
r600g: Implement ARB_texture_view
Signed-off-by: Glenn Kennard <glenn.kennard at gmail.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit a1fc78911e9a6439db94d6ae91d5672c76e5fb1c
Author: Glenn Kennard <glenn.kennard at gmail.com>
Date: Sat Oct 17 00:52:39 2015 +0200
r600g: Pass conservative depth parameters to hw
Supported on R700 and up.
Signed-off-by: Glenn Kennard <glenn.kennard at gmail.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit de51676b410ff3ccab1df765f8eee15126c9de4c
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Thu Oct 22 15:32:13 2015 +0200
i965/nir/opt_peephole_ffma: Bypass fusion if any operand of fadd and fmul is a const
When both fadd and fmul instructions have at least one operand that is a
constant and it is only used once, the total number of instructions can
be reduced from 3 (1 ffma + 2 load_const) to 2 (1 fmul + 1 fadd); because
the constants will be progagated as immediate operands of fmul and fadd.
This patch detects these situations and prevents fusing fmul+fadd into ffma.
Shader-db results on i965 Haswell:
total instructions in shared programs: 6235835 -> 6225895 (-0.16%)
instructions in affected programs: 1124094 -> 1114154 (-0.88%)
total loops in shared programs: 1979 -> 1979 (0.00%)
helped: 7612
HURT: 843
GAINED: 4
LOST: 0
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit fb3b5669cee85781b603f612228387e9a2e4120f
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Fri Oct 23 16:31:41 2015 +0200
util: Add list_is_singular() helper function
Returns whether the list has exactly one element.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 94ff35204dba0ddbd7f5c4342206c8acba22d32f
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Thu Oct 22 15:25:23 2015 +0200
nir/nir_opt_peephole_ffma: Move this lowering pass to the i965 driver
Because the next patch will add an optimization that is specific to i965,
we want to move this loweing pass to that driver altogether.
This is safe because i965 is the only consumer.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 96b22fb080894ba1840af2372f28a46cc0f40c76
Author: Kristian Høgsberg Kristensen <krh at bitplanet.net>
Date: Wed Nov 4 14:58:54 2015 -0800
glsl: Use array deref for access to vector components
We've assumed that we could lower per-component vector access from
vec[i] = scalar
to
vec = ir_triop_vector_insert(vec, scalar, i)
but with SSBOs (and compute shader SLM and tesselation outputs) this is
no longer valid. If a vector is "externally visible", multiple threads
can write independent components simultaneously. With lowering to
ir_triop_vector_insert, each thread read the entire vector, changes one
component, then writes out the entire vector. This is racy.
Instead of generating a ir_binop_vector_extract when we see v[i], we
generate ir_dereference_array. We then add a lowering pass to lower the
ir_dereference_array to ir_binop_vector_extract for rvalues and for to
vector_insert for lvalues in a separate lowering pass.
The resulting IR is the same as before, but we now have a window between
ast->ir conversion and the lowering pass where v[i] appears in the IR as
an array deref. This lets us run lowering passes that lower the vector
access to I/O (eg for SSBO load/store) before we lower the per-component
access to full vector writes.
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Signed-off-by: Kristian Høgsberg Kristensen <krh at bitplanet.net>
commit 60dd5287ff8dbbbe0dbe76bdff6d13c7a5ea9ef0
Author: Kristian Høgsberg Kristensen <krh at bitplanet.net>
Date: Wed Nov 4 14:55:32 2015 -0800
glsl: Lower UBO and SSBO access in glsl linker
All GLSL IR consumers run this lowering pass so we can move it to the
linker. This moves the pass up quite a bit, but that's the point: it
needs to run before we throw away information about per-component vector
access.
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Signed-off-by: Kristian Høgsberg Kristensen <krh at bitplanet.net>
commit f0e95c2500fdb720d4102976f17361c294e1f3a3
Author: Kristian Høgsberg Kristensen <krh at bitplanet.net>
Date: Wed Nov 4 14:50:51 2015 -0800
glsl: Drop exec_list argument to lower_ubo_reference
We always pass in shader->ir and we already pass in the shader, so just
drop the exec_list. Most passes either take just a exec_list or a
shader, so this seems more consistent.
Reviewed-by: Timothy Arceri <timothy.arceri at collabora.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Signed-off-by: Kristian Høgsberg Kristensen <krh at bitplanet.net>
commit 213f86416f5a107d3f517e049df27fc5c5a9a28e
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Sat Oct 31 16:31:59 2015 -0400
nir/glsl: switch to using the builder
v2: use nir_bulder_cf_insert (Ken)
Signed-off-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit fbbfb7c0250b105555a9869e80bc9c77adf1b997
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Fri Oct 30 23:56:49 2015 -0400
nir/glsl: make emit() take nir_ssa_def * sources
Again, this matches what the builder will have to do.
Signed-off-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit a60e990dd25e2fb45799a7a5cfa58abc9abf7665
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Fri Oct 30 23:47:46 2015 -0400
nir/glsl: convert nir_visitor::result to a nir_ssa_def *
Its only user now returns a nir_ssa_def *, and we'll need this since the
builder returns a nir_ssa_def *.
Signed-off-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 30fe8eaa8e65e656d2bc95f499791eebea7d7dc9
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Fri Oct 30 23:32:50 2015 -0400
nir/glsl: make evaluate_rvalue() return a nir_ssa_def *
A long time ago, before NIR was even merged to master, glsl_to_nir used
registers and these sources were actually register sources. But nowadays
everything in glsl_to_nir is an SSA value, so stop pretending that by
evaluating an rvalue we can get an arbitrary nir_src. Most importantly,
we need this since the builder takes nir_ssa_def * sources directly.
Signed-off-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 6f4216232921370e513e56d38cf894c94ae63fa6
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Mon Nov 9 22:25:27 2015 +0000
st/mesa: Destroy buffer object's mutex.
Ideally we should have a _mesa_cleanup_buffer_object function in
src/mesa/bufferobj.c so that the destruction logic resided in a single
place.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit db54673b54ee7e2c49d5aa6f77d2fff3eed0aa24
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Oct 9 15:49:49 2015 -0700
nir: Store PatchInputsRead and PatchOutputsWritten in nir_shader_info.
These tessellation shader related fields need plumbing through NIR.
v2: Use uint32_t instead of uint64_t to match the source type of
GLbitfield (caught by Iago Toral).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 437d7b611972c52fac32cb54038d3b278f66fd5a
Author: Eric Anholt <eric at anholt.net>
Date: Mon Nov 9 09:12:20 2015 -0800
vc4: Avoid loading undefined (newly-allocated) FBO contents.
Since X has undefined contents in new pixmaps, it will allocate new
textures for an FBO and draw to them without an explicit clear. For
VC4, it's much faster to emit a clear than the load of the actual
undefined memory contents, so just do that instead.
commit 5980389bbf98b8186ba6a06392d92b82fa9efad3
Author: Eric Anholt <eric at anholt.net>
Date: Mon Nov 9 08:56:01 2015 -0800
vc4: Return NULL when we can't make our shadow for a sampler view.
I'm not sure what the caller does is appropriate (just have a NULL sampler
at this slot), but it fixes the immediate crash.
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
commit eb8fb0064dbde7a363c2f99466a51b346b09a029
Author: Eric Anholt <eric at anholt.net>
Date: Fri Nov 6 11:07:25 2015 -0800
vc4: Return GL_OUT_OF_MEMORY when buffer allocation fails.
I was afraid our callers weren't prepared for this, but it looks like
at least for resource creation, mesa/st throws an error appropriately.
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
commit 84608e07e7f45b14a77e4f771484f0091a6e7c14
Author: Eric Anholt <eric at anholt.net>
Date: Tue Oct 27 16:14:05 2015 -0700
vc4: Add CL dumping for GL_ARRAY_PRIMITIVE.
commit 855a3ca598734273f53c5e316f1d825aea3dd6da
Author: Eric Anholt <eric at anholt.net>
Date: Mon Nov 9 08:51:47 2015 -0800
vc4: Fix a compiler warning.
commit fb3da129d1086df21122f032dd64d4b1c480cb70
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Tue Jul 28 15:00:47 2015 -0700
glsl: Use shared storage variable type for shared variables
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Timothy Arceri <timothy.arceri at collabora.com>
commit 32746fc9b49db5eccdc228e12cbce4734f1020f9
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Tue Jul 28 14:56:49 2015 -0700
glsl: Add shared variable type
Shared variables are stored in a common pool accessible by all threads
in a compute shader local work group.
These variables are similar to OpenCL's local/__local variables.
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Timothy Arceri <timothy.arceri at collabora.com>
commit c0ac4740a75f0701637df1ea82c450bb8c31a63a
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Sun Nov 8 19:07:43 2015 -0800
glsl: Add space to shader_storage in print_visitor
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Timothy Arceri <timothy.arceri at collabora.com>
commit 007d96730e03ae208b7baa981122b821e72efe92
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Tue Jul 28 14:56:49 2015 -0700
glsl: Align comments on variables types
v2:
* Split from patch to add ir_var_shader_shared (tarceri)
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Timothy Arceri <timothy.arceri at collabora.com>
commit 8b28b3553139c19efed6d54d0a21315867371864
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Sun Mar 15 13:53:06 2015 -0700
glsl: Parse shared keyword for compute shader variables
v2:
* Move shared parsing under storage qualifiers (tarceri)
* Fail to compile if shared is used in non-compute shader (tarceri)
* Use separate shared_storage bit for shared variables (tarceri)
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Timothy Arceri <timothy.arceri at collabora.com>
commit a4a46fe3fa566b2918f7323e7f0eede17f118f03
Author: Timothy Arceri <timothy.arceri at collabora.com>
Date: Sat Nov 7 10:53:53 2015 +1100
glsl: simplify interface block stream qualifier validation
Qualifiers on member variables are redundent all we need to do
if check if it matches the stream associated with the block and
throw an error if its not.
Reviewed-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Cc: Emil Velikov <emil.l.velikov at gmail.com>
commit 3ea3727998add8ba201e48934febc96be2cbdb99
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Nov 9 07:13:29 2015 -0500
docs: note that ARB_copy_image was added to nv50, nvc0 in this release
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 28f6faca518843b1ee30644a7bfb7aadd6551df1
Author: Brian Paul <brianp at vmware.com>
Date: Mon Jul 6 14:53:06 2015 -0600
st/wgl: add null pointer check for HUD texture
Fixes crash when using HUD with Nobel Clinician Viewer.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 75d1e363ff142b273b30d8cd236bb1c92c1b2f27
Author: Brian Paul <brianp at vmware.com>
Date: Mon Jun 15 19:14:42 2015 -0600
st/wgl: fix double-present on swapbuffers bug
The stw_st_framebuffer_present_locked() function was getting called
twice per SwapBuffers. First, when st_context_iface::flush() was
called from DrvSwapBuffers() because the ST_FLUSH_FRONT flag was
given. Second, by stw_st_swap_framebuffer_locked() which does the
actual SwapBuffers.
Two code changes:
1. Pass ST_FLUSH_END_OF_FRAME, instead of ST_FLUSH_FRONT.
2. Move the implementation of stw_flush_current_locked() into
DrvSwapBuffers() since it's not called anywhere else.
Not much change in perf for benchmarks like Lightsmark, but some simple
Mesa demos are measurably faster.
Reviewed-by: José Fonseca <jfonseca at vmware.com>
commit 8083943e2e5b3f2a7201650a586b597dff481d43
Author: Brian Paul <brianp at vmware.com>
Date: Mon Jun 1 08:45:07 2015 -0600
st/wgl: reorder pixel formats to put MSAA formats last
And put 8-bit/channel formats before 5/6/5 formats.
The ChoosePixelFormat() function seems to be finicky about format
selection. Putting the MSAA formats after the non-MSAA formats
means most apps get a low-numbered format. Now we generally get
the same pixel format regardless of whether using vgpu9 or 10.
VMware bug 1455030
Reviewed-by: José Fonseca <jfonseca at vmware.com>
commit e524df5ef32fe8fada0695417bd86413d836a6bb
Author: José Fonseca <jfonseca at vmware.com>
Date: Thu Mar 22 12:16:17 2012 +0000
st/wgl: Don't rely on GDI to bookkeep pixelformat for us.
This allows to use apitrace's retracediff script on Windows to retrace and
compare two builds of a Mesa based opengl32.dll/ICD side-by-side.
See also https://github.com/apitrace/apitrace/commit/e4a4f15f5b92e0abbd24d7d053da25f8278c9f64
commit 24abbaff9ad177624c2b4906c7d94f5d91ac3cc0
Author: Michel Dänzer <michel.daenzer at amd.com>
Date: Thu Aug 21 18:30:44 2014 +0900
winsys/radeon: Use CPU page size instead of hardcoding 4096 bytes v3
Fixes GPUVM conflicts with non-4K page size.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92738
v2: Replace sanitization of VM base address alignment with comment why
that's not necessary.
v3: Use unsigned instead of long as the type for the size_align member.
(Marek)
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Christian König <christian.koenig at amd.com> (v1)
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit df4f9b0236e3dcfb94eb160b599657a315822c82
Author: Christian König <christian.koenig at amd.com>
Date: Fri Nov 6 15:15:56 2015 -0500
radeon/uvd: add H.265/HEVC to legal notes
Signed-off-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
commit 519502d08fe5fefebd618e191eec4462dae3bd9a
Author: Leo Liu <leo.liu at amd.com>
Date: Wed Nov 4 16:38:28 2015 -0500
st/omx: add headless support
This will allow dec/enc/transcode without X
v2: use env override even with X,
use loader_open_device instead of open
v3: clean up
Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
commit 25526d77b1b69822145bcf11411e9398426e2984
Author: Leo Liu <leo.liu at amd.com>
Date: Thu Nov 5 11:56:37 2015 -0500
st/va: use vl screen drm support from vl_wys_drm
v2: move the dup to vl_wys_drm for pipe loader
Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
commit 7da86e0ec0cd38dcf58db97bb5c8a0eff9a3dd15
Author: Leo Liu <leo.liu at amd.com>
Date: Wed Nov 4 16:24:26 2015 -0500
vl: add drm support for vl_screen
This will allow the state trackers to use render nodes
with screen creation
v2: dup fd for pipe loader
Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
commit d115e47099b6c3ceb27d0c462eb559df6d1f9fd7
Author: Leo Liu <leo.liu at amd.com>
Date: Thu Nov 5 11:22:22 2015 -0500
st/va: fix build fails with pipe loader
There is no dev in drv, and dev should be from vl_screen here
Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
commit ffb60e77882d2da9f42a76d602114cdb26dd25bc
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Fri Nov 6 00:33:48 2015 +0100
nvc0: enable compute support on Fermi
Altough the compute support is still not complete because textures and
surfaces need to be implemented, it allows to launch very simple compute
kernel like one which reads reading MP performance counters.
This turns on PIPE_CAP_COMPUTE and PIPE_SHADER_COMPUTE.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit e06238cb9e50e3b994d5abac921ad800692a90af
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Nov 7 18:48:55 2015 -0500
nv50/ir: fix emission of s[] args in certain situations
There might only be a single arg (e.g. cvt), so use mode rather than
looking at the source directly. Also we don't want to rely on the type
of the value, which can be unreliable, but instead use the
instruction's. This works out well since mkSplit doesn't adjust the
type.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit af218217d71152df8562b7f087086197f28080fe
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Nov 7 18:47:40 2015 -0500
nv50/ir: only take abs value when computing high result
Not reachable from TGSI since it only has UMUL, no IMUL. However it's
surprising that setting argument types to s32 will cause sign to get
lost.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 53cbb11707a502a31bb9f0380d730840245ee9b2
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Nov 6 00:44:10 2015 -0500
nouveau: avoid queueing too much work onto a single fence
Force the fence to get kicked off, which won't actually wait for its
completion, but any additional work will be put onto a fresh list.
This fixes crashes in teximage-colors --benchmark with too many active
maps.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 0f5b1409fd2f9b26c45e750a37947d27c892ee60
Author: Dave Airlie <airlied at gmail.com>
Date: Sun Nov 8 07:55:17 2015 +1000
llvmpipe: disable front updates for now
As pointed out by Emil, this sometimes hangs, appears to be due to threading
need to rethink how this stuff works for llvmpipe.
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 87711183ac35d85ca7d2c2ee67536fe689d6bef3
Author: Dave Airlie <airlied at gmail.com>
Date: Sat Oct 31 16:19:43 2015 +1000
virgl: wrap ret assignment with braces to do correct thing
Coverity reported that ret could only be 0 or 1, since it
was setting ret = fn() > 0, instead of doing (ret = fn()) > 0.
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 6c731d85666abb61c49e5b4affa196545f5ac086
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Sat Nov 7 12:01:50 2015 -0800
nir: Add a nir_deref_tail helper
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 7d90e570f311066d1fd1eaafe681a8c939c86bae
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri May 1 11:26:40 2015 -0700
nir/types: Add an is_vector_or_scalar helper
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit d43e16b1638cdadc7fcff2007b106e2a559dae7d
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Nov 5 16:37:47 2015 -0800
i965/fs: Use regs_read/written for post-RA scheduling in calculate_deps
Previously, we were assuming that everything read/wrote exactly 1 logical
GRF (1 in SIMD8 and 2 in SIMD16). This isn't actually true. In
particular, the PLN instruction reads 2 logical registers in one of the
components. This commit changes post-RA scheduling to use regs_read and
regs_written instead so that we add enough dependencies.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92770
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit c839174d55216cf1da5cdc4bf0f735ab8359d221
Author: Jason Ekstrand <jason at jlekstrand.net>
Date: Thu Oct 22 16:53:27 2015 -0700
nir/validate: Add better validation of load/store types
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit d57ede92b7832f01df2aa5755c8c34b4de4866d4
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Nov 3 12:20:18 2015 +0100
radeonsi: add register definitions for Stoney
There are a few non-stoney changes too.
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
commit 2658777f468e8c0d71669a043ff7401672717622
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Nov 1 13:43:26 2015 +0100
radeonsi: add workarounds for CP DMA to stay on the fast path
v2: set emit_scratch_reloc, add a NULL check
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit fc0416ef5d7775b00f13a5fa83620abb7b1669a0
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Oct 31 01:33:42 2015 +0100
radeonsi: unify CP DMA preparation logic
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 89da3b4458762a76de2774118bbb53953f01c562
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Oct 31 01:21:01 2015 +0100
radeonsi: unify CP DMA code determining various flags
v2: don't call get_flush_flags twice per function
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit c3e527f93d4281ad6e2ca165eaf6ff588e4faefa
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Oct 31 01:03:42 2015 +0100
radeonsi: only enable write confirmation on the last CP DMA packet
This should improve performance for big copies that need to be split.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 8e9ade7eb3582fc541700ade1d232a329da890b0
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Nov 7 00:41:05 2015 -0500
nv50/ir: allow emission of immediates in imul/imad ops
Nothing actually uses this yet (due to complications), but the emission
logic is right.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 393d0c336bc766a123e139ae85383663f81e00d1
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Nov 6 19:28:29 2015 -0500
nv50/ir: properly set the type of the constant folding result
This removes the hack used for merge, which only covers a fraction of
the cases.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 2f9aaed7499499679d44e47b7a070df237f77683
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Nov 6 19:13:35 2015 -0500
nv50/ir: add support for const-folding OP_CVT with F64 source/dest
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 76957389fc6952e59c1f0f1cbdf74f6949a7a956
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Feb 22 19:49:49 2015 -0500
nv50/ir: add fp64 opcode emission support for G200 (NVA0)
Need to emulate rcp/rsq before providing full fp64 support
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit f979d3cfec2b336801fe59ccd264111f403428f5
Author: Hans de Goede <hdegoede at redhat.com>
Date: Thu Nov 5 14:32:38 2015 +0100
nv50/ir: Add support for 64bit immediates to checkSwapSrc01
Now that we support 64 bit immediates in insnCanLoad, we need to swap
64 bit immediate sources too for optimal effect.
Signed-off-by: Hans de Goede <hdegoede at redhat.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 9f2f8bda6e060cb85f6e099a4ad65c58cde36ba0
Author: Hans de Goede <hdegoede at redhat.com>
Date: Thu Nov 5 14:32:37 2015 +0100
nvc0/ir: Teach insnCanLoad about double immediates
Teach insnCanLoad about double immediates, together with the
"Add support for merge-s to the ConstantFolding pass"
This turns the following (nvc0) code:
1: mov u32 $r2 0x00000000 (8)
2: mov u32 $r3 0x3fe00000 (8)
3: add f64 $r0d $r0d $r2d (8)
Into:
1: add f64 $r0d $r0d 0.500000 (8)
Signed-off-by: Hans de Goede <hdegoede at redhat.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 428506ece2c7627392d0f02c7f83021caa46bb4f
Author: Hans de Goede <hdegoede at redhat.com>
Date: Thu Nov 5 14:32:36 2015 +0100
nv50/ir: Add support for merge-s to the ConstantFolding pass
This allows later passes like LoadPropagation to properly deal with 64
bit immediates.
If the new 64 bit load this introduces does not get optimized away then
split64BitOpPostRA() will split this into 2 instructions again.
Signed-off-by: Hans de Goede <hdegoede at redhat.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 2437f0085372355980864454964749ac8231ca44
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Nov 6 17:58:42 2015 -0500
nv50/ir: disallow 64-bit immediates on nv50 targets
No instructions are able to load short immediates like nvc0 can.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 11e3dac36e7b992e30efbce4473451c4e1ac617f
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Nov 6 17:18:01 2015 -0500
nv50/ir: allow movs with TYPE_F64 destinations to be split
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit b487b55f7d08c00f2efabc097c7138403528893f
Author: Hans de Goede <hdegoede at redhat.com>
Date: Thu Nov 5 14:32:35 2015 +0100
gm107/ir: Add support for double immediates
Add support for encoding double immediates (up to 20 bits of precision)
into the generated gm107 machine-code.
Signed-off-by: Hans de Goede <hdegoede at redhat.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 12c850d01ce2bf364f2b1719154df789d43a7a59
Author: Hans de Goede <hdegoede at redhat.com>
Date: Thu Nov 5 14:32:34 2015 +0100
nvc0/ir: Add support for double immediates
Add support for encoding double immediates (up to 20 bits of precision)
into the generated nvc0 machine-code.
Signed-off-by: Hans de Goede <hdegoede at redhat.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 51694072218b5ae84b5d8f98ee2172d7c5d61b31
Author: Francisco Jerez <currojerez at riseup.net>
Date: Fri Nov 6 13:19:56 2015 -0800
i965/nir/fs: Add comment for no-op memory barrier functions
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit faa119307035787f5e421dd6a9eb4d0101de963b
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Sat Oct 10 13:00:04 2015 -0700
i965/nir/fs: Implement new barrier functions for compute shaders
For these nir intrinsics, we emit the same code as
nir_intrinsic_memory_barrier:
* nir_intrinsic_memory_barrier_atomic_counter
* nir_intrinsic_memory_barrier_buffer
* nir_intrinsic_memory_barrier_image
We treat these nir intrinsics as no-ops:
* nir_intrinsic_group_memory_barrier
* nir_intrinsic_memory_barrier_shared
v3:
* Add comment for no-op cases (curro)
v4:
* Moving comment to a separate patch authored by curro
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 9d65f3208bbded17119c7ad38f4b692d3ed00635
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Sat Oct 10 08:59:42 2015 -0700
nir: Add new barrier functions for compute shaders
When these functions are called in glsl-ir, we create a corresponding
nir intrinsic function call.
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 91f188710ad8dce79936c5d28fd7b9a91b6d870a
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Fri Oct 9 14:16:05 2015 -0700
glsl: Add new barrier functions for compute shaders
When these functions are called in GLSL code, we create an intrinsic
function call:
* groupMemoryBarrier => __intrinsic_group_memory_barrier
* memoryBarrierAtomicCounter => __intrinsic_memory_barrier_atomic_counter
* memoryBarrierBuffer => __intrinsic_memory_barrier_buffer
* memoryBarrierImage => __intrinsic_memory_barrier_image
* memoryBarrierShared => __intrinsic_memory_barrier_shared
v2:
* Consolidate with memoryBarrier function/intrinsic creation (curro)
v3:
* Instead of add_memory_barrier_function, add an intrinsic_name
parameter to _memory_barrier (curro)
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 6bad554d98004e6c8ab46e8cbe73f3b3024e55c5
Author: Boyuan Zhang <boyuan.zhang at amd.com>
Date: Wed Sep 23 10:11:08 2015 +0200
radeon/uvd: fix VC-1 simple/main profile decode v2
We just needed to set the extra width/height fields to get this working.
v2 (chk): rebased, CC stable added, commit message added, fixed coding style
Signed-off-by: Boyuan Zhang <boyuan.zhang at amd.com>
Signed-off-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
commit ed55def44febbe1662ddcc0c33a23308899ce488
Author: Boyuan Zhang <boyuan.zhang at amd.com>
Date: Wed Sep 23 10:11:07 2015 +0200
st/vaapi: fix vaapi VC-1 simple/main corruption v2
Apply the start code fix only to advanced profile.
v2 (chk): add commit message
Signed-off-by: Boyuan Zhang <boyuan.zhang at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
commit cc1e5c972eff8c774c93c8dc51d89b550d00633e
Author: Julien Isorce <j.isorce at samsung.com>
Date: Fri Nov 6 09:45:22 2015 +0000
st/va: add support for RGBX and BGRX in VPP
Before it was only possible to convert a NV12 surface to
RGBA or BGRA. This patch uses the same post processing
function, "handleVAProcPipelineParameterBufferType", but
add definitions for RGBX and BGRX.
This patch also makes vlVaQuerySurfaceAttributes more generic
to avoid copy and pasting the same lines.
Signed-off-by: Julien Isorce <j.isorce at samsung.com>
Reviewed-by: Christian K<C3><B6>nig <christian.koenig at amd.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 42a5e143a8d58a0ad15dd5747449eb4b57c87177
Author: Julien Isorce <j.isorce at samsung.com>
Date: Fri Nov 6 09:45:19 2015 +0000
vl/buffers: add RGBX and BGRX to the supported formats
Useful is one wants to create RGBX or BGRX surfaces.
The infrastructure is such that it required just a
few definitions to support these formats.
Signed-off-by: Julien Isorce <j.isorce at samsung.com>
Reviewed-by: Christian K<C3><B6>nig <christian.koenig at amd.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit bf6acbb2db4baaf18ae5a139142acf06e84d1b9c
Author: Julien Isorce <j.isorce at samsung.com>
Date: Fri Nov 6 09:45:17 2015 +0000
st/va: properly use brackets in vlVaAcquireBufferHandle's switch
In "switch (mem_type)" the brackets were surrounding "case+default"
instead of "case" only.
Signed-off-by: Julien Isorce <j.isorce at samsung.com>
Reviewed-by: Christian K<C3><B6>nig <christian.koenig at amd.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit bfc245e9ac430aab0b3c4c2a1b7767793f2854b0
Author: Julien Isorce <j.isorce at samsung.com>
Date: Fri Nov 6 09:45:11 2015 +0000
st/va: properly indent buffer.c, config.c, image.c and picture.c
Some lines were using 4 indentation spaces instead of 3.
Signed-off-by: Julien Isorce <j.isorce at samsung.com>
Reviewed-by: Christian K<C3><B6>nig <christian.koenig at amd.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 6459e780ae44d8826322e0dc2466d0ee6d9e9800
Author: Rob Clark <robclark at freedesktop.org>
Date: Tue Oct 27 11:38:34 2015 -0400
freedreno/a4xx: fix blend color
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 7465e161248b94d0bd1cdae6fc4c501ecfcf9b0b
Author: Rob Clark <robclark at freedesktop.org>
Date: Tue Oct 27 11:33:32 2015 -0400
freedreno: update generated headers
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 6f5e0c08a477c6872e8be6d1b09aea97db7fe125
Author: Guillaume Charifi <guillaume.charifi at sfr.fr>
Date: Fri Nov 6 11:17:25 2015 -0500
freedreno: add a305 support
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 8f55ebe802ea930d14eef9cd622aeb9a8d989e01
Author: Boyan Ding <boyan.j.ding at gmail.com>
Date: Fri Oct 16 15:15:38 2015 +0800
freedreno/ir3: Use nir_foreach_variable
Signed-off-by: Boyan Ding <boyan.j.ding at gmail.com>
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 99597d033a62bdfa31148714f4d2c40f84655a5a
Author: Rob Clark <robdclark at gmail.com>
Date: Wed Oct 21 10:57:15 2015 -0400
nir: some small cleanups
The various cf nodes all get allocated w/ shader as their ralloc_parent,
so lets make this more explicit. Plus couple other corrections/
clarifications.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit d68226087cf5f2f686d6c8f3377c5a1dec3d8bc4
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Nov 5 23:12:52 2015 -0500
nvc0: reintroduce BGRA4 format support
Commit 342e68dc60 (nvc0: remove BGRA4 format support) removed the
support to fix a WoW trace. However after further experimentation, I was
able to get the blit to work by using a different "fake" format in the
2d engine.
The reason why this worked on nv50 is that nv50 falls back to the 3d
blit path in case either the src or the dst aren't "faithfully"
supported, while nvc0 only does it for the dst format. RG8 is better
supported by the nvc0 2d engine than R16.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 581111c4d67c65305dcae83789ac504deeec9da2
Author: Brian Paul <brianp at vmware.com>
Date: Thu Nov 5 19:03:39 2015 -0700
mesa: report enum name in glClientActiveTexture() error string
As we do for glActiveTexture(). Trivial.
commit 497bde6727260e7719c680dc483b10c0751a3fcd
Author: Julien Isorce <julien.isorce at gmail.com>
Date: Thu Nov 5 08:24:45 2015 +0000
st/va: fix memory leak on error in vlVaCreateSurfaces2
Found by coverity: CID #1337953
Signed-off-by: Julien Isorce <j.isorce at samsung.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit e0b896c86c92c4dd02aea7fb5eb8eabe089b9e58
Author: Julien Isorce <julien.isorce at gmail.com>
Date: Thu Nov 5 08:24:44 2015 +0000
st/va: indent vlVaQuerySurfaceAttributes and vlVaCreateSurfaces2
Some lines were using 4 indentation spaces instead of 3.
Signed-off-by: Julien Isorce <j.isorce at samsung.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 8dcf807cb43383590ba193c7ff20b8a98e4a9f65
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Oct 13 15:30:03 2015 -0700
i965: Fix scalar VS float[] and vec2[] output arrays.
The scalar VS backend has never handled float[] and vec2[] outputs
correctly (my original code was broken). Outputs need to be padded
out to vec4 slots.
In fs_visitor::nir_setup_outputs(), we tried to process each vec4 slot
by looping from 0 to ALIGN(type_size_scalar(type), 4) / 4. However,
this is wrong: type_size_scalar() for a float[2] would return 2, or
for vec2[2] it would return 4. This looked like a single slot, even
though in reality each array element would be stored in separate vec4
slots.
Because of this bug, outputs[] and output_components[] would not get
initialized for the second element's VARYING_SLOT, which meant
emit_urb_writes() would skip writing them. Nothing used those values,
and dead code elimination threw a party.
To fix this, we introduce a new type_size_vec4_times_4() function which
pads array elements correctly, but still counts in scalar components,
generating correct indices in store_output intrinsics.
Normally, varying packing avoids this problem by turning varyings into
vec4s. So this doesn't actually fix any Piglit or dEQP tests today.
However, if varying packing is disabled, things would be broken.
Tessellation shaders can't use varying packing, so this fixes various
tcs-input Piglit tests on a branch of mine.
v2: Shorten the implementation of type_size_4x to a single line (caught
by Connor Abbott), and rename it to type_size_vec4_times_4()
(renaming suggested by Jason Ekstrand). Use type_size_vec4
rather than using type_size_vec4_times_4 and then dividing by 4.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 5ae37ae6151623303300047d7465d199df8199a4
Author: Roland Scheidegger <sroland at vmware.com>
Date: Thu Nov 5 18:00:40 2015 +0100
llvmpipe: disable texture cache
There are some weird problems with 8-wide vectors.
commit ba093a099af13a630c255b34dc5d315760248e5f
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Oct 30 20:44:57 2015 -0400
nouveau: send back a debug message when waiting for a fence to complete
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 4f6cd5fad03757e371b66049dcd42855e4853c14
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Oct 30 18:41:09 2015 -0400
nv50,nvc0: provide debug messages with shader compilation stats
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 4335b28840be53ad3c230a4f2dfc2262bf56a0a7
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Oct 30 17:23:22 2015 -0400
nouveau: add support for sending debug messages via KHR_debug
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 6706cc1671bfd8e6c021db8b68815959fa7fceba
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Oct 30 23:25:59 2015 -0400
st/clover: provide a path for drivers to call through to pfn_notify
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
[ Francisco Jerez: Clean up clover::context interface by passing
around a function object. ]
commit c93c9d220baa60fdd0e685a072a61857d3a2846b
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Oct 30 23:28:01 2015 -0400
st/mesa: set debug callback for debug contexts
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit fc76cc05e39839c0933320f28b4cc9041d4e7770
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Oct 30 03:17:35 2015 -0400
gallium: expose a debug message callback settable by context owner
This will allow gallium drivers to send messages to KHR_debug endpoints
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit e587590a83588133d7a9044e3935585f675bbb30
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Nov 5 00:33:22 2015 -0500
st/mesa: account for texture views when doing CopyImageSubData
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit eea3c907cc480a105224b21be51d62bc64ea1057
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Fri Oct 30 11:10:02 2015 +0100
i965/fs: Do not mark used surfaces in FS_OPCODE_GET_BUFFER_SIZE
Do it in the visitor, like we do for other opcodes.
v2: use const, get rid of useless surf_index temporary (Curro)
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit eca4c43a33c5c1bb63c8aa9d0506ed2ba3f9d8cb
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Fri Oct 30 10:57:47 2015 +0100
i965/vec4: Do not mark used surfaces in VS_OPCODE_GET_BUFFER_SIZE
Do it in the visitor, like we do for other opcodes.
v2: use const, get rid of useless surf_index temporary (Curro)
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 6105d1d0a02c7eea83b327965713be3bada306f7
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Fri Oct 30 10:24:12 2015 +0100
i965/vec4: Do not mark used direct surfaces in VS_OPCODE_PULL_CONSTANT_LOAD
Right now the generator marks direct surfaces as used but leaves marking of
indirect surfaces to the caller. Just make the callers handle marking in both
cases for consistency.
v2: Use const, do not add unnecessary temporary (Curro)
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit d7013988fb1d1c277e1fbce8623abddc43f78e05
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Fri Oct 30 08:48:57 2015 +0100
i965/fs: Do not mark used direct surfaces in UNIFORM_PULL_CONSTANT_LOAD
Right now the generator marks direct surfaces as used but leaves marking of
indirect surfaces to the caller. Just make the callers handle marking in both
cases for consistency.
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 027b64a55afc0fe8efcf9f6217192807e285c830
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Fri Oct 30 08:39:11 2015 +0100
i965/fs: Do not mark direct used surfaces in VARYING_PULL_CONSTANT_LOAD
Right now the generator marks direct surfaces as used but leaves marking of
indirect surfaces to the caller. Just make the callers handle marking in both
cases for consistency.
v2: Use const and remove useless surf_index temporary (Curro)
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 6c5f371a27f901d5bc60cf5a2a11cf6629f96f78
Author: Neil Roberts <neil at linux.intel.com>
Date: Mon Sep 7 18:23:14 2015 +0100
i965/skl+: Enable support for 16x multisampling
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit aa3f9aaf31e9056a255f9e0472ebdfdaa60abe54
Author: Neil Roberts <neil at linux.intel.com>
Date: Mon Sep 28 18:22:32 2015 +0100
mesa/meta: Use interpolateAtOffset for 16x MSAA copy blit
Previously there was a problem in i965 where if 16x MSAA is used then
some of the sample positions are exactly on the 0 x or y axis. When
the MSAA copy blit shader interpolates the texture coordinates at
these sample positions it was possible that it would jump to a
neighboring texel due to rounding errors. It is likely that these
positions would be used on 16x MSAA because that is where they are
defined to be in D3D.
To fix that this patch makes it use interpolateAtOffset in the blit
shader whenever 16x MSAA is used and the GL_ARB_gpu_shader5 extension
is available. This forces it to interpolate the texture coordinates at
the pixel center to avoid these problematic positions.
This fixes ext_framebuffer_multisample-unaligned-blit and
ext_framebuffer_multisample-clip-and-scissor-blit with 16x MSAA on
SKL+.
v2: Use interpolateAtOffset instead of interpolateAtSample
v3: Always try to enable GL_ARB_gpu_shader5 in the shader
[Ian Romanick]
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit b080b3d54d99dfb46b5e8a6eb94fdbdeb937f255
Author: Neil Roberts <neil at linux.intel.com>
Date: Thu Oct 22 10:55:35 2015 +0200
meta/blit: Always try to enable GL_ARB_sample_shading
Previously this extension was only enabled when blitting between two
multisampled buffers. However I don't think it does any harm to just
enable it all the time. The ‘enable’ option is used instead of
‘require’ so that the shader will still compile if the extension isn't
available in the cases where it isn't used. This will make the next
patch simpler because it wants to add another optional extension.
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 2dd76ec16e599bd919962f439b59fdd73e85ff94
Author: Neil Roberts <neil at linux.intel.com>
Date: Wed Sep 16 17:43:33 2015 +0100
meta: Support 16x MSAA in the multisample scaled blit shader
v2: Fix the x_scale in the shader. Remove the doubts in the commit
message.
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 1a22b12fc51e80c20c700f93904ffd12caa73473
Author: Neil Roberts <neil at linux.intel.com>
Date: Fri Sep 11 18:09:46 2015 +0100
i965/meta: Support 16x MSAA in the meta stencil blit
The destination rectangle is now drawn at 4x4 the size and the shader
code to calculate the sample number is adjusted accordingly.
Acked-by: Ben Widawsky <ben at bwidawsk.net>
commit a6804654283a9d03bee92d61eee5b1d036c8db68
Author: Neil Roberts <neil at linux.intel.com>
Date: Wed Sep 9 17:44:17 2015 +0100
i965/fs/skl+: Fix calculating gl_SampleID for 16x MSAA
In order to accomodate 16x MSAA, the starting sample pair index is now
3 bits rather than 2 on SKL+.
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit bf6bd7eaf09fadc516a1e46635ed8590f4d88535
Author: Neil Roberts <neil at linux.intel.com>
Date: Wed Sep 9 14:38:08 2015 +0100
i965: Support allocating the MCS buffer for 16x MSAA
When 16 samples are used the MCS buffer needs 64 bits per pixel.
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit b4c2e6054fe830c299113b143622bcd2158cd257
Author: Neil Roberts <neil at linux.intel.com>
Date: Wed Sep 9 14:36:42 2015 +0100
i965: Support calculating the bits needed to set up 16x MSAA
The gen7_surface_msaa_bits function already returns the right values
for 16 samples but it just needs its assert to be relaxed.
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit 1a97cac767425b22e56fe698127795bc287bb773
Author: Neil Roberts <neil at linux.intel.com>
Date: Tue Sep 15 16:34:35 2015 +0100
i965/fs: Add a sampler program key for whether the texture is 16x MSAA
When 16x MSAA is used for sampling with texelFetch the compiler needs
to use a different instruction which passes more arguments for the MCS
data. Previously on skl+ it was unconditionally using this new
instruction. However since 16x MSAA is probably going to be pretty
rare, it is probably worthwhile to avoid using this instruction for
the other sample counts. In order to do that this patch adds a new
member to brw_sampler_prog_key_data to track when a sampler refers to
a buffer with 16 samples.
Note that this isn't done for the vec4 backend because it wouldn't
change how many registers it uses.
Acked-by: Ben Widawsky <ben at bwidawsk.net>
commit 4ef27745c8ed5153464db22950a90d74d2ef4435
Author: Neil Roberts <neil at linux.intel.com>
Date: Wed Sep 9 15:59:36 2015 +0100
i965/vec4/skl+: Use ld2dms_w instead of ld2dms
In order to support 16x MSAA, skl+ has a wider version of ld2dms that
takes two parameters for the MCS data. The MCS data in the response
still fits in a single register so we just need to ensure we copy both
values rather than just the lower one.
Acked-by: Ben Widawsky <ben at bwidawsk.net>
commit e386fb0dee40d0f2342b43b6750b64c8174463a9
Author: Neil Roberts <neil at linux.intel.com>
Date: Tue Sep 8 15:52:09 2015 +0100
i965/fs/skl+: Use ld2dms_w instead of ld2dms
In order to support 16x MSAA, skl+ has a wider version of ld2dms that
takes two parameters for the MCS data. The MCS data retrieved from the
ld_mcs instruction already returns 4 or 8 registers and is documented
to return zeroes for the mcsh value when the sample count is less than
16.
v2: Use get_lowered_simd_width to fall back to SIMD8 instructions when
the message length would be too long in SIMD16.
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit 20250e854eca3209133d592d98559ac474a5f60f
Author: Neil Roberts <neil at linux.intel.com>
Date: Wed Sep 16 11:48:42 2015 +0100
i965: Program 16x MSAA sample positions.
This is the standard pattern used by the other 3D graphics API.
BDW has slots for these values, but they aren't actually used until
SKL. Even though the documentation for BDW says they must be zero, it
doesn't seem to cause any harm to program them anyway.
The comment above for the 8x sample positions says that the hardware
implements centroid interpolation by picking the centre-most sample
that is inside the primitive. That implies that it might be worthwhile
to pick a pattern that includes 0.5,0.5. However by experimentation
this doesn't seem to actually be the case. With the sample positions
in this patch, if I modify the piglit test below so that it instead
reports the centroid position, it reports 0.492188,0.421875 which
doesn't match any of the positions. If I modify the sample positions
so that they include one at exactly 0.5,0.5 it doesn't help and it
reports another position which is even further from the center for
some reason.
arb_gpu_shader5-interpolateAtSample-different
Kenneth Graunke experimented with some other patterns that have a
higher standard deviation but I think after some discussion it was
decided that it would be better to pick the same pattern as the other
graphics API in case there are games that rely on this pattern.
(Based on a patch by Kenneth Graunke)
Cc: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit 5048da974e68a05b86a0cec494e1380e81978684
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Jan 28 23:58:43 2015 -0800
i965: Handle 16x MSAA in IMS dimension munging code.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Neil Roberts <neil at linux.intel.com>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit b9f8e729c88ad0d934422976a20a7c765016fcb8
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Nov 3 17:16:49 2015 -0800
nir: Rename nir_live_variables.c to nir_liveness.c.
It doesn't actually operate on variables.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 5c6f21579d7db802f4db96bae8b166e7409afabe
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Nov 3 17:15:24 2015 -0800
nir: Rename live_variables to live_ssa_defs.
This computes liveness of SSA values, not nir_variables.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 56774e63028b2997a7d8c0abb5009a4c79f9a453
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Tue Oct 20 13:08:09 2015 +0200
i965/vec4: select predicate based on writemask for sel emissions
Equivalent to commit 8ac3b525c but with sel operations. In this case
we select the PredCtrl based on the writemask.
This patch helps on cases like this:
1: cmp.l.f0.0 vgrf40.0.x:F, vgrf0.zzzz:F, vgrf7.xxxx:F
2: cmp.nz.f0.0 null:D, vgrf40.xxxx:D, 0D
3: (+f0.0) sel vgrf41.0.x:UD, vgrf6.xxxx:UD, vgrf5.xxxx:UD
In this case, cmod propagation can't optimize instruction #2, because
instructions #1 and #2 have different writemasks, and we can't update
directly instruction #2 writemask because our code thinks that sel at
instruction #3 reads all four channels of the flag, when it actually
only reads .x.
So, with this patch, the previous case becames this:
1: cmp.l.f0.0 vgrf40.0.x:F, vgrf0.zzzz:F, vgrf7.xxxx:F
2: cmp.nz.f0.0 null:D, vgrf40.xxxx:D, 0D
3: (+f0.0.x) sel vgrf41.0.x:UD, vgrf6.xxxx:UD, vgrf5.xxxx:UD
Now only the x channel of the flag is used, allowing dead code
eliminate to update the writemask at the second instruction:
1: cmp.l.f0.0 vgrf40.0.x:F, vgrf0.zzzz:F, vgrf7.xxxx:F
2: cmp.nz.f0.0 null.x:D, vgrf40.xxxx:D, 0D
3: (+f0.0.x) sel vgrf41.0.x:UD, vgrf6.xxxx:UD, vgrf5.xxxx:UD
So now cmod propagation can simplify out #2:
1: cmp.l.f0.0 vgrf40.0.x:F, attr18.wwww:F, vgrf7.xxxx:F
2: (+f0.0.x) sel vgrf41.0.x:UD, vgrf6.xxxx:UD, vgrf5.xxxx:UD
Shader-db numbers:
total instructions in shared programs: 6235835 -> 6228008 (-0.13%)
instructions in affected programs: 219850 -> 212023 (-3.56%)
total loops in shared programs: 1979 -> 1979 (0.00%)
helped: 1192
HURT: 0
commit bb73fc4cb82c1abdf47aa373c78c2a85fe29b3ec
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Nov 4 22:42:41 2015 -0500
nouveau: relax fence emit space assert
We also have the "reserved for kick" space available. Some of my earlier
changes can probably be removed, but this is a quick fix for some of the
rarer fallout.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: <mesa-stable at lists.freedesktop.org>
commit 6d3a24bce80a32063aedfe568efd5532aea4c875
Author: Eric Anholt <eric at anholt.net>
Date: Wed Nov 4 13:27:16 2015 -0800
vc4: When the create ioctl fails, free our cache and try again.
This greatly increases the pressure you can put on the driver before
create fails. Ultimately we need to let the kernel take control of
our cached BOs and just take them from us (and other clients)
directly, but this is a very easy patch for the moment.
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
commit 3f7c96c36cb18a9e4616d373369a130416884bf9
Author: Eric Anholt <eric at anholt.net>
Date: Wed Nov 4 13:10:28 2015 -0800
vc4: Print the rounded shader size in debug output.
It's surprising to see "0kb" printed for debug on short shaders, while
4kb alignment won't be suprising.
commit 4a951f1c0847353101d28db583e1dd397fdce9ba
Author: Eric Anholt <eric at anholt.net>
Date: Wed Nov 4 13:13:39 2015 -0800
vc4: Fix dumping the size of BOs allocated/cached.
60MB of cached BOs are a lot less scary than 600MB.
commit 5bbd522452cfe86fc600203fe1a9b056582e2000
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Nov 4 14:26:37 2015 -0500
mesa/tests: add glBufferStorageEXT to ES 3.1 dispatch list
I thought that aliased functions didn't need to be added, but that might
only be if the function aliases something in the same {desktop,ES}
space. Resolves the dispatch sanity test failure.
Fixes: 13b19aa81 (mesa: expose support for GL_EXT_buffer_storage)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92824
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit bdf6cef0333bf7278e2e2347aaae399288e87dcd
Author: Brian Paul <brianp at vmware.com>
Date: Sat Oct 31 07:02:36 2015 -0600
vbo: fix another GL_LINE_LOOP bug
Very long line loops which spanned 3 or more vertex buffers were not
handled correctly and could result in stray lines.
The piglit lineloop test draws 10000 vertices by default, and is not
long enough to trigger this. Even 'lineloop -count 100000' doesn't
trigger the bug.
For future reference, the issue can be reproduced by changing Mesa's
VBO_VERT_BUFFER_SIZE to 4096 and changing the piglit lineloop test to
use glVertex2f(), draw 3 loops instead of 1, and specifying -count
1023.
Acked-by: Sinclair Yeh <syeh at vmware.com>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit d31481e70ab0da293d4c3010815f643f161b7168
Author: Brian Paul <brianp at vmware.com>
Date: Tue Nov 3 14:34:15 2015 -0700
svga: implement 'white_fragments' option for VGPU10 fragment shaders
When we emulate XOR logicop mode with blend-subtract, we need to ensure
that the fragment shader always emits white. We had this implemented
for VGPU9, but not VGPU10.
VMware bug 1545492.
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
commit 149ac1fe43a87ee4219f9979dcce2de7964c31a9
Author: Brian Paul <brianp at vmware.com>
Date: Wed Oct 28 19:05:27 2015 -0600
u_vbuf: minor code reformatting / line wrapping
Trivial.
commit e450d4371a4166f57a7e412d2c1e68aa1162a703
Author: Brian Paul <brianp at vmware.com>
Date: Wed Oct 28 19:02:38 2015 -0600
u_vbuf: add some const qualifiers
Trivial.
commit 3f98c812b30d739b744d70267a28a25afcaa8b13
Author: Brian Paul <brianp at vmware.com>
Date: Sat Oct 31 07:44:49 2015 -0600
svga: use new enum indices_mode type
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
commit fa6efbd27d1c725f38e960005d8806521bd58156
Author: Brian Paul <brianp at vmware.com>
Date: Sat Oct 31 07:44:23 2015 -0600
util/indices: replace #define tokens with enum type
To ease debugging in gdb.
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
commit c3d7caa1e006f00c3544a79a0be7d78904ce4177
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Thu Oct 22 22:22:14 2015 +0200
i965: check inst->predicate when clearing flag_live at dead code eliminate
Detected by Matt Turner while reviewing commit
a59359ecd22154cc2b3f88bb8c599f21af8a3934
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit c19443bc8b68ef4697ead1998286e42bd4d8a572
Author: Roland Scheidegger <sroland at vmware.com>
Date: Wed Nov 4 14:21:43 2015 +0100
gallivm: fix sampling for s3tc srgb formats when using texture cache
This actually stored the values as 8bit linear values in the cache,
then did another srgb->linear conversion...
We don't want to do the former (decoding 8bit srgb values to 8bit linear
completely defeats the purpose of srgb in the first place), so just decode
to 8bit srgb.
Fixes piglit.spec.ext_texture_srgb.texwrap formats-s3tc tests.
commit d56a1478a8006af48aa65ab62e676e5f974f1ec3
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Tue Oct 13 20:50:25 2015 -0700
i965/meta: Assert fast clears and rep clears never overlap
There is nothing wrong with the code today, but as one modifies the code it
turns out to be not too difficult to mess up the code, and this easy assertion
should catch such driver implementation failures quickly.
Cc: Kristian Høgsberg <krh at bitplanet.net>
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Chad Versace <chad.versace at intel.com>
Reviewed-by: Neil Roberts <neil at linux.intel.com>
commit 13b19aa815661cd17b74c8694b6c466bfaf75740
Author: Ryan Houdek <sonicadvance1 at gmail.com>
Date: Mon Nov 2 19:30:18 2015 -0600
mesa: expose support for GL_EXT_buffer_storage
This extension requires ES 3.1 since it relies on glMemoryBarrier.
For testing purposes I temporarily moved glMemoryBarrier to be an ES 3.0
function.
This has been tested with the piglit in the ML and the Dolphin emulator.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 8e4cf900f0af9eb8a72c81a0e5e393906b11764a
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Wed Nov 4 08:41:29 2015 +1100
glsl: make sure to only add subroutines to resource list
Over looked in 763cd8c080353.
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit f6b3c163f954c4fb5a525af39ce906f63b445e89
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Wed Nov 4 14:50:49 2015 +1100
glsl: remove old TODO
SSBO support now exists as of commits f24e5e and f408a13dd30.
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit 6e3b380387378e9f8e92eed3dc4a95767857b0de
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Fri Oct 16 10:28:48 2015 +1100
docs: Mark AoA as done for i965
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 5b75dbd7be09fdc80eff8141ef47c63a6a913c98
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Fri Oct 16 10:28:47 2015 +1100
i965: enable ARB_arrays_of_arrays
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit fb77da89f51fd82d5cee95400acb20ad74d9e7bc
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Sat Oct 31 10:31:37 2015 +1100
i965: add support for image AoA
V3: clamp array index to the correct size (the size of the current array
rather than the inner array) Francisco Jerez.
V2: avoid useless zero-initialization and addition for the first AoA level,
avoid redundant temporary, make use of type_size_scalar(), rename aoa_size
to element_size, assign the indirect indexing temporary directly to
image.reladdr, and replace while loop with a for loop. All suggested
by Francisco Jerez.
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 9285ed98f7557722fbb94f47c5bc138ef5dd9c70
Author: Roland Scheidegger <sroland at vmware.com>
Date: Tue Oct 27 05:34:00 2015 +0100
llvmpipe: add cache for compressed textures
compressed textures are very slow because decoding is rather complex
(and because there's no jit code code to decode them too for non-technical
reasons).
Thus, add some texture cache which holds a couple of decoded blocks.
Right now this handles only s3tc format albeit it could be extended to work
with other formats rather trivially as long as the result of decode fits into
32bit per texel (ideally, rgtc actually would decode to more than 8 bits
per channel, but even then making it work for it shouldn't be too difficult).
This can improve performance noticeably but don't expect wonders (uncompressed
is unsurprisingly still faster). It's also possible it might be slower in
some cases (using nearest filtering for example or if there's otherwise not
many cache hits, the cache is only direct mapped which isn't great).
Also, actual decode of a block relies on util code, thus even though always
full blocks are decoded it is done texel by texel - this could obviously
benefit greatly from simd-optimized code decoding full blocks at once...
Note the cache is per (raster) thread, and currently only used for fragment
shaders.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 39b4dfe6ab1003863778a25c091c080e098833ec
Author: Oded Gabbay <oded.gabbay at gmail.com>
Date: Tue Nov 3 10:36:01 2015 +0200
llvmpipe: use simple coeffs calc for 128bit vectors
There are currently two methods in llvmpipe code to calculate coeffs to
be used as inputs for the fragment shader. The two methods use slightly
different ways to do the floating point calculations and thus produce
slightly different results.
The decision which method to use is determined by the size of the vector
that is used by the platform.
For vectors with size of more than 128bit, a single-step method is used,
in which coeffs_init_simple() + attribs_update_simple() are called.
For vectors with size of 128bit or less, a two-step method is used, in
which coeffs_init() + attribs_update() are called.
This causes some piglit tests (clip-distance-bulk-copy,
interface-vs-unnamed-to-fs-unnamed) to fail when using platforms with
128bit vectors (such as ppc64le or x86-64 without AVX).
This patch makes platforms with 128bit vectors use the single-step
method (aka "simple" method) instead of the two-step method.
This would make the resulting coeffs identical between more platforms,
make sure the piglit tests passes, and make debugging and maintainability
a bit easier as the generated LLVM IR will be the same for more platforms.
The performance impact is negligible for x86-64 without AVX, and
basically non-existent for ppc64le, as it can be seen from the following
benchmarking results:
- glxspheres, on ppc64le:
- original code: 4.892745317 frames/sec 5.460303857 Mpixels/sec
- with the patch: 4.932083873 frames/sec 5.504205571 Mpixels/sec
- Additional 0.8% performance boost
- glxspheres, on x86-64 without AVX:
- original code: 20.16418809 frames/sec 22.50323395 Mpixels/sec
- with the patch: 20.31328989 frames/sec 22.66963152 Mpixels/sec
- Additional 0.74% performance boost
- glmark2, on ppc64le:
- original code: score of 58
- with my change: score of 57
- glmark2, on x86-64 without AVX:
- original code: score of 175
- with the patch: score of 167
- Impact of of -4.5% on performance
- OpenArena, on ppc64le:
- original code: 3398 frames 1719.0 seconds 2.0 fps
255.0/505.9/2773.0/0.0 ms
- with the patch: 3398 frames 1690.4 seconds 2.0 fps
241.0/497.5/2563.0/0.2 ms
- 29 seconds faster with the patch, which is about 2%
- OpenArena, on x86-64 without AVX:
- original code: 3398 frames 239.6 seconds 14.2 fps
38.0/70.5/719.0/14.6 ms
- with the patch: 3398 frames 244.4 seconds 13.9 fps
38.0/71.9/697.0/14.3 ms
- 0.3 fps slower with the patch (about 2%)
Additional details can be found at:
http://lists.freedesktop.org/archives/mesa-dev/2015-October/098635.html
Signed-off-by: Oded Gabbay <oded.gabbay at gmail.com>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit 59bbe2681b73c3795b7298e2486d5fde7c464ed5
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Nov 2 21:43:40 2015 -0800
nir: Properly invalidate metadata in nir_opt_remove_phis().
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Eduardo Lima Mitev <elima at igalia.com>
Cc: mesa-stable at lists.freedesktop.org
commit bc3942e2970c60a816cf954b1fa4d416d0852bd9
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Nov 2 21:38:56 2015 -0800
nir: Properly invalidate metadata in nir_lower_vec_to_movs().
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Eduardo Lima Mitev <elima at igalia.com>
Cc: mesa-stable at lists.freedesktop.org
commit 0f037bd71ffe083c05cd0867ef54bce91ff84243
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Nov 2 21:21:25 2015 -0800
nir: Properly invalidate metadata in nir_opt_copy_prop().
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Eduardo Lima Mitev <elima at igalia.com>
Cc: mesa-stable at lists.freedesktop.org
commit 4cb7546066f3f06b8030b8fce78f82469b0c6980
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Nov 2 21:28:26 2015 -0800
nir: Properly invalidate metadata in nir_remove_dead_variables().
v2: Preserve live_variables too (Jason).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Eduardo Lima Mitev <elima at igalia.com>
commit 8bb44510fca5315bbdd61502c72c22c7198c0daf
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Nov 2 21:05:08 2015 -0800
nir: Properly invalidate metadata in nir_split_var_copies().
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Eduardo Lima Mitev <elima at igalia.com>
Cc: mesa-stable at lists.freedesktop.org
commit aea40091f003f8772afce3562b0f8c6a17dad07f
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Nov 2 21:02:37 2015 -0800
nir: Properly invalidate metadata in nir_lower_global_vars_to_local().
v2: Preserve nir_metadata_live_variables as well (caught by Jason).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Eduardo Lima Mitev <elima at igalia.com>
commit 531be601d5f9ac4f8a9cc77240ba865fda077709
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Oct 28 10:11:11 2015 -0700
nir: Unexpose _impl versions of copy_prop and dce
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 4bc16ad2176efda5f8c59e222b4735ee35c434b5
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Fri Oct 23 16:10:02 2015 -0700
mesa: rename UniformBlockStageIndex to InterfaceBlockStageIndex
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Cc: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Cc: Iago Toral <itoral at igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
commit cf3121ed1885b257217dbac24a131dbfd5f8e438
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Oct 30 10:07:23 2015 -0700
i965/vec4: Send from GRF in atomic operations.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 3b37155a68acc351cba86a1fa142bd0de2192d4c
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Oct 28 13:50:08 2015 +0100
gallium/radeon: allow returning SDMA fences from pipe->flush
pipe->flush never returned SDMA fences. This fixes it.
This is only an issue on amdgpu where fences can signal out of order.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 7f9122c9680a882fee5a9d5a8e09c3e3b7466937
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Oct 28 12:59:38 2015 +0100
gallium/radeon: always return the last SDMA fence on SDMA flush if needed
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 36fd65381756ed1b8f774f7fcdd555941a3d39e1
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Mar 11 23:14:31 2015 -0700
i965: Add scalar geometry shader support.
This is hidden behind INTEL_SCALAR_GS=1 for now, as we don't yet support
instanced geometry shaders, and Orbital Explorer's shader spills like
crazy. But the infrastructure is in place, and it's largely working.
v2: Lots of rebasing.
v3: (feedback from Kristian Høgsberg)
- Handle stride and subreg_offset correctly for ATTRs; use a helper.
- Fix missing emit_shader_time_end() call.
- Delete dead code after early EOT in static vertex case to avoid
tripping asserts in emit_shader_time_end().
- Use proper D/UD type in intexp2().
- Fix "EndPrimitve" and "to that" typos.
- Assert that invocations == 1 so we know this is missing.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit c9541a74e4d179ad844bdf8af1e3de541c5b14c2
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Sep 23 20:52:19 2015 -0700
i965: Add scalar GS input lowering code.
We really ought to compute the VUE map at link time and stash it, rather
than recomputing it here, but with the mess of program structures I
wasn't sure where to put it. We can improve that later.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 4861835d1cc07e5068694905b5a3538303f6de32
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Nov 3 12:51:32 2015 -0800
i965: Fix the fs_visitor GS constructor to take shader_time_index.
Jason reworked this so it isn't simply ST_GS anymore...it's either -1
(not enabled) or an actual offset.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 5d4b019d2a6d4deb4db11780618515cf1fa8a4fc
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Tue Oct 13 20:50:19 2015 -0700
i965/gen8+: Extract color clear surface state
On future generation platforms the color clear value is stored elsewhere in the
surface state. By extracting this logic, we can cleanly implement the difference
in an upcoming patch.
Should have no functional impact.
v2: Move hunk from the next patch into this patch (Matt)
Whitespace fix (Ben)
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Neil Roberts <neil at linux.intel.com>
commit f3223ebd6c6ae35b14fe463b8889cf93df1e9aac
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Tue Oct 13 20:50:18 2015 -0700
i965/gen8+: Remove redundant zeroing of surface state
The allocate_surface_state already zeroes out the surface state, and doing it
later in the function is destructive for what we want to accomplish when we
split out support for gen9 fast clears (next patch).
NOTE: Only dword 12 actually needed to be fixed, but it seemed more consistent
to remove the other instances as well. I can make an argument both ways (open
coding it, vs. not). I can rework the next patch if requires.
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Chad Versace <chad.versace at intel.com>
Reviewed-by: Neil Roberts <neil at linux.intel.com>
commit e8874074916d5216942ff02fb3083a97e136da4c
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Tue Nov 3 19:33:08 2015 +0100
nvc0: add missing compute parameters required by clover
This fixes crashes with some piglit OpenCL tests.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit e640ba41ed1eaeecc735ebd18fa62f05577830cb
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Tue Nov 3 19:32:49 2015 +0100
nvc0: handle NULL pointer in nvc0_get_compute_param()
To get the size (in bytes) of a compute parameter, clover first calls
get_compute_param() with a NULL data pointer. The RET() macro is based
on nv50.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit dde33fc23c4ef8b8e02fb5768161fdaa078847d5
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Fri Oct 23 11:30:16 2015 -0700
i965/skl: PCI ID cleanup and brand strings
A few new PCI ids are added here, and one is removed (0x190B) because it no
longer seems to exist anywhere.
v2-4:
Only use ascii characters (Ilia)
0x1921 is no longer marked as f
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky at intel.com>
commit 7cbd6608f544591bc6aadf48877608b30a78ccb8
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Thu Oct 29 17:30:35 2015 -0700
i965/skl: Add GT4 PCI IDs
Like other gen8+ hardware, the hardware automatically scales up thread counts.
We must be careful about the URB sizes since GT4 adds another slice.
One of the existing PCI IDs is actually mislabeled as GT3. Arguably this is a
real bug since the URB size will be wrong. Because this patch is simply meant to
add the missing IDs, that will be fixed in a later patch.
v2: No longer relevant.
v3: Update the wm thread count to support GT4. The WM thread count is used to
determine the maximum scratch space required. Currently the code always
allocates the maximum amount even though lower GT SKUs require less. The formula
is threads_per_psd * subslices_per_slice * slices
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky at intel.com>
commit 55365a7ad50c2e4547f58995a8e3411d8f2b00a2
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Tue Oct 13 15:04:54 2015 -0700
mesa: Add spec citations for DispatchCompute*
Note: The OpenGL 4.3 - 4.5 specification language for DispatchCompute
appears to have an error regarding the max allowed values. When adding
the specification citation, we note why the code does not match the
specification language.
v2:
* Updates based on review from Iago
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Cc: Iago Toral Quiroga <itoral at igalia.com>
Cc: Marta Lofstedt <marta.lofstedt at intel.com>
Reviewed-by: Marta Lofstedt <marta.lofstedt at intel.com>
commit 44c399f20af49607c799326ad4dd0f74c5214d4c
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Tue Oct 13 15:04:54 2015 -0700
mesa: Update DispatchComputeIndirect errors for indirect parameter
There is some discrepancy between the return values for some error
cases for the DispatchComputeIndirect call in the ARB_compute_shader
specification. Regarding the indirect parameter, in one place the
extension spec lists that the error returned for invalid values should
be INVALID_OPERATION, while later it specifies INVALID_VALUE.
The OpenGL 4.3 and OpenGLES 3.1 specifications appear to be consistent
in requiring the INVALID_VALUE error return in this case.
Here we update the code to match the main specifications, and update
the citations use the main specification rather than the extension
specification.
v2:
* Updates based on review from Iago
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Cc: Iago Toral Quiroga <itoral at igalia.com>
Cc: Marta Lofstedt <marta.lofstedt at intel.com>
Reviewed-by: Marta Lofstedt <marta.lofstedt at intel.com>
commit 0b19f651958c3888588190c8c8a9e701173a2aa2
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Oct 26 11:35:57 2015 -0700
i965/fs: Clean up FBH code.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit c22d62f5991f1c26c58c9ae1891202ea437d2f7b
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Oct 26 11:35:57 2015 -0700
i965/vec4: Clean up FBH code.
It did a bunch of unnecessary stuff, emitting an extra MOV included.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 7c81a6a647257c309cb1ca36c60aa4bfa8e2e022
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Oct 26 06:58:56 2015 -0700
i965: Replace default case with list of enum values.
If we add a new file type, we'd like to get warnings if it's not
handled.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit d9b09f8a306dfd471e45b5294c3adcb119114387
Author: Matt Turner <mattst88 at gmail.com>
Date: Sun Oct 25 20:49:08 2015 -0700
i965/vec4: Don't disable channels in any/all comparisons.
We've made a mistake in calling the Channel Enable bits "writemask",
because they do more than control which channels of the destination are
written -- they actually control which channels are enabled (surprise!
surprise!)
So, if we emit
cmp.z.f0(8) null.xy<1>D g10<4,4,1>.xyzzD g2<0,4,1>.xyzzD
mov(8) g12<1>.xUD 0x00000000UD
(+f0.all4h) mov(8) g12<1>.xUD 0xffffffffUD
where the CMP instruction has only .xy channel enables, it won't write
the .zw channels of the flag register, which are of course read by the
+f0.all4 predicate.
We need to always emit CMP instructions whose flag result might be read
by such a predicate with all channels enabled.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit f4466c856f6147885be52aff6314452784b30189
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Fri Oct 30 14:30:35 2015 +0200
mesa: fix uniforms calculation in glGetProgramiv
Since introduction of SSBO, UniformStorage contains not just uniforms
but also buffer variables, this needs to be taken in to account when
calculating active uniforms with GL_ACTIVE_UNIFORMS and
GL_ACTIVE_UNIFORM_MAX_LENGTH.
No Piglit regressions.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Eduardo Lima Mitev <elima at igalia.com>
Reviewed-by: Timothy Arceri <timothy.arceri at collabora.com>
commit efb333acb7ab4f9007cbeb0653783689101b0dd5
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Fri Oct 30 12:02:51 2015 +0200
mesa: fix program resource queries for atomic counter buffers
gl_active_atomic_buffer contains index to UniformStorage, we need to
calculate resource index for that gl_uniform_storage.
Fixes following CTS tests:
ES31-CTS.program_interface_query.atomic-counters
ES31-CTS.program_interface_query.atomic-counters-one-buffer
No Piglit regressions.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Marta Lofstedt <marta.lofstedt at intel.com>
commit c2c124f89194fe33af522f090aa8e71f2c3aa474
Author: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
Date: Wed Oct 21 12:09:21 2015 +0300
glsl: join calculate_array_size() and calculate_array_stride()
These helpers are ran for same case the same loop. Here joined
their operation so the loop is ran just once. Also fixed
out-of-memory condition here.
v2: Make the loop simpler to read as per Tapani's suggestion
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Tested-by: Tapani Pälli <tapani.palli at intel.com>
commit af7c98a9c75b17fc8c8ed0989aa732766e5b06d1
Author: Ryan Houdek <sonicadvance1 at gmail.com>
Date: Sun Nov 1 21:25:27 2015 -0600
mesa: expose support for OES/EXT_draw_elements_base_vertex to OpenGL ES
This has been tested with the piglits in the mailing list and
on the Dolphin emulator.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 985b51551a9bafec86604714d5faf3065dad4812
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Nov 1 20:13:13 2015 -0500
nouveau: set MaxDrawBuffers to the same value as MaxColorAttachments
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org
commit 00bb5247166f821767b0322f7626f5980b60497e
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Sun Nov 1 23:28:02 2015 +0100
nv50: use correct heaps for FP and GP code segments
This is just a cosmetic change. Trivial.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
commit 39bb59a56610e67c26df6f92d2c844b2a6f04082
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Fri Oct 16 21:19:45 2015 -0700
mesa/sso: Add compute shader support
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Marta Lofstedt <marta.lofstedt at intel.com>
[itoral at igalia.com: Reviewed-by for all except the ctx->_Shader change]
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 6e118550502f56410426ff4623b796e7e09eb5f9
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Fri Oct 16 21:14:10 2015 -0700
mesa/sso: Add MESA_VERBOSE=api trace support
v2:
* Use %u for unsigned values (Iago)
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 5bfe2835c2e0d3b7b3f11063f6120103f228676b
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Thu Oct 15 10:27:00 2015 -0700
i965: Setup pull constant state for compute programs
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit a4a416f5674f9bbe214056d8a456a2545f02f294
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Tue Oct 13 17:19:54 2015 -0700
main/get: Add MAX_COMBINED_COMPUTE_UNIFORM_COMPONENTS
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
Reviewed-by: Marta Lofstedt <marta.lofstedt at intel.com>
commit 218e94906d877889b2b124187d8e17b7f0879122
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Thu Oct 15 14:47:34 2015 -0700
glsl: OpenGLES GLSL 3.1 precision qualifiers ordering rules
The OpenGLES GLSL 3.1 specification uses the precision qualifier
ordering rules from ARB_shading_language_420pack.
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
Reviewed-by: Marta Lofstedt <marta.lofstedt at intel.com>
commit b6e9b2b7a0affabd80f14d63284cd0ffe4745136
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Tue Oct 13 17:18:52 2015 -0700
glsl: Add compute shader builtin variables for OpenGLES 3.1
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
Reviewed-by: Marta Lofstedt <marta.lofstedt at intel.com>
commit 67635a0a713e54939f1f72ba8db2b3099988a925
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Oct 31 19:54:38 2015 -0400
nouveau: get rid of tabs
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 0ef8c5cb96f6b1fea7c18c25fbff2adb6d7d0736
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Fri Oct 30 18:19:34 2015 -0400
i965/sched: don't calculate live intervals for post-RA scheduling
For some reason, this causes assertions on gm965 only. In any case, it's
unnecessary since we don't need liveness information in the post-RA
scheduler.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92744
Cc: Mark Janes <mark.a.janes at intel.com>
Signed-off-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 425d8c2578a1e51ecbbc2ac6138af68817a52cb0
Author: Dave Airlie <airlied at gmail.com>
Date: Sat Oct 31 18:04:26 2015 +1000
virgl/vtest: fix extra malloc
This somehow got added twice, drop the first one.
Reported by Coverity.
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 8d731ebd33211d8b9c108fa60bfc854b2a8464c5
Author: Dave Airlie <airlied at gmail.com>
Date: Sat Oct 31 16:07:52 2015 +1000
virgl: free sampler view on failure path
Reported by Coverity.
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 7153b12651f4d6e3b160a8d577a084a32be08c40
Author: Dave Airlie <airlied at gmail.com>
Date: Sat Oct 31 16:11:29 2015 +1000
gallium/swrast: fixup build breakage and warnings
The front buffer rendering changes broke an interface, I didn't
fix up all of them.
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 2b676570960277d47477822ffeccc672613f9142
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Oct 9 01:38:08 2015 +0100
gallium/swrast: fix front buffer blitting. (v2)
So I've known this was broken before, cogl has a workaround
for it from what I know, but with the gallium based swrast
drivers BlitFramebuffer from back to front or vice-versa
was pretty broken.
The legacy swrast driver tracks when a front buffer is used
and does the get/put images when it is mapped/unmapped,
so this patch attempts to add the same functionality to the
gallium drivers.
It creates a new context interface to denote when a front
buffer is being created, and passes a private pointer to it,
this pointer is then used to decide on map/unmap if the
contents should be updated from the real frontbuffer using
get/put image.
This is primarily to make gtk's gl code work, the only
thing I've tested so far is the glarea test from
https://github.com/ebassi/glarea-example.git
v2: bump extension version,
check extension version before calling get image. (Ian)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91930
Cc: <mesa-stable at lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 103de0225b1e22aabc3e132ff30393765061ff03
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Fri Oct 16 10:28:45 2015 +1100
glsl: set image access qualifiers for AoA
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 7b3684877c97a23c62c95609fd20c845dc33f44c
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Oct 27 14:50:14 2015 -0700
i965: Do legacy userclipping in OpenGL ES 1.x contexts.
Commit fba4823a disabled user clipping for everything except
compatibility profile. Core profile and OpenGL ES 2.0+ have all removed
the classic, OpenGL 1.0 user clip planes. ES 1.x, however, still has
them.
Fixes OpenGL ES 1.1 conformance mustpass.c and userclip.c
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Tested-by: Olivier Berthier <olivierx.berthier at intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92639
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92641
commit f3d4d10a1d483cff7b3fbb6db4d6d752dd002243
Author: Emmanuel Gil Peyrot <emmanuel.peyrot at collabora.com>
Date: Thu Oct 29 15:22:19 2015 +0000
gbm.h: Add a missing stddef.h include for size_t.
This was causing compilation issues when one of its providers wasn’t
already included before gbm.h.
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
commit 7bac333508835776573e6f3192c819dbe4303480
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Oct 28 09:54:15 2015 +0000
winsys/virgl: rework line wrapping/indent
Wrap some of the 'omg it's getting out of hand' long lines, and
re-indent where things feel off.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit 493e410d552e97572ca9a492d23648f6a236e4a4
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Oct 29 10:17:04 2015 +0000
virgl: unwrap the includes
Include what you want, rather than relying on a header foo.h N levels
down the include chain, to provide something that you need.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit 7154d48c6e02c6cb29d877a3fac9de98f7cb1b4a
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Oct 28 12:50:47 2015 +0000
winsys/virgl: remove temporary ret variable
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit bdcb005788f1fb1cb47c5c658d0a25db60b1e0d2
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Oct 28 12:49:08 2015 +0000
winsys/virgl: always memset prior to ioctl
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit e992715da23ddb3759971bd3d1fc385c899f919a
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Oct 28 12:28:35 2015 +0000
winsys/virgl: use MALLOC to match FREE
The uppercase versions are wrappers which must be matched.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit 72d7d1e224049f3f22e1275df99e6e8e31de0506
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Oct 28 12:27:14 2015 +0000
winsys/virgl: remove calloc/malloc casts
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit 1ce685f05e798d1b3c0526b5431f8109dd8803fa
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Oct 28 12:38:35 2015 +0000
winsys/virgl: throw in some inline wrappers
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit 78be78b68172f702bb053ecb39105b2550e34454
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Oct 28 11:36:00 2015 +0000
virgl: introduce virgl_query() inline wrapper
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit dafcb21405622eae3f8aa49000142f870549cc9b
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Oct 28 11:21:49 2015 +0000
virgl: use virgl_screen/surface upcast wrappers
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit 7af46b9c747cbd503a2b97f00f1c603f1b75aaff
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Oct 28 11:14:02 2015 +0000
virgl: introduce and use virgl_transfer/texture/resource inline wrappers
The only two remaining cases of (struct virgl_resource *) require a
closer look. Either the error checking is missing or the arguments
provided feel wrong.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit 6b123fa07ff9d73d6e67416c2372eab5c17282b6
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Oct 28 10:48:31 2015 +0000
virgl: add virgl_context/sampler_view/so_target() upcast wrappers
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit 1f43e4e1a3395592a9d0843cdba725a2ea45fa74
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Oct 28 11:57:55 2015 +0000
winsys/virgl/drm: drop unneeded forward declaration
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit e0056228f6b4fb7614332c9b2edef891c9b6ee6f
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Oct 28 10:21:54 2015 +0000
virgl: remove sw_winsys pointer from virgl_screen
The screen already has a pointer to the (base) winsys object.
With the latter of which implemented/sub-classed as either drm or sw
based one, depending on the target.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit 0c82c2fb0b5d7c3b481190667a481bf2dd126e36
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Oct 29 10:10:35 2015 +0000
virgl: rename virgl.h to virgl_screen.h
Provide a more meaningful name considering it's purpose.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit 87f7d61e1973fe8279833d966daf75708f312b0e
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Oct 28 14:39:45 2015 +0000
virgl: move virgl_hw.h into the driver dir
Strictly speaking virgl_hw.h should reside in the driver folder, as
it describes the hardware. Moving it allows us to nuke the following
strange dependency
winsys/vtest > driver > winsys/drm
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit 014f8ef2ff7885a2856f9558c693f8d45adb400d
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Mon Oct 26 11:53:36 2015 +0000
virgl: straighten the includes confusion
Use the relevant GALLIUM_foo_CFLAGS which has all the requirements
(not to mention VISIBITY_CFLAGS) and keep ../ out of the include
directives.
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit 2c705d2220fc2a737fe093897e7d4da5825fd5ab
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Wed Oct 28 10:05:27 2015 +0000
virgl: remove the _FILE_OFFSET_BITS defines
The build already sets it as needed.
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit a05648fd7ede68d694166aea24b4d96ccf12e4d5
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Mon Oct 26 11:51:47 2015 +0000
winsys/virgl/drm: add all files to the tarball
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit 8b9e69e2eae8c3c7bd23f390c064ae34a4f410a1
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Wed Oct 28 10:08:25 2015 +0000
winsys/virgl/vtest: list all files in Makefile.sources
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit 73308ca802e8d5343ca7a32bd6a9a552f3b45456
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Mon Oct 26 11:36:50 2015 +0000
virgl: move sources list to Makefile.sources
... and add the missing files while we're at it.
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit c1bf71f77c9d4bc83fa7dc987b56f98350430d7c
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Wed Oct 28 11:47:18 2015 +0000
virgl: fix drm.h include path
The drm/ prefix is required, if using the kernel provided headers. As
most distros don't ship them it and we already depend on libdrm (which
adds the relevant -I flag) just drop the drm/ from the include.
Once a libdrm release with the virtgpu_drm.h header is released, we can
drop our local copy of the file.
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit 60418a28ea11b3e1d9365acfc168a8f8f5b41965
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Oct 30 17:23:18 2015 +0000
i965: enable ARB_shader_clock on gen7+
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 4379ca22f18f5731248ee794ab651db721ba38b2
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Wed Oct 7 11:50:01 2015 +0100
i965: Implement nir_intrinsic_shader_clock
v2:
- Add a few const qualifiers for good measure.
- Drop unneeded retype()s (Matt)
- Convert timestamp to SIMD8/16, as fs_visitor::get_timestamp() returns
SIMD4 (Connor)
v3:
- Remove unneeded temporary + MOV (Connor)
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 6a15517242214c739bfdd8b6a480ecca81e776d6
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Fri Oct 9 10:40:35 2015 +0100
i965/fs: move the fs_reg::smear() from get_timestamp() to the callers
We're about to reuse get_timestamp() for the nir_intrinsic_shader_clock.
In the latter the generalisation does not apply, so move the smear()
where needed. This also makes the function analogous to the vec4 one.
v2: Tweak the comment - The caller -> We (Matt, Connor).
v3: More comment tweaks (Connor)
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 7682844f34401f1d27c9c8f80eadbcb57286e7c4
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Wed Oct 7 11:59:26 2015 +0100
nir: add shader_clock intrinsic
v2: Add flags and inline comment/description.
v3: None of the input/outputs are variables
v4: Drop clockARB reference, relate code motion barrier comment wrt
intrinsic flag.
v5: Drop the "thus we can eliminate..." comment (Connor)
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit f1d98fc90ab6f1f424b26a5d3b3ead3b8614069a
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Fri Oct 2 10:25:51 2015 +0100
glsl: add support for the clock2x32ARB function
v2: correctly set the return type
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 51265c1b85be8e3dedf32c0652e33b55f9ae7139
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Fri Oct 2 09:56:37 2015 +0100
glsl: add ARB_shader_clock infrastructure
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit e916d5e013f01a76f7f11b60aa8b7ca5987f5193
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Fri Oct 2 09:49:47 2015 +0100
mesa: add infra for ARB_shader_clock
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 0d0329df8fc95754a8edd76d1da0b32e2aaf83df
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Sat Oct 17 11:24:50 2015 +0200
nv50: do not create an invalid HW query type
While we are at it, store the rotate offset for occlusion queries to
nv50_hw_query like on nvc0.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Pierre Moreau <pierre.morrow at free.fr>
commit 5f1eeb799bd9bcdb32382961e57ef74253701ed2
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Sat Oct 17 01:04:27 2015 +0200
nv50: move HW queries to nv50_query_hw.c/h files
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Pierre Moreau <pierre.morrow at free.fr>
commit 76b48ceee9a02d5c41a6d4e1d3b089409d8303e4
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Sun Oct 18 18:33:41 2015 +0200
nv50: move nva0_so_target_save_offset() to its correct location
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Pierre Moreau <pierre.morrow at free.fr>
commit 2e3fe0379edd4c0c2c6e87a53b077d77e5fff24e
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Sat Oct 17 00:14:28 2015 +0200
nv50: add a header file for nv50_query
Like for nvc0, this will allow to split different types of queries and
to prepare the way for both global performance counters and MP counters.
While we are at it, make use of nv50_query struct instead of pipe_query.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
commit e7ed3963ed33134cc214f0a8b8e4b8cb6029887d
Author: Julien Isorce <j.isorce at samsung.com>
Date: Fri Oct 30 11:42:53 2015 +0000
st/va: add support to export a surface as dmabuf
I.e. implements:
VaAcquireBufferHandle
VaReleaseBufferHandle
for memory of type VA_SURFACE_ATTRIB_MEM_TYPE_DRM_PRIME
And apply relatives change to:
vlVaMapBuffer
vlVaUnMapBuffer
vlVaDestroyBuffer
Implementation inspired from cgit.freedesktop.org/vaapi/intel-driver
Tested with gstreamer-vaapi with nouveau driver.
Signed-off-by: Julien Isorce <j.isorce at samsung.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
commit 802ba6f8655bf967299b027204ecdd5855050609
Author: Julien Isorce <j.isorce at samsung.com>
Date: Fri Oct 30 11:42:52 2015 +0000
st/va: implement VaDeriveImage
And apply relatives change to:
vlVaBufferSetNumElements
vlVaCreateBuffer
vlVaMapBuffer
vlVaUnmapBuffer
vlVaDestroyBuffer
vlVaPutImage
It is unfortunate that there is no proper va buffer type and struct
for this. Only possible to use VAImageBufferType which is normally
used for normal user data array.
On of the consequences is that it is only possible VaDeriveImage
is only useful on surfaces backed with contiguous planes.
Implementation inspired from cgit.freedesktop.org/vaapi/intel-driver
Signed-off-by: Julien Isorce <j.isorce at samsung.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
commit 5e763aaa21654d0591b7da14c573fc03d4a60205
Author: Julien Isorce <j.isorce at samsung.com>
Date: Fri Oct 30 11:42:51 2015 +0000
st/va: add more errors checks in vlVaBufferSetNumElements and vlVaMapBuffer
Signed-off-by: Julien Isorce <j.isorce at samsung.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
commit 86eb4131a908cb09a256778d1b415a44f0157858
Author: Julien Isorce <j.isorce at samsung.com>
Date: Fri Oct 30 11:42:50 2015 +0000
st/va: add headless support, i.e. VA_DISPLAY_DRM
This patch allows to use gallium vaapi without requiring
a X server running for your second graphic card.
Signed-off-by: Julien Isorce <j.isorce at samsung.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
commit 1bdea0e5793a466d098dc3a34ce39798a17aa207
Author: Julien Isorce <j.isorce at samsung.com>
Date: Fri Oct 30 11:42:49 2015 +0000
st/va: handle Video Post Processing for configs
Add support for VA_PROFILE_NONE and VAEntrypointVideoProc
in the 4 following functions:
vlVaQueryConfigProfiles
vlVaQueryConfigEntrypoints
vlVaCreateConfig
vlVaQueryConfigAttributes
Signed-off-by: Julien Isorce <j.isorce at samsung.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
commit 0b868807e4d6f209d5fec9948a5994936138ffcc
Author: Julien Isorce <j.isorce at samsung.com>
Date: Fri Oct 30 11:42:48 2015 +0000
st/va: add colospace conversion through Video Post Processing
Add support for VPP in the following functions:
vlVaCreateContext
vlVaDestroyContext
vlVaBeginPicture
vlVaRenderPicture
vlVaEndPicture
Add support for VAProcFilterNone in:
vlVaQueryVideoProcFilters
vlVaQueryVideoProcFilterCaps
vlVaQueryVideoProcPipelineCaps
Add handleVAProcPipelineParameterBufferType helper.
One application is:
VASurfaceNV12 -> gstvaapipostproc -> VASurfaceRGBA
Signed-off-by: Julien Isorce <j.isorce at samsung.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
commit 05b6ce42097d6ebd2820129e8155113abce0bb42
Author: Julien Isorce <j.isorce at samsung.com>
Date: Fri Oct 30 11:42:47 2015 +0000
st/va: implement dmabuf import for VaCreateSurfaces2
For now it is limited to RGBA, BGRA, RGBX, BGRX surfaces.
Signed-off-by: Julien Isorce <j.isorce at samsung.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
commit adf11331186b1e63ed3cadbcea102ecdd18627e3
Author: Julien Isorce <j.isorce at samsung.com>
Date: Fri Oct 30 11:42:46 2015 +0000
st/va: implement VaCreateSurfaces2 and VaQuerySurfaceAttributes
Inspired from http://cgit.freedesktop.org/vaapi/intel-driver/
especially src/i965_drv_video.c::i965_CreateSurfaces2.
This patch is mainly to support gstreamer-vaapi and tools that uses
this newer libva API. The first advantage of using VaCreateSurfaces2
over existing VaCreateSurfaces, is that it is possible to select which
the pixel format for the surface. Indeed with the simple VaCreateSurfaces
function it is only possible to create a NV12 surface. It can be useful
to create a RGBA surface to use with video post processing.
The avaible pixel formats can be query with VaQuerySurfaceAttributes.
Signed-off-by: Julien Isorce <j.isorce at samsung.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
commit d42029d2d9bc6b65ccf847dc9ba2e70b496d0299
Author: Julien Isorce <j.isorce at samsung.com>
Date: Fri Oct 30 11:42:45 2015 +0000
st/va: do not destroy old buffer when new one failed
If formats are not the same vlVaPutImage re-creates the video
buffer with the right format. But if the creation of this new
video buffer fails then the surface looses its current buffer.
Let's just destroy the previous buffer on success.
Signed-off-by: Julien Isorce <j.isorce at samsung.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
commit 87109e5f88131b78232e42c8fe246002867fb247
Author: Julien Isorce <j.isorce at samsung.com>
Date: Fri Oct 30 11:42:44 2015 +0000
st/va: properly defines VAImageFormat formats and improve VaCreateImage
Added PIPE_VIDEO_CHROMA_FORMAT_NONE in p_format.h
and return it by default in ChromaToPipe.
Renamed YCbCrToPipe to VaFourccToPipeFormat because it now
contains RGB.
Implemented PipeFormatToVaFourcc which will be used later in
VlVaDeriveImage.
Note that gstreamer-vaapi check all the VAImageFormat fields.
Signed-off-by: Julien Isorce <j.isorce at samsung.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
commit 7b8cc375851286e0da59fd0afde28c67b3bcabf1
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Tue Oct 27 14:21:12 2015 +0100
main: fix basename match's check if it's an array or struct
Commit 4565b6f did not update the basename match's check for
the case that string would exactly match the name of the
variable if the suffix "[0]" were appended to it.
Fixes two dEQP-GLES31 tests:
dEQP-GLES31.functional.program_interface_query.shader_storage_block.resource_list.block_array
dEQP-GLES31.functional.program_interface_query.shader_storage_block.resource_list.block_array_single_element
v2:
- Change the position of rname_has_array_index_zero to avoid an out-of-bounds
read. Reported by Tapani Pälli.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit f7f1bc6cca251193105d59811d7313e69e867d78
Author: Kristian Høgsberg <krh at bitplanet.net>
Date: Wed Oct 28 10:58:09 2015 -0700
i965: Fix invalid memory accesses after resizing brw_codegen's store table
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 73caa26e4319f4e0bbc0bf1d5d455ab0d53d20a3
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Tue Jun 9 10:26:53 2015 -0700
i965/sched: use liveness analysis for computing register pressure
Previously, we were using some heuristics to try and detect when a write
was about to begin a live range, or when a read was about to end a live
range. We never used the liveness analysis information used by the
register allocator, though, which meant that the scheduler's and the
allocator's ideas of when a live range began and ended were different.
Not only did this make our estimate of the register pressure benefit of
scheduling an instruction wrong in some cases, but it was preventing us
from knowing the actual register pressure when scheduling each
instruction, which we want to have in order to switch to register
pressure scheduling only when the register pressure is too high.
This commit rewrites the register pressure tracking code to use the same
model as our register allocator currently uses. We use the results of
liveness analysis, as well as the compute_payload_ranges() function that
we split out in the last commit. This means that we compute live ranges
twice on each round through the register allocator, although we could
speed it up by only recomputing the ranges and not the live in/live out
sets after scheduling, since we only shuffle around instructions within
a single basic block when we schedule.
Shader-db results on bdw:
total instructions in shared programs: 7130187 -> 7129880 (-0.00%)
instructions in affected programs: 1744 -> 1437 (-17.60%)
helped: 1
HURT: 1
total cycles in shared programs: 172535126 -> 172473226 (-0.04%)
cycles in affected programs: 11338636 -> 11276736 (-0.55%)
helped: 876
HURT: 873
LOST: 8
GAINED: 0
v2: use regs_read() in more places.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit c1860299b807c6a7c237962977294580f9f17c86
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Fri Jun 12 12:01:35 2015 -0700
i965/fs: split out calculation of payload live ranges
We'll need this for the scheduler too, since it wants to know when the
live ranges of payload registers end in order to model them in our
register pressure calculations.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 45cd76e342d1e8ecea38e2048b96cf5be3a30fab
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Sat Jun 6 10:55:21 2015 -0400
i965: dump scheduling cycle estimates
The heuristic we're using is rather lame, since it assumes everything is
non-uniform and loops execute 10 times, but it should be enough for
measuring improvements in the scheduler that don't result in a change in
the number of instructions.
v2:
- Switch loops and cycle counts to be compatible with older shader-db.
- Make loop heuristic 10x to match with spilling code.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 486268bdb03a36faf09d84e0458ff49dd1325c40
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Sat Jun 6 13:32:21 2015 -0400
i965: always run the post-RA scheduler
Before, we would only do scheduling after register allocation if we
spilled, despite the fact that the pre-RA scheduler was only supposed to
be for register pressure and set the latencies of every instruction to
1. This meant that unless we spilled, which we rarely do, then we never
considered instruction latencies at all, and we usually never bothered
to try and hide texture fetch latency. Although a later commit removes
the setting the latency to 1 part, we still want to always run the
post-RA scheduler since it's able to take the false dependencies that
the register allocator creates into account, and it can be more
aggressive than the pre-RA scheduler since it doesn't have to worry
about register pressure at all.
Test master post-ra-sched diff %diff
bench_OglPSBump2 396.730 402.386 5.656 +1.400%
bench_OglPSBump8 244.370 247.591 3.221 +1.300%
bench_OglPSPhong 241.117 242.002 0.885 +0.300%
bench_OglPSPom 59.555 59.725 0.170 +0.200%
bench_OglShMapPcf 86.149 102.346 16.197 +18.800%
bench_OglVSTangent 388.849 395.489 6.640 +1.700%
bench_trex 65.471 65.862 0.390 +0.500%
bench_trexoff 69.562 70.150 0.588 +0.800%
bench_heaven 25.179 25.254 0.074 +0.200%
Reviewed-by: Jason Ekstrand <jasoan.ekstrand at intel.com>
commit 85fce2d2f50335b1d204dbaedc36cdd37164a9c0
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Sun Jun 7 00:37:27 2015 -0400
i965/sched: write-after-read dependencies are free
Although write-after-write dependencies have the same latency as
read-after-write dependencies due to how the register scoreboard works,
write-after-read dependencies aren't checked by the EU at all, so
they're purely a constraint on how the scheduler can order the
instructions.
v2: fix accumulator dependencies too.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 6f231fddff1661c2ca2cfb7bb7a0e6a970bcbf40
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Fri Jun 5 19:20:57 2015 -0400
i965: fix cycle estimates when there's a pipeline stall
The issue time for an instruction is how many cycles it takes to
actually put it into the pipeline. If there's a pipeline stall that
causes the instruction to be delayed, we should first take that into
account to figure out when the instruction would start executing and
*then* add the issue time. The old code had it backwards, and so we
would underestimate the total time whenever we thought there would be a
pipeline stall by up to the issue time of the instruction.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 04c42f3ab56a19089b46dea48615aeef8b8225da
Author: Eric Anholt <eric at anholt.net>
Date: Tue Jul 28 11:35:03 2015 -0700
vc4: Allow user index buffers, to avoid slow readback for shadow IBs.
Improves low-settings openarena performance by 31.9975% +/- 0.659931%
(n=7).
commit 06fa2e864acea8f34eb3821523b1924fe8efdc9b
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Oct 29 23:25:08 2015 -0400
nv50: mark contexts shareable, compile at creation time
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit f768eaa87d3413610df645dcc94b06fa1fbe0005
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Oct 29 22:18:25 2015 -0400
nv50: allow per-sample interpolation to be forced via rast
Uses the same technique as for nvc0 of fixups before upload, and
evicting in case of state change. Removes one source of variants kept by
st/mesa.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 85ee2f7fcf59991308632d7e3a64e9a1d22fe24c
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu Oct 29 16:08:45 2015 -0700
i965: Add INTEL_DEBUG=nocompact to disable instruction compaction.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 93268939e44fec7065ceda737fbe6a063203d127
Author: Matt Turner <mattst88 at gmail.com>
Date: Sun Oct 25 19:05:56 2015 -0700
i965: Add INTEL_DEBUG=hex to print the hex with the disassembly.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 18b194925f5f80eccb53e07609083049b981d60c
Author: Matt Turner <mattst88 at gmail.com>
Date: Sun Oct 25 19:16:39 2015 -0700
i965: Print the type and writemask on null destinations.
These are often useful in debugging, and the writemask (actually
"Channel Enables") determines more than just what goes into the
destination.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit bcdf664682ea027b38e3c610e4e038956b1bb0de
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Oct 26 04:09:35 2015 -0700
i965: Test fixed_hw_reg.file against BRW_IMMEDIATE_VALUE, not IMM.
No functional change, since they were both 3, but BRW_IMMEDIATE_VALUE is
the hardware value and IMM was the IR value -- and you can see that
BRW_IMMEDIATE_VALUE was correctly used in the context of this patch.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit ee46c1e6261584326e9153a22861a16778803506
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Oct 28 21:19:52 2015 -0700
i965/vec4: Test against BRW_IMMEDIATE_VALUE, not IMM.
No functional change, since they were both 3, but BRW_IMMEDIATE_VALUE is
the hardware value and IMM was the IR value -- and you can see that
BRW_IMMEDIATE_VALUE was correctly used in the context of this patch.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 8c4151b866181198cb850137a6b65052e79554b1
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu Oct 29 10:29:55 2015 -0700
i965/fs: Use group(4, 0) to emit an exec-size 4 MOV.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 9115fa1d132b3ed38180f05c303f9190cde23878
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Oct 28 21:11:46 2015 -0700
i965/cfg: Handle no-idom case in cfg_t::dump_domtree().
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 5916b073f6b60b66e86a71b11cc3dc856d780144
Author: Matt Turner <mattst88 at gmail.com>
Date: Sun Oct 25 17:44:59 2015 -0700
i965/disasm: Remove unused _addr_mode argument from src_ia1().
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit e09e5f992eb233a4e2afb505e150befd7a67deac
Author: Matt Turner <mattst88 at gmail.com>
Date: Sun Oct 25 17:20:54 2015 -0700
i965: Set correct field for indirect align16 addrimm.
This has been wrong since the initial import of the i965 driver.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit fa142773d9a7d3249396fe2547da24eaf58962c1
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Oct 23 23:15:03 2015 -0700
i965/vec4: Drop brw_set_default_* before popping insn state.
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 11a7b6bbaaa8790f580ccdd99ac1798629df2041
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Oct 23 23:13:07 2015 -0700
i965/vec4: Remove unnecessary #includes from the generator.
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 744cc036b9734da13be85183e668536a69b7d224
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Oct 30 10:39:13 2015 +1000
r600: enable SB for geom shaders on pre-evergreen
I've checked with piglit and one tests fails, but it fails
on evergreen as well, so will get fixed later.
Otherwise SB seems to be working fine for geom shaders on my
rv635.
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit c6b24448b578c4a8ab031923df3ef1e2d865d5bb
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Oct 22 15:35:15 2015 -0700
i965/vec4: Eliminate the vec4_generator class altogether.
We really weren't taking advantage of vec4_generator being a class.
By adding a "p" parameter to the helper methods, and "prog_data" to
ones which need binding table information, we can convert everything
to static functions.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 1a094a2ee2d63073ac12c8ab0dbd38c0e9270cf5
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Oct 22 15:04:52 2015 -0700
i965/vec4: Move vec4_generator class definition into the .cpp file.
The public API for the generator is brw_vec4_generate_code(); nobody
actually needs to use the class. This means we can extend it without
triggering the recompiles associated with altering brw_vec4.h.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 4cba8f5d21e4b50343e7c7bfbeb603b59c5d71dd
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Oct 22 15:01:27 2015 -0700
i965/vec4: Wrap vec4_generator in a C function.
vec4_generator is a class for convenience, but only exports a single
method as its public API. It makes much more sense to just export a
single function.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 73ff0ead3688519eb76ea8bc32eabb9004e6f37b
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Oct 22 16:04:15 2015 -0700
i965/vec4: Convert src_reg/dst_reg to brw_reg at the end of the visitor.
This patch makes the visitor convert registers to the HW_REG file at the
very end, after register allocation, post-RA scheduling, and dependency
control flagging. After that, everything is in fixed brw_regs.
This simplifies the code generator, as it can just use the hardware
registers rather than having to interpret our abstract files. In
particular, interpreting the UNIFORM file meant reading prog_data
to figure out where push constants are supposed to start.
Having the part of the code that performs register allocation also
translate everything to hardware registers seems sensible.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit f75f21a24ae2dd83507f3d4d8007f0fcfe6db802
Author: Ivan Kalvachev <ikalvachev at gmail.com>
Date: Sun Oct 25 01:16:58 2015 +0300
r600g: Fix special negative immediate constants when using ABS modifier.
Some constants (like 1.0 and 0.5) could be inlined as immediate inputs
without using their literal value. The r600_bytecode_special_constants()
function emulates the negative of these constants by using NEG modifier.
However some shaders define -1.0 constant and want to use it as 1.0.
They do so by using ABS modifier. But r600_bytecode_special_constants()
set NEG in addition to ABS. Since NEG modifier have priority over ABS one,
we get -|1.0| as result, instead of |1.0|.
The patch simply prevents the additional switching of NEG when ABS is set.
[According to Ivan Kalvachev, this bug was fond via
https://github.com/iXit/Mesa-3D/issues/126 and
https://github.com/iXit/Mesa-3D/issues/127]
Signed-off-by: Ivan Kalvachev <ikalvachev at gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
CC: <mesa-stable at lists.freedesktop.org>
commit 24c90888aeaf90b13700389b91b74bf63ee9f28d
Author: Nicolai Hähnle <nhaehnle at gmail.com>
Date: Fri Oct 23 01:06:15 2015 +0200
st/mesa: fix mipmap generation for immutable textures with incomplete pyramids
Without the clamping by NumLevels, the state tracker would reallocate the
texture storage (incorrect) and even fail to copy the base level image
after reallocation, leading to the graphical glitch of
https://bugs.freedesktop.org/show_bug.cgi?id=91993 .
A piglit test has been submitted for review as well (subtest of
arb_texture_storage-texture-storage).
v2: also bypass all calls to st_finalize_texture (suggested by Marek Olšák)
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 65f6caf43e8bbea7c8a0d4e146ad7186c276ff9a
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Wed Oct 14 14:32:43 2015 -0700
mesa: Enable ASTC in GLES' [NUM_]COMPRESSED_TEXTURE_FORMATS queries
In OpenGL ES, the COMPRESSED_TEXTURE_FORMATS query returns the set of
supported specific compressed formats. Since ASTC formats fit within
that category, include them in the set and update the
NUM_COMPRESSED_TEXTURE_FORMATS query as well.
This enables GLES2-based ASTC dEQP tests to run. See the Bugzilla for
more info.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92193
Reported-by: Tapani Pälli <tapani.palli at intel.com>
Suggested-by: Ian Romanick <ian.d.romanick at intel.com>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 8090a1c32692e89b79d89f4dc959a26532dd2f91
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Tue Oct 13 21:05:07 2015 -0700
mesa/texcompress: Restrict FXT1 format to desktop GL subset
In agreement with the extension spec and commit
dd0eb004874645135b9aaac3ebbd0aaf274079ea, filter FXT1 formats to the
desktop GL profiles. Now we no longer advertise such formats as supported
in an ES context and then throw an INVALID_ENUM error when the client
tries to use such formats with CompressedTexImage2D.
Fixes the following 26 dEQP tests:
* dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_invalid_border
* dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_invalid_border_cube_neg_x
* dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_invalid_border_cube_neg_y
* dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_invalid_border_cube_neg_z
* dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_invalid_border_cube_pos_x
* dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_invalid_border_cube_pos_y
* dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_invalid_border_cube_pos_z
* dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_invalid_size
* dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_level_max_cube_pos
* dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_level_max_tex2d
* dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_neg_level_cube
* dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_neg_level_tex2d
* dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_neg_width_height_cube_neg_x
* dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_neg_width_height_cube_neg_y
* dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_neg_width_height_cube_neg_z
* dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_neg_width_height_cube_pos_x
* dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_neg_width_height_cube_pos_y
* dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_neg_width_height_cube_pos_z
* dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_neg_width_height_tex2d
* dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_width_height_max_cube_neg_x
* dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_width_height_max_cube_neg_y
* dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_width_height_max_cube_neg_z
* dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_width_height_max_cube_pos_x
* dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_width_height_max_cube_pos_y
* dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_width_height_max_cube_pos_z
* dEQP-GLES2.functional.negative_api.texture.compressedteximage2d_width_height_max_tex2d
v2. Use _mesa_is_desktop_gl() (Ilia, Ian)
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
commit 0260620ab35615838a76bf218788adc957212934
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Wed Oct 28 11:20:36 2015 +0100
nvc0: expose a group of performance metrics on Fermi
This allows to monitor those performance metrics through
GL_AMD_performance_monitor.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
commit 6166a8e369b86395ffec7229257f797662f9d1aa
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Oct 28 15:38:53 2015 -0400
st/mesa: create temporary textures with the same nr_samples as source
Not sure if this is actually reachable in practice (to have a complex
copy with MS textures).
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit afbe8b6085c4761c25b7bc49a051a08e10a87805
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Tue Oct 27 13:18:42 2015 +0200
glsl: add fragdata arrays to program resource list
This makes sure that user is still able to query properties about
variables that have gotten removed by opt_dead_builtin_varyings pass.
Fixes following OpenGL ES 3.1 test:
ES31-CTS.program_interface_query.output-layout
No Piglit regressions.
v2: cleanup, drop extra parenthesis (Topi)
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Marta Lofstedt <marta.lofstedt at intel.com>
commit 6ce0857e30a8484f1b190ccf37631d64e629a468
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Tue Oct 27 13:18:41 2015 +0200
mesa: add fragdata_arrays list to gl_shader
This is required to store information about fragdata arrays, currently
these variables get lost and cannot be retrieved later in sensible way
for program interface queries. List will be utilized by next patch.
Patch also modifies opt_dead_builtin_varyings pass to build list when
lowering fragdata arrays. This is identical approach as taken with
packed varyings pass.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Marta Lofstedt <marta.lofstedt at intel.com>
commit 85f1f0441326ef3f49a4edeac474599db471ef7f
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Thu Oct 22 10:07:54 2015 +0200
glsl: fix GL_BUFFER_DATA_SIZE value for shader storage blocks with unsize arrays
From ARB_program_interface_query:
"For the property of BUFFER_DATA_SIZE, then the implementation-dependent
minimum total buffer object size, in basic machine units, required to hold
all active variables associated with an active uniform block, shader
storage block, or atomic counter buffer is written to <params>. If the
final member of an active shader storage block is array with no declared
size, the minimum buffer size is computed assuming the array was declared
as an array with one element."
Fixes the following dEQP-GLES31 tests:
dEQP-GLES31.functional.program_interface_query.shader_storage_block.buffer_data_size.named_block
dEQP-GLES31.functional.program_interface_query.shader_storage_block.buffer_data_size.unnamed_block
dEQP-GLES31.functional.program_interface_query.shader_storage_block.buffer_data_size.block_array
v2:
- Fix comment's indentation and explain that the parser already
checked that unsized array is in last element of a shader
storage block (Iago).
- Add assert (Iago).
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit cf93251bedc831dc252afaec82d654de3cbd9a48
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Oct 28 22:02:39 2015 -0700
docs: Mark GL_ARB_fragment_layer_viewport as done on i965.
commit 8c902a580a490181e7cde29073b11181db4614f8
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Jun 17 13:06:18 2015 -0700
i965: Implement ARB_fragment_layer_viewport.
Normally, we could read gl_Layer from bits 26:16 of R0.0. However, the
specification requires that bogus out-of-range 32-bit values written by
previous stages need to appear in the fragment shader as-written.
Instead, we pass in the full 32-bit value from the VUE header as an
extra flat-shaded varying. We have the SF override the value to 0
when the previous stage didn't actually write a value (it's actually
defined to return 0).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit 5392328a3218c0a69301badefe8fed79ca0d8642
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Oct 26 00:52:14 2015 -0700
i965: Make calculate_attr_overrides return the URB read offset.
Traditionally, we've hardcoded "URB Entry Read Offset" to 1 (which
represents 2 vec4 varying slots) to skip over the 8 DWord VUE header.
In order to support ARB_fragment_layer_viewport, we'll need to read
from that header. This patch adds the basic plumbing necessary to
calculate a value dynamically and hook it up in the SBE packets.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit b3d19d20f27c9169641051ac6f855481e58623b3
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Oct 26 00:14:13 2015 -0700
glsl: Mark gl_ViewportIndex and gl_Layer varyings as flat.
Integer varyings need to be flat qualified - all others were already.
I think we just missed this. Presumably some hardware passes this via
sideband and ignores attribute interpolation, so no one has noticed.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit b94cdcdada251bb8e866cb7af0f2ff222b55a918
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Oct 26 01:03:12 2015 -0700
i965/fs: Properly check for PAD in fragment shaders with > 16 varyings.
Commit 268008f98c3810b9f276df985dc93efc0c49f33e changed unused VUE map
slots to be initialized with BRW_VARYING_SLOT_PAD, not COUNT. I missed
updating this. It also means that commit message was wrong, as some
code *did* rely slots being initialized to COUNT.
This may fix a bug with SSO programs with > 16 FS input varyings.
I think we probably just emitted extra pointless code, but probably
didn't break anything. We might also just have no tests for that.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit 6ae47a3eb4e30fa92dd60e4a16e016e8585c3c48
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Oct 26 01:02:18 2015 -0700
i965: Update stale comment about unused VUE map slots.
I changed this from COUNT to PAD in commit 268008f98c3810b9f276df985dc93ef.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit 5227e915803079e5e72a0b2fde3a11d62af8df99
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Oct 23 23:25:33 2015 -0400
nv50/ir: adapt to new method for passing in cull/clip distance masks
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit a5bae7b31d642ad55bc7bed4f2130788413a1d21
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Tue Oct 20 18:50:54 2015 -0400
nvc0: share shaders between contexts and build immediately
Avoid deferring building shaders until draw time, should hopefully
reduce any stuttering, as well as enable shader-db style analysis.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit b75fff70d82474a571c59c2a3a01e4f9f02286a7
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Tue Oct 20 18:03:40 2015 -0400
nvc0: do upload-time fixups for interpolation parameters
Unfortunately flatshading is an all-or-nothing proposition on nvc0,
while GL 3.0 calls for the ability to selectively specify explicit
interpolation parameters on gl_Color/gl_SecondaryColor which would
override the flatshading setting. This allows us to fix up the
interpolation settings after shader generation based on rasterizer
settings.
While we're at it, we can add support for dynamically forcing all
(non-flat) shader inputs to be interpolated per-sample, which allows
st/mesa to not generate variants for these.
Fixes the remaining failing glsl-1.30/execution/interpolation piglits.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 77f58c04cc287b72e2b859d71591da158db6830a
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Oct 2 00:01:23 2015 -0700
nir: Copy "patch" flag from ir_variable to nir_variable.
This was introduced in GLSL IR after NIR development had branched.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 9c8208f2c15445b00ba170ff96a9ea4ce6c083e1
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Oct 8 23:53:47 2015 -0700
nir: Add intrinsics for tessellation shader system values.
nir_intrinsic_load_patch_vertices_in corresponds to gl_PatchVerticesIn,
a special input in both the TCS and TES stages.
nir_intrinsic_load_tess_coord corresponds to gl_TessCoord, a special
tessellation evaluation shader input.
nir_intrinsic_load_tess_level_outer/inner correspond to the
gl_TessLevelOuter[] and gl_TessLevelInner[] evaluation shader inputs,
which we treat as system values because they're stored specially.
(These intrinsics are only for the TES - the TCS uses output variables.)
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit bf05af3f0e8769f417bbd995470dc1b8083a0df9
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Oct 28 00:53:20 2015 -0700
i965: Fix missing BRW_NEW_*_PROG_DATA flagging caused by cache reuse.
Consider the case of two nearly identical GLSL fragment shaders:
out vec4 color;
void main() { color = vec4(1); }
and
layout(early_fragment_tests) in;
out vec4 color;
void main() { color = vec4(1); }
These shaders compile to the exact same assembly, but have distinct
values for brw_wm_prog_data::early_fragment_tests.
Since these are two independent GLSL shaders, they have different
program keys - notably, brw_wm_prog_key::program_string_id differs.
When uploading the second, brw_upload_cache will find an existing copy
of the assembly in the cache BO, which means matching_data will be
non-NULL. Although we create a second cache item (with the new key
and prog_data), we set item->offset to the existing copy and avoid
re-uploading duplicate assembly.
However, brw_search_cache() would only flag BRW_NEW_*_PROG_DATA if
item->offset differed from the supplied offset. With reuse, both
programs have the same offset, but prog_data changed. We have to
flag it, but failed to.
To fix this, we simply need to check if the aux (prog_data) pointer
changed. If either the assembly or the prog_data differs, flag it.
This fixes a regression since 1bba29ed403e735ba0bf04ed8aa2e571884f,
where Topi fixed brw_upload_cache() to actually reuse identical
assembly. Prior to that, reuse basically never happened due to bugs.
Unfortunately, this code apparently wasn't prepared to handle reuse!
Fixes GPU hangs in Dolphin on Broadwell.
Huge thanks to Pierre Bourdon and Ilia Mirkin for debugging this
and helping track down the real issue.
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92623
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Tested-by: Pierre Bourdon <delroth at gmail.com>
commit 37402014e80f991169f9e05c1520667ba3930baf
Author: Laurent Carlier <lordheavym at gmail.com>
Date: Wed Oct 28 15:47:09 2015 +0100
clover: fix building fix clang-3.8
https://bugs.freedesktop.org/show_bug.cgi?id=92705
v2.1: use Linker::Flags::None instead of 0 and emplace_back()
Signed-off-by: Laurent Carlier <lordheavym at gmail.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit d0693d7515efb9a747b7fe1d0a21a1ca4bdf33a0
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Oct 28 20:52:50 2015 -0400
nv50: add ARB_copy_image support
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit ebbd7b41c0be8666f47b06cb83ae5e5117088ea1
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Oct 28 16:18:18 2015 -0400
nvc0: add ARB_copy_image support
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 3bbb8715acd1cb85ea7aa7763c06cd12347a1a9a
Author: Julien Isorce <j.isorce at samsung.com>
Date: Tue Oct 20 17:34:23 2015 +0100
nvc0: fix crash when nv50_miptree_from_handle fails
Signed-off-by: Julien Isorce <j.isorce at samsung.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
commit 2bf224b3f96f926ba442d2b33a6f50d33e31cee0
Author: Brian Paul <brianp at vmware.com>
Date: Tue Oct 27 13:50:10 2015 -0600
vbo: replace assertion with conditional in vbo_compute_max_verts()
With just the right sequence of per-vertex commands and state changes,
it's possible for this assertion to fail (such as with viewperf11's
lightwave-06-1 test). Instead of asserting, return 0 so that the
caller knows the VBO is full and needs to be flushed.
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
commit 8e9c3070bf45cd33a77537c6769d422d2c9fa8c3
Author: Brian Paul <brianp at vmware.com>
Date: Wed Oct 28 11:03:21 2015 -0600
mesa: minor formatting fix in get_tex_rgba_compressed()
commit f04f13622f3e71bee057d60a6be9c53b92b56cc9
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Aug 24 02:55:20 2015 +0200
st/mesa: implement ARB_copy_image
I wonder if the craziness was worth it.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit ce9db16e1c101204cdb6b2482aa1b4c7d0c59d41
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Aug 24 01:19:35 2015 +0200
gallium: add PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
For ARB_copy_image.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit e82c527f1fc2f8ddc64954ecd06b0de3cea92e93
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Aug 24 01:08:48 2015 +0200
radeonsi: allow copying between compatible compressed and uncompressed formats
which is where a block in src maps to a pixel in dst and vice versa.
e.g. DXT1 <-> R32G32_UINT
DXT5 <-> R32G32B32A32_UINT
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 6a4dc1ad492d7d53c5c17e6eb975f0ed44b6741d
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Oct 27 11:11:19 2015 +0100
mesa: set TargetIndex in VDPAURegister*SurfaceNV (v2)
We initialized Target, but not TargetIndex.
This is required since 7d7dd1871174905dfdd3ca874a09d9.
v2: do it in the right place. Noticed by Brian Paul.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92645
Reviewed-by: Brian Paul <brianp at vmware.com>
commit bfc73ff10eafad59b6ae9ca3991f9f1a3700b3a1
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Oct 7 12:38:12 2015 +0100
i965: remove unneeded src_reg copy in emit_shader_time_write
The variable is already of type src_reg. creating a new instance only to
destroy it seems unnecessary.
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 0325f6822899fa58963094e3bb6433e3c6d5b374
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Oct 7 12:38:11 2015 +0100
i965: remove cache_aux_free_func array
There is only one function that can be called, which is well known at
compilation time.
The abstraction used here seems unnecessary, so let's use a direct call
to brw_stage_prog_data_free() when appropriate, cut down the size of
struct brw_cache.
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 74fcc4c41fe547ea5fb8e23f25fc71b25f5afe96
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Tue Oct 27 09:33:01 2015 +0100
main: fix GL_MAX_NUM_ACTIVE_VARIABLES value for shader storage blocks
The maximum number of active variables for shader storage blocks should
take into account the specific rules for shader storage blocks, i.e. for
an active shader storage block member declared as an array, an entry
will be generated only for the first array element, regardless of its type.
Fixes 3 dEQP-GLES31.functional.* tests:
dEQP-GLES31.functional.program_interface_query.shader_storage_block.active_variables.named_block
dEQP-GLES31.functional.program_interface_query.shader_storage_block.active_variables.unnamed_block
dEQP-GLES31.functional.program_interface_query.shader_storage_block.active_variables.block_array
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 03c92ffbf636ef9333f4575602e4de471ec7cdba
Author: Boyuan Zhang <boyuan.zhang at amd.com>
Date: Fri Oct 23 13:44:23 2015 -0400
st/vdpau: disable RefPicList for Vdpau HEVC
Signed-off-by: Boyuan Zhang <boyuan.zhang at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Leo Liu <leo.liu at amd.com>
commit ad2752e94b535dbcf01829464431ce242068de53
Author: Boyuan Zhang <boyuan.zhang at amd.com>
Date: Fri Oct 23 13:37:48 2015 -0400
st/va: add VAAPI HEVC decode support
Signed-off-by: Boyuan Zhang <boyuan.zhang at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Leo Liu <leo.liu at amd.com>
commit 38c3d7cfc42f00c47f720ab293ad88b9a0f637f2
Author: Boyuan Zhang <boyuan.zhang at amd.com>
Date: Fri Oct 23 12:30:33 2015 -0400
radeon/uvd: implement and add flag for VAAPI HEVC decode
Signed-off-by: Boyuan Zhang <boyuan.zhang at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Leo Liu <leo.liu at amd.com>
commit 231605d14d3ca75ce99ea01d75868a2f2862504d
Author: Boyuan Zhang <boyuan.zhang at amd.com>
Date: Fri Oct 23 12:12:19 2015 -0400
vl: add RefPicList defines for VAAPI HEVC decode
Signed-off-by: Boyuan Zhang <boyuan.zhang at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Leo Liu <leo.liu at amd.com>
commit 16c49da63a72aa4b1dce5c90397ee4af2f6a8f9d
Author: Marta Lofstedt <marta.lofstedt at intel.com>
Date: Mon Oct 26 10:58:37 2015 +0100
mesa: Draw indirect is not allowed if the default VAO is bound.
From OpenGL ES 3.1 specification, section 10.5:
"DrawArraysIndirect requires that all data sourced for the
command, including the DrawArraysIndirectCommand
structure, be in buffer objects, and may not be called when
the default vertex array object is bound."
Signed-off-by: Marta Lofstedt <marta.lofstedt at linux.intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 93eb4f9287576e346838e7b38fec9b42518605f6
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Oct 26 11:11:44 2015 +0100
winsys/amdgpu: remove the dcc_enable surface flag
dcc_size is sufficient and doesn't need a further comment in my opinion.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
commit 3aebc596b339b1b787ed0dfc27793263d48b2819
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Oct 22 22:55:19 2015 +0200
radeonsi: add debug flags that disable DCC and DCC fast clear
For debugging, bug reports, etc.
This is not in the radeonsi directory, but it is about radeonsi.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
commit 235d38584cd47faa2837cd66ebdc770f295f47c4
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Oct 22 22:48:32 2015 +0200
radeonsi: properly check if DCC is enabled and allocated
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
commit 5bc5dca0cbcb1a13fbe9b3a33489e88531d1eb33
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Oct 22 11:10:14 2015 +0200
radeonsi: simplify DCC handling in si_initialize_color_surface
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
commit 3daa7e5147f164e822269f13c3bcccfa6446fa83
Author: Marta Lofstedt <marta.lofstedt at intel.com>
Date: Mon Oct 26 11:50:24 2015 +0100
mesa: Draw indirect is not allowed when xfb is active and unpaused
OpenGL ES 3.1 specification, section 10.5:
"An INVALID_OPERATION error is generated if
transform feedback is active and not paused."
Signed-off-by: Marta Lofstedt <marta.lofstedt at linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 2c91e086563541271668f9ea6ca58689c0c97d44
Author: Marta Lofstedt <marta.lofstedt at intel.com>
Date: Mon Oct 26 11:22:27 2015 +0100
mesa: Draw Indirect return wrong error code on unalinged
From OpenGL 4.4 specification, section 10.4 and
Open GL Es 3.1 section 10.5:
"An INVALID_VALUE error is generated if indirect is not a multiple
of the size, in basic machine units, of uint."
However, the current code follow the ARB_draw_indirect:
https://www.opengl.org/registry/specs/ARB/draw_indirect.txt
"INVALID_OPERATION is generated by DrawArraysIndirect and
DrawElementsIndirect if commands source data beyond the end
of a buffer object or if <indirect> is not word aligned."
V2: After discussions on the list, it was suggested to
only keep the INVALID_VALUE error.
Signed-off-by: Marta Lofstedt <marta.lofstedt at linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 4565b6f4fb59d261f9128ffe91c0787af4b15ea4
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Wed Oct 21 14:34:29 2015 +0200
main: Remove interface block array index for doing the name comparison
From ARB_program_query_interface spec:
"uint GetProgramResourceIndex(uint program, enum programInterface,
const char *name);
[...]
If <name> exactly matches the name string of one of the active resources
for <programInterface>, the index of the matched resource is returned.
Additionally, if <name> would exactly match the name string of an active
resource if "[0]" were appended to <name>, the index of the matched
resource is returned. [...]"
"A string provided to GetProgramResourceLocation or
GetProgramResourceLocationIndex is considered to match an active variable
if:
[...]
* if the string identifies the base name of an active array, where the
string would exactly match the name of the variable if the suffix
"[0]" were appended to the string;
[...]
"
Fixes the following two dEQP-GLES31 tests:
dEQP-GLES31.functional.program_interface_query.shader_storage_block.resource_list.block_array
dEQP-GLES31.functional.program_interface_query.shader_storage_block.resource_list.block_array_single_element
v2:
- Add AoA support (Timothy)
- Apply it too for GetUniformLocation(), GetUniformName() and others
because ARB_program_interface_query says that they are equivalent
to GetProgramResourceLocation() and GetProgramResourceName() (Tapani)
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 3359ad6cda49fb977d837eb00e8ae4d781d95c2a
Author: Eric Anholt <eric at anholt.net>
Date: Wed Aug 5 20:05:56 2015 -0700
vc4: Add support for copy propagation with unpack flags present.
total instructions in shared programs: 89251 -> 87862 (-1.56%)
instructions in affected programs: 52971 -> 51582 (-2.62%)
commit 01ca4f207efac555ff5f729dce1687a68ba65400
Author: Eric Anholt <eric at anholt.net>
Date: Mon Oct 26 13:45:06 2015 -0700
vc4: Rewrite the pack instructions as a MOV with a dst pack flag
Another step in reducing the special-casing of instructions.
commit 72fa2ae20b979ced1b4dde16f81b28d02a2e3b7b
Author: Eric Anholt <eric at anholt.net>
Date: Mon Oct 26 14:16:19 2015 -0700
vc4: Move dst pack setup out to a helper function with more asserts.
commit 99a9a5a345fab8bbf36ab4e42581f8ee04a59a63
Author: Eric Anholt <eric at anholt.net>
Date: Sat Oct 24 17:35:03 2015 -0700
vc4: Switch the unpack ops to being unpack flags on a mov.
This paves the way for copy propagating our unpacks. We end up with a
small change on shader-db:
total instructions in shared programs: 89390 -> 89251 (-0.16%)
instructions in affected programs: 19041 -> 18902 (-0.73%)
which appears to be because we no longer convert MOVs for an FMAX dst,
r4.unpack, r4.unpack (instead of the previous MOV dst, r4.unpack), and
this ends up with a slightly better schedule.
commit 548b05d53f3c89630aa77fc92ff174f5d8162ab2
Author: Eric Anholt <eric at anholt.net>
Date: Mon Oct 26 13:22:18 2015 -0700
vc4: Drop some confused code about pack/unpack handling.
At one point I thought packs and unpacks were in the same field of the
instruction. They aren't. These instructions therefore never cause a
pack.
total instructions in shared programs: 89472 -> 89390 (-0.09%)
instructions in affected programs: 15261 -> 15179 (-0.54%)
commit a7b424e835269d9aab6ba9b7b23f836474682725
Author: Eric Anholt <eric at anholt.net>
Date: Mon Oct 26 14:07:44 2015 -0700
vc4: Reduce MOV special-casing in QIR-to-QPU.
I'm going to introduce some more types of MOV, which also want the elision
of raw MOVs.
commit 652a864b257650e730ecec9e5882d765840a02e1
Author: Eric Anholt <eric at anholt.net>
Date: Mon Oct 26 13:17:33 2015 -0700
vc4: Fix up the test for whether the unpack can be from r4.
We can do 16a/16b from float as well. No difference on shader-db.
commit 3d7a088608b38b3a460ad7ba5c7fb575815c8a43
Author: Eric Anholt <eric at anholt.net>
Date: Mon Oct 26 13:57:57 2015 -0700
vc4: Don't try to follow MOVs across a pack.
commit 6eb0760f4896d2dd45820ec1fcab36496228b761
Author: Eric Anholt <eric at anholt.net>
Date: Sat Oct 24 17:49:03 2015 -0700
vc4: Only copy propagate raw MOVs.
No problems being fixed, but needed for the new unpack changes.
commit 0ccacfa0170f19e08228e7404e77a9da8f5f633c
Author: Eric Anholt <eric at anholt.net>
Date: Sat Oct 24 17:33:30 2015 -0700
vc4: If a QIR source has an unpack set, print it.
Not used yet, but will be.
commit 8034e7d6f1be3c9c1a9626b64830617ccf000ecc
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Jul 28 18:16:37 2015 -0700
glsl: Convert TES gl_PatchVerticesIn into a constant when using a TCS.
When a TCS is present, the TES input gl_PatchVerticesIn is actually a
constant - it's simply the # of output vertices specified by the TCS
layout qualifiers. So, we can replace the system value with a constant,
which may allow further optimization, and will likely be more efficient.
If the TCS is absent, we can't do this optimization.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 8f84a8e257291168ec4b394b1eaa6acef1538cea
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Fri Oct 16 09:18:24 2015 -0700
i965: Add missing close-parenthesis in error messages
Trivial.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
commit 7070c8879adff2a1204d7473f119d8194eff919b
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Thu Oct 15 12:50:12 2015 -0700
i965: Fix is-renderable check in intel_image_target_renderbuffer_storage
Previously we could create a renderbuffer with format
MESA_FORMAT_R8G8B8A8_UNORM, convert that renderbuffer to an EGLImage,
then FAIL to convert the EGLImage back to a renderbuffer because
reasons. Just use the same check in
intel_image_target_renderbuffer_storage that brw_render_target_supported
uses.
There are more checks in brw_render_target_supported, but I don't think
they are necessary here. A different approach would be to refactor
brw_render_target_supported to take rb->Format and rb->NumSamples as
parameters (instead of a gl_renderbuffer) and use the new function here.
Fixes:
ES2-CTS.gtf.GL2ExtensionTests.egl_image.egl_image
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Tested-by: Tapani Pälli <tapani.palli at intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92476
Cc: "10.3 10.4 10.5 10.6 11.0" <mesa-stable at lists.freedesktop.org>
commit a3d0359aff7a9be90149c416844f330b4f9a15ed
Author: Timothy Arceri <timothy.arceri at collabora.com>
Date: Tue Oct 27 06:58:15 2015 +1100
glsl: keep track of intra-stage indices for atomics
This is more optimal as it means we no longer have to upload the same set
of ABO surfaces to all stages in the program.
This also fixes a bug where since commit c0cd5b var->data.binding was
being used as a replacement for atomic buffer index, but they don't have
to be the same value they just happened to end up the same when binding is 0.
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Cc: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: Alejandro Piñeiro <apinheiro at igalia.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90175
commit 711489648bcce5cd8fcf14e73e5affe069010c01
Author: Roland Scheidegger <sroland at vmware.com>
Date: Mon Oct 26 16:44:47 2015 +0100
gallivm: disable f16c when not using AVX
f16c intrinsic can only be emitted when AVX is used. So when we disable AVX
due to forcing 128bit vectors we must not use this intrinsic (depending on
llvm version, this worked previously because llvm used AVX even when we didn't
tell it to, however I've seen this fail with llvm 3.3 since
718249843b915decf8fccec92e466ac1a6219934 which seems to have the side effect
of disabling avx in llvm albeit it only touches sse flags really, but
with ea421e919ae6e72e1319fb205c42a6fb53ca2f82 it's now really disabled).
Albeit being able to use AVX with 128bit vectors also would have its uses, the
code as is really was meant to emulate jit code creation for less capable cpus.
v2: add some (ifdefed out) missing de-featuring options for simulating
less capable cpus.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit a61be1a79897931e3efb5b9119c48e1fb1257db4
Author: Julien Isorce <j.isorce at samsung.com>
Date: Fri Oct 23 13:25:47 2015 +0100
st/va: pass picture desc to begin and decode
At least vl_mpeg12_decoder uses the picture
desc in begin_frame and decode_bitstream.
https://bugs.freedesktop.org/show_bug.cgi?id=92634
Signed-off-by: Julien Isorce <j.isorce at samsung.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
commit 8ae4317c3643f1728f99172812df6df2d30456bb
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Mon Oct 26 11:13:14 2015 +0200
mesa: add additional checks for uniform location query
Patch adds additional check to make sure we don't return locations for
structures or arrays of structures.
From page 79 of the OpenGL 4.2 spec:
"A valid name cannot be a structure, an array of structures, or any
portion of a single vector or a matrix."
v2: use without-array() to simplify code (Timothy)
No Piglit or CTS regressions observed.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit a305d59baa4ad9f8ebbe74b53f022e8ff6636c29
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Sun Oct 25 10:17:08 2015 +0000
docs: add news item and link release notes for 11.0.4
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
commit 47dd80a35df94dc9b5ba16bf102b85751024ca09
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Sun Oct 25 10:04:09 2015 +0000
docs: add sha256 checksums for 11.0.4
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
(cherry picked from commit ec14e6f8fd05999b482e0785d8cd286042c9c254)
commit bddb7a51c3d0403767dc691e91e6186b3c3c1c1f
Author: Emil Velikov <emil.velikov at collabora.com>
Date: Sat Oct 24 19:34:01 2015 +0100
docs: add release notes for 11.0.4
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
(cherry picked from commit 31bf24703193cc23961923e01548b1acb2760a93)
commit fcb39f5b6a0c7cc92b4260b44a3f327ec84ef47a
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Jul 25 21:29:28 2015 -0700
i965: Make brw_varying_to_offset take a const pointer to the VUE map.
It doesn't modify it.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit a2eba3362f1c120e5e70b56568d44470cb75fdc8
Author: Eric Anholt <eric at anholt.net>
Date: Tue Aug 4 21:23:53 2015 -0700
vc4: Fix names of the 16-bit unpacks
They're only f16-to-f32 on a float operation, otherwise they're
i16-to-i32.
commit a238ad372d0914b8a95c3521c52639a4ddee7bae
Author: Eric Anholt <eric at anholt.net>
Date: Sat Oct 24 17:38:26 2015 -0700
vc4: Don't try to register coalesce into the VPM across non-raw MOVs.
No known bugs, just something I noticed while updating optimization code
for other changes.
commit ae1d3322ccfd4758614167f4c6087d8acabe3cc5
Author: Eric Anholt <eric at anholt.net>
Date: Sat Oct 24 17:04:49 2015 -0700
vc4: Take advantage of the 8888 pack function in pack_unorm_4x8.
One instruction instead of four, and it turns out you do this a lot for
the Over operator.
total uniforms in shared programs: 32168 -> 32087 (-0.25%)
uniforms in affected programs: 318 -> 237 (-25.47%)
total instructions in shared programs: 89830 -> 89472 (-0.40%)
instructions in affected programs: 6434 -> 6076 (-5.56%)
commit f09ed63f4342846e361242233162799140674d5f
Author: Eric Anholt <eric at anholt.net>
Date: Sat Oct 24 16:30:30 2015 -0700
vc4: Fix the test for skipping raw MOVs.
I don't know what previous test was trying to do, but it dates back to the
first add of vc4_qpu_emit.c. No change to shader-db.
commit 9ecfc6baf1c92a9050942e0f015ba4e9e2619cb9
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Fri Oct 23 14:38:39 2015 -0700
i965: Remove unused devinfo revision
I left the function to obtain the revision because it is, and will continue to
be useful in the future. I'd rather not have to dig it up every time we need it.
Comments left at the implementation to say as much.
This was accidentally left here when I moved the early platform support:
commit 28ed1e08e8ba98ebd4ff0b56326372f0df9c73ad
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Fri Aug 7 13:58:37 2015 -0700
i965/skl: Remove early platform support
Signed-off-by: Ben Widawsky <benjamin.widawsky at intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit b0342f48d07568f77cde035b861f8eb67f941ae4
Author: Fabio Pedretti <fabio.ped at libero.it>
Date: Thu Oct 15 10:00:23 2015 +0200
docs/index.html: fix typo
Reviewed-by: Boyan Ding <boyan.j.ding at gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 1e8d0cc62897fc90ac7dc9a92e80e714e52d3e77
Author: Rob Clark <robclark at freedesktop.org>
Date: Fri Oct 23 13:37:26 2015 -0400
freedreno: remove unnecessary null checks
According to piglit/xonotic/neverball/stc, blend/rasterize/zsa state
will always be bound (never null). And the null checks were in-
consistent anyways, so remove them.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 6529daca391912246c13e6f76e885026d2ce88be
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date: Sat Oct 24 01:47:45 2015 +0200
radeonsi: Implement DCC fast clear.
Uses the DCC buffer instead of the CMASK buffer. The ELIMINATE_FAST_CLEAR
still works. Furthermore, with DCC compression we can directly clear
to a limited set of colors such that we do not need a postprocessing step.
v2 Marek: check dcc_buffer && dirty_level_mask in set_sampler_view
Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit 205a3ce5c158349dda7082f44e95301526b9f183
Author: Roland Scheidegger <sroland at vmware.com>
Date: Thu Oct 22 23:58:50 2015 +0200
gallivm: fix tex offsets with mirror repeat linear
Can't see why anyone would ever want to use this, but it was clearly broken.
This fixes the piglit texwrap offset test using this combination.
Reviewed-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 71ff5af5dd308e4a53b66b7530cc01ec4bf5715e
Author: Roland Scheidegger <sroland at vmware.com>
Date: Thu Oct 22 23:49:41 2015 +0200
gallivm: fix sampling with texture offsets in SoA path
When using nearest filtering and clamp / clamp to edge wrapping results could
be wrong for negative offsets. Fix this by adding the offset before doing
the conversion to int coords (could also use floor instead of trunc int
conversion but probably more complex on "typical" cpu).
This fixes the piglit texwrap offset failures with this filter/wrap combo
(which only leaves the linear/mirror repeat combination broken).
Reviewed-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit fb586e1edb207328534f554a9afaf2c07434e08e
Author: Roland Scheidegger <sroland at vmware.com>
Date: Thu Oct 22 22:28:28 2015 +0200
softpipe: fix using non-zero layer in non-array view from array resource
For vertex/geometry shader sampling, this is the same as for llvmpipe - just
use the original resource target.
For fragment shader sampling though (which does not use first-layer based mip
offsets) adjust the sampling code to use first_layer in the non-array cases.
While here also fix up some code which looked wrong wrt buffer texel fetch
(no piglit change).
Reviewed-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit fe707c0373cf73f9323014f7bc38f20120d4f096
Author: Roland Scheidegger <sroland at vmware.com>
Date: Thu Oct 22 22:26:52 2015 +0200
llvmpipe: fix using non-zero layer in non-array view from array resource
Just need to use resource target not view target when calculating
first-layer based mip offsets. (This is a gl specific problem since
d3d10 does not distinguish between non-array and array resources neither
at the resource nor view level, only at the shader level.)
Fixes new piglit arb_texture_view sampling-2d-array-as-2d-layer test.
Reviewed-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 830e57b82d21fd324059b7a7074b047ad41d0aa4
Author: Alex Deucher <alexander.deucher at amd.com>
Date: Fri Oct 23 18:31:57 2015 -0400
radeonsi: add Stoney to si_init_gs_info()
This patch was originally written before stoney support
was merged. Add stoney.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
commit 48b5f104ac4e0c3ddbff87520adb7a9d2a254c67
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date: Wed Oct 21 00:10:39 2015 +0200
radeonsi: Enable DCC.
Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit 81ebd6a88289663677ebb97f788afb53fb84dfd5
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date: Wed Oct 21 00:10:38 2015 +0200
radeonsi: Add FLUSH_AND_INV_CB_DATA_TS for DCC.
Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit bb77467df9863c522c8d8550e295e2ad7bbef37c
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date: Wed Oct 21 00:10:37 2015 +0200
radeonsi: Disable operations that do not work with DCC.
Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit afa357c3b01322df31034f84613a4d8401a9486e
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date: Wed Oct 21 00:10:36 2015 +0200
radeonsi: Allocate buffers for DCC.
As the alignment requirements can be 32 KiB or more, also adding
an aligned buffer creation function.
DCC is disabled for textures that can be shared as sharing the
DCC buffers has not been implemented yet.
Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit edf6a4537c5febbe38780819df30cbfffc74c329
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Oct 22 23:36:11 2015 +0200
radeonsi: only apply the SNORM blit workaround to *8_SNORM
Like the comment says. This fixes DCC, which doesn't like blitting RG16
as RGBA8.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit e1c098f2381de53bd0a3260d330b057c8bfb3156
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Oct 22 23:32:16 2015 +0200
util/format: add helper util_format_is_snorm8
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 06083046a4a6e8321cc0230f84208c8e10947105
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Oct 19 02:45:56 2015 +0200
radeonsi: add another requirement for PARTIAL_ES_WAVE
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 0d2cb35f689675bfe00c281513547544fe46d894
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Oct 18 22:22:22 2015 +0200
radeonsi: merge two ifs setting WD_SWITCH_ON_EOP
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit ca18f12dbb8d7b8542b33aac70866a27bb5d89e7
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Oct 18 22:17:04 2015 +0200
radeonsi: make PARTIAL_ES_WAVE globally dependent on SWITCH_ON_EOI
This catches the other cases that enable SWITCH_ON_EOI.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 2070af2fb121674ba21ae38c6c2ded8ae8ae413f
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Oct 18 22:07:01 2015 +0200
radeonsi: add one more SWITCH_ON_EOI requirement for Hawaii and VI
The VI condition depends on geometry shaders and MAX_PRIMGRP_IN_WAVE.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit a6b5684e998845f0c503e5a2c2b40bb47c5daa57
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Oct 18 21:51:41 2015 +0200
radeonsi: only apply the instancing bug workaround to Bonaire
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 96d5879d3850a7e0c921da0c8bfa7ba9993b6aa6
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Oct 18 21:43:30 2015 +0200
radeonsi: add SWITCH_ON_EOI requirement for 4 SE parts
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 7e056f872fb3f476ff48f159b72e29905afad6aa
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Oct 18 21:28:54 2015 +0200
radeonsi: remove unnecessary PARTIAL_VS_WAVE setting for streamout
hardware does this automatically
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 3a157e6e68b3f01fe5814f6313ec0811115b0694
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Oct 22 21:32:23 2015 +0200
radeonsi: allow unbinding vertex shaders
Draw calls without a vertex shader are skipped.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 07b3cc6ecf6588647094ff73c3dbbdc227c7f92e
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Oct 22 22:19:34 2015 +0200
radeonsi: allow unbinding pixel shaders and remove the dummy shader
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 50bb2decf70b59ac8021048c0f8baf05ab3766f6
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Oct 22 22:18:49 2015 +0200
radeonsi: add draw_vbo check for a NULL pixel shader
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit ed95cb3a310951c9623fa6757226359c60fa7375
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Oct 22 22:17:28 2015 +0200
radeonsi: add checks for a NULL pixel shader
This will allow removing the dummy PS.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit d842d2f25190fea353b0eb104ae83062fbd2c245
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Oct 22 22:14:53 2015 +0200
gallium/util: add a test for NULL fragment shaders
Just to validate that radeonsi doesn't crash.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit dd05824b8968c723fba767698b496691e8dc81e3
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Oct 22 19:46:07 2015 +0200
st/mesa: don't load state parameters if there are none
Out of 7063 shaders from my shader-db:
- 6564 (93%) shaders don't have any state parameters.
- 347 (5%) shaders have 1 state parameter for WPOS lowering.
- The remaining 2% have more state parameters, usually matrices.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 98546bfd038bc07a8cc7fed259c5022486bba473
Author: Samuel Li <samuel.li at amd.com>
Date: Thu Oct 22 12:06:43 2015 -0400
radeonsi: add Stoney pci ids
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
Signed-off-by: Samuel Li <samuel.li at amd.com>
Cc: mesa-stable at lists.freedesktop.org
commit bf0d0ce0d57dce5df8195942d2eda6389d341fea
Author: Samuel Li <samuel.li at amd.com>
Date: Fri Aug 21 15:35:46 2015 -0400
radeonsi: add support for Stoney asics (v3)
v2 (agd): rebase on mesa master, split pci ids to
separate commit
v3 (agd): use carrizo for llvm processor name for
llvm 3.7 and older
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Samuel Li <samuel.li at amd.com>
Cc: mesa-stable at lists.freedesktop.org
commit e05021ff72abb7de6506c90dd70a9f7ab490bf90
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Oct 23 02:14:31 2015 -0400
nvc0: respect edgeflag attribute width
The edgeflag comes in as ubyte with glEdgeFlagPointer but as float with
plain immediate glEdgeFlag. Avoid reading bytes that weren't meant for
the edgeflag in the pointer case.
Fixes intermittent failures with gl-2.0-edgeflag piglit (and valgrind
complaints about reading uninitialized memory).
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org
commit ea421e919ae6e72e1319fb205c42a6fb53ca2f82
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Fri Oct 23 11:40:25 2015 +0100
gallivm: Explicitly disable unsupported CPU features.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92214
CC: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit 70b06fb5d55d639fd74596a2ff6971cb57c030ca
Author: Eric Anholt <eric at anholt.net>
Date: Wed Aug 19 09:38:14 2015 -0700
vc4: Convert blending to being done in 4x8 unorm normally.
We can't do this all the time, because you want blending to be done in
linear space, and sRGB would lose too much precision being done in 4x8.
The win on instructions is pretty huge when you can, though.
total uniforms in shared programs: 32065 -> 32168 (0.32%)
uniforms in affected programs: 327 -> 430 (31.50%)
total instructions in shared programs: 92644 -> 89830 (-3.04%)
instructions in affected programs: 15580 -> 12766 (-18.06%)
Improves openarena performance at 1920x1080 from 10.7fps to 11.2fps.
commit 8e701fda499af0387f5c72f7bc14510182738647
Author: Eric Anholt <eric at anholt.net>
Date: Thu Jan 8 18:07:15 2015 -0800
vc4: Add QIR/QPU support for the 8-bit vector instructions.
commit 817a7eb588c7d6536cb469f4ca7447b49268bc00
Author: Eric Anholt <eric at anholt.net>
Date: Fri Oct 23 16:34:01 2015 +0100
vc4: Don't try to CSE non-SSA instructions.
This can happen when we're doing destination packing -- we don't know
what's in the rest of the register.
Signed-off-by: Eric Anholt <eric at anholt.net>
commit 5b2fb138bc5ff68af27d8435cbc01f83a09ee078
Author: Eric Anholt <eric at anholt.net>
Date: Tue Aug 18 22:38:34 2015 -0700
nir: Add opcodes for saturated vector math.
This corresponds to instructions used on vc4 for its blending inside of
shaders. I've seen these opcodes on other architectures before, but I
think it's the first time these are needed in Mesa.
v2: Rename to 'u' instead of 'i', since they're all 'u'norm (from review
by jekstrand)
commit 1066a372d8a260aef29ffb6226e8691c07ec696a
Author: Eric Anholt <eric at anholt.net>
Date: Fri Oct 23 15:26:12 2015 +0100
vc4: Add dumping of VC4_PACKET_GL_INDEXED_PRIMITIVE.
commit 7d7fbcdf4e1683d1aef19c7ee08cc222d8279672
Author: Eric Anholt <eric at anholt.net>
Date: Fri Oct 23 14:43:41 2015 +0100
vc4: Add a workaround for HW-2116 (state counter wrap fails).
I haven't proven that this happens (I've got other GPU hangs in the
way), but the closed driver also does this and it's documented as an
errata.
commit 73f610453296d7e8039ab05179d714d684d50fb3
Author: Eric Anholt <eric at anholt.net>
Date: Fri Oct 23 14:41:47 2015 +0100
vc4: Fix missing \n in a perf_debug().
commit 8f60dc83f7edba51037662c2637f830feeea3fc6
Author: Kristian Høgsberg Kristensen <krh at bitplanet.net>
Date: Tue Oct 20 23:22:27 2015 -0700
i965/fs: Allow copy propagating into new surface access opcodes
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
Signed-off-by: Kristian Høgsberg Kristensen <krh at bitplanet.net>
commit 0cb7d7b4b7c32246d4c4225a1d17d7ff79a7526d
Author: Kristian Høgsberg Kristensen <krh at bitplanet.net>
Date: Wed Oct 21 23:43:34 2015 -0700
i965/fs: Optimize ssbo stores
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
Write groups of enabled components together.
Signed-off-by: Kristian Høgsberg Kristensen <krh at bitplanet.net>
commit feff21d1a6ba49a0d6f7526e1ff473a0b574c92e
Author: Kristian Høgsberg Kristensen <krh at bitplanet.net>
Date: Wed Oct 21 22:49:14 2015 -0700
i965/fs: Drop offset_reg temporary in ssbo load
Now that we don't read each component one-by-one, we don't need the
temoprary vgrf for the offset. More importantly, this register was type
UD while the nir source was type D. This broke copy propagation and left
a redundant MOV in the generated code.
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
Signed-off-by: Kristian Høgsberg Kristensen <krh at bitplanet.net>
commit 0a5a738252afdd64b778024bcd130473b9a6224e
Author: Kristian Høgsberg Kristensen <krh at bitplanet.net>
Date: Tue Oct 20 23:31:49 2015 -0700
i965/fs: Avoid scalar destinations in emit_uniformize()
The scalar destination registers break copy propagation. Instead compute
the results to a regular register and then reference a component when we
later use the result as a source.
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
Signed-off-by: Kristian Høgsberg Kristensen <krh at bitplanet.net>
commit a19bf6d3ccbab6170ccfb7e04316a58f3e19396c
Author: Kristian Høgsberg Kristensen <krh at bitplanet.net>
Date: Tue Oct 20 23:16:51 2015 -0700
i965/fs: Don't uniformize surface index twice
The emit_untyped_read and emit_untyped_write helpers already uniformize
the surface index argument. No need to do it before calling them.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Signed-off-by: Kristian Høgsberg Kristensen <krh at bitplanet.net>
commit aedc0aab19c233cc084211959ef2b6be1c500bb7
Author: Kristian Høgsberg Kristensen <krh at bitplanet.net>
Date: Tue Oct 20 23:07:56 2015 -0700
i965/fs: Use unsigned immediate 0 when eliminating SHADER_OPCODE_FIND_LIVE_CHANNEL
The destination for SHADER_OPCODE_FIND_LIVE_CHANNEL is always a UD
register. When we replace the opcode with a MOV, make sure we use a UD
immediate 0 so copy propagation doesn't bail because of non-matching
types.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Signed-off-by: Kristian Høgsberg Kristensen <krh at bitplanet.net>
commit 24a3a697e5e029767c2d210a94d47c52c5e5e299
Author: Kristian Høgsberg Kristensen <krh at bitplanet.net>
Date: Fri Oct 16 21:58:14 2015 -0700
i965/fs: Read all components of a SSBO field with one send
Instead of looping through single-component reads, read all components
in one go.
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Signed-off-by: Kristian Høgsberg Kristensen <krh at bitplanet.net>
commit de5a450bd360d24db65cbba5b6633f800fda0d2e
Author: Kristian Høgsberg Kristensen <krh at bitplanet.net>
Date: Fri Oct 16 21:38:05 2015 -0700
i965: Don't use message headers for untyped reads
We always set the mask to 0xffff, which is what it defaults to when no
header is present. Let's drop the header instead.
v2: Only remove header for untyped reads. Typed reads always need the
header.
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Signed-off-by: Kristian Høgsberg Kristensen <krh at bitplanet.net>
commit 2f1bc1da864f8d169427b911bf60e1023321e420
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Fri Oct 23 15:32:30 2015 +0200
i965/vec4: check opcode on vec4_instruction::reads_flag(channel)
Commit f17b78 added an alternative reads_flag(channel) that returned
if the instruction was reading a specific channel flag. By mistake it
only took into account the predicate, but when the opcode is
VS_OPCODE_UNPACK_FLAGS_SIMD4X2 there isn't any predicate, but the flag
are used.
That mistake caused some regressions on old hw. More information on
this bug:
https://bugs.freedesktop.org/show_bug.cgi?id=92621
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit fb064901e9bd83a63d486f246b9ea943cd00f6cd
Author: Eric Anholt <eric at anholt.net>
Date: Wed Oct 21 16:40:46 2015 +0100
vc4: Use Rob's NIR-based user clip lowering.
commit b3797a8f8858a471ab602c7e165f5fa78e611693
Author: Eric Anholt <eric at anholt.net>
Date: Mon Aug 10 11:28:53 2015 -0700
vc4: Also dump the decimation mode for resolved stores.
commit 7516cbd26153bd0cc8a548744ea2443b9ea43cc0
Author: Eric Anholt <eric at anholt.net>
Date: Mon Aug 10 11:27:21 2015 -0700
vc4: Use VC4_GET_FIELD and other defines in dumping VC4_RENDER_CONFIG.
commit b0963ce75871e2b34856b8e24c8ad427f64be62a
Author: Eric Anholt <eric at anholt.net>
Date: Thu Oct 22 11:31:56 2015 +0100
vc4: Add a sentinel after simulator buffers for buffer overflow detection.
This is a little bit like the mprotect-based fencing I've experimented
with, but it's simple and low overhead. The downside is that only catches
writes, not reads.
It didn't catch any bad writes on a current piglit run, but may be useful
in the future.
commit f408a13dd3089483c78803e961ba8a4df8b4cbba
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Wed Oct 21 09:46:48 2015 +0200
glsl: fix shader storage block member rules when adding program resources
Commit f24e5e did not take into account arrays of named shader
storage blocks.
Fixes 20 dEQP-GLES31.functional.ssbo.* tests:
dEQP-GLES31.functional.ssbo.layout.single_struct_array.per_block_buffer.shared_instance_array
dEQP-GLES31.functional.ssbo.layout.single_struct_array.per_block_buffer.packed_instance_array
dEQP-GLES31.functional.ssbo.layout.single_struct_array.per_block_buffer.std140_instance_array
dEQP-GLES31.functional.ssbo.layout.single_struct_array.per_block_buffer.std430_instance_array
dEQP-GLES31.functional.ssbo.layout.single_struct_array.single_buffer.shared_instance_array
dEQP-GLES31.functional.ssbo.layout.single_struct_array.single_buffer.packed_instance_array
dEQP-GLES31.functional.ssbo.layout.single_struct_array.single_buffer.std140_instance_array
dEQP-GLES31.functional.ssbo.layout.single_struct_array.single_buffer.std430_instance_array
dEQP-GLES31.functional.ssbo.layout.single_nested_struct_array.per_block_buffer.shared_instance_array
dEQP-GLES31.functional.ssbo.layout.single_nested_struct_array.per_block_buffer.packed_instance_array
dEQP-GLES31.functional.ssbo.layout.single_nested_struct_array.per_block_buffer.std140_instance_array
dEQP-GLES31.functional.ssbo.layout.single_nested_struct_array.per_block_buffer.std430_instance_array
dEQP-GLES31.functional.ssbo.layout.single_nested_struct_array.single_buffer.shared_instance_array
dEQP-GLES31.functional.ssbo.layout.single_nested_struct_array.single_buffer.packed_instance_array
dEQP-GLES31.functional.ssbo.layout.single_nested_struct_array.single_buffer.std140_instance_array
dEQP-GLES31.functional.ssbo.layout.single_nested_struct_array.single_buffer.std430_instance_array
dEQP-GLES31.functional.ssbo.layout.random.all_per_block_buffers.2
dEQP-GLES31.functional.ssbo.layout.random.all_per_block_buffers.29
dEQP-GLES31.functional.ssbo.layout.random.all_per_block_buffers.33
dEQP-GLES31.functional.ssbo.layout.random.all_shared_buffer.3
V2:
- Rename some variables (Timothy)
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Timothy Arceri <timothy.arceri at collabora.com>
commit 582ecb3b9132ff3690900e5426c982187d640c87
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Oct 23 00:45:49 2015 +0800
ilo: add support for scratch spaces
When a kernel reports a non-zero per-thread scratch space size, make sure the
hardware state is correctly set up, and a scratch bo is allocated.
commit 4a7d18296a9e80d2c5458bf77f8eb88913433c90
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Oct 23 00:24:26 2015 +0800
ilo: fix scratch space setup in core
Move scratch_size out of ilo_state_shader_kernel_info and
ilo_state_compute_interface_info. A scratch space is shared by all
kernels/interfaces. Update builder to emit relocs for scratch bos.
commit 3994ef5f1b7386c17dff532cb5d04a7823520c7a
Author: Timothy Arceri <timothy.arceri at collabora.com>
Date: Thu Oct 22 16:18:44 2015 +1100
glsl: remove excess location qualifier validation
Location has never been able to be a negative value because it has
always been validated in the parser.
Also the linker doesn't check for negatives like the comment claims.
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 5145243018e4456994e73bffdb0296b8fedd6fbe
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Oct 23 12:11:43 2015 +1000
docs: update relnotes to mention virgl driver.
commit b3b82fe8ea1f7d02c93513920143cba2fe145b6c
Author: Dave Airlie <airlied at gmail.com>
Date: Fri Mar 13 14:15:47 2015 +1000
virgl/vtest: add vtest driver
virgl/vtest is a swrast driver that allows the
virgl acceleration to be tested without having
a virtual machine.
The backend has a unix socket server that
this connects to.
This is run by setting
LIBGL_ALWAYS_SOFTWARE=y
GALLIUM_DRIVER=virpipe
In this mode all renderering is sent over
a socket to the remote renderer, and the
results are readback and copies to the screen
using drisw. This works well enough to develop
new features and to help debug.
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit a8987b88ff1db4ac00720a9b56c4bc3aeb666537
Author: Dave Airlie <airlied at redhat.com>
Date: Thu Jan 22 15:11:47 2015 +1000
virgl: add driver for virtio-gpu 3D (v2)
virgl is the 3D acceleration backend for the
virtio-gpu shipping with qemu.
The 3D acceleration is designed around gallium
and TGSI as the virtualisation layer. The backend
renderer translates the virgl interface into
OpenGL currently.
This is the initial import of the driver to mesa.
The kernel driver portions are lined up for drm-next.
Currently this driver supports up to GL3.3 and some
misc extensions if the host driver exposes it. It is
planned to iterate the virgl API to new GL levels
as mesa host drivers gain features.
v2: fix resource tracking across flushes to avoid
->bind hack in mapping.
consolidate mapping and waiting code for transfers.
use u_range for dirt tracking.
handle larger shaders in protocol.
include virtgpu_drm.h in mesa for now.
add translation layer for gallium tgsi to virgl tgsi.
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 531f5d1270782927911c5c720201e86c6f40182d
Author: Dave Airlie <airlied at redhat.com>
Date: Thu Jan 22 15:18:05 2015 +1000
tgsi: try and handle overflowing shaders. (v2)
This is used to detect error in virgl if we overflow the shader
dumping buffers.
v2: return a bool.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 041081dc219dcf7f61748284033c6fd7627acc69
Author: Dave Airlie <airlied at gmail.com>
Date: Mon Sep 16 10:13:55 2013 +1000
tgsi: add option to dump floats as hex values
This adds support to the parser to accept hex values as floats,
and then adds support to the dumper to allow the user to select
to dump float as 32-bit hex numbers.
This is required to get accurate values for virgl use of TGSI.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 231d53923918f4a885e74da0a063dcbf1a4353e3
Author: Sinclair Yeh <syeh at vmware.com>
Date: Tue Oct 13 12:58:26 2015 -0700
svga: Condition preemptive flush on draw emission
On ultra high resolution modes, the preemptive flush flag can be
set midway through command submission, a condition that cannot be
recovered from a flush-retry, causing rendering artifacts.
This patch prevents a preemtive_flush until a draw has been
emitted.
Signed-off-by: Sinclair Yeh <syeh at vmware.com>
Reviewed-by: Thomas Hellstrom <thellstrom at vmware.com>
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 99effaa9658a34eb07255bb1964569c8a86e8dda
Author: Brian Paul <brianp at vmware.com>
Date: Fri Oct 16 16:14:46 2015 -0600
svga: try to avoid index generation for some primitive types
The svga device doesn't directly support quads, quad strips or polygons
so we have to convert those types to indexed triangle lists. But we
can sometimes avoid that if we're drawing flat/constant-colored prims
and we don't have to worry about provoking vertex.
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
Reviewed-by: José Fonseca <jfonseca at vmware.com>
commit 129d34da494840628b2bb1cbb6397d50dab3c999
Author: Brian Paul <brianp at vmware.com>
Date: Fri Oct 16 16:12:19 2015 -0600
svga: avoid provoking vertex conversion when possible
Provoking vertex comes into play when doing flat shading. But if we know
that all fragments in a primitive are the same color, the provoking vertex
doesn't matter. Check for that case and use whichever provoking vertex
convention is supported by the device.
This avoids generating an index buffer to do the PV conversion.
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
Reviewed-by: José Fonseca <jfonseca at vmware.com>
commit 1082735bb69e9f64cb3991a52f0e270902917855
Author: Brian Paul <brianp at vmware.com>
Date: Thu Oct 22 15:36:25 2015 -0600
svga: detect constant color writes in fragment shaders
Examine the fragment shader to try to detect TGSI shaders which use
"MOV OUT[0], CONST[i]" to write a constant value for the fragment color.
In this case, all fragments will have the same color (unless blending is
enabled).
This is a common case for OpenGL code such as: glColor(), glBegin(),
glVertex(), ..., glEnd() when lighting/fog/etc are disabled. In this
case, the Mesa/gallium state tracker actually generates a simple
"MOV OUT[0], CONST[i]" fragment shader.
This will be used by the next commit to avoid provoking vertex conversion
(creating/rewriting an index buffer) when drawing flat-shaded primitives.
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
Reviewed-by: José Fonseca <jfonseca at vmware.com>
commit df0f817e311dbf9af110779086a27429905b1faf
Author: Brian Paul <brianp at vmware.com>
Date: Wed Oct 21 13:58:04 2015 -0600
mesa: check for unchanged line width before error checking
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 990afdc04551e89ec9b5d29a05a9da798c07ccc3
Author: Brian Paul <brianp at vmware.com>
Date: Wed Oct 21 13:42:37 2015 -0600
st/mesa: use _mesa_RasterPos() when possible
The st_RasterPos() function goes to great pains to implement the
rasterpos transformation. It basically uses gallium's draw module to
execute the vertex shader to draw a point, then capture that point's
attributes.
But glRasterPos isn't typically used with a vertex shader so we can
usually use the old/fixed-function implementation which is a lot simpler
and faster.
This can add up for legacy apps that make a lot of calls to glRasterPos.
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit af0399a1ce5acea464219f63399284cb175fa1f4
Author: Brian Paul <brianp at vmware.com>
Date: Wed Oct 21 13:42:21 2015 -0600
tnl: remove t_rasterpos.c
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit 234d5320bbe373b9197e63f92326398b54c16fe9
Author: Brian Paul <brianp at vmware.com>
Date: Wed Oct 21 13:40:58 2015 -0600
drivers/common: use _mesa_RasterPos instead of _tnl_RasterPos
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit 614a74376702b9f49343c9d71339cbb002971e6b
Author: Brian Paul <brianp at vmware.com>
Date: Wed Oct 21 13:39:15 2015 -0600
mesa: copy rasterpos evaluation code into core Mesa
We'll remove it from the tnl module next. By lifting this code into core
Mesa we can use it from the gallium state tracker.
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit 9919f560996cc0014df757cc542bf477c5402c00
Author: Brian Paul <brianp at vmware.com>
Date: Wed Oct 21 13:38:23 2015 -0600
vbo: optimize vertex copying when 'wrapping'
Instead of calling memcpy() 'n' times, we can do it all at once since
the source and dest regions are all contiguous.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 7b636581253fe858ac883e3d3eec21173ac069d4
Author: Alex Deucher <alexander.deucher at amd.com>
Date: Thu Oct 22 12:24:42 2015 -0400
radeon/uvd: don't expose HEVC on old UVD hw (v3)
The section for UVD 2 and older was not updated
when HEVC support was added. Reported by Kano
on irc.
v2: integrate the UVD2 and older checks into the
main switch statement.
v3: handle encode checking as well. Encode is
already checked in the top case statement, so
drop encode checks in the lower case statement.
Reviewed-by: Christian König <christian.koenig at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
Cc: mesa-stable at lists.freedesktop.org
commit 8cf84a7e470dbd3b46ce4081459d2ecfab22c2d5
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Fri Oct 9 18:39:42 2015 +0200
i965/vec4: print predicate control at brw_vec4 dump_instruction
v2: externalize pred_ctrl_align16 from brw_disasm.c instead of adding
a copy on brw_vec4.c, as suggested by Matt Turner
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 92ae101ed0dff689f207abf61f68167009de4e29
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Thu Oct 1 16:41:30 2015 +0200
i965/vec4: use an envvar to decide to print the assembly on cmod_propagation tests
The complete way to do this would be parse INTEL_DEBUG and
print the output if DEBUG_VS (or a new one) is present
(see intel_debug.c).
But that seems like an overkill for the unit tests, that
after all, the most common use case is being run when
calling make check.
v2: use the same idea for the fs counterpart too, as suggested by
Matt Turner
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 8fc8fcc04f584b32cd5bf633da8e3508249e339d
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Wed Sep 30 13:39:30 2015 +0200
i965/vec4: Add unit tests for cmod propagation pass
This include the same tests coming from test_fs_cmod_propagation, (non
vector glsl types included) plus some new with vec4 types, inspired on
the regressions found while the optimization was a work in progress.
Additionally, the check of number of instructions after the
optimization was changed from EXPECT_EQ to ASSERT_EQ. This was done to
avoid a crash on failing tests that expected no optimization, as after
checking the number of instructions, there were some checks related to
this last instruction opcode/conditional mod.
v2: update tests after Matt Turner's review of the optimization pass
v3: tweaks on the tests (mostly on the comments), after Matt Turner's
review
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 627f94b72e0e9443ad116f072599a7342269f297
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Mon Sep 28 17:00:19 2015 +0200
i965/vec4: adding vec4_cmod_propagation optimization
vec4 port of fs_cmod_propagation.
Shader-db results (no vec4 grepping):
total instructions in shared programs: 6240413 -> 6235841 (-0.07%)
instructions in affected programs: 401933 -> 397361 (-1.14%)
total loops in shared programs: 1979 -> 1979 (0.00%)
helped: 2265
HURT: 0
v2: remove extra space and combine two if blocks, as suggested by
Matt Turner
v3: add condition check to bail out if current inst and inst being
scanned has different writemask, as pointed by Matt Turner
v3: updated shader-db numbers
v4: remove block from foreach_inst_in_block_*_starting_from after
commit 801f151917fedb13c5c6e96281a18d833dd6901f
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit a59359ecd22154cc2b3f88bb8c599f21af8a3934
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Wed Oct 14 20:26:43 2015 +0200
i965/vec4: track and use independently each flag channel
vec4_live_variables tracks now each flag channel independently, so
vec4_dead_code_eliminate can update the writemask of null registers,
based on which component are alive at the moment. This would allow
vec4_cmod_propagation to optimize out several movs involving null
registers.
v2: added support to track each flag channel independently at vec4
live_variables, as v1 assumed that it was already doing it, as
pointed by Francisco Jerez
v3: general cleaningn after Matt Turner's review
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 8ac3b525c77cb5aae9e61bd984b78f6cbbffdc1c
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Fri Oct 9 16:59:20 2015 +0200
i965/vec4: nir_emit_if doesn't need to predicate based on all the channels
v2: changed comment, as suggested by Matt Turner
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 1095d837dc5744b65d4e65ee551046d5d884f607
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu Oct 22 12:26:27 2015 -0700
i965/vec4/gs: Fix signed/unsigned comparison warning.
commit e2707c8765b15b7ac666067160307c7f9d2d8b4d
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Oct 20 18:31:02 2015 -0700
i965/fs: Emit a single ADD instruction for SET_SAMPLE_ID on Gen8+.
Gen8+ lifted the register region restriction that an instruction whose
destination spans two registers must have sources that also span two
registers.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 0f74796e33cb15ec0c79bc2b5d0c766dc5068b41
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Oct 20 18:29:42 2015 -0700
i965/fs: Drop unnecessary write-enable-all from SET_SAMPLE_ID.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit e2344e11ce8ddefb89a222bbf63a7c60e8ba5655
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Oct 20 18:23:50 2015 -0700
i965/fs: Trim unneeded channels in SampleID setup.
The AND and SHR produce a scalar value that we had been replicating
across $dispatch_width channels. The immediate MOV produces only four
useful channels of data.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit e10fc055e7dc5281f03a77088a24392098e3473b
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Oct 20 17:51:12 2015 -0700
i965/fs: Use type-W for immediate in SampleID setup.
Not a functional difference, but register is loaded with a signed
immediate (V) and added to a signed type (D) producing a signed result
(D).
Also change the type of g0 to allow for compaction.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit cfb67c3d0656927270302ef17d2d9de065ec44fe
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Oct 19 10:51:42 2015 -0700
i965/vec4: Initialize LOD to 0.0f for textureQueryLevels() and texture().
We implement textureQueryLevels (which takes no arguments, save the
sampler) using the resinfo message (which takes an argument of LOD).
Without initializing it, we'd generate a MOV from the null register to
load the LOD argument.
Essentially the same logic applies to texture. A vertex shader cannot
compute derivatives and so cannot produce an LOD, so TXL with an LOD of
0.0 is used.
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 65ffaf2740e40cc155b55fae81166181a9b616a2
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Jun 29 14:04:14 2015 -0700
i965: Note that the UV immediate type is Gen6+.
commit 718249843b915decf8fccec92e466ac1a6219934
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Wed Oct 21 17:19:41 2015 +0100
gallivm: Translate all util_cpu_caps bits to LLVM attributes.
This should prevent disparity between features Mesa and LLVM
believe are supported by the CPU.
http://lists.freedesktop.org/archives/mesa-dev/2015-October/thread.html#96990
Tested on a i7-3720QM w/ LLVM 3.3 and 3.6.
v2: Increase SmallVector initial size as suggested by Gustaw Smolarczyk.
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
CC: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
commit 627c15cde46a76e9bce4425646c5caba11788ec4
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Mon Oct 19 23:13:09 2015 -0700
i965/fs: Disable CSE optimization for untyped & typed surface reads
An untyped surface read is volatile because it might be affected by a
write.
In the ES31-CTS.compute_shader.resources-max test, two back to back
read/modify/writes of an SSBO variable looked something like this:
r1 = untyped_surface_read(ssbo_float)
r2 = r1 + 1
untyped_surface_write(ssbo_float, r2)
r3 = untyped_surface_read(ssbo_float)
r4 = r3 + 1
untyped_surface_write(ssbo_float, r4)
And after CSE, we had:
r1 = untyped_surface_read(ssbo_float)
r2 = r1 + 1
untyped_surface_write(ssbo_float, r2)
r4 = r1 + 1
untyped_surface_write(ssbo_float, r4)
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 13a5805b646b19fd9c155d5c586ad1967d7d9e00
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Thu Oct 22 11:29:17 2015 +0800
ilo: make sure there is HiZ before resolving
We do not want to perform a depth resolve on an MCS enabled surface.
commit 0b6f6ee50f3b25c21dd8c9ca339d006141340666
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Thu Oct 22 11:19:05 2015 +0800
ilo: fix max thread count for HS on Gen8
It is in DW2 on Gen8.
commit 8eefdacb3892da662f85377f4fe1a33dbff2ce7a
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Tue Oct 20 14:29:41 2015 -0700
i965: Advertise ARB_shader_stencil_export (gen9+)
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 1db44252d01bf7539452ccc2b5210c74b8dcd573
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Tue Oct 20 14:29:39 2015 -0700
i965: Implement ARB_shader_stencil_export (gen9+)
v2: remove useless source_stencil_to_render_target (Ken)
Squash in the actual packing function, which also got to
v2:
Move the definition of the OPCODE outside of FB_WRITE opcodes (Matt)
Reorder the regioning to be in VWH order (Matt)
Don't retype src in the backend, just assert instead (Matt)
Rename the debug prints to something better (Matt)
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 5fa7114652068735347c8715d1fc1d2cef72c433
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Tue Oct 20 14:29:37 2015 -0700
i965/fs: Enumerate logical fb writes arguments
Gen9 adds the ability to write out a stencil value, so we need to expand the
virtual payload by one. Abstracting this now makes that change easier to read.
I was admittedly confused early on about some of the hardcoding. If people
believe the resulting code is inferior, I am not super attached to the patch.
v2:
Remove explicit numbering from the enumeration (Matt).
Use a real naming scheme, and reference it in the opcode definition (Curro)
Add a missed hardcoded logical position in get_lowered_simd_width (Ben)
Add an assertion to make sure the component numbering is correct (Ben)
Cc: Matt Turner <mattst88 at gmail.com>
Cc: Francisco Jerez <currojerez at riseup.net>
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 18a631eb9056857a9ced477e7e3d1a435a906be2
Author: Brian Paul <brianp at vmware.com>
Date: Wed Oct 21 16:07:33 2015 -0600
svga: fix clip plane regression after recent tgsi_scan change
Before the change "tgsi/scan: use properties for clip/cull distance
writemasks", the tgsi_shader_info::num_written_clipdistance field
was a multiple of four, now it's an accurate count. In the svga
driver, we need a minor change to the loop test.
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
commit 48c76eae8e52fba2fe22d2cfa7f3c94a5420feb2
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Jul 10 00:16:19 2015 -0700
i965: Implement gl_InvocationID.
It's stored in bits 31:27 of g1 (along with the URB handles).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit c5ae34f38f239d346090212a9f33a947a3b7642e
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Sep 23 18:59:57 2015 -0700
i965: Implement nir_intrinsic_load_primitive.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit b3ebf03b8406f9f1cd215b98ebdd3fc751f73559
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Jun 29 22:50:28 2015 -0700
i965: Add a fs_visitor constructor that takes a brw_gs_compile.
Unlike the vs/wm structs, brw_gs_compile is actually useful: it contains
the input VUE map and information about the control data headers.
Passing this in allows us to share that code in brw_gs.c, and calculate
them before deciding on vec4 vs. scalar mode, as it's independent of
that choice.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 55dfd39b5f18f820694cad74ce40a3e0d3d6a0c4
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Jun 26 16:20:21 2015 -0700
i965: Add a brw->scalar_gs flag controlled by INTEL_SCALAR_GS=1.
This patch introduces a brw->scalar_gs flag, similar to brw->scalar_vs,
which controls whether or not to use SIMD8 geometry shaders.
For now, we control it via a new environment variable, INTEL_SCALAR_GS.
This provides a convenient way to try it out.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit ac0a33666bdab6e4d9abca6ae6ee19cb03919dcc
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue May 5 20:19:04 2015 -0700
i965: Make emit_urb_writes() reserve space for GS header information.
Geometry shaders have additional header data at the beginning of their
output URB entries. Shaders that use EndPrimitive() or multiple streams
have a control data header; shaders with a dynamic vertex count have an
additional vec4 slot to hold the 32-bit vertex count (and 96 bits of
padding).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit cb755996d91e9f44c93121f9534b0c59bb3ec201
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Mar 12 01:55:44 2015 -0700
i965: Make emit_urb_writes() only set EOT for the VS.
The GS will emit a bunch of vertices, and we don't want to do an EOT
prematurely. We'll emit GS_OPCODE_THREAD_END when we want to terminate
the thread.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 6ae419b94d7a7d2dfbb9a2908d28ca5aea4724e3
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Mar 12 05:52:13 2015 -0700
i965: Make fs_visitor::emit_urb_writes reusable for scalar GS.
GS doesn't have ClampVertexColor, and we don't want to go through VS
structures.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 72d84ae7ceaed4e723376a18d09689be183e0155
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Sep 29 14:43:29 2015 -0700
i965: Introduce a brw_vue_prog_data::include_vue_handles flag.
Tessellation shaders and SIMD8 geometry shaders may need to resort to
the pull model for inputs at times. When set, the state upload code
will tell the hardware to provide URB handles for input data.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit ac98888afdc121e6eaafc9c5393647a2df4baef6
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Sep 29 14:32:02 2015 -0700
i965: Introduce a new SHADER_OPCODE_URB_READ_SIMD8 opcode.
In scalar mode, geometry shader inputs can easily take up hundreds of
registers. This makes pushing VUE entries impractical; we'll need to
resort to the pull model in some cases.
To support this, we introduce a new opcode corresponding to the "URB
Read SIMD8" message.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit bea75227829512ab0e4766e00ac1b509c7586667
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed May 6 00:04:10 2015 -0700
i965: Introduce new SHADER_OPCODE_URB_WRITE_SIMD8_MASKED/PER_SLOT opcodes.
In the vec4 backend, we have a vec4_instruction::urb_write_flags field.
There are many kinds of flags for SIMD4x2 messages.
However, there are really only two (per-slot offset, use channel masks)
for SIMD8 messages. Rather than adding a boolean flag for per-slot
offsets (polluting all instructions), I decided to just make three new
opcodes.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 0e57694745979286cda0cd414cc6d1f4efe5408b
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Oct 21 12:03:21 2015 -0700
i965/gs: Do prog_data setup and other calculations in brw_compile_gs
This commit moves the large pile of setup calculations we have to do for
geometry shaders out of brw_gs_emit and into brw_compile_gs. This has a
couple of nice implications. First, it's less work that the caller of
brw_compile_gs has to do. Second, it's consistent with the vertex and
fragment stages. Finally, it allows us to put brw_gs_compile back behind
the API boundary where it belongs.
v2 (Jason Ekstrand):
- Pull the changes to use nir info into a separate patch
- Put brw_gs_compile into brw_shader.h rather than brw_vec4_gs_visitor.h
so that we can use it for scalar GS.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit f3bc73073af70a7fe4d2612c80bfb5ae5820b963
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Oct 21 12:02:08 2015 -0700
i965/gs: Use NIR info for setting up prog_data
Previously, we were pulling bits from GL data structures in order to set up
the prog_data. However, in this brave new world of NIR, we want to be
pulling it out of the NIR shader whenever possible. This way, we can move
all this setup code into brw_compile_gs without depending on the old GL
stuff.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit fac9b21e037f9ce456039fbf35cd5fa573dee229
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Oct 20 17:12:03 2015 -0700
i965/gs: Pull prog_data out of brw_gs_compile
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 6ac2bbec16d73f0cc58fc520c4165239461c59b3
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Oct 20 16:40:30 2015 -0700
i965/gs: Use NIR instead of the brw_geometry_program for GS metadata
With this, we can remove the geometry program from brw_gs_compile.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 72148de217786473bb2bb02b99f49fd28bdda0e2
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Oct 20 16:21:09 2015 -0700
i965/gs: Move the mem_ctx argument to brw_compile_gs
This makes it better match the other brw_compile_* functions.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 8e8b527b27b5b31f88e85e9878652a11c7fa5ca4
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Oct 20 16:46:50 2015 -0700
i965/gs: Set static_vertex_count unconditionally on GEN8+
We always have NIR, so there's no reason for the check.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 2686477d3757de50c31aa193bde8ad57fe539e44
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Oct 20 17:40:19 2015 -0700
nir: Constify nir_gs_count_vertices
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 4eb84a03becec582a3a26ceee470334f0fba4721
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Oct 20 16:35:44 2015 -0700
nir/info: Add more information about geometry shaders
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 3c5d24363a4c3e332d9b0820b4682d3a336d00f7
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Tue Oct 20 14:29:38 2015 -0700
i965: (trivial) rename computes stencil to gen9
All the documentation I can find says that this bit (and functionality) only
exists on SKL+. Since the bit isn't yet used, there is no real impact here.
The original code was added by Ken here (a surprisingly long time ago):
commit f3c6d6f1e151f6a44a76038dccebe4434038dcb1
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 29 21:00:27 2012 -0800
i965: Update 3DSTATE_PS, 3DSTATE_WM, and add 3DSTATE_PS_EXTRA.
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit c643518452ce9a0c107c5666e2caa7806a04e7d4
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Tue Oct 20 14:29:36 2015 -0700
i965: Correct the comment about fb write payload
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit f1147a238ab35a56fa7d1c64f6025ff3b909dad8
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Thu Oct 8 16:44:30 2015 -0700
mesa/glformats: Undo code changes from _mesa_base_tex_format() move
The refactoring commit, c6bf1cd, accidentally reverted cd49b97
and 99b1f47. These changes caused more code to be added to the
function and removed the existing support for ASTC. This patch
reverts those modifications.
v2. Actually include ASTC support again.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92221
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
commit 2ce659b5e422f7e7639d6e451160c197717df823
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Oct 19 19:02:16 2015 -0700
i965: Mark compacted 3-src instructions as Gen8+.
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 05cc56cca3abac0dc8e34469a260fe3c635a12d8
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Oct 19 18:59:53 2015 -0700
i965: Add const to brw_compact_inst_bits.
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit b29f92daec59a4181a45175b6bfc6e636c57fb33
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Oct 19 15:08:28 2015 -0700
i965: Add mask_control_ex field and handle it in compaction.
Documentation is sparse, but it appears to have existed on G45 and ILK
as a second bit extension of the mask_control field. Setting the pair of
bits to 0b11 enables "NoCMask".
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 3ec9d96d435d5f57b35d4a8c75149fd75eaba187
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Oct 19 14:47:17 2015 -0700
i965: Add devinfo->gen assertions for acc_wr_control.
... and for flag_subreg_nr since it's right near by.
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit d14907b94676fb563761866fca5bdf0492cdb8df
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Oct 19 14:46:18 2015 -0700
i965: Prepare for next commit by adding more whitespace.
We're going to add a field with a longer name that wouldn't align with
the rest.
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 35f3f06c8a2e614beac90cf25b9dfff98bb420dc
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Oct 19 15:01:20 2015 -0700
i965: Compact acc_wr_control only on Gen6+.
It only exists on Gen6+, and the next patches will add compaction
support for the (unused) field in the same location on earlier
platforms.
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit ee868c46e80d5a394e14846552bcb2fd77df419c
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Oct 19 14:41:36 2015 -0700
i965: Add devinfo parameter to brw_compact_inst_* funcs.
The next commit will add assertions dependent on devinfo->gen.
Use compact()/uncompact() macros where possible, like the 3-src code
does.
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 4a132349c333aba9f4dc264d35d5b366ed5e3759
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu Oct 15 15:13:12 2015 -0700
i965/vec4: Don't emit MOVs for unused URB slots.
Otherwise we'd emit a MOV from the null register (which isn't allowed).
Helps 24 programs in shader-db (the geometry shaders in GSCloth):
instructions in affected programs: 302 -> 262 (-13.25%)
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 04703762e544bc732f6f8b07033221dfbd58159f
Author: Nigel Stewart <nigels at users.sourceforge.net>
Date: Mon Oct 12 21:26:37 2015 +1000
osmesa: Expose GL entry points for Windows build via DEF file.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92437
CC: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Jose Fonseca <jfonseca at vmware.com>
commit 99c4079c37ac04a0dad4ead3117f786706c80aaf
Author: Jonathan Gray <jsg at jsg.id.au>
Date: Sat Oct 10 17:42:40 2015 +1100
configure.ac: ensure RM is set
GNU make predefines RM to rm -f but this is not required by POSIX
so ensure that RM is set. This fixes "make clean" on OpenBSD.
v2: use AC_CHECK_PROG
Signed-off-by: Jonathan Gray <jsg at jsg.id.au>
CC: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit ee77796a5c97105bf7e92e3a7931ee0f331a0545
Author: Neil Roberts <neil at linux.intel.com>
Date: Tue Oct 20 11:56:15 2015 +0200
i965/fs: Disable opt_sampler_eot for more message types
In bfdae9149e0 I disabled the opt_sampler_eot optimisation for TG4
message types because I found by experimentation that it doesn't work.
I wrote in the comment that I couldn't find any documentation for this
problem. However I've now found the documentation and it has
additional restrictions on further message types so this patch updates
the comment and adds the others.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 801f151917fedb13c5c6e96281a18d833dd6901f
Author: Neil Roberts <neil at linux.intel.com>
Date: Tue Oct 20 11:16:00 2015 +0200
i965: Remove block arg from foreach_inst_in_block_*_starting_from
Since 49374fab5d793 these macros no longer actually use the block
argument. I think this is worth doing to make the macros easier to use
because they already have really long names and a confusing set of
arguments.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 38ceeeadaa2f5f0a21dba9f5339fbc4cba66dece
Author: Timothy Arceri <timothy.arceri at collabora.com>
Date: Wed Oct 21 13:44:10 2015 +1100
glsl: check for arrays of arrays when assigning explicit locations
This fixes assigning explicit locations in the CTS test:
ES31-CTS.explicit_uniform_location.uniform-loc-arrays-of-arrays
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 9a04057ef130e1539aa94babd2e35ce53e6f1e1e
Author: Timothy Arceri <timothy.arceri at collabora.com>
Date: Wed Oct 21 13:37:11 2015 +1100
glsl: add is_array_of_arrays() helper
As suggested by Ian Romanick
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 156b7d3113757eb437dfcfa3ca7ef9b03f3097b2
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Oct 20 19:51:56 2015 -0700
glsl: Fix bad indentation in bit_logic_result_type().
The first level of indentation was using 4 spaces. Mesa uses 3.
Trivial.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
commit fd01840c0bd3b22d058a65a17ad30e3b45813b60
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Wed Aug 5 15:49:22 2015 +1000
glsl: add AoA support to subroutines
process_parameters() will now be called earlier because we need
actual_parameters processed earlier so we can use it with
match_subroutine_by_name() to get the subroutine variable, we need
to do this inside the recursive function generate_array_index() because
we can't create the ir_dereference_array() until we have gotten to the
outermost array.
For the remainder of the array dimensions the type doesn't matter so we
can just use the existing _mesa_ast_array_index_to_hir() function to
process the ast.
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit a59c1adcc665b70ca5a8fbfebe3f0d6e05ad2778
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Tue Oct 20 12:18:51 2015 +0300
glsl: fix record type detection in explicit location assign
Check current_var directly instead of using the passed in record_type.
This fixes following failing CTS test:
ES31-CTS.explicit_uniform_location.uniform-loc-types-structs
No Piglit regressions.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Marta Lofstedt <marta.lofstedt at intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit 1f48ea1193e3659c3f94b5de31d9200c1d500e72
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Tue Oct 20 10:24:50 2015 +0300
glsl: do not try to reserve explicit locations for buffer variables
Explicit locations are only used with uniform variables.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Marta Lofstedt <marta.lofstedt at intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit 96bbb3707f402149ae48bc3991febeed86c4fa21
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Tue Oct 20 08:32:15 2015 +0300
glsl: skip buffer variables when filling UniformRemapTable
UniformRemapTable is used only for remapping user specified uniform
locations to driver internally used ones, shader storage buffer
variables should not utilize uniform locations.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Marta Lofstedt <marta.lofstedt at intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit f1682fdafa54bb2e710707c441ed652358e57502
Author: Brian Paul <brianp at vmware.com>
Date: Tue Oct 20 18:22:43 2015 -0600
svga: add switch case for PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
A third instance of this was needed but missed in the previous commit.
Return 32 as for the two other cases.
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
commit b48e16fa2f8b96bb36a6e0a92b6d842c1c246006
Author: Brian Paul <brianp at vmware.com>
Date: Sat Oct 17 12:07:32 2015 -0600
draw: fix splitting of line loops (v2)
When the draw module splits long line loops, the sections are emitted
as line strips. But the primitive type wasn't set correctly so each
section was being drawn as a loop, introducing extra line segments.
To fix this, we pass a new DRAW_LINE_LOOP_AS_STRIP flag to the run()
function. The linear/elt_run() functions have to check for this flag
and set their primitive type accordingly.
No piglit regressions. Fixes piglit's lineloop with -count 4097 or
higher.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=81174
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit 876d07d8377bb61417ba2f443afa8b7a30b9de81
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Thu Aug 13 11:19:47 2015 -0700
i965/gen9: Remove temporary variable 'bpp' in tr_mode_..._texture_alignment()
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 06ec19bca4a8d9c714769c658aeb401697ab6bba
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Wed Aug 12 16:39:05 2015 -0700
i965/gen9: Remove temporary variable 'align_yf' in tr_mode_..._texture_alignment()
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 8f8c450bc7c1652b8c76f7e716273f0f784d30c0
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Wed Sep 23 16:13:00 2015 -0700
i965/gen9: Remove parameter 'brw' from tr_mode_..._texture_alignment()
V2: Rebased on master.
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit a5a00bd7472dc8876e1bec9a7172af7d332ac95e
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Wed Sep 23 16:12:26 2015 -0700
i965/gen9: Reuse YF alignment tables in tr_mode_..._texture_alignment()
Patch just does some refactoring to make the code look better. No
functional changes in here.
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit f2215809377234aa2073502587e1803c8952bea3
Author: Brian Paul <brianp at vmware.com>
Date: Thu Oct 15 22:57:08 2015 -0600
vbo: convert display list GL_LINE_LOOP prims to GL_LINE_STRIP
When a long GL_LINE_LOOP prim was split across primitives we drew
stray lines. See previous commit for details.
This patch converts GL_LINE_LOOP prims into GL_LINE_STRIP prims so
that drivers don't have to worry about the _mesa_prim::begin/end flags.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=81174
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
Acked-by: Sinclair Yeh <syeh at vmware.com>
commit d79595bf0230824b241545c0a0bd2294525df088
Author: Brian Paul <brianp at vmware.com>
Date: Thu Oct 15 22:31:50 2015 -0600
vbo: fix GL_LINE_LOOP stray line bug
When long GL_LINE_LOOP primitives don't fit in one vertex buffer they
have to be split across buffers. The code to do this was basically correct
but drivers had to pay special attention to the _mesa_prim::begin,end flags
in order to draw the sections of the line loop properly. Apparently, the
only drivers to do this were those using the old 'tnl' module for software
vertex processing.
Now we convert the split pieces of GL_LINE_LOOP prims into GL_LINE_STRIP
primitives so that drivers don't have to worry about the special begin/end
flags. The only time a driver will get a GL_LINE_LOOP prim is when the
whole thing fits in one vertex buffer.
Mostly fixes bug 81174, but not completely. There's another bug somewhere
in the src/gallium/auxiliary/draw/ code. If the piglit lineloop test is
run with -count 4096, rendering is correct, but with -count 4097 there are
stray lines. 4096 is a magic number in the draw code (search for "4096").
Also note that this does not fix long line loops in display lists. The
next patch fixes that.
v2: fix incorrect -1 in vbo_compute_max_verts(), per Charmaine. Remove
incorrect assertion which was added in vbo_copy_vertices().
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=81174
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=49779
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=28130
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
Reviewed-by: Sinclair Yeh <syeh at vmware.com>
commit 03d2f085394011f704f5702a92128b5677733c38
Author: Brian Paul <brianp at vmware.com>
Date: Fri Oct 16 11:19:40 2015 -0600
vbo: add new vbo_compute_max_verts() helper function
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
Reviewed-by: Sinclair Yeh <syeh at vmware.com>
commit 002c5c1da3a2db60607fb184b9c6343415987fb5
Author: Brian Paul <brianp at vmware.com>
Date: Thu Oct 15 20:33:52 2015 -0600
vbo: simplify some code in vbo_exec_End()
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
Reviewed-by: Sinclair Yeh <syeh at vmware.com>
commit d916175c4d965942325bbb4a684fac45fb6ab9e2
Author: Brian Paul <brianp at vmware.com>
Date: Thu Oct 15 21:25:18 2015 -0600
vbo: simplify some code in vbo_copy_vertices()
As before, use a new 'last_prim' pointer to simplify things. Plus, add
some const qualifiers.
v2: use 'sz' in another place, per Sinclair. And update subject line.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
Reviewed-by: Sinclair Yeh <syeh at vmware.com>
commit d24c3a680e9282c11bd411d0c4dbcff561c0f4ca
Author: Brian Paul <brianp at vmware.com>
Date: Thu Oct 15 20:18:32 2015 -0600
vbo: simplify some code in vbo_exec_wrap_buffers()
Use a new 'last_prim' pointer to simplify things.
v2: remove unneeded assert(exec->vtx.prim_count > 0)
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
Reviewed-by: Sinclair Yeh <syeh at vmware.com>
commit 1637cec8f894f80937fe7c1b1f4fe4d245d6005b
Author: Brian Paul <brianp at vmware.com>
Date: Thu Oct 15 21:21:56 2015 -0600
vbo: replace the comment on vbo_copy_vertices()
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
Reviewed-by: Sinclair Yeh <syeh at vmware.com>
commit e05ffcf1d94d01da37b4f488aa05716c62ff6547
Author: Brian Paul <brianp at vmware.com>
Date: Thu Oct 15 20:22:25 2015 -0600
vbo: make vbo_exec_vtx_wrap() static
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
Reviewed-by: Sinclair Yeh <syeh at vmware.com>
commit 971b56c643f35a2fb2f0f21cd5fd45ce9b155d4b
Author: Brian Paul <brianp at vmware.com>
Date: Thu Oct 15 14:11:54 2015 -0600
vbo: remove unneeded ctx parameter for merge_prims()
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
Reviewed-by: Sinclair Yeh <syeh at vmware.com>
commit 6cc596c66bb41cd3fa60bbf630c9ea4f661a64cc
Author: Brian Paul <brianp at vmware.com>
Date: Thu Oct 15 22:30:22 2015 -0600
tnl: add some comments in render_line_loop code
And remove '(void) flags' line which is not needed.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
Reviewed-by: Sinclair Yeh <syeh at vmware.com>
commit f7272032bec2e92e05e9c870e9655ca069d3d988
Author: Brian Paul <brianp at vmware.com>
Date: Thu Oct 15 09:52:09 2015 -0600
mesa: simple whitespace fix in texstore.c
commit f6d4e20d10d2316b70b73676e97b2c1e5cf7634a
Author: Brian Paul <brianp at vmware.com>
Date: Thu Oct 15 12:33:00 2015 -0600
vbo: reduce number of vertex buffer mappings for vertex attributes
Whenever we got a glColor, glNormal, glTexCoord, etc. call outside a
glBegin/End pair, we'd immediately map a vertex buffer to begin
accumulating vertex data. In some cases, such as with display lists,
this led to excessive vertex buffer mapping. For example, if we have
a display list such as:
glNewList(42, GL_COMPILE);
glBegin(prim);
glVertex2f();
...
glVertex2f();
glEnd();
glEndList();
Then did:
glColor3f();
glCallList(42);
We'd map a vertex buffer as soon as we saw glColor3f but we'd never
actually write anything to it. Note that the vertex position data
was put into a vertex buffer during display list compilation.
With this change, we delay mapping the vertex buffer until we actually
have a vertex to write to it (triggered by a glVertex() call). In the
above case, we no longer map a vertex buffer when setting the color and
calling the list.
For drivers such as VMware's, reducing buffer mappings gives improved
performance.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit d11fefa96165836ffeed531a74319a64aa98a696
Author: Brian Paul <brianp at vmware.com>
Date: Thu Oct 15 11:54:06 2015 -0600
st/mesa: optimize 4-component ubyte glDrawPixels
If we didn't find a gallium surface format that exactly matched the
glDrawPixels format/type combination, we used some other 32-bit packed
RGBA format and swizzled the whole image in the mesa texstore/format code.
That slow path can be avoided in some common cases by using the
pipe_samper_view's swizzle terms to do the swizzling at texture sampling
time instead.
For now, only GL_RGBA/ubyte and GL_BGRA/ubyte combinations are supported.
In the future other formats and types like GL_UNSIGNED_INT_8_8_8_8 could
be added.
v2: fix incorrect swizzle setup (need to invert the tex format's swizzle)
Reviewed by: Jose Fonseca <jfonseca at vmware.com>
commit cf405922eb2bd4d1dfae896caa9d58980875e7ec
Author: Brian Paul <brianp at vmware.com>
Date: Thu Oct 15 09:54:29 2015 -0600
mesa: make memcpy_texture() non-static
So that we can use it directly from the mesa/gallium state tracker.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
Reviewed-by: Sinclair Yeh <syeh at vmware.com>
commit 31ae52acceb7defc84080e32db6d5b1b0fe2eace
Author: Brian Paul <brianp at vmware.com>
Date: Thu Oct 15 09:38:00 2015 -0600
st/mesa: check for out-of-memory in st_DrawPixels()
Before, if make_texture() or st_create_texture_sampler_view() failed
we silently no-op'd the glDrawPixels. Now, set GL_OUT_OF_MEMORY.
This also allows us to un-nest a bunch of code.
v2: also check if allocation of sv[1] fails, per Jose.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit c5de38abc9eb71ba89fb1332946ee034e5a0c649
Author: Brian Paul <brianp at vmware.com>
Date: Thu Oct 15 09:32:50 2015 -0600
st/mesa: use MAX3() instead of MAX2(MAX2) in draw_textured_quad()
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
Reviewed-by: Sinclair Yeh <syeh at vmware.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit e24d04e436ed48d4a0aac90590cbaa40da936208
Author: Brian Paul <brianp at vmware.com>
Date: Thu Oct 15 08:43:02 2015 -0600
mesa: fix incorrect opcode in save_BlendFunci()
Fixes assertion failure with new piglit
arb_draw_buffers_blend-state_set_get test.
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit b1f8ef5ae3697b9b73f2ad7d07714f945c5175c3
Author: Brian Paul <brianp at vmware.com>
Date: Thu Oct 15 08:40:54 2015 -0600
mesa: add more cases to print_list() in dlist.c
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 6994d8ec01273f15d91e5330960194630c1c02e0
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Oct 17 23:42:13 2015 +0100
i965: silence incompatible pointer type warning
src/mesa/drivers/dri/i965/brw_program.c:94:39:
warning: passing argument 1 of ‘_mesa_init_gl_program’ from incompatible
pointer type [-Wincompatible-pointer-types]
return _mesa_init_gl_program(&prog->program, target, id);
^
Runtime was unaffected as brw_geometry_program is subclassed from
gl_geometry_program, thus the address passed was the same.
Fixes: bcb56c2c69d (program: convert _mesa_init_gl_program() to take
struct gl_program *)
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 814f31457e9ae83d4f1e39236f704721b279b73d
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Oct 20 18:26:02 2015 +0200
gallium: add PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
This avoids a serious r600g bug leading to a GPU hang.
The chances this bug will get fixed are pretty low now.
I deeply regret listening to others and not pushing this patch, leaving
other users with a GPU-crashing driver. Yes, it should be fixed
in the compiler and it's ugly, but users couldn't care less about that.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86720
Cc: 11.0 10.6 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 921feb8782bdc3c459922858bee6d55919467436
Author: Eric Anholt <eric at anholt.net>
Date: Fri Jul 31 20:58:57 2015 -0700
vc4: Switch our vertex attr lowering to being NIR-based.
This exposes more information to NIR's optimization, and should be
particularly useful when we do range-based optimization.
total uniforms in shared programs: 32066 -> 32065 (-0.00%)
uniforms in affected programs: 21 -> 20 (-4.76%)
total instructions in shared programs: 93104 -> 92630 (-0.51%)
instructions in affected programs: 31901 -> 31427 (-1.49%)
commit 85b946478c326df853926ed18bfbd898c0a514ef
Author: Eric Anholt <eric at anholt.net>
Date: Tue Oct 20 10:49:10 2015 +0100
vc4: Add limited support for ibfe/ubfe.
This is just enough to cover our unpack modes, which will be used by some
new NIR-based lowering in the next commit.
commit 8910ebd8e8ed7e163ae69bb85cda55531675e95d
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Oct 17 23:17:52 2015 +0200
tgsi/scan: use properties for clip/cull distance writemasks
No changes needed for drivers already relying on tgsi_shader_info.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 7c75f23cb92f7e4a55f2ae31df9274338ec60531
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Oct 17 23:17:52 2015 +0200
st/mesa: pass the clip distance array size to drivers
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit e70c66197ea10cf052010c7352420a2ae0b0a50a
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Oct 17 23:15:28 2015 +0200
gallium: add new properties for clip and cull distance usage
The TGSI usage mask can't be used, because these are declared as an output
array of 2 elements.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 67f489ded3a4c575e203dc82368ebe645e72079a
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Oct 17 22:50:11 2015 +0200
mesa: replace UsesClipDistance with ClipDistanceArraySize
This is more practical and needed by gallium.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 8339585b1206232c1df165108ef6adadb0829ab0
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Oct 18 15:09:24 2015 +0200
radeonsi: enable BC_OPTIMIZE if centroid isn't used
This solution was recommended by a Catalyst developer.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 38391835b5cbdd52e7a3221ff98f402aefa1639b
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Oct 17 23:59:52 2015 +0200
radeonsi: fix the export_prim_id field size in the shader key
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 9b54ce3362f117b4d46497b578211bb26554dd78
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Oct 7 01:48:18 2015 +0200
radeonsi: support thread-safe shaders shared by multiple contexts
The "current" shader pointer is moved from the CSO to the context, so that
the CSO is mostly immutable.
The only drawback is that the "current" pointer isn't saved when unbinding
a shader and it must be looked up when the shader is bound again.
This is also a prerequisite for multithreaded shader compilation.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit e57dd7a08bfeacab47d64c3adeb392f8c15ca793
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Sep 28 00:04:39 2015 +0200
st/mesa: create shaders which have only one variant immediatelly (v2)
v2: fix the condition when lacking sample shading
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit b99645f8190b267231443829aefad1e73c4c25d4
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Oct 20 00:12:53 2015 +0200
st/mesa: negate the can_force_persample_interp flag
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit f4e938e9aee14d42e2175c84ebe7ee32b0bcf8c5
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Sep 27 23:36:59 2015 +0200
st/mesa: decouple shaders from contexts if they are shareable
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit d74e7b6fb9dca5622c17413821d4cfcc67472e76
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Sep 27 21:02:15 2015 +0200
gallium: add PIPE_CAP_SHAREABLE_SHADERS
I'll let drivers figure out how to do it.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 12321966aec5e635c51208f409737dd1ddc3c883
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Mar 17 14:46:04 2015 +0100
radeonsi: add support for ARB_texture_view
All tests pass. We don't need to do much - just set CUBE if the view
target is CUBE or CUBE_ARRAY, otherwise set the resource target.
The reason this can be so simple is that texture instructions
have a greater effect on the target than the sampler view.
Thanks Glenn for the piglit test.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 6bd9e0351205dc475f45b58979702b5cf414aa07
Author: Boyan Ding <boyan.j.ding at gmail.com>
Date: Fri Oct 16 15:15:39 2015 +0800
vc4: Use nir_foreach_variable
Signed-off-by: Boyan Ding <boyan.j.ding at gmail.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 2832ca95ecce064c7d841a3a374c2179f56161be
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Sat Oct 17 20:22:14 2015 +1100
glsl: fix stream qualifier for blocks with an instance name
This also removes the validation from the parser as it is not required
and once arb_enhanced_layouts comes along we wont be able to do validation
on the stream qualifier in the parser anyway as it adds constant expression
support to the stream qualifier.
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Cc: 11.0 <mesa-stable at lists.freedesktop.org>
commit aa9f06b3ea99b318469c3d140651f4b4986896a6
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Sun Oct 18 09:12:40 2015 +1100
glsl: fix regression when building interface field name for SSBOs
Fixes regression cased by bb5aeb854915ba67abc56257f830d002c956439e
We don't care about the swizzle when building the name so just skip over it.
Tested-by: Markus Wick <markus at selfnet.de>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit 867284a8f07b69887f8adb109fb6c71156668227
Author: Leo Liu <leo.liu at amd.com>
Date: Fri Aug 28 08:45:11 2015 -0400
st/omx/dec/h264: fix field picture type 0 poc disorder
Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
commit 2eed9e6b756d1e0232ad749cb89e97d535e141bd
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Wed Aug 12 11:34:54 2015 -0700
i965/gen9: Handle the GL_TEXTURE_{1D, 1D_ARRAY} targets inside switch
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit de862f03accb12b044ced60cb98f47a055457223
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu Oct 15 16:01:11 2015 -0700
i965/fs: Localize variables' scopes.
commit 35a2d259f27f5b41f29a1112ca48093dac09c364
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Oct 14 02:23:25 2015 -0700
i965/fs: Consider type mismatches in saturate propagation.
NIR considers bcsel to produce and consume unsigned types, leading to
SEL instructions operating on unsigned types when the data is really
floating-point. Previous to this patch, saturate propagation would
happily transform
(+f0) sel g20:UD, g30:UD, g40:UD
mov.sat g50:F, g20:F
into
(+f0) sel.sat g20:UD, g30:UD, g40:UD
mov g50:F, g20:F
But since the meaning of .sat is dependent on the type of the
destination register, this is not valid.
Instead, allow saturate propagation to change the types of dest/source
on instructions that are simply copying data in order to propagate the
saturate modifier.
Fixes bad code gen in 158 programs.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 9e17c36b8ba79e688011a5fd293ad5f42da21b66
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Oct 14 02:12:09 2015 -0700
i965: Extract can_change_source_types() functions.
Make them members of fs_inst/vec4_instruction for use elsewhere.
Also fix the fs version to check that dst.type == src[1].type and for
!saturate.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 41c474df53d9dcd5fd8e24eba5b7acc2b3c32795
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Oct 15 11:39:06 2015 -0700
i965/vs: Move URB entry_size and read_length calculations to compile_vs
Reviewed-By: Eduardo Lima Mitev <elima at igalia.com>
commit 6980372010ad5929c0b4b0a0370d281cbd6f8b2e
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Oct 8 17:09:54 2015 -0700
i965: Move the entire compiler API into a single file
At this point, the compiler API has been substantially simplified. In the
spirit of Kristian's making a compiler library, this commit makes a single
header file that contains, more-or-less, the entire compiler API.
There's still a bit of cleanup to do particularly in the area of geometry
shaders. However, this gets us much closer to having a separate compiler.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 4467344c829f1dccdf74e27bef2c5fda72552be6
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Oct 8 16:20:34 2015 -0700
i965: Rename brw_foo_emit to brw_compile_foo
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 67db9072b9fde74277f74f7303366b8bdd3a711e
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Oct 8 16:01:44 2015 -0700
i965/fs: Move some of the prog_data setup into brw_wm_emit
This commit moves the common/modern stuff. Some legacy stuff such as
setting use_alt_mode was left because it needs to know whether or not we're
an ARB program.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 4e711872d024ce41c8b07b1150d8a393de21e26d
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Oct 8 15:28:26 2015 -0700
i965/cs: Rework cs_emit to take a nir_shader and a brw_compiler
This commit removes all dependence on GL state by getting rid of the
brw_context parameter and the GL data structures.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 657863bb5c895fac7f5e52dfd025d07bf52f94a8
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Oct 8 14:39:56 2015 -0700
i965/gs: Rework gs_emit to take a nir_shader and a brw_compiler
This commit removes all dependence on GL state by getting rid of the
brw_context parameter and the GL data structures. Unfortunately, we still
have to pass in the gl_shader_program for gen6 because it's needed for
transform feedback.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 5d8bf6de6166a686a006478a420bcd373860e9ee
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Oct 8 13:53:33 2015 -0700
i965/vs: Rework vs_emit to take a nir_shader and a brw_compiler
This commit removes all dependence on GL state by getting rid of the
brw_context parameter and the GL data structures.
v2 (Jason Ekstrand):
- Patch use_legacy_snorm_formula through as a function argument rather
than trying to go through the shader key.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 22ad44910e993e1acd0b4052722fe786626008b5
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Oct 5 19:27:28 2015 -0700
i965/fs: Rework wm_fs_emit to take a nir_shader and a brw_compiler
This commit removes all dependence on GL state by getting rid of the
brw_context parameter and the GL data structures.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 0ca401327ef9e280b3a8b008f1e41477afec3a35
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Oct 5 19:26:02 2015 -0700
i965: Use a const nir_shader in backend_shader
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 8f1d968704858d78d7e78a6b88db3ea2bc0cf749
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Oct 5 17:41:46 2015 -0700
i965/vec4: Remove gl_program and gl_shader_program from the generator
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 5e86f5b3d21fe8e96676bb0608990d72dbf61b85
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Oct 5 16:01:33 2015 -0700
i965/fs: Remove the gl_program from the generator
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 688d2e45855299dcf474791f29d65040ce5cb2dc
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Oct 8 15:47:09 2015 -0700
nir/info: Add a few bits of info for fragment shaders
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 4889c73dd1ed0af7920b950f6810361a6eeabcc2
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Oct 8 15:02:25 2015 -0700
nir/info: Add compute shader local size to nir_shader_info
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit fe399f3a69689a78ca4a5fb5a6b76435adcd41e5
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Oct 8 15:36:51 2015 -0700
nir/info: Move the GS info into a stage-specific info union
This way we can have other stage-specific info without consuming too much
extra space. While we're at it, we make sure that the geometry info is
only set if we're actually a goemetry shader.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 16619477bc800d32b5bf2f38dd544960cf66c284
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Oct 8 15:59:56 2015 -0700
mesa: Move gl_frag_depth_layout from mtypes.h to shader_enums.h
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 5d4bc5ec1339fcdafae957e3473f3c2c9931bb23
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Oct 5 16:54:36 2015 -0700
nir: Add a label to nir_shader_info
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit e00314bc57a59b3f816daba6249e7b7157761f86
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Oct 5 15:49:34 2015 -0700
i965/asm: Explicitly use a nir_instr for IR annotations
Now that everything goes through NIR, we don't need this to be a void
pointer anymore.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit b23a4859f4dbbcca7d6a637010167d470211e45b
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Mon Oct 19 14:29:28 2015 +0100
scons: Build nir/glsl_types.cpp once.
Undoes early hacks, and ensures nir/glsl_types.cpp is built once, and
only once.
The root problem is that SCons doesn't know about NIR nor any source
file in the NIR_FILES source list.
Tested with libgl-gdi and libgl-xlib scons targets.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 530eb39c71d2f42ef5d6c556aff77c322434f4e2
Author: Brian Paul <brianp at vmware.com>
Date: Mon Oct 19 08:41:37 2015 -0600
svga: fix incorrect round-down arithmetic
Spotted by Roland. Luckily, this code should never really be hit
since the const buffer size and offset should already be multiples
of 16. I could probably add more assertions to that effect, but
let's just fix the arithmetic for now.
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit 6f3954618b0fe273af76af79ce9ec56566b79b2a
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Mon Oct 19 10:37:14 2015 +0200
glsl: fix segfault when indirect indexing a buffer variable which is an array
Fixes a regression added by bb5aeb854915ba67abc56257f830d002c956439e.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
commit b0a44f1017be51c3eb612da2a6ccd5df5695c25a
Author: Indrajit Das <indrajit-kumar.das at amd.com>
Date: Fri Oct 16 12:18:45 2015 +0530
st/va: Added support for NV12 to IYUV conversion in vlVaGetImage
Reviewed-by: Christian König <christian.koenig at amd.com>
commit 381c17d695b39f9ab501f5aa5a3cc42c8519ac3b
Author: Indrajit Das <indrajit-kumar.das at amd.com>
Date: Thu Oct 15 15:42:43 2015 +0530
st/va: Used correct parameter to derive the value of the "h" variable in vlVaCreateImage
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 36c93e96590b39362bb0159f5f55f1ad1db5e145
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Fri Oct 16 11:43:18 2015 +0200
glsl_to_tgsi: Use {Num}UniformBlocks instead of {Num}BufferInterfaceBlocks
The latter holds both UBOs and SSBOs, but here we only want UBOs.
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 5a9ff87d0f10bae5dba4b2bebd28f2625cd485aa
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Fri Oct 16 11:40:52 2015 +0200
st/mesa: Use {Num}UniformBlocks instead of {Num}BufferInterfaceBlocks
The latter holds both UBOs and SSBOs, but here we only want UBOs.
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 55403665b6bff3778ba335e9fd7821fc9a11ad2b
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Fri Oct 16 11:31:46 2015 +0200
i965: Do not use NumBufferInterfaceBlocks
This is the only place in the driver where we use this. Since we now work
with separate index spaces, always use NumUniformBlocks and
NumShaderStorageBlocks instead of NumBufferInterfaceBlocks to be more
consistent with the rest of the code.
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 14c3db7bc59a6b10f5a13930c0274d4155cb8791
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Fri Oct 16 11:27:43 2015 +0200
main: GL_ACTIVE_UNIFORM_BLOCK_MAX_NAME_LENGTH is about UBOS, not SSBOs
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit fba582efc7d66140b5c18ada4d5cd93c9c1e5967
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Fri Oct 16 11:16:46 2015 +0200
main: Use NumUniformBlocks to count UBOs
Now that we have separate index spaces for UBOs and SSBOs we do not need
to iterate through BufferInterfaceBlocks any more, we can just take the
UBO count directly from NumUniformBlocks.
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 86ccb2a16f6d21be29cd99d38831eab6079ce107
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Oct 16 22:53:05 2015 +0800
ilo: set VME for 3DSTATE_PS
When the bit is not set, we can see sampling artifacts on triangle edges when
the mip filter is not GEN6_MIPFILTER_NONE.
commit d04126a773f8a70ff6ae549751dc674133ea26b0
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Oct 16 16:19:30 2015 +0800
ilo: ignore prefer_linear_threshold when zero
This was the intended behavior but it did not work as intended until now.
commit a445e0f7efcaa0ff21b5fe4faa3f73f3b73dcfe8
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Oct 16 09:50:12 2015 +0800
ilo: remove some unused kernel params
commit 6e132f4730a41baa36bf31c1b5f47933d07cee8c
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Oct 16 09:46:25 2015 +0800
ilo: remove unused ilo_shader_get_type()
commit 29a0f7479dd09ca60bed084fd6e5f736a6340cb5
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Tue Oct 13 14:09:24 2015 +0800
ilo: remove u_debug.h inclusion from ilo_core.h
Move it to ilo_debug.h.
commit 3fe568e2a472b764e96b67cf57ef63f40cdce5a6
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Tue Oct 13 14:05:41 2015 +0800
ilo: remove u_memory.h inclusion from ilo_core.h
We do not make allocations generally in the core.
commit fc5ae0c13f71f049065b1422c20491d2264ae164
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Sat Oct 17 17:33:14 2015 +0200
nvc0: do not bind input params at compute state init on Fermi
It looks like binding a constant buffer on compute overwrites the 3D
state. To avoid that, we already re-bind all the 3D constant buffers
after launching a compute grid but this is not enough.
Binding the constant buffer of input parameters for the compute state at
initialization corrupts the 3D constant buffers, and it's just useless
to bind it because this is not needed until we really launch a grid.
This fixes some piglit regressions related to interpolation tests
introduced in "nvc0: enable compute support by default on Fermi".
Fixes: 00d6186 (nvc0: enable compute support by default on Fermi)
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit ca2b807ca32dcf531fbf96d9fa0026679abbf111
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Oct 15 15:34:06 2015 -0700
i965/vs: Drop hack that created NIR for fixed function vertex programs.
Marek made core Mesa call ProgramStringNotify(), which solves this
properly. The hack is no longer needed.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit dbac0a6352053bd6106feff88d95b0fd38b82afe
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Oct 15 15:17:19 2015 -0700
i965/nir: Switch on shader stage in nir_lower_outputs().
VS, GS, and FS continue doing the same thing they did before. We can
simplify the FS code a bit because it is always scalar.
Compute shaders now assert that there are no outputs instead of doing
a loop over 0 outputs.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 7c10af64258ca3a839d9fc1f14957ef556878b43
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Oct 10 22:43:19 2015 +0200
radeonsi: don't use the AMDGPU intrinsic for CMP
No difference according to shader-db.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
commit f2cdb68c8bb905cd76edae383e1cbbe0ae2c69ea
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Oct 10 22:19:19 2015 +0200
radeonsi: use LRP from gallivm
Totals:
SGPRS: 344552 -> 344368 (-0.05 %)
VGPRS: 197132 -> 197552 (0.21 %)
Code Size: 7375376 -> 7366304 (-0.12 %) bytes
LDS: 91 -> 91 (0.00 %) blocks
Scratch: 1679360 -> 1615872 (-3.78 %) bytes per wave
Totals from affected shaders:
SGPRS: 47736 -> 47552 (-0.39 %)
VGPRS: 27952 -> 28372 (1.50 %)
Code Size: 1392724 -> 1383652 (-0.65 %) bytes
LDS: 39 -> 39 (0.00 %) blocks
Scratch: 513024 -> 449536 (-12.38 %) bytes per wave
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit eb11efc989020d6786e834d07dbfdb426802a696
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Oct 10 21:27:24 2015 +0200
radeonsi: don't emit AMDGPU intrinsics for integer abs, min, max
No difference according to shader-db. (with the new S_ABS_I32 pattern)
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
commit d72a26ec5de04d0b951b4acd66e00352afdc279d
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Oct 10 19:59:57 2015 +0200
radeonsi: don't emit AMDGPU intrinsics for EX2, ROUND, TRUNC
No difference according to shader-db.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
commit 6660ca7121183b5ce777b1bd3613afdd19640b13
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Oct 10 02:40:20 2015 +0200
radeonsi: initialize output, temp, and address registers to "undef"
This removes "v_mov v0, 0" which typically occurs before exports.
Totals:
SGPRS: 345216 -> 344552 (-0.19 %)
VGPRS: 197684 -> 197132 (-0.28 %)
Code Size: 7390408 -> 7375376 (-0.20 %) bytes
LDS: 91 -> 91 (0.00 %) blocks
Scratch: 1842176 -> 1679360 (-8.84 %) bytes per wave
Totals from affected shaders:
SGPRS: 101336 -> 100672 (-0.66 %)
VGPRS: 53920 -> 53368 (-1.02 %)
Code Size: 2170176 -> 2155144 (-0.69 %) bytes
LDS: 2 -> 2 (0.00 %) blocks
Scratch: 1015808 -> 852992 (-16.03 %) bytes per wave
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
commit 529c5e77402012aa0c0a11ee71a1a65e51edb496
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Oct 10 22:05:58 2015 +0200
gallivm: implement the correct version of LRP
The previous version has precision issues. This can be a problem
with tessellation. Sadly, I can't find the article where I read it
anymore. I'm not sure if the unsafe-fp-math flag would be enough to revert
this.
v2: added the comment
commit a2197cac7fd6ce3f897a89121f5e499d28a3888e
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Oct 10 21:24:28 2015 +0200
gallivm: set correct opcode info from unary/binary/ternary emits
and clear the emit_data structure.
The new radeonsi min/max opcode implementation requires this.
(it looks good according to Roland S.)
commit 5bc871a4caf97f4e07830ea463f445994c8d13b5
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Oct 7 02:36:38 2015 +0200
radeonsi: implement vertex color clamping
This is only supported in the compatibility profile (without GS and tess).
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 208d1ed38ddb7de8211a9ffc3d89ae176ef7e9d4
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Oct 7 01:47:00 2015 +0200
radeonsi: implement fragment color clamping
using the shader key for now.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit acc6a07874e6af133310adcc6c58898cf4312a6c
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Oct 9 01:37:57 2015 +0200
radeonsi: clean up other scratch buffer functions
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 9098d7e9bd97fd3d674fc93441ea9ab01c2779c7
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Oct 9 01:35:32 2015 +0200
radeonsi: clean up copy-pasted scratch buffer updates
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 938a1bee34cc8e0c22a9b99c6b3d247b88e94cc2
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Oct 9 01:14:12 2015 +0200
radeonsi: unify shader create functions
The shader specifies the processor type, so use that instead.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit b0167809f1e88f3676db78b1c1934aea35e55be5
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Oct 9 01:08:42 2015 +0200
radeonsi: unify shader delete functions
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit aa060e276c203baf4691d4a4722accd5bdbb8526
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Oct 9 00:54:17 2015 +0200
radeonsi: fix a GS copy shader leak
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit c4f086f3999894c9b6fe2de466add3bb09c8b354
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Oct 9 00:49:13 2015 +0200
radeonsi: remove an unused ctx parameter in si_shader_destroy
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 4f4f477d6dd8ba5e0d37dbba50d28c1a85accf39
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Oct 9 00:20:30 2015 +0200
radeonsi: print export_prim_id from the shader key
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit b11edf887236b53b489f5df14152ac651b0b3857
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Oct 8 22:23:18 2015 +0200
radeonsi: disable NaNs for LS and HS
They're disabled for all other shaders except compute, but I forgot
to do this for tess stages.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 73e3fba3356a58dadf46f2cc5d68d8eda824fccb
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Oct 7 01:28:18 2015 +0200
radeonsi: clean up si_llvm_init_export_args
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 82335978bb3a68f1acf200bdfb683db4d8dd3cea
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Oct 9 01:11:31 2015 +0200
tgsi: move pipe_shader_from_tgsi_processor function to util
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 8c5647db5e7ade454745caf97ac7c04f64b08c79
Author: Brian Paul <brianp at vmware.com>
Date: Wed Oct 14 09:08:50 2015 -0600
mesa: remove FLUSH_VERTICES() in _mesa_MatrixMode()
Changing the matrix mode alone has no effect on rendering and does
not need to trigger a flush or state validation.
Reviewed-by: Eric Anholt <eric at anholt.net>
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit 3c6156a4a7b647cc55cbe3a4c13d53b5ffe505e6
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Oct 17 14:20:01 2015 +0200
st/mesa: fix clip state dependencies
This allows removing FLUSH_VERTICES in MatrixMode.
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 006fcc0da674ca18ebf07771e3c309997ab32798
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Oct 17 19:05:46 2015 +0200
gallium/hud: fix possible NULL pointer dereference
Trivial.
commit 3272f632eec768c79000836e9bc45b90229789e7
Author: Brian Paul <brianp at vmware.com>
Date: Sat Oct 17 10:02:04 2015 -0600
scons: fix MSVC, MinGW build
Duplicate the glsl_types_hack.cpp work-around from the libgl-xlib target.
commit 7e6aafd6ab89ad8bc113f67eb666a90b979cdb8e
Author: Rob Clark <robclark at freedesktop.org>
Date: Sat Oct 17 09:49:19 2015 -0400
build: fix make-check after a6a6a71
commit a6a6a71092ba912803ae2b47eb56e3afdf36feb5
Author: Rob Clark <robclark at freedesktop.org>
AuthorDate: Sat Oct 10 14:13:50 2015 -0400
glsl: (mostly) remove libglsl_util
Was a bit too ambitious on removal of libglsl_util.. it is still needed
by some of the tests.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit b7963b6926c06666b24453344c47f12e369e8fd1
Author: Rob Clark <robclark at freedesktop.org>
Date: Sat Oct 17 09:28:23 2015 -0400
build: fix out-of-tree build after b9b40ef
commit b9b40ef9b7644ea24768bc8b7464b1719efe99bf
Author: Rob Clark <robclark at freedesktop.org>
AuthorDate: Sat Oct 10 13:55:07 2015 -0400
nir: remove dependency on glsl
broke things for i965 out of tree build.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit c188235d1be7d4fc65d99d2620d0dcdec5a21c84
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Sun Oct 11 11:23:54 2015 +0200
nvc0: add support for performance monitoring metrics on Fermi
As explained in the CUDA toolkit documentation, "a metric is a
characteristic of an application that is calculated from one or more
event values."
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit a6a6a71092ba912803ae2b47eb56e3afdf36feb5
Author: Rob Clark <robclark at freedesktop.org>
Date: Sat Oct 10 14:13:50 2015 -0400
glsl: (mostly) remove libglsl_util
Now that NIR does not depend on glsl, we can (mostly[*]) get rid of the
libglsl_util hack.
[*] glsl_compiler is the one remaining user of libglsl_util
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit b9b40ef9b7644ea24768bc8b7464b1719efe99bf
Author: Rob Clark <robclark at freedesktop.org>
Date: Sat Oct 10 13:55:07 2015 -0400
nir: remove dependency on glsl
Move glsl_types into NIR, now that the dependency on glsl_symbol_table
has been split out.
Possibly makes sense to rename things at this point, but if we do that
I'd like to keep it split out into a separate patch to make git history
easier to follow (IMHO).
v2: fix android build
v3: I f***ing hate scons.. but at least it builds
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 183db3a64557d5d231ef58ab5666286f323ff333
Author: Rob Clark <robclark at freedesktop.org>
Date: Sat Oct 10 13:26:03 2015 -0400
glsl: move half<->float convertion to util
Needed in NIR too, so move out of mesa/main/imports.c
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 60690cb3b3082b7397c48769ec28b5570f6b7d7e
Author: Rob Clark <robclark at freedesktop.org>
Date: Sat Oct 10 12:39:57 2015 -0400
glsl: move builtin vector types to glsl_types.cpp
First step at untangling NIR's dependency on glsl_types without bringing
in the dependency on glsl_symbol_table. The builtin types are now in
glsl_types (which will end up in NIR), but adding them to the symbol-
table stays in builtin_types.cpp (which will not be part of NIR).
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 33de998230414bf5603927424ffca85792b176d1
Author: Rob Clark <robclark at freedesktop.org>
Date: Fri Oct 9 16:27:45 2015 -0400
glsl: couple shader_enums cleanups
Add missing enum to gl_system_value_name() and move VARYING_SLOT_MAX /
FRAG_RESULT_MAX / etc into shader_enums.h as suggested by Emil.
v2: add STATIC_ASSERT()'s
Reported-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Emil Velikov <emil.velikov at collabora.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 698cdbf49207c30bc2ac38e2f16e531dd3a54db3
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Thu Oct 15 14:10:35 2015 +1100
glsl: initialise record array count to 1
This was only being done in one of the two process methods.
Fixes an issue with samplers using the array size of a previous record.
Tested-by: Marek Olšák <marek.olsak at amd.com>
Cc: Jason Ekstrand <jason at jlekstrand.net>
commit 3c87377d0b0d07249ba94d6cb22a8b324bb06ba6
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Thu Jul 23 08:32:00 2015 +1000
nir: add atomic lowering support for AoA
Cc: Francisco Jerez <currojerez at riseup.net>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 2e1798f183427d704d32d68165248519781ae864
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Thu Jul 23 08:31:59 2015 +1000
nir: wrapper for glsl_type arrays_of_arrays_size()
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit fd5e0581dda40fbf72f166cb583ea37e0f812d09
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Oct 14 15:49:58 2015 -0400
configure: show which gallium drivers/sts are built
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 2023906667cf349284cd3d3921dc1dcbb7506014
Author: Brian Paul <brianp at vmware.com>
Date: Fri Oct 16 14:31:22 2015 -0600
tgsi: initialize ctx.file in tgsi_dump_instruction()
Fixes segfault because of uninitialized file pointer.
Trivial.
commit a3b17575512f0bb614234ab1834b7b36e1124082
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Fri Oct 16 10:21:44 2015 +0200
nvc0: add a note about MP counters on GF100/GF110
MP counters on GF100/GF110 (compute capability 2.0) are buggy
because there is a context-switch problem that we need to fix.
Results might be wrong sometimes, be careful!
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 0461260d772ed91bec7cd36727c82ca4e6d71275
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Wed Oct 14 01:15:43 2015 +0200
nvc0: add MP counters variants for GF100/GF110
GF100 and GF110 chipsets are compute capability 2.0, while the other
Fermi chipsets are compute capability 2.1. That's why, some MP counters
are different between these chipsets and we need to handle variants.
Signed-off-by: Samuel Pitoiet <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit ec5001d25b281455869149bff5fa9d8c497b0cd4
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Tue Oct 13 22:16:23 2015 +0200
nvc0: move SW/HW queries info to their respective files
This will help for handling HW SM queries variants on Fermi.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 00d61869a5e8e8ecdb5613f1b2aab5019d71d77e
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Fri Oct 9 16:53:18 2015 +0200
nvc0: enable compute support by default on Fermi
Compute support was not enabled by default because weird effects
on 3D state happened, but I can't reproduce them anymore.
This also enables MP performance counters by default on Fermi.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 8cd4b8478aac56f0ed516c4ff13f8af012fb8eaa
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Mon Sep 28 17:29:37 2015 +0200
nvc0: allow only one active query for the MP counters group
Because we can't expose the number of hardware counters needed for each
different query, we don't want to allow more than one active query
simultaneously to avoid failure when the maximum number of counters
is reached. Note that these groups of GPU counters are currently only
used by AMD_performance_monitor.
Like for Kepler, this limits the maximum number of active queries
to 1 on Fermi.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit cef22f3490f9809a6e77949f73448efac23be7ee
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Fri Oct 9 16:10:19 2015 +0200
nvc0: read MP counters of all GPCs on Fermi
When a card has more than one GPC, the grid used by the compute
kernel which reads MP performance counters seems to be too small.
The consequence is that the kernel is not launched on all TPCs.
Increasing the grid size using the number of GPCs now launches
enough blocks and we can read MP performance counters of all TPCs.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 1825898e0471915673e572db4f61f1fd42461150
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Tue Oct 6 22:24:31 2015 +0200
nvc0: store the number of GPCs to nvc0_screen
NOUVEAU_GETPARAM_GRAPH_UNITS param returns the number of GPCs, the total
number of TPCs and the number of ROP units. Note that when the DRM
version is too old the default number of GPCs is fixed to 4.
This will be used to launch the compute kernel which is used to read MP
performance counters over all GPCs.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit c4896c99cbe10b829981250465baf0b00e18ba40
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Fri Oct 9 11:22:20 2015 +0200
nvc0: fix unaligned mem access when reading MP counters on Fermi
Memory access have to be aligned to 128-bits. Note that this
doesn't happen when the card only has TPC.
This patch fixes the following dmesg fail:
gr: GPC0/TPC1/MP trap: global 00000004 [MULTIPLE_WARP_ERRORS] warp 000f
[UNALIGNED_MEM_ACCESS]
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 7abd707251f29aaf27f83644e47d2dc8b75e10c6
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Fri Oct 9 11:18:45 2015 +0200
nvc0: fix monitoring multiple MP counters queries on Fermi
For strange reasons, the signal id depends on the slot selected on Fermi
but not on Kepler. Fortunately, the signal ids are just offseted by the
slot id!
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 4fcb661711c19a6c315267733e4cdcaee9f5e95b
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Fri Oct 9 11:14:31 2015 +0200
nvc0: fix queries which use multiple MP counters on Fermi
Queries which use more than one MP counters was misconfigured and
computing the final result was also wrong because sources need to
be configured on different hardware counters instead.
According to the blob, computing the result is now as follows:
FOR i..n
val += ctr[i] * pow(2, i)
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 6353f620cdb86009812ad2e850b79374e85ecec2
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Fri Oct 9 11:01:56 2015 +0200
nvc0: allow to use 8 MP counters on Fermi
On Fermi, we have one domain of 8 MP counters while we have
two domains of 4 MP counters on Kepler.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit cac897197b4ab021e06ed8b023f11035557be55e
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Fri Oct 9 15:33:23 2015 +0200
nvc0: fix sequence field init for MP counters on Fermi
Sequence fields are located at MP[i] + 0x20 in the buffer object.
This is used to check if result is available for MP[i].
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 409658c367c50bfb2fae6dec7d5b0ab5db16fe57
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Fri Oct 9 10:55:25 2015 +0200
nvc0: correctly enable the MP counters' multiplexer on Fermi
Writing 0x408000 to 0x419e00 (like on Kepler) has no effect on Fermi
because we only have one domain of 8 counters. Instead, we have to
write 0x80000000.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit c3570c3fb9ee78ab7af2de781a7056b3642bebb9
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Fri Oct 9 10:54:15 2015 +0200
nvc0: rip off the kepler MP-enabling logic from the Fermi codepath
Writing 0x1fcb to 0x419eac is definitely not related to MP counters and
has no effect on Fermi (although this enables MP counters on Kepler).
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit dab7e0ed09073b0fd7c37d0fabd70f302acbce32
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Fri Oct 9 10:45:04 2015 +0200
nvc0: split out begin_query() hook used by MP counters
The way we configure MP performance counters is going to pretty
different between Fermi and Kepler. Having two separate functions
is much better.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit d4ecc2bce458c28355f7ecdea72b619578a69fd5
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Fri Oct 9 10:36:39 2015 +0200
nvc0: remove useless call to query_get_cfg() in nvc0_hw_sm_query_end()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit efe37519b0cb0cadea57455d1d2457af09e2e7dd
Author: Brian Paul <brianp at vmware.com>
Date: Mon Oct 12 18:40:27 2015 -0600
svga: only count hardware buffer mappings for HUD
Don't count client memory buffer mappings since they're basically free.
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
commit 9bc7e3105aeadbe360ca9f060c50a181d3fa7a3d
Author: Neha Bhende <nbhende at vmware.com>
Date: Fri Oct 9 16:10:16 2015 -0600
svga: add new GALLIUM_HUD queries
Add new GALLIUM_HUD queries for:
num-shaders
num-resources
num-state-objects
num-validations
map-buffer-time
num-surface-views
num-resources-mapped
num-flushes
Most of this patch was originally written by Neha. Additional clean-ups
and num-flushes counter added by Brian Paul.
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
commit f413f1a17c506d5d4474a1baa0556a9e9f554c63
Author: Brian Paul <brianp at vmware.com>
Date: Thu Oct 8 21:06:18 2015 -0600
svga: use new svga_new_shader_variant() function
To simplify upcoming new HUD shader count implementation.
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
commit 8d0d5dca5bd076ef363d3e923e6473916f3a9d35
Author: Brian Paul <brianp at vmware.com>
Date: Thu Oct 8 21:03:27 2015 -0600
svga: pass context to svga_tgsi_vgpu9_translate()
Will be used for upcoming change.
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
commit 615b37a0e260ad8bd108a3e57a2a6f0eb6284246
Author: Brian Paul <brianp at vmware.com>
Date: Thu Oct 8 21:00:37 2015 -0600
svga: remove svga_tgsi_vgpu9_translate() call in GS path
We can never have geometry shaders with vgpu9.
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
commit cb473c46feb17d652f69836bf0d8843803fe77cd
Author: Brian Paul <brianp at vmware.com>
Date: Thu Oct 15 07:26:49 2015 -0600
glsl: silence warning about unhandled ast_unsized_array_dim case in switch
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
commit afff809fea373f849b648983bff8390c090b7145
Author: Brian Paul <brianp at vmware.com>
Date: Thu Oct 15 07:25:51 2015 -0600
st/mesa: fix incorrect pointer type arguments in st_new_program()
Silences 5 warnings of the type:
state_tracker/st_cb_program.c: In function 'st_new_program':
state_tracker/st_cb_program.c:108:7: warning: passing argument 1 of
'_mesa_init_gl_program' from incompatible pointer type [enabled by default]
return _mesa_init_gl_program(&prog->Base, target, id);
^
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 4627e8058ec1bc02cc2b6464ff83394b2d16879e
Author: Brian Paul <brianp at vmware.com>
Date: Fri Oct 16 09:10:22 2015 -0600
Revert "mesa: remove FLUSH_VERTICES() in _mesa_MatrixMode()"
This reverts commit 0de5e0f3fb0f3671a3ecec6ab4473f9131ecd0ae.
Michel Dänzer spotted two piglit regressions from the change. I suspect
that removing the FLUSH_VERTICES() actually exposed a bug elsewhere but
I don't have time to hunt down the root issue at this time.
commit ccbb52ac1117aa99144785bc032dd459f24b8ba1
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Fri Oct 16 08:44:38 2015 +0200
glsl: fix check SSBOs support for builtin functions
has_shader_storage_buffer_objects() returns true also if the OpenGL
context is 4.30 or ES 3.1.
Previously, we were saying that all atomic*() GLSL builtin functions
for SSBOs were not available when OpenGL ES 3.1 context was in use.
Fixes 48 dEQP-GLES31 tests:
dEQP-GLES31.functional.ssbo.atomic.*
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit dc8c221e2890cc9913dfc99e1e0fcb73c89af52c
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Tue Oct 13 08:49:57 2015 +0300
mesa: Set api prefix to version string when overriding version
Otherwise there are problems when user overrides version and application
such as Piglit wants to detect used api with glGetString(GL_VERSION).
This makes it currently impossible to run glslparsertest tests for
OpenGL ES when using version override.
Below is example when using MESA_GLES_VERSION_OVERRIDE=3.1.
Before:
"3.1 Mesa 11.1.0-devel (git-24a1a15)"
After:
"OpenGL ES 3.1 Mesa 11.1.0-devel (git-78042ff)"
v2: only include api prefix for OpenGL ES (Boyan Ding)
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
commit c8f5274b52682f4e1b767251b50f6191d8251079
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Thu Oct 15 08:47:09 2015 +0200
nir: Get the number of SSBOs and UBOs right
Before d31f98a272e429d and 56e2bdbca36a20 we had a sigle index space for UBOs
and SSBOs, so NumBufferInterfaceBlocks would contain the combined number of
blocks, not just one kind. This means that for shader programs using both
UBOs and SSBOs, we were setting num_ssbos and num_ubos to a larger number than
we should. Since the above commits we have separate index spaces for each
so we can just get the right numbers.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit f534f331ca354bcb138e2b8f6d6d80147ee4a186
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Thu Oct 15 08:48:03 2015 +0200
i965/vec4: Use the right number of UBOs
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 6f9ca3026693e061ee55fa6d5f16d9ec0e744b59
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Thu Oct 15 08:47:40 2015 +0200
i965/fs: use the right number of UBOs
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit ef7a5638290234a9d1f0574585174539e2c126eb
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Oct 15 16:28:17 2015 -0400
freedreno: add debug option to dirty state after draw
Similar to "dclear", "ddraw" will mark all state dirty after each draw.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 6206da736c84c4f7316ab586c886b4865fda8805
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Oct 15 16:22:23 2015 -0400
freedreno/a3xx: cache-flush is needed after MEM_WRITE
Otherwise the mem2gmem blit would see potentially bogus texture
coordinates. Fixes an issue that shows up with glamor.
CC: "11.0" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit fefffdc2b21c35f4a08a55103ec1932faafe5993
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Oct 15 13:30:24 2015 -0400
gallium/util: fix debug_get_flags_option on 32-bit harder
(yes, we want PRI?64, but we want the x version rather than the u
version)
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 7599f8b167321cb8adb2ba51a53163752b668532
Author: Chih-Wei Huang <cwhuang at android-x86.org>
Date: Thu Oct 15 23:46:32 2015 +0800
nv30: include the header of ffs prototype
It fixes a building error of the android 6.0 64-bit target.
Signed-off-by: Chih-Wei Huang <cwhuang at linux.org.tw>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org
commit d31005e3e5588b20760c774f14ac0ea80375a181
Author: Chih-Wei Huang <cwhuang at android-x86.org>
Date: Thu Oct 15 23:46:30 2015 +0800
nv50/ir: use C++11 standard std::unordered_map if possible
Note Android version before Lollipop is not supported.
Signed-off-by: Chih-Wei Huang <cwhuang at linux.org.tw>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org
commit 5f106153f55219d5092f9ba7c019316ea69baef4
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Oct 15 09:20:24 2015 -0700
nir/prog: Don't double-insert the fog-coord variable
nir_variable_create already inserts it in the right list for us so
inserting it again causes a linked list corruption.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit b705005584730cff75f5bbe057832d8b1106124a
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Oct 8 18:36:27 2015 -0700
nir/glsl: Use shader_prog->Name for naming the NIR shader
This has the better name to use. Aparently, sh->Name is usually 0.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Neil Roberts <neil at linux.intel.com>
commit eb893c220c8af9e7400973ce3eca41246379889b
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Oct 9 07:05:11 2015 -0700
nir: Add helpers for creating variables and adding them to lists
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 635daef76ede735d97e202446d6477b7d2cf2f86
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Oct 9 07:02:57 2015 -0700
nir/prog: Use nir_foreach_variable
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 5d954fd5cb4b35b896b90100956d45eaa30edacb
Author: Brian Paul <brianp at vmware.com>
Date: Wed Oct 14 09:53:53 2015 -0600
mesa: wrap a ridiculously long line in es1_conversion.c
Reviewed-by: Eric Anholt <eric at anholt.net>
commit d8c23d156d9b014a52d83d1a2eb051981b5203f3
Author: Brian Paul <brianp at vmware.com>
Date: Wed Oct 14 09:53:26 2015 -0600
mesa: add num_buffers() helper in blend.c
Reviewed-by: Eric Anholt <eric at anholt.net>
commit dfbd62e772d4373f4ab7553b556931085a70488a
Author: Brian Paul <brianp at vmware.com>
Date: Wed Oct 14 10:08:18 2015 -0600
mesa: optimize _UsesDualSrc blend flag setting
For glBlendFunc and glBlendFuncSeparate(), the _UsesDualSrc flag
will be the same for all buffers, so no need to compute it N times.
Reviewed-by: Eric Anholt <eric at anholt.net>
commit d21e17f48f8e155918de9420378a3b233e4ca98c
Author: Brian Paul <brianp at vmware.com>
Date: Wed Oct 14 09:34:39 2015 -0600
mesa: fix incorrect error string in _mesa_BlendEquationiARB()
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 1d751655012c7b8aafbeb90d02e5314a8eedc890
Author: Brian Paul <brianp at vmware.com>
Date: Wed Oct 14 09:35:53 2015 -0600
mesa: move validate_blend_factors() call after no-change check
A redundant call to glBlendFuncSeparateiARB() is more likely than getting
invalid values, so do the no-op check first.
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 34de3c4c1635a42c884da3321fc35ef07be34a6e
Author: Brian Paul <brianp at vmware.com>
Date: Wed Oct 14 09:45:36 2015 -0600
mesa: optimize no-change check in _mesa_BlendEquationSeparate()
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 2dfedf105d07e9a1f65f9bc76369cb33edf59cc9
Author: Brian Paul <brianp at vmware.com>
Date: Wed Oct 14 09:41:11 2015 -0600
mesa: optimize no-change check in _mesa_BlendEquation()
Same story as preceeding change to _mesa_BlendFuncSeparate().
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 6fd29e6c31e14e7b0f3c530798a1fc983eee17af
Author: Brian Paul <brianp at vmware.com>
Date: Wed Oct 14 09:31:41 2015 -0600
mesa: optimize no-change check in _mesa_BlendFuncSeparate()
Streamline the checking for no state change in _mesa_BlendFuncSeparate()
(and _mesa_BlendFunc()). If _BlendFuncPerBuffer is false, we only need
to check the 0th buffer state. Move argument validation after the no-op
check.
I'm looking at an app that issues about 1000 redundant glBlendFunc()
calls per frame!
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 083b3f5cb4c5bd701d6a371282d7dc8c4f5fcaa8
Author: Brian Paul <brianp at vmware.com>
Date: Wed Oct 14 09:10:19 2015 -0600
mesa: short-cut new_state == _NEW_LINE in _mesa_update_state_locked()
We can skip to the end of _mesa_update_state_locked() if only the
_NEW_LINE flag is set since none of the derived state depends on it
(just like _NEW_CURRENT_ATTRIB). Note that we still call the
ctx->Driver.UpdateState() function, of course.
v2: use bitmask-based test, per Eric.
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 0de5e0f3fb0f3671a3ecec6ab4473f9131ecd0ae
Author: Brian Paul <brianp at vmware.com>
Date: Wed Oct 14 09:08:50 2015 -0600
mesa: remove FLUSH_VERTICES() in _mesa_MatrixMode()
Changing the matrix mode alone has no effect on rendering and does
not need to trigger a flush or state validation.
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 67d8518a0e5a3df400a6e70de667d69e4b6ce9c5
Author: Chih-Wei Huang <cwhuang at android-x86.org>
Date: Mon Oct 12 23:36:59 2015 +0800
mesa: android: Fix the incorrect path of sse_minmax.c
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
Fixes: 669cfc267a1 (android: mesa: fix the path of the SSE4_1
optimisations)
Signed-off-by: Chih-Wei Huang <cwhuang at linux.org.tw>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 45f0392ceb463612ec2f31c52adedf5440fffc32
Author: Mauro Rossi <issor.oruam at gmail.com>
Date: Sun Oct 11 13:49:38 2015 +0200
i965: android: add the i965_compile_FILES sources to the driver
i965_compile_FILES are needed otherwise we'll error out as below:
target SharedLib: i915_dri (out/target/product/x86/obj/SHARED_LIBRARIES/i915_dri_intermediates/LINKED/i915_dri.so)
external/mesa/src/mesa/drivers/dri/i965/brw_ir_fs.h:181: error: undefined reference to 'fs_inst::~fs_inst()'
...
...
external/mesa/src/mesa/drivers/dri/i965/intel_screen.c:1484: error: undefined reference to 'brw_compiler_create'
collect2: error: ld returned 1 exit status
build/core/shared_library.mk:81: recipe for target 'out/target/product/x86/obj/SHARED_LIBRARIES/i965_dri_intermediates/LINKED/i965_dri.so' failed
make: *** [out/target/product/x86/obj/SHARED_LIBRARIES/i965_dri_intermediates/LINKED/i965_dri.so] Error 1
[Emil Velikov: tweak commit message]
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit bcb56c2c69dd1695d7828d831d71c957e7e497c6
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Tue Oct 13 11:26:09 2015 +0100
program: convert _mesa_init_gl_program() to take struct gl_program *
Rather than accepting a void pointer, only to down and up cast around
it, convert the function to take the base (struct gl_program) pointer.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 2034bdd46ce757a18fdb3498f6a0232db16522f3
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Oct 10 16:13:38 2015 +0100
nir: include nir_instr_set.h in the tarball
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
commit 8da9e154b7a2463369b32a10742af3a5695eb2ab
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Sat Jun 6 09:10:55 2015 +1000
glsl: Allow arrays of arrays in GLSL ES 3.10 and GLSL 4.30
V3: use a check_*_allowed style function for requirements checking
rather than has_* which doesn't encapsulate the error message
V2: add missing 's' to the extension name in error messages
and add decimal place in version string
Reviewed-by: Marta Lofstedt <marta.lofstedt at intel.com>
commit f22b7933e2e9c31b3730f5b1d9c060d2e1377d20
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Fri Oct 9 22:00:20 2015 +1100
glsl: allow for AoA in calculating offset to ubo start region
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit bb5aeb854915ba67abc56257f830d002c956439e
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Fri Oct 9 21:54:09 2015 +1100
glsl: build ubo name and indexing offset for AoA
V2: split out unrelated change as suggested by Samuel
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit 8cf1333b189b73dccdbccaca7e113f7b467982fa
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Tue Aug 25 14:15:25 2015 +1000
glsl: link uniform block arrays of arrays
This adds support for setting up the UniformBlock structures for AoA
and also adds support for resizing AoA blocks with a packed layout.
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit d9f1f2bbc6690e7ef85d79a857dbb64cf5fd1cd8
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Thu Jun 4 11:19:05 2015 +1000
glsl: Add AoA support when checking for non-const index
When checking for non-const indexing of interfaces
take into account arrays of arrays
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit 082b1ca2fe75a9b4c2936d4d918b5d0d4f0c6c50
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Mon Mar 16 15:31:11 2015 +1100
glsl: Add support for lowering interface block arrays of arrays
V2: make array processing functions static
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit 132b9e9dd97a2ab7d3be7945b3d990e94fd1513a
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Sun Jul 19 14:08:44 2015 +1000
glsl: add AoA support for an inteface with unsized array members
Add support for setting the max access of an unsized member
of an interface array of arrays.
For example ifc[j][k].foo[i] where foo is unsized.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit d1d05c0f85daf3445d9b4c9cebb3940e6a251fa6
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Thu Mar 12 19:52:47 2015 +1100
glsl: add AoA support for linking interface blocks with unsized members
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit dd89880dc0924162e751141f9388e5dba089d1c0
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Mon May 12 20:25:26 2014 +1000
glsl: avoid hitting assert for arrays of arrays
Also add TODO comment about adding proper support
Signed-off-by: Timothy Arceri <t_arceri at yahoo.com.au>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 2d7a98de18e4cdd69daa63b09b504d01ad4c9f50
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Sun Aug 30 21:08:22 2015 +1000
glsl: add AoA support for atomic counters
This marks all counters in an AoA as active.
For AoA all but the innermost array are treated as separate
counters/uniforms. The Nvidia binary also goes further and
finds inactive counters in the AoA, in future we should do
this too, however this gets things working for the time being.
This change also removes the use of UniformHash for atomic counters,
this avoids having to generate name strings used as hash keys.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 261a434996079b29a476a3c67e1e580cf3db76ba
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Fri Sep 18 22:51:40 2015 +1000
glsl: add std140 layout support for AoA
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 176e6930e6c24dfce7cc730faa2612d27689a4df
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Sat Jul 18 17:24:22 2015 +1000
i965: add arrays of arrays support for varyings
V2: get the correct vector elements value for outputs
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit be822b89ac81e1fa66dfa16d108bf1deb29d4db2
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Thu Sep 17 14:17:17 2015 +1000
glsl: calculate AoA uniform offset correctly for structs
This allows the correct offset to be calculated for use in indirect
indexing of samplers.
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit 410609c9688d3f6ad808d33928a7d9589a708a40
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Sat Jul 11 21:38:54 2015 +1000
glsl: remove dead code in a single pass
Currently only one ir assignment is removed for each var in a single
dead code optimisation pass. This means if a var has more than one
assignment, then it requires all the glsl optimisations to be run again
for each additional assignment to be removed.
Another pass is also required to remove the variable itself.
With this change all assignments and the variable are removed in a single
pass.
Some of the arrays of arrays conformance tests that were looping
through 8 dimensions ended up with a var with hundreds of assignments.
This change helps ES31-CTS.arrays_of_arrays.InteractionFunctionCalls1
go from around 3 min 20 sec -> 2 min
ES31-CTS.arrays_of_arrays.InteractionFunctionCalls2 went from
around 9 min 20 sec to 7 min 30 sec
I had difficulty getting the public shader-db to give a consistent result
with or without this change but the results seemed unchanged at between
15-20 seconds.
Thomas Helland measured change with shader-db on his machine from
approx 117 secs to 112 secs.
V3: Simplify freeing of list as suggested by Ian, and spelling fixes.
V2: Add assert to be sure references are counted before assignments.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Tested-By: Thomas Helland <thomashelland90 at gmail.com>
Tested-by: Ian Romanick <ian.d.romanick at intel.com>
commit d337da81f28d6a5a65d0a09f9b1ddf905dc7c3aa
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Tue Jun 24 07:43:05 2014 +1000
glsl: dont allow gl_PerVertex to be redeclared as an array of arrays
V3: move patch after fixes to ast for AoA and add const to helper
as suggested by Ian
V2: move single dimensional array detection into a helper
Signed-off-by: Timothy Arceri <t_arceri at yahoo.com.au>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit dea0af8f826ca9ad638a158fdaacb2a4436f11d7
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Thu Oct 15 14:35:41 2015 +1100
glsl: check that only the outermost array is unsized
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit 3129359ed7461b90fe6ea70641ec7a858dd656de
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Thu Oct 15 14:32:41 2015 +1100
glsl: allow AoA to be sized by initializer or constructor
V2: Split out unsized array validation to its own patch as
suggested by Samuel.
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit 296a7ea471fd327ab60d9723bd395e6b34dc9334
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Wed Jul 29 11:57:44 2015 +1000
glsl: add support for initialising sampler AoA
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit db280e951a1bcb2318240cb6db296b31abac37cd
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Sun Jul 5 15:18:10 2015 +1000
glsl: Add support for linking uniform arrays of arrays
V3: Fix setting of data.location for struct AoA UBO members
V2: Handle arrays of arrays in the same way structures are handled
The ARB_arrays_of_arrays spec doesn't give very many details on how
AoA uniforms are intended to be implemented. However in the
ARB_program_interface_query spec there are details that show AoA are
intended to be handled in a similar way to structs.
Issues 7 from the ARB_program_interface_query spec:
We define rules consistent with our enumeration rules for
other complex types. For existing one-dimensional arrays, we enumerate
a single entry if the array is an array of basic types, or separate
entries for each array element if the array is an array of structures.
We follow similar rules here. For a uniform array such as:
uniform vec4 a[5][4][3];
we enumerate twenty different entries ("a[0][0][0]" through
"a[4][3][0]"), each of which is treated as an array with three elements.
This is morally equivalent to what you'd get if you worked around the
limitation in current GLSL via:
struct ArrayBottom { vec4 c[3]; };
struct ArrayMid { ArrayBottom b[3]; };
uniform ArrayMid a[5];
which would enumerate "a[0].b[0].c[0]" through "a[4].b[3].c[0]".
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit ff31c243e38332999b617d479a0dca61b15bc1c6
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Oct 13 15:15:57 2015 -0700
i965: Don't hardcode FS in "validation failed!" message.
Instead, print "Scalar VS" or "Scalar FS". Otherwise it's really
confusing which stage is broken.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit a274eff9ffffaa7726e7e36f59c1051cd0dfa701
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Mon Oct 12 20:28:28 2015 -0700
glsl: Support uint index in lower_vector_insert
The ES31-CTS.compute_shader.pipeline-compute-chain test case generates
an unsigned index by using gl_LocalInvocationID.x and
gl_LocalInvocationID.y as array indices.
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit ab04adcf63cb4553c66b703645c2991340b5637d
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Mon Oct 12 20:22:14 2015 -0700
glsl: Support uint index in do_vec_index_to_cond_assign
The ES31-CTS.compute_shader.pipeline-compute-chain test case generates
an unsigned index by using gl_LocalInvocationID.x and
gl_LocalInvocationID.y as array indices.
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 0d1eef536bc744f5c4dcdf854ad6adfdfe4f4dcb
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Wed Oct 14 11:33:03 2015 -0700
i965/fs: Ignore compute shaders in brw_nir_lower_inputs
The commit shown below caused compute shaders to hit the unreachable
in the default of the switch block. Since compute shaders don't have
any inputs, we can make brw_nir_lower_inputs a no-op for CS.
commit 2953c3d76178d7589947e6ea1dbd902b7b02b3d4
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Aug 14 15:15:11 2015 -0700
i965/vs: Map scalar VS input locations properly; avoid tons of MOVs.
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 63728dac57c18df0f45bb2482f60188fac2d1efe
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Mon Oct 12 17:18:51 2015 -0700
i965/fs: Simplify FS in brw_nir_lower_inputs to only support scalar mode
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 9abbf65d0ae8bd3e1e50d4bdfdf0d80191ace9aa
Author: Brian Paul <brianp at vmware.com>
Date: Tue Oct 13 20:12:56 2015 -0600
mesa: remove unused functions in program.c
replace_registers() and adjust_param_indexes() were unused.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 9d4ce8073611355d94ec675500a9bc209790e86a
Author: Brian Paul <brianp at vmware.com>
Date: Tue Oct 13 09:34:53 2015 -0600
mesa: minor indentation fix in _mesa_BindTextureUnit()
commit 77eef8137056314c4d458f215a899e3eec42e910
Author: Brian Paul <brianp at vmware.com>
Date: Tue Oct 13 09:32:34 2015 -0600
mesa: remove unused texUnit local in _mesa_BindTextureUnit()
The texture unit is error-checked before this and the texUnit var
is unused, so remove it.
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 14f7ce42484c31a45fcb6aabdf503f7496a9a94c
Author: Krzysztof Sobiecki <sobkas at gmail.com>
Date: Wed Oct 14 10:03:00 2015 -0600
st/fbo: use pipe_surface_release instead of pipe_surface_reference
pipe_surface_reference have problems with deleted contexts,
so use of pipe_surface_release might be more appropriate.
Fixes Wasteland 2 Director's Cut crash on start.
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 93267887a06e760b4b20618523df5e8aa4e70307
Author: Marta Lofstedt <marta.lofstedt at intel.com>
Date: Wed Oct 14 13:35:32 2015 +0200
glsl: Enable split of lower UBOs and SSBO also for compute shaders
The split of Uniform blocks and shader storage block only loops
up to MESA_SHADER_FRAGMENT and igonres compute shaders.
This cause segfault when running the OpenGL ES 3.1 CTS tests
with GL_ARB_compute_shader enabled.
V2: Changed to use MESA_SHADER_STAGES instead of
MESA_SHADER_COMPUTE
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
Signed-off-by: Marta Lofstedt <marta.lofstedt at linux.intel.com>
commit 5423c1e855c65ae6f562895791aac982141266db
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Wed Oct 14 11:50:06 2015 +0100
glsl: Include util/strndup.h.
Fixes Windows builds.
Trivial.
commit ac257f1070add308004c5c79a8acfdef5a6778da
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Wed Oct 14 11:01:29 2015 +0300
glsl: calculate TOP_LEVEL_ARRAY_SIZE and STRIDE when adding resources
Patch moves existing calculation code from shader_query.cpp to happen
during program resource list creation.
No Piglit or CTS regressions were observed during testing.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit b76159b09617a07b9e3d53d64d31d4835702827f
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Tue Oct 13 14:17:49 2015 +0300
glsl: add top level array size and stride to gl_uniform_storage
Patch adds 2 new fields to gl_uniform_storage so that we don't need to
calculate these values during runtime shader queries. This is required by
upcoming changes to free GLSL IR after linking.
Patch moves 3 booleans inside structure so that structure size stays the
same after this change.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit d3f45888045c84b2bc382a34d169a0ede4774a24
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Fri Oct 9 14:41:21 2015 +0200
i965: Adapt SSBOs to work with their own separate index space
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 56e2bdbca36a20f2601d32830a7b4ef556803ebe
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Fri Oct 9 13:54:41 2015 +0200
glsl/lower_ubo_reference: lower UBOs and SSBOs to separate index spaces
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit d31f98a272e429d5782192919b7628494ad1adf3
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Thu Oct 1 10:17:30 2015 +0200
mesa: Add {Num}UniformBlocks and {Num}ShaderStorageBlocks to gl_shader{_program}
These arrays provide backends with separate index spaces for UBOS and SSBOs.
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 27dccf097d053b085c498a7bcab47197a5e83525
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Thu Oct 1 09:08:20 2015 +0200
mesa: Rename {Num}UniformBlocks to {Num}BufferInterfaceBlocks
Currently, these arrays in gl_shader and gl_shader_program hold both
UBOs and SSBOs, so this looks like a better name. We were already
using NumBufferInterfaceBlocks in gl_shader_program, so this makes
things more consistent as well.
In a later patch we will add {Num}UniformBlocks and
{Num}ShaderStorageBlocks which will contain only references to
UBOs and SSBOs respectively that will provide backends with
a separate index space for both types of objects.
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 9de651b261286f15ae000e4a698587b805b95d2b
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Mon Oct 5 11:42:43 2015 +0200
glsl: Fix variable_referenced() for vector_{extract,insert} expressions
We get these when we operate on vector variables with array accessors
(i.e. things like a[0] where 'a' is a vec4). When we call variable_referenced()
on these expressions we want to return a reference to 'a' instead of NULL.
This fixes a problem where we pass a[0] as the first argument to an atomic
SSBO function that expects a buffer variable. In order to check this, we use
variable_referenced(), but that is currently returning NULL in this case, since
the underlying rvalue is a vector_extract expression.
Tested-by: Markus Wick <markus at selfnet.de>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit baee16bf02eedc6a32381d79da6c7ac942f782ae
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Mon Sep 28 10:47:22 2015 +0200
nir: split SSBO min/max atomic instrinsics into signed/unsigned versions
NIR is typeless so this is the only way to keep track of the
type to select the proper atomic to use.
v2:
- Use imin,imax,umin,umax for the intrinsic names (Connor Abbott)
- Change message for unreachable paths (Michael Schellenberger)
Tested-by: Markus Wick <markus at selfnet.de>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit be800ef6d80fc43279780e652e611253428d7a78
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Tue Oct 13 11:59:59 2015 +0200
i965/vec4: fix indentation in vec4_visitor::calculate_live_intervals
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 9d2bbca98d2712f7bafe66cb3bc08859ff14133e
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Tue Oct 13 11:26:21 2015 +0200
i965/fs: Fix indentation in fs_live_variables::compute_start_end
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 4a168ad797af26b31c64e408fb5f84838bf37b4e
Author: Brian Paul <brianp at vmware.com>
Date: Mon Oct 12 14:50:17 2015 -0600
mesa: clean up comments for gl_current_attrib struct
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit a7b6e6192a2cb36a36aaf12153de2e4b2c6e1cef
Author: Brian Paul <brianp at vmware.com>
Date: Mon Oct 12 14:16:37 2015 -0600
vbo: make void vbo_exec_BeginVertices() static
Not called from any other file. Rename and move before use.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 84719ad9df5a48ef8c92461956abda1b20cdbefc
Author: Brian Paul <brianp at vmware.com>
Date: Mon Oct 12 11:01:23 2015 -0600
vbo: document vbo_exec_context fields
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit d65b029dc20a1680c1e0203c493720f7a03a803c
Author: Brian Paul <brianp at vmware.com>
Date: Mon Oct 12 10:58:49 2015 -0600
vbo: minor clean-ups for vbo_exec_fixup_vertex()
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 7f67bfaa7471ac297ec86be122f251b271cea2ca
Author: Brian Paul <brianp at vmware.com>
Date: Mon Oct 12 10:53:59 2015 -0600
vbo: add assertion in ATTR_UNION macro
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 3491ec5930b15d5417bdf17b2a70fedaada969f1
Author: Brian Paul <brianp at vmware.com>
Date: Mon Oct 12 10:52:58 2015 -0600
vbo: add comments, braces in ATTR_UNION() in vbo_exec_api.c
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit e729f36c0904de24978c11f4eac3d5b64de3deec
Author: Brian Paul <brianp at vmware.com>
Date: Mon Oct 12 10:47:26 2015 -0600
vbo: fix whitespace in vbo_exec_draw.c
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 8fbb72c2977f652b0790b0fcf5f87286549e39f0
Author: Brian Paul <brianp at vmware.com>
Date: Mon Oct 12 10:43:36 2015 -0600
vbo: move 'tmp' var initialization
Improve readability a bit.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit a1cbf85de0a0c06a95086ea52d2260343e1783c4
Author: Brian Paul <brianp at vmware.com>
Date: Mon Oct 12 10:43:11 2015 -0600
vbo: improve fprintf() formatting
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit a639bbf0987873a0214f0ef562755fa0130b1236
Author: Brian Paul <brianp at vmware.com>
Date: Mon Oct 12 09:55:57 2015 -0600
vbo: simplify vertex array initializations in vbo_context.c
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 20f31ae37c42b4c98e0a55ba6b2e57ad9d1c277b
Author: Brian Paul <brianp at vmware.com>
Date: Mon Oct 12 11:26:16 2015 -0600
vbo: get rid of needless NR_MAT_ATTRIBS constant
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit dd293d8aae324ac7b9d5297e33a1e732e1f3f4d3
Author: Brian Paul <brianp at vmware.com>
Date: Mon Oct 12 11:32:35 2015 -0600
vbo: fix incorrect switch statement in init_mat_currval()
The variable 'i' is a value in [0, MAT_ATTRIB_MAX-1] so subtracting
VERT_ATTRIB_GENERIC0 gave a bogus value and we executed the default
switch clause for all loop iterations.
This doesn't fix any known issues but was clearly incorrect.
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit c73c481c4a8fbe454cfd6a0014d25beb175c0a7f
Author: Brian Paul <brianp at vmware.com>
Date: Thu Oct 8 14:45:28 2015 -0600
mesa: pass caller name to create_textures()
Simpler than the dsa flag approach.
commit 6a506689db287ea41b3374bd3174a5da78b56d16
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Thu Oct 1 16:46:55 2015 +0200
glsl: fix matrix stride calculation for std430's row_major matrices with two columns
This is the result of applying several rules:
From OpenGL 4.3 spec, section 7.6.2.2 "Standard Uniform Block Layout":
"2. If the member is a two- or four-component vector with components
consuming N basic machine units, the base alignment is 2N or 4N,
respectively."
[...]
"4. If the member is an array of scalars or vectors, the base alignment
and array stride are set to match the base alignment of a single array
element, according to rules (1), (2), and (3), and rounded up to the
base alignment of a vec4."
[...]
"7. If the member is a row-major matrix with C columns and R rows, the
matrix is stored identically to an array of R row vectors with C
components each, according to rule (4)."
[...]
"When using the std430 storage layout, shader storage blocks will be
laid out in buffer storage identically to uniform and shader storage
blocks using the std140 layout, except that the base alignment and
stride of arrays of scalars and vectors in rule 4 and of structures in
rule 9 are not rounded up a multiple of the base alignment of a vec4."
In summary: vec2 has a base alignment of 2*N, a row-major mat2xY is
stored like an array of Y row vectors with 2 components each. Because
of std430 storage layout, the base alignment of the array of vectors
is not rounded up to vec4, so it is still 2*N.
Fixes 15 dEQP tests:
dEQP-GLES31.functional.ssbo.layout.single_basic_type.std430.row_major_lowp_mat2
dEQP-GLES31.functional.ssbo.layout.single_basic_type.std430.row_major_mediump_mat2
dEQP-GLES31.functional.ssbo.layout.single_basic_type.std430.row_major_highp_mat2
dEQP-GLES31.functional.ssbo.layout.single_basic_type.std430.row_major_lowp_mat2x3
dEQP-GLES31.functional.ssbo.layout.single_basic_type.std430.row_major_mediump_mat2x3
dEQP-GLES31.functional.ssbo.layout.single_basic_type.std430.row_major_highp_mat2x3
dEQP-GLES31.functional.ssbo.layout.single_basic_type.std430.row_major_lowp_mat2x4
dEQP-GLES31.functional.ssbo.layout.single_basic_type.std430.row_major_mediump_mat2x4
dEQP-GLES31.functional.ssbo.layout.single_basic_type.std430.row_major_highp_mat2x4
dEQP-GLES31.functional.ssbo.layout.single_basic_array.std430.row_major_mat2
dEQP-GLES31.functional.ssbo.layout.single_basic_array.std430.row_major_mat2x3
dEQP-GLES31.functional.ssbo.layout.single_basic_array.std430.row_major_mat2x4
dEQP-GLES31.functional.ssbo.layout.instance_array_basic_type.std430.row_major_mat2
dEQP-GLES31.functional.ssbo.layout.instance_array_basic_type.std430.row_major_mat2x3
dEQP-GLES31.functional.ssbo.layout.instance_array_basic_type.std430.row_major_mat2x4
v2:
- Add spec quote in both commit log and code (Timothy)
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Marta Lofstedt <marta.lofstedt at intel.com>
commit 685335639a982b398d305b8f314fc3857fcdbead
Author: Christian König <christian.koenig at amd.com>
Date: Sun Oct 11 20:13:25 2015 +0200
r600/vce: enable VCE for trinity/richland
Signed-off-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
commit 83de93309e38ce3af0c8f92ef54446db70b2cb38
Author: Christian König <christian.koenig at amd.com>
Date: Sun Oct 11 20:09:52 2015 +0200
r600/uvd: disable UVD tiling by default
It has only minimal advantages for post processing and doesn't work with VCE.
Signed-off-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
commit 24a1a157a694e961aaad611a8bf9d47ce8cf47f6
Author: Glenn Kennard <glenn.kennard at gmail.com>
Date: Wed Oct 7 17:17:34 2015 +0200
r600g: Enable GL_ARB_gpu_shader5 extension
Signed-off-by: Glenn Kennard <glenn.kennard at gmail.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 1befb7ed9856381cbfe874f361fae73b8e331bb4
Author: Glenn Kennard <glenn.kennard at gmail.com>
Date: Wed Oct 7 17:17:33 2015 +0200
r600g/sb: SB support for UBO indexing
Signed-off-by: Glenn Kennard <glenn.kennard at gmail.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 80c5062abfdef28e23615f44b214760449f6a582
Author: Glenn Kennard <glenn.kennard at gmail.com>
Date: Mon Sep 21 16:21:37 2015 +0200
r600g/sb: Support gs5 sampler indexing (v2)
[airlied: v2 cayman fixups]
Signed-off-by: Glenn Kennard <glenn.kennard at gmail.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit bd198b9f0a292a9ff4ffffec3a29bad23d62caba
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Aug 14 16:01:33 2015 -0700
i965/vs: Simplify fs_visitor's ATTR file.
Previously, ATTR was indexed by VERT_ATTRIB_* slots; at the end of
compilation, assign_vs_urb_setup() translated those into GRF units,
and converted ATTR to HW_REGs.
This patch moves the transslation earlier, making ATTR work in terms of
GRF units from the beginning. assign_vs_urb_setup() simply has to add
the number of payload registers and push constants to obtain the final
hardware GRF number. (We can't do this earlier as those values aren't
known.)
ATTR still supports reg_offset; however, it's simply added to reg.
It's not clear whether this is valuable or not.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit bf97f8d467ad1d485c2327da3f4fe1f9e1dc7379
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Oct 12 17:15:32 2015 -0400
nouveau: avoid double-emitting fence
The act of ensuring that there is space can cause a flush to happen,
which will emit the current screen fence. If that is the fence we're
trying to wait on, then it will have been emitted as a result of doing
the PUSH_SPACE. Don't attempt to emit it a second time.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Fixes: 8053c9208f (nouveau: avoid emitting new fences unnecessarily)
Cc: mesa-stable at lists.freedesktop.org
commit eeb444bc995c25224ce661c49dd5df6266e370d1
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Fri Oct 9 15:26:20 2015 -0700
glsl: Never allow the sequence operator anywhere in an array size
Fixes:
spec/glsl-1.20/compiler/structure-and-array-operations/array-size-sequence-in-parenthesis.vert
spec/glsl-es-1.00/compiler/array-sized-by-sequence-in-parenthesis.vert
spec/glsl-es-3.00/compiler/array-sized-by-sequence-in-parenthesis.vert
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 92635a84a7f464b827baa406578420dd6109e1a4
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Oct 7 14:26:29 2015 -0700
glsl: In later GLSL versions, sequence operator is cannot be a constant expression
Fixes:
ES3-CTS.shaders.negative.constant_sequence
spec/glsl-es-3.00/compiler/global-initializer/from-sequence.vert
spec/glsl-es-3.00/compiler/global-initializer/from-sequence.frag
v2: Fix a couple copy-and-paste mistake in the spec quotations.
Suggested by Matt.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
commit 05e4601c6b9ce456cc4a4c395677a22125d889d2
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Oct 7 13:03:53 2015 -0700
glsl: Add method to determine whether an expression contains the sequence operator
This will be used in the next patch to enforce some language sematics.
v2: Fix inverted logic in
ast_function_expression::has_sequence_subexpression. The method
originally had a different name and a different meaning. I fixed the
logic in ast_to_hir.cpp, but I only changed the names in
ast_function.cpp.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Marta Lofstedt <marta.lofstedt at intel.com> [v1]
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
commit bb329f2ff6e8bf8910a467b09f69a4d843689617
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Oct 6 17:05:55 2015 -0700
glsl: Restrict initializers for global variables to constant expression in ES
v2: Combine this check with the existing const and uniform checks. This
change depends on the previous patch (glsl: Only set
ir_variable::constant_value for const-decorated variables).
Fixes:
ES2-CTS.shaders.negative.initialize
ES3-CTS.shaders.negative.initialize
spec/glsl-es-1.00/compiler/global-initializer/from-attribute.vert
spec/glsl-es-1.00/compiler/global-initializer/from-uniform.vert
spec/glsl-es-1.00/compiler/global-initializer/from-uniform.frag
spec/glsl-es-1.00/compiler/global-initializer/from-global.vert
spec/glsl-es-1.00/compiler/global-initializer/from-global.frag
spec/glsl-es-1.00/compiler/global-initializer/from-varying.frag
spec/glsl-es-3.00/compiler/global-initializer/from-uniform.vert
spec/glsl-es-3.00/compiler/global-initializer/from-uniform.frag
spec/glsl-es-3.00/compiler/global-initializer/from-in.vert
spec/glsl-es-3.00/compiler/global-initializer/from-in.frag
spec/glsl-es-3.00/compiler/global-initializer/from-global.vert
spec/glsl-es-3.00/compiler/global-initializer/from-global.frag
Note: spec/glsl-es-3.00/compiler/global-initializer/from-sequence.*
still fail because the result of a sequence operator is still considered
to be a constant expression.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92304
Reviewed-by: Tapani Pälli <tapani.palli at intel.com> [v1]
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com> [v1]
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
commit 3524d6df33b1e3716992f9a555ffb0f7b1ae2f4f
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Oct 7 12:52:58 2015 -0700
glsl: Only set ir_variable::constant_value for const-decorated variables
Right now we're also setting for uniforms, and that doesn't seem to hurt
things. The next patch will make general global variables in GLSL ES,
and those definitely should not have constant_value set!
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
commit 5bc68f0f2b80b21997435742af74c49eb72891f7
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Thu Oct 8 17:32:41 2015 -0700
glsl: Use constant_initializer instead of constant_value to determine whether to keep an unused uniform
This even matches the comment "uniform initializers are precious, and
could get used by another stage."
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
commit 313372cae8e10e4b9a3de093d65c0a0d8954bb0d
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Thu Oct 8 14:24:25 2015 -0700
glsl/linker: Use constant_initializer instead of constant_value to initialize uniforms
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
commit 8acce5d53af44a3d1d05a26e69559fd35f835de4
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Thu Oct 8 11:13:00 2015 -0700
ff_fragment_shader: Use binding to set the sampler unit
This is the way layout(binding=xxx) works from GLSL. The old method
just happened to work (and significantly predated support for
layout(binding=xxx)), but future changes will break this.
v2: Remove some stale comments. Suggested by Matt and Chris Forbes.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
commit 43b07eb60faba1c65fc6f7a99087d051b00e9c0f
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Fri Oct 9 14:17:32 2015 -0700
glsl: Allow built-in functions as constant expressions in OpenGL ES 1.00
In d4a24745 (August 2012), Paul made functions calls not be constant
expressions in GLSL ES 1.00. Since this feature was added in desktop
GLSL 1.20, we believed that it was added in GLSL ES 3.00. That turns
out to be completely wrong. Built-in functions have always been allowed
as constant expressions in GLSL ES, and the patch adds the (many) spec
quotations to prove it.
While we never previously encountered this, a later patch enforces a GLSL
ES 1.00 rule that global variable initializers must be constant
expressions. Without this fix, several dEQP tests fail.
Fixes:
tests/spec/glsl-es-1.00/compiler/const-initializer/from-function.frag
tests/spec/glsl-es-1.00/compiler/const-initializer/from-function.vert
tests/spec/glsl-es-1.00/compiler/const-initializer/from-sequence-in-function.frag
tests/spec/glsl-es-1.00/compiler/const-initializer/from-sequence-in-function.vert
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Cc: "10.0 10.1 10.2 10.3 10.4 10.5 10.6 11.0" <mesa-stable at lists.freedesktop.org>
Yes, I know we don't maintain stable branches that far back, but that
*is* how far back this bug goes!
commit 45ed627d894aa4d51682e8b07e7234bbc6e7c02d
Author: Nicolai Hähnle <nhaehnle at gmail.com>
Date: Sun Oct 4 00:44:00 2015 +0200
u_vbuf: fix vb slot assignment for translated buffers
Vertex attributes of different categories (constant/per-instance/
per-vertex) go into different buffers for translation, and this is now
properly reflected in the vertex buffers passed to the driver.
Fixes e.g. piglit's point-vertex-id divisor test.
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 7a1143f29e477601f2b34b23d154edd5699352b1
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Wed Oct 7 09:28:43 2015 +0200
glsl: include variable name in error messages about initializers
Also fix style / wrong indentation along the way and make the messages
more uniform.
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit f09c229cc6db838ae595fb57f5e6386a035bdf42
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Wed Oct 7 09:21:36 2015 +0200
glsl: shader outputs cannot have initializers
GLSL Spec 4.20.8, 4.3 Storage Qualifiers:
"Initializers in global declarations may only be used in declarations of
global variables with no storage qualifier, with a const qualifier or
with a uniform qualifier."
We do this for input variables, but not for output variables. AMD and NVIDIA
proprietary drivers don't allow this either.
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 8281a7c5333d9b78aabf9ce3e9cc7077ccca9413
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Fri Oct 9 07:57:19 2015 +0200
i965: Fix unsafe pointer when dumping VS/FS IR
For the VS and FS stages that use ARB_vertex_program or
ARB_fragment_program we don't have a shader program, however,
when debuging is enabled, we call brw_dump_ir like this:
brw_dump_ir("vertex", prog, &vs->base, &vp->program.Base);
where vs will be NULL (since prog is NULL).
As pointed out by Chris, this &vs->base is not really a dereference,
it simply computes a new address that just happens to be 0x0 because
the offset of base in brw_shader is 0. Then brw_dump_ir will see a
NULL pointer and not do anything. This is why this does not crash at
the moment. However, this does not look very safe (it would crash
for any location of base that is not the first in brw_shader), so
patch it to prevent a potential (even if unlikely) problem in the
future.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit bcfaab38858fdcfbd8ffeaf6b0e3da8a726f02e6
Author: Dave Airlie <airlied at gmail.com>
Date: Wed Sep 30 17:48:38 2015 +1000
mesa/uniforms: fix get_uniform for doubles (v2)
The initial glGetUniformdv support didn't cover all the
casting cases that are apparantly legal, and cts seems to
test for them.
I've updated the piglit test to cover these cases now.
v2: fix indentation - it's all broken in this file (Ilia)
fix src/dst index tracking in light of fp64 support (Ilia)
cc: "11.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit c8083b1adc79073c0d6fc3bb87d6a18e41c779c4
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Thu Oct 8 16:51:50 2015 +0800
ilo: improve Gen8 defines based on its PRMs
commit 4642d53a03122e6d3214ed12cb327898917eb84e
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Oct 9 12:27:04 2015 -0700
i965/vec4: Implement b2f and b2i using negation.
Curro added this in commit 3ee2daf23d (before the vec4/NIR backend was
added) but it was missed in the new NIR backend. Add it there as well.
instructions in affected programs: 1857 -> 1810 (-2.53%)
helped: 15
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 9fe458335ffd35366ef0f4b741aad0cdb3503783
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Oct 10 04:29:39 2015 -0400
nv50,nvc0: don't base decisions on available pushbuf space
We still have to push everything out, might as well kick earlier and
flip pushbufs when we know we'll need it. This resolves some issues with
the new policy of making sure that we always leave a bit of room at the
end for fences.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Fixes: 47d11990b (nouveau: make sure there's always room to emit a fence)
Cc: mesa-stable at lists.freedesktop.org
commit 8053c9208f30964d89dc4e262fdf2148f0664696
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Oct 10 01:56:09 2015 -0400
nouveau: avoid emitting new fences unnecessarily
Right now we emit on every kick, but this is only necessary if something
will ever be able to observe that the fence completed. If there are no
refs, leave the fence alone and emit it another day.
This also happens to work around an issue for the kick handler -- a kick
can be a result of e.g. nouveau_bo_wait or explicit kick, or it can be
due to lack of space in the pushbuf. We want the emit to happen in the
current batch, so we want there to always be enough space. However an
explicit kick could take the reserved space for the implicitly-triggered
kick's fence emission if it happened right after. With the new mechanism,
hopefully there's no way to cause two fences to be emitted into the same
reserved space.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Fixes: 47d11990b (nouveau: make sure there's always room to emit a fence)
Cc: mesa-stable at lists.freedesktop.org
commit 06abd1a25e6388858b7f3a9f3ae245dc39b5ed15
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Sat Oct 10 21:59:27 2015 +0200
nvc0: make use of NVC0_COMPUTE_CLASS for GF110
In theory, GF110+ should also support NVC8_COMPUTE_CLASS but, in practice,
a ILLEGAL_CLASS dmesg fail appears when using it.
This fixes compute support and MP performance counters on GF110.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit a23bdd1fae196e91ebfbb4b0c7730652c63a91ea
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Mar 12 05:26:40 2015 -0700
i965/gs: Make MAX_GS_INPUT_VERTICES a #define in brw_context.h.
For scalar VS, I'll need this in brw_fs.cpp as well. It seems silly to
redeclare it in three places.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 2953c3d76178d7589947e6ea1dbd902b7b02b3d4
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Aug 14 15:15:11 2015 -0700
i965/vs: Map scalar VS input locations properly; avoid tons of MOVs.
Previously, we used nir_lower_io with the scalar type_size function,
which mapped VERT_ATTRIB_* locations to...some numbers. Then, in
fs_visitor::nir_setup_inputs(), we created temporaries indexed by
those numbers, and emitted MOVs from the actual ATTR registers to
those temporaries. Virtually all of these were copy propagated away,
but it's still ugly.
This patch reworks our input lowering to produce NIR lower_input
intrinsics that properly index into the ATTR file, so we can access
it directly.
No changes in shader-db.
v2: Fix unreachable() message (Ken), update commit message (Matt).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 6842ad79125371e7e61baac8e6b8a77583f79065
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Aug 25 17:09:40 2015 -0700
i965/vs: Fix a subtlety in the nr_attributes == 0 workaround.
nr_attributes is used to compute first_non_payload_grf, which is the
first register we're allowed to use for ordinary register allocation.
The hardware requires us to read at least one pair of values, but we're
completely free to overwrite that garbage register with whatever we like.
Instead of altering nr_attributes, we should alter urb_read_length, which
only affects the amount we ask the VF to read. This should save us a
register in trivial cases (which admittedly isn't very useful).
While we're at it, improve the explanation in the comments.
v2: Actually do what I said (caught by Ilia).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 031d3501322aee0a1474c7f2a9b79f9fa9947430
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Aug 25 16:59:12 2015 -0700
i965/vs: Unify URB entry size/read length calculations between backends.
Both the vec4 and scalar VS backends had virtually identical URB entry
size and read length calculations. We can move those up a level to
backend-agnostic code and reuse it for both.
Unfortunately, the backends need to know nr_attributes to compute
first_non_payload_grf, so I had to store that in prog_data. We could
use urb_read_length, but that's nr_attributes rounded up to a multiple
of two, so doing so would waste a register in some cases.
There's more code to be removed in the vec4 backend, but that will
come in a follow-on patch.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit a4e988f4814d80b27102c48020c4338a6d86c6da
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Oct 5 16:21:10 2015 -0700
i965/cfg: Fix cfg_t::dump() when a block has no immediate dominator.
Switch statements introduce a bogus loop with an unconditional break at
the end of the loop, just before the while...so the while is unreachable
and has no immediate dominator.
v2: With less exuberance
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 2496cfd771cff250bce5c53ca9d79dbf64d7cbcf
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Oct 10 17:09:00 2015 +0100
docs: add news item and link release notes for 11.0.3
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
commit 55a8f072ead8fe948347c90e28deba00953b1dad
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Oct 10 17:02:43 2015 +0100
docs: add sha256 checksums for 11.0.3
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
(cherry picked from commit b4bfea0094d0037b1f66f3437e44e333f2f0c3f6)
commit 8337a31bcc2865dfa1c4b0e0cf16294e0f7e4bf5
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Oct 10 16:21:58 2015 +0100
docs: add release notes for 11.0.3
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
(cherry picked from commit 914966befcd57764941405707d8f57d3e7e7f768)
commit 82b324c24bc28ae99a6110706c85460b71d26077
Author: Chad Versace <chad.versace at intel.com>
Date: Thu Oct 8 12:21:19 2015 -0700
i965/gen8: Remove gen<8 checks in gen8 code
Some assertions in gen8_surface_state.c checked for gen < 8.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 8a0c85b25853decb4a110b6d36d79c4f095d437b
Author: Chad Versace <chad.versace at intel.com>
Date: Thu Oct 8 12:06:24 2015 -0700
i965/gen9: Enable rep clears on gen9
The (gen < 9) check in brw_clear() was too broad. It disabled all types
of fast color clears:
a. singlesample rep clears
b. singlesample MCS fast clears
c. multisample MCS fast clears
The MCS clears are still buggy, but the rep clear works well. So let's
enable it.
Reviewed-by: Neil Roberts <neil at linux.intel.com>
commit dcd59a9e322edeea74187bcad65a8e56c0bfaaa2
Author: Chad Versace <chad.versace at intel.com>
Date: Thu Oct 8 11:53:08 2015 -0700
i965/gen9: Disable MCS for 1x color surfaces
Fast color clears are disabled for gen9 (see the checks in
brw_meta_fast_clear), so there is no reason to allocate the MCS and
track its clear/resolve state.
Reviewed-by: Neil Roberts <neil at linux.intel.com>
commit 4c4ba5a8c32c0a58b5874bdb4b42cb12e6b1c2f5
Author: Roland Scheidegger <sroland at vmware.com>
Date: Fri Oct 9 23:12:14 2015 +0200
tgsi: (trivial) kill c99-ism.
commit d695c676ea61f48f121969462ece708b739a02c0
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Oct 5 22:13:34 2015 +0200
program: remove _mesa_init_*_program wrappers
They didn't do anything useful.
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 092f0427dcc15e36666f24c817957727632ed377
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Oct 5 21:42:42 2015 +0200
program: remove other unused functions
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 5042a3eef8d4e4314d0463b83d267875fd3dd910
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Oct 5 21:41:03 2015 +0200
program: remove unused cloning and combining functions
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit c947a3a4c4fbd210fd19a78d7b07ccfdd6f03812
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Oct 5 21:39:17 2015 +0200
program: remove unused function _mesa_find_line_column
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit ee01942eb595b05aff47b4fdcd358508f2d6f14c
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Oct 5 22:46:44 2015 +0200
st/mesa: release the glsl_to_tgsi visitor after translation
Reviewed-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
Tested-by: Brian Paul <brianp at vmware.com>
commit e5073e8d0c1ea98c7e5cfff8fe69cd779bc129d9
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Oct 5 03:47:44 2015 +0200
st/mesa: translate tessellation shaders into TGSI when we get them
Reviewed-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
Tested-by: Brian Paul <brianp at vmware.com>
commit 897177020bb702cd18eafcc1d8c4e7f502a8a65d
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Oct 5 03:26:48 2015 +0200
st/mesa: translate geometry shaders into TGSI when we get them
Reviewed-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
Tested-by: Brian Paul <brianp at vmware.com>
commit a907b5dd162b7911b8c21f6d54837831bc078059
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Oct 5 03:26:48 2015 +0200
st/mesa: translate fragment shaders into TGSI when we get them
Reviewed-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
Tested-by: Brian Paul <brianp at vmware.com>
commit 46021ace514cf2ba91733dfcfd258073b90c0354
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Oct 5 02:47:37 2015 +0200
st/mesa: translate vertex shaders into TGSI when we get them
The translate functions is split into two:
- translation to TGSI
- creating the variant (TGSI transformations only)
Reviewed-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
Tested-by: Brian Paul <brianp at vmware.com>
commit de6a004035f3de5879648f8afb4670ae82f4ad02
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Oct 5 01:22:20 2015 +0200
st/mesa: fix glDrawPixels with a texture
The samplers for DrawPixels data and the pixel map are assigned to slots
which don't overlap with the existing sampler slots.
The texture coordinates for the user texture are uploaded as a constant.
Reviewed-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
Tested-by: Brian Paul <brianp at vmware.com>
commit f15bb3e633d577fe6d8d7bc2c64497c6ac4c2021
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Oct 4 02:38:55 2015 +0200
st/mesa: implement DrawPixels shader transformation using tgsi_transform_shader
Reviewed-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
Tested-by: Brian Paul <brianp at vmware.com>
commit b55b986dc9c89a3a4fb3956dcd269216f59b06ee
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Oct 4 18:23:33 2015 +0200
st/mesa: make Z/S drawpix shaders independent of variants, don't use Mesa IR v2
- there is no connection to user fragment shaders, so having these as
shader variants makes no sense
- don't use Mesa IR, use TGSI
- don't create gl_fragment_program, just create the shader CSO
v2: generate exactly the same shader as before to fix llvmpipe
Reviewed-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
Tested-by: Brian Paul <brianp at vmware.com>
commit f4ec81032bb9c1460794d3d843d0ffe47a181291
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Oct 4 02:38:55 2015 +0200
st/mesa: implement glBitmap shader transformation using tgsi_transform_shader
Reviewed-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
Tested-by: Brian Paul <brianp at vmware.com>
commit 3eedb633710733b38f612bdd5b2b490a7f854c9e
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Oct 4 01:01:16 2015 +0200
st/mesa: remove old emulation for VS and FS variants
Reviewed-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
Tested-by: Brian Paul <brianp at vmware.com>
commit c04e91a0e9abb424cb68c7e310ca9e5adf7f7be8
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Oct 4 00:33:11 2015 +0200
st/mesa: use TGSI utility to emulate features for FS variants
Reviewed-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
Tested-by: Brian Paul <brianp at vmware.com>
commit 941721ee2a90811b225db3241e280ea4ab27ea40
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Oct 4 00:33:11 2015 +0200
st/mesa: use TGSI utility to emulate features for VS variants
Reviewed-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
Tested-by: Brian Paul <brianp at vmware.com>
commit 4bbe418b4b35039e72b72bd9dff1ebdd96014d5f
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Oct 3 22:44:30 2015 +0200
st/mesa: decrease the size of st_vertex_program
The other variables can't be moved.
Reviewed-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
Tested-by: Brian Paul <brianp at vmware.com>
commit 4a21edf067b3fdcc58d9df5cbdcd04430b8077f3
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Oct 3 22:35:22 2015 +0200
st/mesa: inline st_prepare_vertex_program
No other shader stage has a "prepare" function.
This will allow removing some variables from st_vertex_program.
Also, prepare_fragment_program was a dead prototype.
Reviewed-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
Tested-by: Brian Paul <brianp at vmware.com>
commit c80c19a9d550745b68ce1df5f6c73e89a41514fa
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Oct 5 00:08:30 2015 +0200
tgsi/scan: add info about declared samplers (v2)
v2: get it from declarations, not instructions
commit 417927ebded4c6f4cee20c7e07a69c666a3f17a8
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Oct 4 00:02:31 2015 +0200
tgsi: add a utility for emulating some GL features
st/mesa will use this, but drivers can use it too.
Reviewed-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
Tested-by: Brian Paul <brianp at vmware.com>
commit 9ea2a86809577cac5006a2bc4fad29fed9cb3ccc
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Oct 5 03:02:42 2015 +0200
mesa: call ProgramStringNotify for fixed-function vertex programs
Drivers weren't notified about this at all.
This allows disabling on-demand compilation in drivers.
Reviewed-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
Tested-by: Brian Paul <brianp at vmware.com>
commit c9b982b72d443b138cfbded2f40350771c0bb321
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Oct 8 18:19:00 2015 -0400
glsl: move shader_enums into nir
First step towards inverting the dependency between glsl and nir (so nir
can be used without glsl). Also solves this issue with 'make distclean'
Making distclean in mesa
make[2]: Entering directory '/mnt/sdb1/Src64/Mesa-git/mesa/src/mesa'
Makefile:2486: ../glsl/.deps/shader_enums.Plo: No such file or directory
make[2]: *** No rule to make target '../glsl/.deps/shader_enums.Plo'. Stop.
make[2]: Leaving directory '/mnt/sdb1/Src64/Mesa-git/mesa/src/mesa'
Makefile:684: recipe for target 'distclean-recursive' failed
make[1]: *** [distclean-recursive] Error 1
make[1]: Leaving directory '/mnt/sdb1/Src64/Mesa-git/mesa/src'
Makefile:615: recipe for target 'distclean-recursive' failed
make: *** [distclean-recursive] Error 1
Reported-by: Andy Furniss <adf.lists at gmail.com>
Reviewed-by: Emil Velikov <emil.velikov at collabora.com>
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 7e441bf025cf8c5d088430d546acb4c0ed58d27b
Author: Francisco Jerez <currojerez at riseup.net>
Date: Sat Aug 29 17:03:08 2015 +0300
mesa: Get rid of texture-dependent image unit derived state.
The point is to avoid having to re-validate all image units when
_NEW_TEXTURE is flagged, which can be expensive if the driver exposes
a large number of image units. This has been reported to fix a 36%
performance regression in the Synmark2 Multithread benchmark on the
i965 driver which exposes 192 image units.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91788
Reported-by: Wendy Wang <wendy.wang at intel.com>
Tested-by: Ye Tian <yex.tian at intel.com>
CC: "11.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 2d97a78b37ddf325d90e056f5eefee0548092530
Author: Francisco Jerez <currojerez at riseup.net>
Date: Sat Aug 29 17:01:11 2015 +0300
i965: Use _mesa_is_image_unit_valid() instead of gl_image_unit::_Valid.
gl_image_unit::_Valid will be removed in a future commit.
Tested-by: Ye Tian <yex.tian at intel.com>
CC: "11.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 25d3338be37ddbfe676716034ec5f29e27323704
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Sep 3 16:12:59 2015 +0300
mesa: Skip redundant texture completeness checking during image validation.
The call to _mesa_test_texobj_completeness() is unnecessary if the
texture is already known to be complete. If the texture object is
dirtied in the meantime _BaseComplete and _MipmapComplete will be
reset to false. _mesa_is_image_unit_valid() will start to be called
more frequently in a future commit, so it seems desirable to avoid the
unnecessary work.
Tested-by: Ye Tian <yex.tian at intel.com>
CC: "11.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 5152db415f4047569822d648fda09bdde4171d6d
Author: Francisco Jerez <currojerez at riseup.net>
Date: Sat Aug 29 16:34:50 2015 +0300
mesa: Expose function to calculate whether a shader image unit is valid.
A future commit will remove all texture object-dependent derived state
from the image unit struct to make validation unnecessary on texture
state changes. Instead of checking gl_image_unit::_Valid drivers will
be required to call this function when needed to find out whether an
image unit is in a valid state and whether access from the shader is
allowed.
Tested-by: Ye Tian <yex.tian at intel.com>
CC: "11.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 5346c1167064d6429c6338974c6342f8346fd34b
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Aug 13 15:02:05 2015 +0300
i965: Don't tell the hardware about our UAV access.
The hardware documentation relating to the UAV HW-assisted coherency
mechanism and UAV access enable bits is scarce and sometimes
contradictory, and there's quite some guesswork behind this commit, so
let me summarize the background first: HSW and later hardware have
infrastructure to support a stricter form of data coherency between
shader invocations from separate primitives. The mechanism is
controlled by the "Accesses UAV" bits on 3DSTATE_VS, _HS, _DS, _GS and
_PS (or _PS_EXTRA on BDW+), and the "UAV Coherency Required" bit on
the 3DPRIMITIVE command.
Regardless of whether "UAV Coherency Required" is set, the hardware
fixed-function units will increment a per-stage semaphore for each
request received if "Accesses UAV" is set for the same or any lower
stage. An implicit DC flush is emitted by the lowermost stage with
"Accesses UAV" set once it's done processing the request, this also
happens regardless of the value of "UAV Coherency Required". The
completion of the DC flush will cause the same stage and all previous
ones to decrement the semaphore, marking the UAV accesses for the
primitive as coherent with L3.
The "UAV Coherency Required" 3DPRIMITIVE bit will cause a pipeline
stall before any threads are dispatched for the first FF stage with
"Accesses UAV" set until the semaphore is cleared for the same stage.
Effectively this guarantees that UAV memory accesses performed by
previous primitives from any stage will be strictly ordered (and
thanks to the implicit DC flush visible in memory) with UAV accesses
from the following primitives.
None of this is required by the usual image, atomic counter and SSBO
GL APIs which have very relaxed cross-primitive coherency and ordering
requirements, so we don't actually ever set the "UAV Coherency
Required" bit -- Ordering with respect to shader invocations from
previous stages on the same primitive where there is a data dependency
is of course already guaranteed as the spec requires, regardless of
this mechanism being enabled. We do set the "Accesses UAV" bits
though since my commit ac7664e493655e290783c23a0412b9c70936da50 (which
this patch partially reverts), mainly because of comments like the
following from the BDW PRM:
> 3DSTATE_GS
>[...]
> 12 Accesses UAV
> Format: Enable
> This field must be set when GS has a UAV access.
There are similar comments in the documentation for the other
3DSTATE_*S commands. The "must" part is misleading and unjustified
AFAIK. Most of the "Accesses UAV" bits don't seem to have any side
effects other than the implicit DC flushes and the related
book-keeping in anticipation for a subsequent primitive with "UAV
Coherency Required" set, so in most cases they are unnecessary and may
incur a performance penalty. There is an exception though. On Gen8+
the PS_EXTRA UAV access bit influences the calculation of the PS
UAV-only and ThreadDispatchEnable signals which on previous
generations were set explicitly by the driver, so we cannot always
avoid enabling it on the PS stage.
The primary motivation for this change is that in fact the hardware
coherency mechanism is buggy and will cause a rather non-deterministic
hang on Gen8 when VS is the only stage with "Accesses UAV" set and the
processing of a request terminates immediately after the implicit DC
flush is sent for a previous primitive with no additional vertices
being emitted for the second primitive, what will cause the hardware
to skip sending a second DC flush and cause the VS to stall
indefinitely waiting for a response from the DC (BDWGFX HSD 1912017).
This hardware bug can be reproduced on current master with the
spec at arb_shader_image_load_store@host-mem-barrier at Indirect/RaW piglit
subtest (if you have the patience to run it a few dozen times).
The proposed workaround is to insert CS STALLs speculatively between
3DPRIMITIVE commands when "Accesses UAV" is enabled for the VS stage
only. Because this would affect one of the hottest paths in the
driver and likely decrease performance even further due to the
unnecessary serialization, and because we don't actually need the
implicit DC flushes, it seems better to just disable them.
Cc: 11.0 <mesa-stable at lists.freedesktop.org>
commit bb59ba8634e3e5e3949103c6013918b8a4953111
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Thu Sep 24 02:18:07 2015 -0400
nir/instr_set: remove unnecessary check in nir_instrs_equal()
This was originally added to nir_instrs_equal() instead of
nir_instr_can_cse() incorrectly, but this was fixed when moving to the
instruction set API (as it had to be, otherwise hashing wouldn't work).
Now, this is dead code since instr_can_rewrite() will only return true
for texture instructions that use an index, so we can turn the check into
an assert. This also means that now nir_instrs_equal(instr, instr) will
always return true unless it assert-fails.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Signed-off-by: Connor Abbott <cwabbott0 at gmail.com>
commit bf5f931aee35e8448a6560545d86deb35f0639b3
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Thu Sep 24 02:10:13 2015 -0400
nir: make nir_instrs_equal() static
This was previously tied to CSE, since it would only work for
instructions where nir_can_cse() (now instr_can_rewrite()) returned
true. Now that CSE uses the instruction set abstraction which only uses
this internally, we can make it local to nir_instr_set.c.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Signed-off-by: Connor Abbott <cwabbott0 at gmail.com>
commit e8308d0523f7dc78b34099cfe2c3d3daedb27d4c
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Fri May 22 00:41:45 2015 -0400
nir/cse: use the instruction set API
This replaces an O(n^2) algorithm with an O(n) one, while allowing us to
import most of the infrastructure required for GVN. The idea is to walk
the dominance tree depth-first, similar when converting to SSA, and
remove the instructions from the set when we're done visiting the
sub-tree of the dominance tree so that the only instructions in the set
are the instructions that dominate the current block.
No piglit regressions. No shader-db changes.
Compilation time for full shader-db:
Difference at 95.0% confidence
-35.826 +/- 2.16018
-6.2852% +/- 0.378975%
(Student's t, pooled s = 3.37504)
v2:
- rebase on start_block removal
- remove useless state struct
- change commit message
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Signed-off-by: Connor Abbott <cwabbott0 at gmail.com>
commit 523a28d3fe0dd371ae01b7353f263a6541480d89
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Thu Sep 24 01:57:04 2015 -0400
nir: add an instruction set API
This will replace direct usage of nir_instrs_equal() in the CSE pass,
which reduces an O(n^2) algorithm with an effectively O(n) one. It'll
also be useful for implementing GVN on top of GCM.
v2:
- Add texture support.
- Add more comments.
- Rename instr_can_hash() to instr_can_rewrite() since it's really more
about whether its uses can be rewritten, and it's implicitly used by
nir_instrs_equal() as well.
- Rename nir_instr_set_add() to nir_instr_set_add_or_rewrite() (Jason).
- Make the HASH() macro less magical (Topi).
- Rewrite the commit message.
v3:
- For sorting phi sources, use a VLA, store pointers to the sources, and
compare the predecessor pointer directly (Jason).
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Signed-off-by: Connor Abbott <cwabbott0 at gmail.com>
commit 005c2efb7b755ac5887dc5938baa7d95a50fe853
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Thu Sep 24 01:05:15 2015 -0400
nir: constify instruction comparison functions
v2: rebase, don't constify nir_srcs_equal() as it's pass-by-value
anyways
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Signed-off-by: Connor Abbott <cwabbott0 at gmail.com>
commit d6bc35934f3d1150a1da0edfb0746cd0ae8bd63b
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Tue Mar 17 01:03:28 2015 -0400
nir: constify nir_ssa_alu_instr_src_components()
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Signed-off-by: Connor Abbott <cwabbott0 at gmail.com>
commit 20d6d812dc9d35cb082142ac6c9744971692797e
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Thu Sep 24 00:54:52 2015 -0400
nir: split out instruction comparison functions
Right now nir_instrs_equal() is tied pretty tightly to CSE, but we're
going to introduce the idea of an instruction set and tie it to that
instead. In anticipation of that, move this into its own file where
we'll add the rest of the instruction set implementation later.
v2: Rebase on texture support.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Signed-off-by: Connor Abbott <cwabbott0 at gmail.com>
commit da361acd1c899d533caec6cae5a336f6ab35e076
Author: Neil Roberts <neil at linux.intel.com>
Date: Fri Jul 17 14:40:03 2015 +0100
i965/fs: Handle non-const sample number in interpolateAtSample
If a non-const sample number is given to interpolateAtSample it will
now generate an indirect send message with the sample ID similar to
how non-const sampler array indexing works. Previously non-const
values were ignored and instead it ended up using a constant 0 value.
The generator will try to determine if the sample ID is dynamically
uniform via nir_src_is_dynamically_uniform. If not it will query the
pixel interpolator in a loop, once for each different live sample
number. The next live sample number is found using emit_uniformize. If
multiple live channels have the same sample number then they will be
handled in a single iteration of the loop. The loop is necessary
because the indirect send message doesn't seem to have a way to
specify a different value for each fragment.
This fixes the following two Piglit tests:
arb_gpu_shader5-interpolateAtSample-nonconst
arb_gpu_shader5-interpolateAtSample-dynamically-nonuniform
v2: Handle dynamically non-uniform sample ids.
v3: Remove the BREAK instruction and predicate the WHILE directly.
Make the tokens arrays const. (Matt Turner)
v4: Iterate over the live channels instead of each possible sample
number.
v5: Don't special case immediate values in
brw_pixel_interpolator_query. Make a better wrapper for the
function to set up the PI send instruction. Ensure that the SHL
instructions are scalar. (Francisco Jerez).
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 728d7bc85f1f101875349690bf1637037a5a1817
Author: Neil Roberts <neil at linux.intel.com>
Date: Mon Oct 5 13:50:56 2015 +0200
i965: Add a second successor to BRW_OPCODE_WHILE
It is possible to directly predicate the WHILE instruction. In this
case there will be a second successor block because the execution can
resume from the instruction after the loop. This will be used in a
subsequent patch.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 886d46b0897182e489e03f7302a575b54004faca
Author: Neil Roberts <neil at linux.intel.com>
Date: Thu Jul 30 12:10:08 2015 +0100
nir: Add a function to determine if a source is dynamically uniform
Adds nir_src_is_dynamically_uniform which returns true if the source
is known to be dynamically uniform. This will be used in a later patch
to add a workaround for cases that only work with dynamically uniform
sources. Note that the function is not definitive, it can return false
negatives (but not false positives). Currently it only detects
constants and uniform accesses. It could easily be extended to include
more cases.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 7129cbf5f4acaa86512c0dd6c127b8fb617fb441
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Sun Oct 4 23:43:20 2015 +0200
nvc0: move HW SM queries to nvc0_query_hw_sm.c/h files
Global performance counters (PCOUNTER) will be added to
nvc0_query_hw_pm.c/h files.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
commit 224fec05eac136d734e6ae06f6aab44d5ba640df
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Sun Oct 4 18:28:55 2015 +0200
nvc0: move HW queries to nvc0_query_hw.c/h files
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
commit 77b6990d14e6a97eb3928c445f3524494da36ad8
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Sun Oct 4 16:01:51 2015 +0200
nvc0: move SW queries to nvc0_query_sw.c/h files
Loosely based on freedreno driver.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
commit 0678530b9e60479f33eabb62f96a40af46edd714
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Sun Oct 4 17:43:15 2015 +0200
nvc0: move nvc0_so_target_save_offset() to its correct location
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
commit 0644196ab13c769570e5e2dcd738ebe5deca5754
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Sun May 17 16:46:54 2015 +0200
nvc0: add a header file for nvc0_query
This will allow to split SW and HW queries in an upcoming patch.
While we are at it, make use of nvc0_query struct instead of pipe_query.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
commit 3da58730eeb51d9490045260e4848ba14bf9bb65
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Mon Oct 5 13:14:26 2015 +0200
main: fix length of values written to glGetProgramResourceiv() for ACTIVE_VARIABLES
Return the number of values written.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
commit d0992fa15a4bfaff59de50e6084a0a14882d3bdb
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Thu Oct 1 14:46:01 2015 +0200
main: buffer array variables can have array size of 0 if they are unsized
From ARB_program_query_interface:
For the property ARRAY_SIZE, a single integer identifying the number of
active array elements of an active variable is written to <params>. The
array size returned is in units of the type associated with the property
TYPE. For active variables not corresponding to an array of basic types,
the value one is written to <params>. If the variable is a shader
storage block member in an array with no declared size, the value zero
is written to <params>.
v2:
- Unsized arrays of arrays have an array size different than zero
v3:
- Arrays and unsized arrays will have an array_stride > 0. Use it
instead of is_unsized_array flag (Timothy).
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
commit 66ca8e6632b2623425f848b9efc16edbed56f306
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Thu Oct 1 15:05:00 2015 +0200
main: consider that unsized arrays have at least one active element
From ARB_shader_storage_buffer_object:
"When using the ARB_program_interface_query extension to enumerate the
set of active buffer variables, only the first element of arrays (sized
or unsized) will be enumerated"
_mesa_program_resource_array_size() is used when getting the name (and
name length) of the active variables. When it is an unsized array,
we want to indicate it has one active element so the returned name
would have "[0]" at the end.
v2:
- Use array_stride > 0 and array_elements == 0 to detect unsized
arrays. Because of that, we don't need is_unsized_array flag
(Timothy)
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
commit 77c0b64ce335c7013de5da3b9ac497cb400ef8ce
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Thu Oct 1 13:13:19 2015 +0200
main: fix TOP_LEVEL_ARRAY_SIZE and TOP_LEVEL_ARRAY_STRIDE
When the active variable is an array which is already a top-level
shader storage block member, don't return its array size and stride
when querying TOP_LEVEL_ARRAY_SIZE and TOP_LEVEL_ARRAY_STRIDE
respectively.
Fixes the following 12 dEQP-GLES31 tests:
dEQP-GLES31.functional.ssbo.layout.single_basic_array.shared.mat3x4
dEQP-GLES31.functional.ssbo.layout.single_basic_array.shared.row_major_mat3x4
dEQP-GLES31.functional.ssbo.layout.single_basic_array.shared.column_major_mat3x4
dEQP-GLES31.functional.ssbo.layout.single_basic_array.packed.mat3x4
dEQP-GLES31.functional.ssbo.layout.single_basic_array.packed.row_major_mat3x4
dEQP-GLES31.functional.ssbo.layout.single_basic_array.packed.column_major_mat3x4
dEQP-GLES31.functional.ssbo.layout.single_basic_array.std140.mat3x4
dEQP-GLES31.functional.ssbo.layout.single_basic_array.std140.row_major_mat3x4
dEQP-GLES31.functional.ssbo.layout.single_basic_array.std140.column_major_mat3x4
dEQP-GLES31.functional.ssbo.layout.single_basic_array.std430.mat3x4
dEQP-GLES31.functional.ssbo.layout.single_basic_array.std430.row_major_mat3x4
dEQP-GLES31.functional.ssbo.layout.single_basic_array.std430.column_major_mat3x4
v2:
- Fix check when the shader storage block is instanced
- Write auxiliary function to do the check.
v3:
- Check if full_instanced_name is NULL just after allocation (Ilia)
- Remove () from one strcmp() in the if statement (Ilia)
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Tested-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 5be9bf2746370ecb180536eb2e5e48391b224dec
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Fri Oct 2 08:43:51 2015 +0200
main: fix goto in program_resource_top_level_array_stride
Use found_top_level_array_stride instead of found_top_level_array_size.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit d8d0e4a81e42678cc8c8b876dfee24d5c2f4ba38
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Thu Oct 8 09:43:41 2015 +0300
mesa: add GL_UNSIGNED_INT_24_8 to _mesa_pack_depth_span
Patch adds missing type (used with NV_read_depth) so that it gets
handled correctly. This fixes errors seen with following CTS test:
ES3-CTS.gtf.GL3Tests.packed_pixels.packed_pixels
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
commit 7d7dd1871174905dfdd3ca874a09d9d7837ac743
Author: Brian Paul <brianp at vmware.com>
Date: Mon Oct 5 08:14:56 2015 -0600
mesa,meta: move gl_texture_object::TargetIndex initializations
Before, we were unconditionally assigning the TargetIndex field in
_mesa_BindTexture(), even if it was already set properly. Now we
initialize TargetIndex wherever we initialize the Target field, in
_mesa_initialize_texture_object(), finish_texture_init(), etc.
v2: also update the meta_copy_image code. In make_view() the
view_tex_obj->Target field was set, but not the TargetIndex field.
Also, remove a second, redundant assignment to view_tex_obj->Target.
Add sanity check assertions too.
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Tested-by: Mark Janes <mark.a.janes at intel.com>
commit d61f492aba354283933b5d84e3daacc45a836141
Author: Brian Paul <brianp at vmware.com>
Date: Sat Oct 3 08:05:33 2015 -0600
mesa: remove unused _mesa_create_nameless_texture()
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Tested-by: Mark Janes <mark.a.janes at intel.com>
commit b373c776933c4d2d00947d92d595368f6d36bc96
Author: Brian Paul <brianp at vmware.com>
Date: Sat Oct 3 07:55:32 2015 -0600
mesa: remove unneeded error check in create_textures()
Callers of create_texture() will either pass target=0 or a validated
GL texture target enum so no need to do another error check inside
the loop.
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Tested-by: Mark Janes <mark.a.janes at intel.com>
commit c71f0d45e6d0081ea814fb0b16baec4e75a07bcb
Author: Kristian Høgsberg Kristensen <krh at bitplanet.net>
Date: Wed Oct 7 05:09:48 2015 -0700
i965: Link compiler unit tests to libi965_compiler.la
We can now link the unit tests against just libi965_compiler.la. This
lets us drop a lot of DRI driver dependencies, but we still pull in all
of libmesa and more.
This also provides a few standalone users of libi965_compiler.la, which
will help us accidentally using i965_dri.so functions from the compiler.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Signed-off-by: Kristian Høgsberg Kristensen <krh at bitplanet.net>
commit 08d890d3bb82eb1f5c71cf2eab1521c20c4d154c
Author: Kristian Høgsberg Kristensen <krh at bitplanet.net>
Date: Tue Oct 6 16:54:52 2015 -0700
i965: Break out backend compiler to its own library
This introduces a new libtool helper library, libi965_compiler.la. This
library is moderately self-contained, but still needs to link to all of
libmesa.la among other things.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Signed-off-by: Kristian Høgsberg Kristensen <krh at bitplanet.net>
commit 9a2573e5fc63f48cde56efdb191c129e7d7fb7b1
Author: Kristian Høgsberg Kristensen <krh at bitplanet.net>
Date: Wed Oct 7 05:13:50 2015 -0700
i965/cs: Get max_cs_threads from brw_compiler devinfo
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Signed-off-by: Kristian Høgsberg Kristensen <krh at bitplanet.net>
commit ee0f0108c8e87b9cfec25bade66670bbc4254139
Author: Kristian Høgsberg Kristensen <krh at bitplanet.net>
Date: Wed Oct 7 05:06:30 2015 -0700
i965: Move brw_get_shader_time_index() call out of emit functions
brw_get_shader_time_index() is all tangled up in brw_context state and
we can't call it from the compiler. Thanks the Jasons recent
refactoring, we can just get the index and pass to the emit functions
instead.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Signed-off-by: Kristian Høgsberg Kristensen <krh at bitplanet.net>
commit ffc841cae5a4a46c462b5ad5d97017154d3327e2
Author: Kristian Høgsberg Kristensen <krh at bitplanet.net>
Date: Wed Oct 7 04:19:39 2015 -0700
i965: Move brw_select_clip_planes() to brw_shader.cpp
We call this from the compiler so move it to brw_shader.cpp.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Signed-off-by: Kristian Høgsberg Kristensen <krh at bitplanet.net>
commit 365e5d78924ffe7d4ce47e3fbadc35c7105e5d34
Author: Kristian Høgsberg Kristensen <krh at bitplanet.net>
Date: Mon Oct 5 14:02:56 2015 -0700
i965: Use util_next_power_of_two() for brw_get_scratch_size()
This function computes the next power of two, but at least 1024. We can
do that by bitwise or'ing in 1023 and calling util_next_power_of_two().
We use brw_get_scratch_size() from the compiler so we need it out of
brw_program.c. We could move it to brw_shader.cpp, but let's make it a
small inline function instead.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Signed-off-by: Kristian Høgsberg Kristensen <krh at bitplanet.net>
commit cc4683992bf34fb09871e976abb8eebe7d68c3fe
Author: Kristian Høgsberg Kristensen <krh at bitplanet.net>
Date: Tue Oct 6 16:11:08 2015 -0700
i965: Move brw_mark_surface_used() to brw_shader.cpp
brw_program.c won't be part of the compiler library, but we need
brw_mark_surface_used() in the compiler. Move to brw_shader.cpp.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Signed-off-by: Kristian Høgsberg Kristensen <krh at bitplanet.net>
commit 469d0e449b78ad68e199dbe60e900487255a5d5d
Author: Kristian Høgsberg Kristensen <krh at bitplanet.net>
Date: Mon Oct 5 22:07:58 2015 -0700
i965/cs: Split out helper for building local id payload
The initial motivation for this patch was to avoid calling
brw_cs_prog_local_id_payload_dwords() in gen7_cs_state.c from the
compiler. This commit ends up refactoring things a bit more so as to
split out the logic to build the local id payload to brw_fs.cpp. This
moves the payload building closer to the compiler code that uses the
payload layout and makes it available to other users of the compiler.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Signed-off-by: Kristian Høgsberg Kristensen <krh at bitplanet.net>
commit 4f33700f5ab6e69072318622651ea81639845ae9
Author: Kristian Høgsberg Kristensen <krh at bitplanet.net>
Date: Mon Oct 5 14:22:23 2015 -0700
i965: Move brw_link_shader() and friends to new file brw_link.cpp
We want to use the rest of brw_shader.cpp with the rest of the compiler
without pulling in the GLSL linking code.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Signed-off-by: Kristian Høgsberg Kristensen <krh at bitplanet.net>
commit 99ca2256c1b8414efd27864bd56f6c95cac55731
Author: Kristian Høgsberg Kristensen <krh at bitplanet.net>
Date: Tue Oct 6 16:19:04 2015 -0700
i965: Configure bufmgr debug options from intel_screen.c
We need the debug flag parsing and INTEL_DEBUG in the compiler, but we
don't want the dependency on bufmgr (libdrm_intel) in there. Move to
intel_screen.c.
There are now only two lines left in brw_process_intel_debug_variable(),
but we keep it in intel_debug.h to avoid having to expose
'debug_control' as a global variable.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
Signed-off-by: Kristian Høgsberg Kristensen <krh at bitplanet.net>
commit 04158fb0f6e1148fdf155f78147cfc58b5d2b82c
Author: Kristian Høgsberg Kristensen <krh at bitplanet.net>
Date: Mon Oct 5 14:13:29 2015 -0700
util: Move DRI parse_debug_string() to util
We want to use intel_debug.c in code that doesn't link to dri common.
v2: Remove unnecessary stddef.h include (Topi), use util/debug.h
in all DRI driver and remove driParseDebugString() (Iago).
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Signed-off-by: Kristian Høgsberg Kristensen <krh at bitplanet.net>
commit ba71d581aeb96c4626500eb5b19f3bef2f40d586
Author: Kristian Høgsberg Kristensen <krh at bitplanet.net>
Date: Mon Oct 5 13:58:05 2015 -0700
i965: Move brw_dump_ir() out of brw_*_emit() functions
We move these calls one level up into the codegen functions.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Signed-off-by: Kristian Høgsberg Kristensen <krh at bitplanet.net>
commit 1fda56cdb2e8d982ccb063e63347103c03aeeadb
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Oct 8 15:50:54 2015 +0100
gallium/ddebug: add missing dd_util.h to sources list
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
commit 62741ff05272f5879fba753121342e27afa340f6
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Oct 8 15:50:12 2015 +0100
gallium/ddebug: automake: sort sources alphabetically
Signed-off-by: Emil Velikov <emil.velikov at collabora.com>
commit 9c528f5dfa69fcb4068df736be441c0db19e6e88
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Oct 5 17:16:02 2015 -0700
nir/sweep: Reparent the shader name
Previously the name of the nir shader was being freed prematurely during
nir_sweep. Since 756613ed35d the name was later being used to generate
filenames for the optimiser debug output and these would end up with
garbage from the dangling pointer.
Co-authored-by: Neil Roberts <neil at linux.intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit c8031a879a3f442a4ca43243914c797615110d9b
Author: Jan Vesely <jano.vesely at gmail.com>
Date: Sat Oct 3 19:19:13 2015 -0500
c11/threads: initialize timeout structure
Signed-off-by: Jan Vesely <jano.vesely at gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 89ae41ab4c9e32db9cbef0cb01a99c8e3efbb289
Author: Boyan Ding <boyan.j.ding at gmail.com>
Date: Thu Oct 8 15:38:15 2015 +0800
docs/relnotes: document EGL_KHR_create_context on llvmpipe and softpipe
Signed-off-by: Boyan Ding <boyan.j.ding at gmail.com>
commit 1efbb8151b402f76df6dbf0b4ed9c2823e3a44fd
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Wed Sep 23 08:52:07 2015 +0200
i965/gs/gen6: Maximum allowed size of SEND messages is 15 (4 bits)
Comit d48ac9306619 addressed this for VS, but we forgot to do the same for
URB writes generated by the gen6 GS.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 3141906fa36839e9276cb65033857c85b39376e5
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Tue Sep 22 13:14:52 2015 +0200
i965: Define FIRST_SPILL_MRF and FIRST_PULL_LOAD_MRF only once and in one place
That should make tracking where we do spills and pull loads a bit easier.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 36e82b137d4a77f24de0fc722c80e445b6e3375c
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Tue Sep 22 13:01:18 2015 +0200
i965: make pull constant loads in gen6 start at MRFs 16/17
So they do not conflict with our (un)spills (MRF 21..23) or our
URB writes (MRF 1..15)
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 0c2add775192f3ee0325d61964ef67f7ca3f6d4e
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Tue Sep 22 12:53:08 2015 +0200
i965: Fix remove_duplicate_mrf_writes so it can handle 24 MRFs in gen6
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit aee28a0aa3bb77b728972d4efcdf93c1cc09c73b
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Thu Oct 8 09:25:16 2015 +0300
mesa: include bad type in error string of _mesa_pack_depth_span
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 4e7fd66cf0986a7eb58800f52d0b8709c2f997d6
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Wed Oct 7 10:04:06 2015 +0300
glsl: add varyings to resource list only with SSO
Varyings can be considered inputs or outputs of a program only when
SSO is in use. With multi-stage programs, inputs contain only inputs
for first stage and outputs contains outputs of the final shader stage.
I've tested that fix works for Assault Android Cactus (demo version)
and does not cause Piglit or CTS regressions in glGetProgramiv tests.
Following ES 3.1 CTS separate shader tests that do query properties
of varyings in SSO shader programs pass:
ES31-CTS.program_interface_query.separate-programs-vertex
ES31-CTS.program_interface_query.separate-programs-fragment
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Tested-by: Dieter Nützel <Dieter at nuetzel-hh.de>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92122
commit 6ad9ebb073fc4ed245ef8e9db4479a52e818cb92
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Oct 7 15:52:09 2015 -0700
mesa: Correctly handle GL_BGRA_EXT in ES3 format_and_type checks
The EXT_texture_format_BGRA8888 extension (which mesa supports
unconditionally) adds a new format and internal format called GL_BGRA_EXT.
Previously, this was not really handled at all in
_mesa_ex3_error_check_format_and_type. When the checks were tightened in
commit f15a7f3c, we accidentally tightened things too far and GL_BGRA_EXT
would always cause an error to be thrown.
There were two primary issues here. First, is that
_mesa_es3_effective_internal_format_for_format_and_type didn't handle the
GL_BGRA_EXT format. Second is that it blindly uses _mesa_base_tex_format
which returns GL_RGBA for GL_BGRA_EXT. This commit fixes both of these
issues as well as adds explicit checks that GL_BGRA_EXT is only ever used
with GL_BGRA_EXT and GL_UNSIGNED_BYTE.
Signed-off-by: Jason Ekstrand <jason.ekstrand at intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92265
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
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