Revision: 39701 http://trac.macosforge.org/projects/macports/changeset/39701 Author: ryandesign@macports.org Date: 2008-08-31 16:48:41 -0700 (Sun, 31 Aug 2008) Log Message: ----------- veriwell: remove unnecessary distname declaration (it's already the default) Modified Paths: -------------- trunk/dports/science/veriwell/Portfile Modified: trunk/dports/science/veriwell/Portfile =================================================================== --- trunk/dports/science/veriwell/Portfile 2008-08-31 23:46:18 UTC (rev 39700) +++ trunk/dports/science/veriwell/Portfile 2008-08-31 23:48:41 UTC (rev 39701) @@ -18,7 +18,6 @@ platforms darwin master_sites sourceforge checksums md5 1c1c6fb05009172d2677e34f0e511a37 -distname ${name}-${version} depends_lib port:help2man # The following prevent conflicts with other Verilog simulators