[Xquartz-changes] mesa: Changes to 'master-darwin-build-fixes'
Jeremy Huddleston
jeremyhu at freedesktop.org
Wed Oct 7 15:36:24 PDT 2015
New branch 'master-darwin-build-fixes' available with the following commits:
commit 9800301a312ac06e0ce0af20e5817ee1e44ed4a5
Author: Jon TURNEY <jon.turney at dronecode.org.uk>
Date: Mon May 12 16:30:26 2014 +0100
applegl: Provide requirements of _SET_DrawBuffers
_SET_DrawBuffers requires driDispatchRemapTable, so we need to link with libmesa
for remap.c. libmesa requires the C++ linker.
Also need to arrange to call _mesa_init_remap_table() to initialize the remap
table.
XXX: There has to be a better way fixing this.
Signed-off-by: Jon TURNEY <jon.turney at dronecode.org.uk>
commit 24eefbd4ca271f22400549dd44ccd409263089e1
Author: Jon TURNEY <jon.turney at dronecode.org.uk>
Date: Sun May 11 14:40:07 2014 +0100
darwin: Suppress type conversion warnings for GLhandleARB
On darwin, GLhandleARB is defined as a void *, not the unsigned int it is on
linux.
For the moment, apply a cast to supress the warning
Possibly this is safe, as for the mesa software renderer the shader program
handle is not a real pointer, but a integer handle
Probably this is not the right thing to do, and we should pay closer attention
to how the GLhandlerARB type is used.
main/shader_query.cpp:49:7: error: no matching function for call to '_mesa_lookup_shader_program_err'
_mesa_lookup_shader_program_err(ctx, program, "glBindAttribLocation");
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../../src/mesa/main/shaderobj.h:81:1: note: candidate function not viable: cannot convert argument of incomplete type 'GLhandleARB' (aka 'void *') to 'GLuint' (aka 'unsigned int')
_mesa_lookup_shader_program_err(struct gl_context *ctx, GLuint name,
^
main/shader_query.cpp:111:13: error: no matching function for call to '_mesa_lookup_shader_program_err'
shProg = _mesa_lookup_shader_program_err(ctx, program, "glGetActiveAttrib");
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../../src/mesa/main/shaderobj.h:81:1: note: candidate function not viable: cannot convert argument of incomplete type 'GLhandleARB' (aka 'void *') to 'GLuint' (aka 'unsigned int')
_mesa_lookup_shader_program_err(struct gl_context *ctx, GLuint name,
^
main/shader_query.cpp:218:7: error: no matching function for call to '_mesa_lookup_shader_program_err'
_mesa_lookup_shader_program_err(ctx, program, "glGetAttribLocation");
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../../src/mesa/main/shaderobj.h:81:1: note: candidate function not viable: cannot convert argument of incomplete type 'GLhandleARB' (aka 'void *') to 'GLuint' (aka 'unsigned int')
_mesa_lookup_shader_program_err(struct gl_context *ctx, GLuint name,
Signed-off-by: Jon TURNEY <jon.turney at dronecode.org.uk>
commit db96821f442f56a24c3ba2b712f9454632c33ed3
Author: Arlie Davis <arlied at google.com>
Date: Thu Sep 17 15:19:24 2015 -0700
mesa: Reduce libGL.so binary size by about 15%
Ok, here's v2 of the change, with the suggested edits.
From 5f393faa058f453408dfc640eecae3fe6335dfed Mon Sep 17 00:00:00 2001
From: Arlie Davis <arlied at google.com>
Date: Tue, 15 Sep 2015 09:58:34 -0700
Subject: [PATCH] This patch significantly reduces the size of the libGL.so
binary. It does not change the (externally visible) behavior of libGL.so at
all.
gl_gentable.py generates a function, _glapi_create_table_from_handle.
This function allocates a large dispatch table, consisting of 1300 or so
function pointers, and fills this dispatch table by doing symbol lookups
on a given shared library. Previously, gl_gentable.py would generate a
single, very large _glapi_create_table_from_handle function, with a short
cluster of lines for each entry point (function). The idiom it generates
was a NULL check, a call to snprintf, a call to dlsym / GetProcAddress,
and then a store into the dispatch table. Since this function processes
a large number of entry points, this code is duplicated many times over.
We can encode the same information much more compactly, by using a lookup
table. The previous total size of _glapi_create_table_from_handle on x64
was 125848 bytes. By using a lookup table, the size of
_glapi_create_table_from_handle (and the related lookup tables) is reduced
to 10840 bytes. In other words, this enormous function is reduced by 91%.
The size of the entire libGL.so binary (measured when stripped) itself drops
by 15%.
So the purpose of this change is to reduce the binary size, which frees up
disk space, memory, etc.
commit 8ea9fa778a04d1535f994e39dcfdae7ee1add37e
Author: Jeremy Huddleston Sequoia <jeremyhu at apple.com>
Date: Wed Feb 11 12:32:56 2015 -0800
glext.h: Add missing include of stddef.h for ptrdiff_t
Signed-off-by: Jeremy Huddleston Sequoia <jeremyhu at apple.com>
commit bbf728f11b45121bf2d03b61bc0ffc69e0ff0836
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Oct 7 21:23:16 2015 +0100
Revert "mesa: enable KHR_debug for ES contexts"
This reverts commit b69cfbdf18fa64606a76761b20bc268f4ac731e5.
This isn't quite baked yet. Seems that despite building the ES piglits,
none of them got executed.
commit 164c8277f0edaab64e3cea43a1cf943ace62b21b
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Oct 7 11:43:58 2015 -0700
egl/dri2: Properly dereference array.
Fixes a regression that broke EGL since
commit 858f2f2ae6d72f338fdd6d544b0c733814e22724
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sun Sep 13 12:25:27 2015 +0100
egl/dri2: ease srgb __DRIconfig conditionals
commit 13e69805ea6a3aa0ec80c2b2430ae4da05c6b1ae
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Oct 2 19:21:54 2015 +0200
radeonsi: fix a GS hang on VI
Broken by one of the cleanups: 0d46c3bc9d09b376d74f7399e1a2d1b0a923640b
Not applicable to stable.
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
commit 5749676d03d1a4964888a2d9a7624d3b96cc4886
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Sep 6 15:43:23 2015 +0200
radeonsi: remove TC L2 cache flush for index buffers on VI
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
commit 6ed8fd3d6703bc51378e05a0e209df58d9844082
Author: Brian Paul <brianp at vmware.com>
Date: Tue Oct 6 16:55:39 2015 -0600
svga: whitespace fixes in svga_sampler_view.c
commit 70c4cde453bc12be5262b88dcb26e97dcb8e0507
Author: Brian Paul <brianp at vmware.com>
Date: Tue Oct 6 16:55:39 2015 -0600
svga: whitespace fixes in svga_resource_buffer.c
commit a2bc4a7b04d6971e093b0d25caf04de11ee07045
Author: Stefan Dösinger <stefandoesinger at gmx.at>
Date: Tue Oct 6 16:55:39 2015 -0600
mesa: Remove GL_ARB_sampler_object depth compare error checking.
Version 3: Simplify the code comment, word wrap commit description.
Version 2: Return GL_FALSE if ARB_shadow is unsupported instead of
pretending to store the value as suggested by Brian Paul.
This fixes a GL error warning on r200 in Wine.
The GL_ARB_sampler_objects extension does not specify a dependency on
GL_ARB_shadow or GL_ARB_depth_texture for setting the depth texture
compare mode and function. Silently ignore attempts to change these
settings. They won't matter without a depth texture being assigned
anyway.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 2bad030ac9c47c316f615db83c52cf0391f64f3f
Author: Brian Paul <brianp at vmware.com>
Date: Tue Oct 6 16:55:39 2015 -0600
svga: round UBO constant buffer size up/down to multiple of 16 bytes
The svga3d device requires constant buffers to be a multiple of 16 bytes
in size. OpenGL UBOs may not fit that restriction. As a work-around,
round the size up if possible, else round down.
Note that this patch only effects UBO constant buffers (index 1 or higher),
not the 0th/default constant buffer.
Fixes the game Grim Fandango Remastered. VMware bug 1510130.
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
Reviewed-by: José Fonseca <jfonseca at vmware.com>
commit 4ea5ed9f51c2ec851ac2d81108035bf7046bbc69
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sun Sep 13 12:36:54 2015 +0100
egl/dri2: enable EGL_KHR_gl_colorspace for swrast
No driver changes needed for softpipe/llvmpipe - things just work.
v2: Whitespace fixes.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Boyan Ding <boyan.j.ding at gmail.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
commit 858f2f2ae6d72f338fdd6d544b0c733814e22724
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sun Sep 13 12:25:27 2015 +0100
egl/dri2: ease srgb __DRIconfig conditionals
One can simplify the if-else chain, by declaring the driconfigs as a
two sized array, whist using srgb as a index to the correct entry.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
commit b69cfbdf18fa64606a76761b20bc268f4ac731e5
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Sep 14 18:35:48 2015 +0100
mesa: enable KHR_debug for ES contexts
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 70643a1389179c214b454a6a49e9f47a768ba904
Author: Matthew Waters <ystreet00 at gmail.com>
Date: Wed Sep 16 16:38:27 2015 +0100
main/get: make KHR_debug enums available everywhere
Move all the enums but CONTEXT_FLAGS. The spec seems quite explicit
about the latter (wrt OpenGL ES)
"In OpenGL ES versions prior to and including ES 3.1 there is no
CONTEXT_FLAGS state and therefore the CONTEXT_FLAG_DEBUG_BIT cannot
be queried."
v2 [Emil Velikov] Rebase.
v3 [Emil Veliokv] Drop the CONTEXT_FLAGS hunk - not applicable for GLES
Signed-off-by: Matthew Waters <ystreet00 at gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit ae6ff72f5a56d71887bd2c59128868f71e5e2e01
Author: Matthew Waters <ystreet00 at gmail.com>
Date: Mon Sep 14 18:35:46 2015 +0100
glapi: add function pointers for KHR_debug for gles
v2 [Emil Velikov]
- Rebase.
- Correct version in gles11 dispatch_sanity.
- Move the extension enable to a separate patch.
Signed-off-by: Matthew Waters <ystreet00 at gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit deb1765ec626b6177f1bf7b2a24f10ed79cf6243
Author: Varad Gautam <varadgautam at gmail.com>
Date: Wed Oct 7 09:48:15 2015 +0530
egl: move memcpy to bring conf->base operations together
Signed-off-by: Varad Gautam <varadgautam at gmail.com>
Suggested-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit f988eff37991272b3e685112136a8b2ae06386bf
Author: Varad Gautam <varadgautam at gmail.com>
Date: Wed Oct 7 09:48:14 2015 +0530
egl: restore surface type before linking config to its display
commit c2c2e9a (egl: implement EGL_KHR_gl_colorspace (v2)) leaves
_EGLConfig->SurfaceType set incorrectly before calling _eglLinkConfig(),
and the bad value is passed around to platform_android. set it to zero
as earlier.
v2: Set SurfaceType to 0, rather than surface_type (Suggested by Emil)
Cc: mesa-stable at lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91596
Signed-off-by: Varad Gautam <varadgautam at gmail.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 47d11990b2ca3eb666b8ac81fee7f7eb5019eba1
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Oct 5 15:19:05 2015 -0400
nouveau: make sure there's always room to emit a fence
I started seeing a lot of situations on nv30 where fence emission
wouldn't fit into the previous buffer (causing assertions). This ensures
that whenever checking for space, we always leave a bit of extra room
for the fence emission commands. Adjusts the nv30 and nvc0 fence
emission logic to bypass the space checking as well.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
commit 64d9d4b73031d1bc23ae869e2afad86ed01edea5
Author: Boyan Ding <boyan.j.ding at gmail.com>
Date: Sun Sep 27 17:16:57 2015 +0800
vc4: use nir two-sided-color lowering
Similar to 9ffc1049ca (freedreno/ir3: use nir two-sided-color lowering).
No piglit regression.
Signed-off-by: Boyan Ding <boyan.j.ding at gmail.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit b6cd39fc4761a3a6276a373e68510fb7fb735a77
Author: Eric Anholt <eric at anholt.net>
Date: Tue Oct 6 16:32:03 2015 -0700
vc4: Fix a leak of the last color read/write surface on context destroy.
commit 922e0680f9152aaacde12636d91b97346b05d61c
Author: Eric Anholt <eric at anholt.net>
Date: Tue Oct 6 16:12:50 2015 -0700
vc4: Fix a memory leak in the simulator case.
We validate per draw call, and need to free the shader per draw call, too.
commit 38610102137d546afc3f543604414f061f1aec88
Author: Mark Janes <mark.a.janes at intel.com>
Date: Fri Apr 10 13:41:19 2015 -0700
mesa: remove unneeded #include of colormac.h
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 3475b68abd8791324f201a141ba5263fcb91e2d0
Author: Mark Janes <mark.a.janes at intel.com>
Date: Fri Apr 10 13:41:18 2015 -0700
radeon/r200: remove unneeded #include of colormac.h
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit eb6b80842ffc27f138cc0221c5465c51d0105c04
Author: Mark Janes <mark.a.janes at intel.com>
Date: Fri Apr 10 13:41:17 2015 -0700
i965: remove unneeded #include of colormac.h
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 83f9f911b2c55a9ca1a27fd665c10913e6dd6291
Author: Mark Janes <mark.a.janes at intel.com>
Date: Fri Apr 10 13:41:16 2015 -0700
i915: remove unneeded #include of colormac.h
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 3bcc780126ec3a479429a42befa27f141ebf8d48
Author: Ville Syrjälä <ville.syrjala at linux.intel.com>
Date: Mon Mar 23 14:47:34 2015 +0200
i915: Drop broken front_buffer_reading/drawing optimization
Bring the following commit over to i915:
commit ec542d74578bbef6b55125dd6aba1dc7f5079e65
Author: Eric Anholt <eric at anholt.net>
Date: Mon Mar 3 10:43:10 2014 -0800
i965: Drop broken front_buffer_reading/drawing optimization.
Not sure if it might fix anything, but since the i965 and i915 used to
share a bunch of that code, it would seem reasonable the same problems
could be present in the i915 code still, and the i965 approach is well
tested by now so bringing it over seems fairly safe.
No piglit regressions on 855.
v2: Rebase on _mesa_is_front_buffer_* refactor.
Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit ea8b77e892cdf6aa4cdd8a9ff312c422b3509ae7
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Thu Sep 17 10:26:45 2015 -0400
mesa/i965: Refactor brw_is_front_buffer_{drawing,reading} to common code
There are multiple similar implementations of these functions, and a
later patch was going to add another.
v2: Move removing intel_framebuffer to a different patch.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 5c4ef9f1d2ae6a1824119aa246eaea727e294e3a
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Oct 6 10:55:40 2015 -0700
st/mesa: Don't override NewFramebuffer just to call _mesa_new_framebuffer
v2: Since state_tracker does not call _mesa_init_driver_functions, we
need to initialize the dd::NewFramebuffer pointer to
_mesa_new_framebuffer here. Suggested by Brian.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit df75babf74d4174f334708e00eaf5399420bc9a1
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Oct 6 10:55:03 2015 -0700
radeon: Don't override NewFramebuffer just to call _mesa_new_framebuffer
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
commit e32a6590a43fa9ff792639e44555019077d461ba
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Oct 6 10:55:03 2015 -0700
i915: Don't override NewFramebuffer just to call _mesa_new_framebuffer
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit ed7f00f564fc2175693560c0697d318cf7b4a13c
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Oct 6 10:55:03 2015 -0700
i965: Don't override NewFramebuffer just to call _mesa_new_framebuffer
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 021f15816e74ec012b8cb904d9f0bc05ff5885b0
Author: Ville Syrjälä <ville.syrjala at linux.intel.com>
Date: Mon Mar 23 14:47:35 2015 +0200
i830: Fix culling with user fbos on gen2
Flip the cull bits when rendering to a user fbo on gen2. This
was already done on gen3 (since before git history starts)
but was missing from the gen2 code.
Fixes rendering of the driver+kart model in supertuxkart kart
selection screen.
Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 3e2c7ca7731362b9f8f872832aeed2f89e70e11c
Author: Ville Syrjälä <ville.syrjala at linux.intel.com>
Date: Mon Mar 23 14:47:32 2015 +0200
i915: Adjust line size limits
The hardware can draw lines 0.5 to 7.5 pixels wide. Adjust the limits
to 1.0-7.0. The old limits seems to be from the era when i915 and i965
were sharing this code.
Not really sure if 1.0-7.0 is correct. Maybe it could be 0.5.7.5 as
those are the hw limits, or maybe some combination of the two?
Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 00ee403883abedb966550d6ab50a1c1f6613175f
Author: Ville Syrjälä <ville.syrjala at linux.intel.com>
Date: Mon Mar 23 14:47:31 2015 +0200
i915: Enable intel_render path for points
The sub-pixel adjustment for points was killed off in
commit 60d762aa625095a8c1f9597d8530bb5a6fa61b4c
Author: Xiang, Haihao <haihao.xiang at intel.com>
Date: Wed Jan 2 11:38:51 2008 +0800
i915: Needn't adjust pixel centers. fix #12944
so if we don't need it in intel_tris.c we don't need it in
intel_render.c either, which means we can allow intel_render.c to render
points.
No apparent regressions on PNV in ES1 or ES2 conformance.
Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 0febd0ecfd1e2a36381ab7793811b9c7891ed82f
Author: Ville Syrjälä <ville.syrjala at linux.intel.com>
Date: Mon Mar 23 14:47:30 2015 +0200
i915: Use COPY_DWORDS for points
The sub-pixel adjustment for points was killed off in
commit 60d762aa625095a8c1f9597d8530bb5a6fa61b4c
Author: Xiang, Haihao <haihao.xiang at intel.com>
Date: Wed Jan 2 11:38:51 2008 +0800
i915: Needn't adjust pixel centers. fix #12944
so we can just as well use COPY_DWORDS().
Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit bcf650496f22961fb66975aba3c8a982dbc72c9e
Author: Ville Syrjälä <ville.syrjala at linux.intel.com>
Date: Mon Mar 23 14:47:27 2015 +0200
i915: Use _tnl_RenderClippedPolygon and _tnl_RenderClippedLine
_tnl_RenderClippedPolygon and _tnl_RenderClippedLine already do most of
what we want so use them.
Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 303895655c6ed837e3d867a450f4322404e86a88
Author: Ville Syrjälä <ville.syrjala at linux.intel.com>
Date: Mon Mar 23 14:47:25 2015 +0200
i915: Handle provoking vertex in intelFastRenderClippedPoly()
intelFastRenderClippedPoly() renders the polygon using triangles. For
polygons the provoking vertex is always the first one, and currently
this function assumes that the provoking vertex for triangles is the
last one. In case the user changed the provoking vertex convention,
the hardware may be configured to treat the first vertex of triangles
as the provoking vertex. So check the convention and emit the triangles
in the appropriate order to avoid having to change the hardware
provoking vertex convention for rendering polygons.
Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 08864265039437260beffcdc3471e5788d142e86
Author: Ville Syrjälä <ville.syrjala at linux.intel.com>
Date: Mon Mar 23 14:47:20 2015 +0200
t_dd_dmatmp: Check provoking vertex convention when rendering quads
When drawing quads using triangles we need to be careful to make
the provoking vertices match when flat shading.
v2: Major rebase on top of Ian's other t_dd_dmatmp.h work.
Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
commit 83d511e1904b565490e6c8335a1d329e0fcf9c41
Author: Ville Syrjälä <ville.syrjala at linux.intel.com>
Date: Mon Mar 23 14:47:19 2015 +0200
t_dd_dmatmp: Disallow flat shading when rendering quad strips via tri strips
When rendering quad strips via tri strips we can't get the provoking
vertex right, so disallow flat shading.
v2: Major rebase on top of Ian's other t_dd_dmatmp.h work.
Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
commit b15b4581d15684d59e1fc4d7cad72ece4dd9fcb0
Author: Ville Syrjälä <ville.syrjala at linux.intel.com>
Date: Mon Mar 23 14:47:18 2015 +0200
t_dd_dmatmp: Allow flat shaded polygons with tri fans
We can allow rendering flat shaded polygons using tri fans if we check
the provoking vertex convention.
v2 (idr): Remove _EXT suffixes from GL_FIRST_VERTEX_CONVENTION.
Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 5ca00e0b8dff529f33c8b1685a9109a78090987c
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Fri Sep 18 14:56:13 2015 -0400
t_dd_dmatmp: Replace fprintf with unreachable
From http://lists.freedesktop.org/archives/mesa-dev/2015-May/084883.html:
"There are no real error cases here, just dead code.
validate_render() is supposed to make sure we never call these
functions if the code can't actually render the primitives. The
fprintf()+return branches should really just contain assert(0) or
equivalent."
I also rearranged the if-else-block in render_quad_strip_verts to look
more like the other functions. A future patch is going to change a
bunch of that code anyway.
v2: Make "unreachable" message more descriptive. Suggested by Iago.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Suggested-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 46b13666d8c045acf066f2982cc0a89b6584f09d
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Sep 30 15:23:38 2015 -0700
radeon: Use C99 initializers for primitive arrays
Using C99 initializers for the primitive arrays makes things more
readable.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Suggested-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 68976a5a009beeb5118a52c31b0e7784202707a3
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Sep 30 15:22:38 2015 -0700
i965: Use C99 initializers for primitive arrays
Using C99 initializers for the primitive arrays makes things more
readable.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Suggested-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit fad5fd3a254c9c37bc25cd356d2bced0dcfe9e26
Author: Ville Syrjälä <ville.syrjala at linux.intel.com>
Date: Mon Mar 23 14:47:29 2015 +0200
i915: Use C99 initializers for primitive arrays
Using C99 initializers for the primitive arrays makes things more
readable.
Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 3801fa65c1ebb44d93cc6c5780906e0fa0d0b676
Author: Brian Paul <brianp at vmware.com>
Date: Mon Oct 5 07:44:36 2015 -0600
tgsi: add const qualifier to silence warning
Trivial.
commit b7766a95e1b81e27624d91edf83dea91fb64a42e
Author: Brian Paul <brianp at vmware.com>
Date: Thu Oct 1 13:12:57 2015 -0600
glsl: whitespace/formatting/typo fixes in link_uniforms.cpp
commit 50d5a36f3575bae38266e2445989c3b672ddbdbf
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Mon Oct 5 11:06:07 2015 +0200
main: array stride for unsized arrays of arrays are calculated like records
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
commit 82db642042585ddb54a2da44730b082062188d65
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Tue Sep 22 16:25:46 2015 +0200
glsl: add std430 layout support for AoA
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
commit 64831832791139328a67b80387f062d39e304d24
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Sun Oct 4 11:23:04 2015 +1100
docs: Mark GL_ARB_enhanced_layouts as in progress
commit dbae576f7f25fef72ca0b9f6f4822e0fddf7d607
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Jun 19 13:36:15 2015 -0700
i965: add EXT_polygon_offset_clamp support to gen4/gen5
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 833fa9a8cd4e3ac447c473ecb0a35294ff5f1e65
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Aug 14 11:19:49 2015 -0700
meta: Update comment about unsupported texture types.
Ken added support for 2DArray (commit ec23d5197e) and 1DArray (commit
14ca61125) last year.
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit d4ff638504acb31ed523c8c862f66a7483014cb7
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Jun 29 09:58:50 2015 -0700
glx: Drop CRAY support.
It couldn't have worked anyway. There were calls to undefined functions.
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 617eb5e6c3058730c118b9178b50f2ab82f6932d
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Sep 23 12:44:44 2015 -0700
glsl: Remove CSE pass.
With NIR, it actually hurts things.
total instructions in shared programs: 6529329 -> 6528888 (-0.01%)
instructions in affected programs: 14833 -> 14392 (-2.97%)
helped: 299
HURT: 1
In all affected programs I inspected (including the single hurt one) the
pass CSE'd some multiplies and caused some reassociation (e.g., caused
(A * B) * C to be A * (B * C)) when the original intermediate result was
reused elsewhere.
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
commit 5a360dcad1fdb91f9129cb21775b9af60cbf57e4
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Oct 2 20:30:41 2015 -0700
i965: Generalize predicated break pass for use in vec4 backend.
instructions in affected programs: 44204 -> 43762 (-1.00%)
helped: 221
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 4098a756b5590a460bdb0ee7d54cca81375f61e8
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Oct 2 20:23:35 2015 -0700
i965/fs: Use backend_instruction in predicated break peephole.
We're not using any fs_inst fields, and the next commit will make the
peephole used by the vec4 backend.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 596441992130460c7d9a792e50eea46d27297d44
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Oct 2 20:18:34 2015 -0700
i965/fs: Remove SNB embedded-comparison support from optimizations.
We never emit IF instructions with an embedded comparison (lost in the
switch to NIR), so this code is not used. If we want to readd support,
we should have a pass that merges a CMP instruction with an IF or a
WHILE instruction after other optimizations have run.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 36ea9922ada5ea99e54231697a4afb31d5f6b9bf
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu Oct 1 10:06:55 2015 -0700
mesa: Add missing _mm_mfence() before streaming loads.
According to the Intel Software Development Manual (Volume 1: Basic
Architecture, 12.10.3 Streaming Load Hint Instruction):
Streaming loads may be weakly ordered and may appear to software to
execute out of order with respect to other memory operations.
Software must explicitly use fences (e.g. MFENCE) if it needs to
preserve order among streaming loads or between streaming loads and
other memory operations.
That is, a memory fence is needed to preserve the order between the GPU
writing the buffer and the streaming loads reading it back.
Reported-by: Joseph Nuzman <joseph.nuzman at intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 93161be9e7150ae5931000627833e714901cf195
Author: Chad Versace <chad.versace at intel.com>
Date: Thu Oct 1 08:06:35 2015 -0700
i965: Fix intel_miptree_is_fast_clear_capable()
There are three types of fast clears:
a. fast depth clears
b. fast singlesample color clears
c. fast multisample color clears
Function intel_miptree_is_fast_clear_capable() checks if a miptree
supports fast clears of type (b).
Rename the function to disambiguate what it does:
old: intel_miptree_is_fast_clear_capable
new: intel_miptree_supports_non_msrt_fast_clear
The functionally accidentally rejected multisampled color surfaces
because it thought they were singlesample array surfaces. Fix that by
explicitly rejecting surfaces with samples > 1.
This fix would have been needed before we enabled layered fast
singlesample color clears (introduced in gen8), which we want to do
eventually. For now, though, this patch changes no behavior; it just
fixes how the driver chooses its behavior.
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 125a04b474d4a07fec892e00fd56340e7d4ab03b
Author: Chad Versace <chad.versace at intel.com>
Date: Thu Oct 1 07:31:31 2015 -0700
i965/mt: Declare some functions as static
intel_tiling_supports_non_msrt_mcs() and
intel_miptree_is_fast_clear_capable() are not used outside of
intel_mipmap_tree.c.
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 73e0dfbaca2fd334fd3505412bf0d38054affd25
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Mon Oct 5 09:02:54 2015 +0200
i965: Make vec4_visitor's destructor virtual
We need a virtual destructor when at least one of the class' methods is virtual.
Failure to do so might lead to undefined behavior when destructing derived classes.
Fixes the following warning:
brw_vec4_gs_visitor.cpp: In function 'const unsigned int* brw::brw_gs_emit(brw_context*, gl_shader_program*, brw_gs_compile*, void*, unsigned int*)':
brw_vec4_gs_visitor.cpp:703:11: warning: deleting object of polymorphic class type 'brw::vec4_gs_visitor' which has non-virtual destructor might cause undefined behaviour [-Wdelete-non-virtual-dtor]
delete gs;
Curro: This shouldn't be causing any actual bugs at the moment because
gen6_gs_visitor is the only subclass of vec4_visitor destroyed through
a pointer of a base class (vec4_gs_visitor *) and its destructor is
basically the same as its parent's. Anyway it seems sensible to change
this so it doesn't bite us in the future.
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit a90feb581a1c0e63bf13aace5d11b6532e881313
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Mon Oct 5 12:50:10 2015 +0300
glsl: set glsl error if binding qualifier used on global scope
Fixes following Piglit test:
global-scope-binding-qualifier.frag
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit 102f6c446b6585b00e1c1cd3c838f7b0899e49a9
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Wed Sep 30 10:24:11 2015 +0200
i965: Assert on the number of combined UBO and SSBO binding table entries
In theory we can't break this assertion since the compiler frontend checks
that we don't exceed any of the individual limits, but it does not hurt to
be extra safe.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 20cbe3688aec2fd371fea096e6a0de0a38c2ae70
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Wed Sep 30 11:06:30 2015 +0200
i965: Reserve binding table space for SSBO surfaces
These share the space with UBO surfaces but we need to make sure we
allocate enough space for both sets (12 of each)
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 41c4d45e08b3bf948f24d007c9b7d0c47f3f89d8
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Wed Sep 30 11:05:49 2015 +0200
i965: Define BRW_MAX_SSBO
Instead of using hard-coded values.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 440f9348c1fb877910cebca5413c4300b6738428
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Wed Sep 30 09:55:00 2015 +0200
i965: Define BRW_MAX_UBO
Instead of using hard-coded values.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 4caa10193f6a88f476807aee56b900b3a02d9a6a
Author: Matt Turner <mattst88 at gmail.com>
Date: Sat Oct 3 10:43:26 2015 -0700
i965/vec4: Remove more dead visitor/vertex program code.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit cd7fa1034adc8891b094a0a52fbbbef0cc708e3d
Author: Matt Turner <mattst88 at gmail.com>
Date: Sat Sep 26 14:40:09 2015 -0700
i965: Don't print line numbers with INTEL_DEBUG=optimizer.
The thing you want to do with the output files is diff them, which is
made more difficult by line numbers changing.
Reviewed-by: Alejandro Piñeiro <apinheiro at igalia.com>
commit 78ec9e28ec759bcaf9781bcbd2b8e051f7df7896
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Oct 4 21:47:33 2015 -0400
nv30: always go through translate module on big-endian
It seems like things are either coming in slighly wrong, or perhaps
uploaded incorrectly, but either way passing them through the translate
module seems to fix everything. Eventually we should figure out what's
going wrong and fix it "for real", but this should do for now.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org
commit 1fec05d1142921cdb5b01d94d886062c57905edc
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Oct 4 21:45:51 2015 -0400
nv30: pretend to have packed texture/surface formats
This puts us in line with what the DDX/DRI2 st are expecting. It also
happens to work... no idea why, but seems better to have it work than to
ask lots of questions.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org
commit 87c3c9acd29655d6c8778ea732f559eebeddd5f6
Author: Michel Dänzer <michel.daenzer at amd.com>
Date: Mon Aug 10 18:44:18 2015 +0900
st/dri: Use packed RGB formats
Fixes Gallium based DRI drivers failing to load on big endian hosts
because they can't find any matching fbconfigs.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71789
Signed-off-by: Michel Dänzer <michel.daenzer at amd.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Tested-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 763cd8c080353482cb41da578cb3d6f7892a0c9f
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Wed Sep 30 11:00:02 2015 +1000
glsl: reduce memory footprint of uniform_storage struct
The uniform will only be of a single type so store the data for
opaque types in a single array.
Cc: Francisco Jerez <currojerez at riseup.net>
Cc: Ilia Mirkin <imirkin at alum.mit.edu>
commit b85757bc72350df609f50e000512bc80d07f1497
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Oct 2 16:40:14 2015 -0700
i965: Remove shader_prog from vec4_gs_visitor.
Unfortunately it has to stay in gen6_gs_visitor.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 21585048a2e21ea9726e7f0b9f9fd98d1105295c
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Oct 2 16:45:09 2015 -0700
i965: Use nir->has_transform_feedback_varyings to avoid shader_prog.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 7768b802e57253e6a91b908e9b855d23f0fd2d3f
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Oct 2 15:55:05 2015 -0700
nir: Add a nir_shader_info::has_transform_feedback_varyings flag.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 5d7f8cb5a511977e256e773716fac3415d01443e
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Oct 1 00:46:19 2015 -0700
nir: Introduce new nir_intrinsic_load_per_vertex_input intrinsics.
Geometry and tessellation shaders process multiple vertices; their
inputs are arrays indexed by the vertex number. While GLSL makes
this look like a normal array, it can be very different behind the
scenes.
On Intel hardware, all inputs for a particular vertex are stored
together - as if they were grouped into a single struct. This means
that consecutive elements of these top-level arrays are not contiguous.
In fact, they may sometimes be in completely disjoint memory segments.
NIR's existing load_input intrinsics are awkward for this case, as they
distill everything down to a single offset. We'd much rather keep the
vertex ID separate, but build up an offset as normal beyond that.
This patch introduces new nir_intrinsic_load_per_vertex_input
intrinsics to handle this case. They work like ordinary load_input
intrinsics, but have an extra source (src[0]) which represents the
outermost array index.
v2: Rebase on earlier refactors.
v3: Use ssa defs instead of nir_srcs, rebase on earlier refactors.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit f2a4b40cf15cbc5eaab1776ad275ed8eead3322f
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Oct 1 00:36:25 2015 -0700
nir/lower_io: Make get_io_offset() return a nir_ssa_def * for indirects.
get_io_offset() already walks the dereference chain and discovers
whether or not we have an indirect; we can just return that rather than
computing it a second time via deref_has_indirect(). This means moving
the call a bit earlier.
By returning a nir_ssa_def *, we can pass back both an existence flag
(via NULL checking the pointer) and the value in one parameter. It
also simplifies the code somewhat. nir_lower_samplers works in a
similar fashion.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 6994ca20aad110734f87ef5297fecd53e8f6e34e
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Sun Oct 4 17:42:41 2015 +1100
glsl: fix whitespace
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 814b7d1ab9e90567034e9601a420ed1be2970c15
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Sep 28 23:50:12 2015 +0200
radeonsi: enable PIPE_CAP_FORCE_PERSAMPLE_INTERP
Now st/mesa won't generate 2 variants for this state.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit b3c55fc669b54589e57a112df75094405e16ff52
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Sep 28 23:46:04 2015 +0200
radeonsi: do force_persample_interp in shaders for non-trivial cases
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 9652bfcf2d2f3be5158ed88b49917bb5a2d8323d
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Sep 28 17:21:10 2015 +0200
radeonsi: implement the simple case of force_persample_interp
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 214de2d815360aa3986eb52a3b3060c33523f1b3
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Sep 28 17:01:21 2015 +0200
radeonsi: move SPI_PS_INPUT_ENA/ADDR registers to a separate state
This will be a derived state used for changing center->sample and
centroid->sample at runtime.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 55d406b71ee96dc7ee2dc2f9dd7df3bd80957f5a
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Sep 28 21:44:54 2015 +0200
tgsi/scan: add interpolation info into tgsi_shader_info
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 6b0f21cb287bde3acaba1b0d18ab1c291acf327f
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Sep 27 19:54:57 2015 +0200
st/mesa: automatically set per-sample interpolation if using SampleID/Pos
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 4e9fc7e4e2fa3b3c77d08c4db545dcc279e849e9
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Sep 27 19:43:00 2015 +0200
st/mesa: set force_persample_interp if ARB_sample_shading is used
This is only a half of the work. The next patch will handle
gl_SampleID/SamplePos, which is the other half of ARB_sample_shading.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit f3b37e321fe5ea8a8c0ff026636d69ce90437a6f
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Sep 27 19:32:07 2015 +0200
gallium: add per-sample interpolation control into rasterizer statOAe
Required by ARB_sample_shading for drivers that don't want a shader variant
in st/mesa.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Acked-by: Roland Scheidegger <sroland at vmware.com>
commit d8932a355dfdd813f903b4f2bd6aab36ea66d14a
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Sep 27 21:08:46 2015 +0200
st/mesa: add ST_DEBUG=precompile support for tessellation shaders
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit dd340b34f30e71db56f1a12768c7332b8224448c
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Sep 27 21:28:22 2015 +0200
mesa: remove Driver.BindImageTexture
Nothing sets it.
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 92709dcb9b7a09f9e5870a832c22197cde557fd4
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Sep 27 21:28:22 2015 +0200
mesa: remove Driver.DeleteSamplerObject
Nothing overrides it.
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 00f6beed02d644189b935b3cc9d70a6f993c034e
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Sep 27 21:28:22 2015 +0200
mesa: remove Driver.EndCallList
Nothing overrides it.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit ef6c0714af57d1aeaa9904fc4bb074e381ef928b
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Sep 27 21:28:22 2015 +0200
mesa: remove Driver.BeginCallList
Nothing overrides it.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit f457964885afedaa47c1ee675c313650d1082473
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Sep 27 21:28:22 2015 +0200
mesa: remove Driver.EndList
Nothing overrides it.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 55735cad007f15fb407f803a0416593997a2045e
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Sep 27 21:28:22 2015 +0200
mesa: remove Driver.NewList
Nothing overrides it.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 7a5493972881cb6beb2e172f4159b39809ab3295
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Sep 27 21:28:22 2015 +0200
mesa: remove Driver.NotifySaveBegin
Nothing overrides it.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 4b8bb2f559b75c953e87c7b6bda17b155a87df15
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Sep 27 21:28:22 2015 +0200
mesa: remove Driver.SaveFlushVertices
Nothing overrides it.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 72a5dff9cbc9ec9edee9e9ef539e4cb3f9051903
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Sep 27 21:28:22 2015 +0200
mesa: remove Driver.FlushVertices
Nothing overrides it.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 91799880b38e889633f136ddd72b4bcbcee150a9
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Sep 27 21:28:22 2015 +0200
mesa: remove Driver.BeginVertices
Nothing overrides it.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 82a950f18799d2ec6793892f469234b87e28bf02
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Sep 27 21:28:22 2015 +0200
mesa: remove Driver.BindArrayObject
Nothing sets it.
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit d1269a844f4d4b498c0b6c886e6273a7da93582e
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Sep 27 21:28:22 2015 +0200
mesa: remove Driver.DeleteArrayObject
Nothing reimplements it.
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 7401807e8dd89f79a98b89cc1bfce5ed89166653
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Sep 27 21:28:22 2015 +0200
mesa: remove Driver.NewArrayObject
Nothing reimplements it.
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 1044f99812bb29fa06c83c7230fe80f867711266
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Sep 27 21:28:22 2015 +0200
mesa: remove Driver.Hint
Nothing sets it.
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 8de82faf95e2f4713370876fecba621a9efe87e7
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Sep 27 21:28:22 2015 +0200
mesa: remove Driver.ColorMaskIndexed
Nothing sets it.
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 379255298f8fa9d9d8d53bf8898345fdd4fd0222
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Sep 27 21:28:22 2015 +0200
mesa: remove some Driver.Blend* hooks
Nothing sets them.
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit a6cc895e935889fce674e3988f326a2bae3b51ce
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Sep 27 21:28:22 2015 +0200
mesa: remove Driver.Accum
Nothing calls it.
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit a4fca2448422f52508cf7c7948102299c2db63d6
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Sep 27 21:28:22 2015 +0200
mesa: remove Driver.ResizeBuffers
Nothing overrides it.
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 6863d5b02a5d982cc71cfc28155a8958adfc65d1
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Sep 27 21:28:22 2015 +0200
mesa: remove Driver.DeleteShaderProgram
Nothing overrides it.
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit b37dcb8c18ec28f1ba0c4f69c4b9680a5db9c2fe
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Sep 27 21:28:22 2015 +0200
mesa: remove Driver.NewShaderProgram
Nothing overrides it.
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 95e03033127f9b93b49301adbf5d4b6ddccfa931
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Sep 27 21:28:22 2015 +0200
mesa: remove Driver.DeleteShader
Nothing overrides it.
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 18123a732b8593bb7add03d1529ace464f46a7ac
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Sep 25 22:48:00 2015 +0200
egl/dri2: don't require a context for ClientWaitSync (v2)
The spec doesn't require it. This fixes a crash on Android.
v2: don't set any flags if ctx == NULL
v3: add the spec note
Cc: 10.6 11.0 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Albert Freeman <albertwdfreeman at gmail.com>
Reviewed-by: Frank Binns <frank.binns at imgtec.com>
commit b78336085bce4d1f36c8d9c72fd3fa41643e3cd1
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Sep 25 22:44:41 2015 +0200
st/dri: don't use _ctx in client_wait_sync
Not needed and it can be NULL.
v2: fix dri2_get_fence_from_cl_event - thanks Albert
Cc: 10.6 11.0 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Albert Freeman <albertwdfreeman at gmail.com>
commit 27b102e7fdbcd2beedc815996e1b5fcb2b612206
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Sep 6 17:37:38 2015 +0200
r600g: only do depth-only or stencil-only in-place decompression
instead of always doing both.
Usually, only depth is needed, so stencil decompression is useless.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit c23c92c965f72f9a0b160834d06a2d631b736081
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Sep 6 17:37:38 2015 +0200
radeonsi: only do depth-only or stencil-only in-place decompression
instead of always doing both.
Usually, only depth is needed, so stencil decompression is useless.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 5804c6adf8361adb5d04feaf578dffbf840475d6
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Sep 6 17:35:06 2015 +0200
gallium/radeon: add separate stencil level dirty flags
We will only do depth-only or stencil-only decompress blits, whichever is
needed by textures, instead of always doing both.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit cc92b9037507ccfb498bdcec27b4d186e230004f
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Sep 27 01:38:48 2015 +0200
radeonsi: dump buffer lists while debugging
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit eb55610c89af669f442418f32df6df60fc412867
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Sep 27 00:58:15 2015 +0200
winsys/radeon: implement cs_get_buffer_list
This is more complicated, because tracking priority_usage needed changing
the relocs_bo type.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 6f48e2bee15c484c4a4685712c6ba1f379ef6853
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Sep 27 00:52:32 2015 +0200
winsys/amdgpu: add winsys function cs_get_buffer_list
For debugging.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 93641f43416b8b8be8944e9d1473369bfda7f302
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Sep 27 00:10:00 2015 +0200
gallium/radeon: stop using "reloc" in a few places
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 2edb0606397d16fe88d7b488285df379aaae5893
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Sep 26 23:18:55 2015 +0200
gallium/radeon: tell the winsys the exact resource binding types
Use the priority flags and expand them.
This information will be used for debugging.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 9bd7928a35c27d3d0898db83bc8db823a6dbee5e
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Sep 26 03:15:40 2015 +0200
radeonsi: add an option for debugging VM faults
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 4502d0bf8857d5900882466a69ca8cae2ee5d90e
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Sep 26 03:14:43 2015 +0200
radeonsi: move dumping the last IB into its own function
v2: indentation fix
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 89f73827d03e28af548cc11247ebd6e2825789af
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Sep 26 03:13:11 2015 +0200
ddebug: separate creation of debug files
This will be used by radeonsi for logging.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 3cd5395206398847d554ddf4cad49192042bd8ef
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Oct 3 13:23:13 2015 +0100
docs: add news item and link release notes for 10.6.9
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 61c35ce4f9ddfc3a36d6330f7feeca14ccbd8a86
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Oct 3 13:16:18 2015 +0100
docs: add sha256 checksums for 10.6.9
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit 8957b696f9cc8a92b2c160c551c34545447ec28a)
commit b2a987fc12fa9eac4781305fbf9196c7bec335dd
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Oct 3 12:37:15 2015 +0100
docs: add release notes for 10.6.9
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit ab9aacce2d26a802bac81fc25748320428996692)
commit 11cabc45b7124e51d5ead42db6dceb5a3755266b
Author: Matthew Waters <ystreet00 at gmail.com>
Date: Mon Sep 14 18:35:45 2015 +0100
egl: rework handling EGL_CONTEXT_FLAGS
As of version 15 of the EGL_KHR_create_context spec, debug contexts
are allowed for ES contexts. We should allow creation instead of
erroring.
While we're here provide a more comprehensive checking for the other two
flags - ROBUST_ACCESS_BIT_KHR and FORWARD_COMPATIBLE_BIT_KHR
v2 [Emil Velikov] Rebase. Minor tweak in commit message.
Cc: Boyan Ding <boyan.j.ding at gmail.com>
Cc: Chad Versace <chad.versace at intel.com>
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91044
Signed-off-by: Matthew Waters <ystreet00 at gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 443d3bf3408984b11f99c1077d167d8331609007
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Oct 2 18:31:17 2015 -0700
i965/wm: Make compute_barycentric_interp_modes take a nir_shader and a devinfo
Now that everything comes in through NIR, we can pick this directly out of
the shader source and don't need to reference the gl_fragment_program.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 1e3c1b107e075b210998998423901092b8fcd79b
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Oct 2 18:16:10 2015 -0700
i965: Use nir_foreach_variable
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 050e4787d3526b8341dd76b59442356f9737ee96
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Oct 2 18:15:06 2015 -0700
nir: Add a nir_foreach_variable macro
This is a common enough operation that it's nice to not have to think about
the arguments to foreach_list_typed every time.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit ca941799ce76eac8afe2503fbacffee057e949d3
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Oct 2 16:39:51 2015 -0700
i965/nir: Remove the prog parameter from brw_nir_lower_inputs
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit a2e1e3d325a70604151ef093ed741e60d078a21a
Author: Tom Stellard <thomas.stellard at amd.com>
Date: Thu Sep 24 16:29:56 2015 +0000
radeon/llvm: Initialize gallivm targets when initializing the AMDGPU target v2
This fixes a race condition in the glx-multithreaded-shader-compile
test.
v2:
- Replace gallivm_init_llvm_{begin,end}() with gallivm_init_llvm_targets().
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Mathias Fröhlich <Mathias.Froehlich at web.de>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
CC: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
commit 76cfd6f1da3748effb480e4f1151910af59fb88a
Author: Tom Stellard <thomas.stellard at amd.com>
Date: Thu Sep 24 15:57:02 2015 +0000
gallivm: Allow drivers and state trackers to initialize gallivm LLVM targets v2
Drivers and state trackers that use LLVM for generating code, must
register the targets they use with LLVM's global TargetRegistry.
The TargetRegistry is not thread-safe, so all targets must be added
to the registry before it can be queried for target information.
When drivers and state trackers initialize their own targets, they need
a way to force gallivm to initialize its targets at the same time.
Otherwise, there can be a race condition in some multi-threaded
applications (e.g. glx-multihreaded-shader-compile in piglit),
when one thread creates a context for a driver that uses LLVM (e.g.
radeonsi) and another thread creates a gallivm context (glxContextCreate
does this).
The race happens when the driver thread initializes its LLVM targets and
then starts using the registry before the gallivm thread has a chance to
register its targets.
This patch allows users to force gallivm to register its targets by
calling the gallivm_init_llvm_targets() function.
v2:
- Use call_once and remove mutexes and static initializations.
- Replace gallivm_init_llvm_{begin,end}() with
gallivm_init_llvm_targets().
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Mathias Fröhlich <Mathias.Froehlich at web.de>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
CC: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
commit 3219b48ae5a5b1288bf1fc1325ebbc7ac9e236df
Author: Tom Stellard <thomas.stellard at amd.com>
Date: Wed Sep 30 15:00:39 2015 +0000
gallium/radeon: Use call_once() when initailizing LLVM targets
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Mathias Fröhlich <Mathias.Froehlich at web.de>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
CC: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
commit bf7b6fd3fd6d98305d64ee6224ca9f9e7ba48444
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Oct 1 15:21:57 2015 -0700
i965/shader: Get rid of the shader, prog, and shader_prog fields
Unfortunately, we can't get rid of them entirely. The FS backend still
needs gl_program for handling TEXTURE_RECTANGLE. The GS vec4 backend still
needs gl_shader_program for handling transfom feedback. However, the VS
needs neither and we can substantially reduce the amount they are used.
One day we will be free from their tyranny.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 404419ee1a57c79982d93eefe4de099d61ad2eee
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Oct 1 18:15:21 2015 -0700
i965/fs,vec4: Get rid of the sanity_param_count
It doesn't exist for anything other than an assert that, as far as I can
tell, isn't possible to trip. Soon, we will remove prog from the visitor
entirely and this will become even more impossible to hit.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit ca6a436f12cb55e9415049a217229c99b02ad3b8
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Oct 1 15:22:23 2015 -0700
i965/vec4: Use nir info instead of pulling things out of [shader_]prog
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 756613ed35d6fd2216b5138731c0c38886b8e14a
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Oct 1 15:12:59 2015 -0700
i965/fs: Use the nir info instead of pulling things out of [shader_]prog
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit b62e36d18fac4a9c9977ddfa4bc2c2dbbcdad1b4
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Oct 1 16:38:59 2015 -0700
i965/fs: Move sampler unit lookup into rescale_texcoord
The texunit variable we create and assign in nir_emit_texture gets passed
through two more layers of function calls before it gets to its sole use in
rescale_texcoord. The best part is that we already pass the sampler into
rescale_texcoord so we can just look it up there.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 7b974c5f902b3f652776471aa35306195247a8a7
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Oct 1 13:52:21 2015 -0700
i965/cs: Remove the prog argument from local_id_payload_dwords
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 7926c3ea7d8f455cbee390d20c78dadf5432b9bc
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Oct 1 12:23:53 2015 -0700
i965/backend_shader: Add a field to store the NIR shader
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 7a8d06b6dd7800caab5c5c51d16b34e03aa45f25
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Oct 1 18:27:38 2015 -0700
nir: Move GS data to nir_shader_info
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit e4fea486da6ee2964ae15380bcdc8676dcc2a515
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Aug 5 17:14:59 2015 -0700
nir: Add a a nir_shader_info struct
This commit also adds code to glsl_to_nir and prog_to_nir to fill it out.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit cd1ae6ebfac22f76d26a5b8659423969b2aeddce
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Aug 5 16:39:32 2015 -0700
nir/glsl: Take a gl_shader_program and a stage rather than a gl_shader
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 30c63571133ed50907ec14172c2f3ef82ee8a34e
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Sep 30 17:01:03 2015 -0700
i965: Move prog_data uniform setup to the codegen level
As of now, uniform setup is more-or-less unified between vec4 and fs and no
longer requires the fs_visitor. This makes uniform setup more of a
language/API thing than a backend compiler thing. This commit moves
setting up the stage_prog_data.params arrays to the same place as we set up
the rest of stage_prog_data.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit ea006c4cb5eb2d98d6bfd5a6c32fcae10b636f17
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Oct 1 08:55:20 2015 -0700
i965: Move binding table setup to codegen time.
Setting up binding tables really has little to do with the actual process
of turning shaders into instructions; it's more part of setting up
prog_data. This commit moves it out of the visitors and with the rest of
the prog_data setup stuff.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 28709e37d96d6b64753ca4dcce5fbfeb75f5b499
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Oct 1 08:30:56 2015 -0700
i965/shader: Pull assign_common_binding_table_offsets out of backend_shader
This really has nothing to do with the backend compiler and we'd like to
eventually be able to set this up earlier in the compile process.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit cdf314cb21377ee7caca05bd1abab6a2b921d213
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Sep 30 17:37:36 2015 -0700
i965/nir: Simplify uniform setup
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 7fee8b6f055831bc070bb36d02a8b1c4d601652a
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Oct 2 10:45:53 2015 -0700
i965/nir: Pull GLSL uniform handling into a common function
The way we deal with GLSL uniforms and builtins is basically the same in
both the vec4 and the fs backend. This commit takes the best parts of both
implementations and pulls the common code into a shared helper function.
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 03c4171b577b06b1d8dde50b6eb9507d8ef4c1ce
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Sep 29 14:07:20 2015 -0700
i965/nir: Pull common ARB program uniform handling into a common function
The way we deal with ARB program uniforms is basically the same in both the
vec4 and the fs backend. This commit takes the best parts of both
implementations and pulls the common code into a shared helper function.
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 390b48fc4a9836b563560581fbfb4833546de0c8
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Sep 30 13:11:23 2015 -0700
i965/vec4: Use the uniform count from nir_assign_var_locations
Previously, we were counting up uniforms as we set them up. However, this
count should be exactly identical to shader->num_uniforms provided by
nir_assign_var_locations. (If it's not, we're in trouble anyway because
that means that locations don't match up.) This matches what the fs
backend is already doing.
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 3de81508ea513bf01f2c996c25a2cfdb5b3231d0
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Sep 30 11:47:01 2015 -0700
i965/shader: Get rid of the setup_vec4_uniform_value helper
It's not used by anything anymore
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 58cea0c2b63db236e6efcae930c5fb936181c2a9
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Sep 30 11:46:36 2015 -0700
i965/shader: Pull setup_image_uniform_values out of backend_shader
I tried to do this once before but Curro pointed out that having it in
backend_shader meant it could use the setup_vec4_uniform_values helper
which did different things in vec4 and fs. Now the setup_uniform_values
function differs only by an assert in the two backends so there's no real
good reason to be using it anymore.
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 5609e0d7b41e861a3359991e8d0f2053b255fc31
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Sep 30 11:02:14 2015 -0700
i965/vec4: Get rid of the uniform_vector_size array
The uniform_vector_size array was only ever used by pack_uniform_registers
which no longer needs it.
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit ea35fb0fbead2902b1ba37e7cdb1523853fabd8b
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Sep 30 10:31:03 2015 -0700
i965/vec4: Use the actual channels used in pack_uniform_registers
Previously, pack_uniform_registers worked based on the size of the uniform
as given to us when we initially set up the uniforms. However, we have to
walk through the uniforms and figure out liveness anyway, so we migh as
well record the number of channels used as we go. This may also allow us
to pack things tighter in a few cases.
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit cd2132f45b8aba7a47502d864b51c11519b4a8f0
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Sep 30 15:19:49 2015 -0700
glsl/types: Make subroutine types have a single matrix column
That way, if we do the usual thing of multiplying vector_elements by
matrix_columns we get the actual number of components in the type as per
component_slots().
While we're at it, we also switch to using the actual C++ field
initializers for vector_elements and matrix_columns.
Reviewed-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit a7e0f755bcb626ed8f8ca773b7d193dd82364513
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Sep 30 16:09:01 2015 -0700
i965: Pull stage_prog_data.nr_params out of the NIR shader
Previously, we had a bunch of code in each stage to figure out how many
slots we needed in stage_prog_data.param. This code was mostly identical
across the stages and had been copied and pasted around. Unfortunately,
this meant that any time you did something special, you had to add code for
it to each of these places. In particular, none of the stages took
subroutines into account; they were working entirely by accident. By
taking this data from the NIR shader, we know the exact number of entries
we need and everything goes a bit smoother.
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit fc3f45234b4ff9545c84fbe8ec5261604d5ab611
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Sep 30 16:06:43 2015 -0700
i965/vs: Move lazy NIR creation to codegen_vs_prog
The next commit will add code to codegen_vs_prog that requires the NIR
shader to be there in all cases. It doesn't hurt anything to just move it
from brw_vs_emit to its only caller.
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 64b145422b928bed75d3665e4149a323b7208470
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Sep 21 11:07:32 2015 -0700
i965/vec4: Delete the old vec4_vp code
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 1153f12076d121fd0213f58f1953872a60da041d
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Sep 21 11:03:29 2015 -0700
i965/vec4: Delete the old ir_visitor code
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit b85761d11d2abff4d45a4938b34c1c7840c97339
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Sep 21 10:42:19 2015 -0700
i965/vec4: Always use NIR
GLSL IR vs. NIR shader-db results for vec4 programs on i965:
total instructions in shared programs: 1499328 -> 1388354 (-7.40%)
instructions in affected programs: 1245199 -> 1134225 (-8.91%)
helped: 7469
HURT: 2440
GLSL IR vs. NIR shader-db results for vec4 programs on G4x:
total instructions in shared programs: 1436799 -> 1325825 (-7.72%)
instructions in affected programs: 1205599 -> 1094625 (-9.20%)
helped: 7469
HURT: 2440
GLSL IR vs. NIR shader-db results for vec4 programs on Iron Lake:
total instructions in shared programs: 1436654 -> 1325682 (-7.72%)
instructions in affected programs: 1205503 -> 1094531 (-9.21%)
helped: 7468
HURT: 2440
GLSL IR vs. NIR shader-db results for vec4 programs on Sandy Bridge:
total instructions in shared programs: 2016249 -> 1787033 (-11.37%)
instructions in affected programs: 1850547 -> 1621331 (-12.39%)
helped: 14856
HURT: 1481
GLSL IR vs. NIR shader-db results for vec4 programs on Ivy Bridge:
total instructions in shared programs: 1848027 -> 1648216 (-10.81%)
instructions in affected programs: 1660279 -> 1460468 (-12.03%)
helped: 14668
HURT: 1369
GLSL IR vs. NIR shader-db results for vec4 programs on Bay Trail:
total instructions in shared programs: 1848027 -> 1648216 (-10.81%)
instructions in affected programs: 1660279 -> 1460468 (-12.03%)
helped: 14668
HURT: 1369
GLSL IR vs. NIR shader-db results for vec4 programs on Haswell:
total instructions in shared programs: 1848027 -> 1648216 (-10.81%)
instructions in affected programs: 1660279 -> 1460468 (-12.03%)
helped: 14668
HURT: 1369
I also ran our full suite of benchmarks on a Haswell and had the following
statistically significant (according to ministat) changes:
Test master-glsl master-nir diff
bench_OglGeomPoint 461.556 463.006 1.450
bench_OglTerrainFlyInst 184.484 187.574 3.090
bench_OglTerrainPanInst 132.412 136.307 3.895
bench_OglTexFilterAniso 19.653 19.645 -0.008
bench_OglTexFilterTri 58.333 58.009 -0.324
bench_OglVSInstancing 65.049 65.327 0.278
bench_trexoff 69.474 69.694 0.220
bench_valley 40.708 41.125 0.417
v2 (Jason Ekstrand):
- Remove more uses of NirOptions as a switch
- New shader-db numbers
- Added benchmark numbers
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 4e0a8e0a50c9ac91cb7a70b92b8d9c6fcc02b7aa
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Oct 1 20:27:06 2015 -0400
i965: don't forget to free image_param on prog_data free
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 19598aaa5d0ea318ebd4a7e731bcaacaa4f3fe7c
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Oct 1 20:21:47 2015 -0400
glsl: avoid leaking hiddenUniforms map when there are no uniforms
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit da2fdf950fe754f9d38b3c2b8e73582ac92c4477
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Oct 1 20:18:19 2015 -0400
mesa: avoid leaking closure when iterating over a string_to_uint_map
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 6b7036498a9eed99c7f726d406d4638f97ddf0af
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Fri Oct 2 10:39:39 2015 -0700
nir: Fix uninitialized 'progress' variable in nir_lower_system_values.
Commit 0a1adaf11d051b71b4c46aabee2e5342f2d6aef3 (nir: Report progress
from nir_lower_system_values().) introduced a bug caught by Valgrind:
==823== Conditional jump or move depends on uninitialised value(s)
==823== at 0xB09020C: convert_block (nir_lower_system_values.c:68)
==823== by 0xB079FB8: foreach_cf_node (nir.c:1310)
==823== by 0xB07A0AF: nir_foreach_block (nir.c:1336)
==823== by 0xB09026B: convert_impl (nir_lower_system_values.c:79)
...
==823== Uninitialised value was created by a stack allocation
==823== at 0xB090249: convert_impl (nir_lower_system_values.c:76)
which is trivially fixed by initializing progress.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 33da78adeef0f0d71c70ac63c53ab70d6e7ebdc2
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Thu May 21 19:26:01 2015 -0400
nir/remove_phis: handle trivial back-edges
Some loops may have phi nodes that look like:
foo = ...
loop {
bar = phi(foo, bar)
...
}
in which case we can remove the phi node and replace all uses of 'bar'
with 'foo'. In particular, there are some L4D2 vertex shaders with loops
that, after optimization, look like:
/* succs: block_1 */
loop {
block block_1:
/* preds: block_0 block_4 */
vec1 ssa_2195 = phi block_0: ssa_2136, block_4: ssa_994
vec1 ssa_7321 = phi block_0: ssa_8195, block_4: ssa_7321
vec1 ssa_7324 = phi block_0: ssa_8198, block_4: ssa_7324
vec1 ssa_7327 = phi block_0: ssa_8174, block_4: ssa_7327
vec1 ssa_8139 = intrinsic load_uniform () () (232)
vec1 ssa_588 = ige ssa_2195, ssa_8139
/* succs: block_2 block_3 */
if ssa_588 {
block block_2:
/* preds: block_1 */
break
/* succs: block_5 */
} else {
block block_3:
/* preds: block_1 */
/* succs: block_4 */
}
block block_4:
/* preds: block_3 */
vec1 ssa_994 = iadd ssa_2195, ssa_2150
/* succs: block_1 */
}
where after removing the second, third, and fourth phi nodes, the loop becomes
entirely dead, and this patch will cause the loop to be deleted entirely.
No piglit regressions.
Shader-db results on bdw:
instructions in affected programs: 5824 -> 5664 (-2.75%)
total loops in shared programs: 2234 -> 2202 (-1.43%)
helped: 32
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Signed-off-by: Connor Abbott <cwabbott0 at gmail.com>
commit d35391cfda13afdb19a47003af260e258575ef45
Author: Kyle Brenneman <kbrenneman at nvidia.com>
Date: Mon Sep 28 12:12:05 2015 -0600
glx: Don't hard-code the name "libGL.so.1" in driOpenDriver (v3)
Add a macro GL_LIB_NAME to hold the filename that configure comes up with
based on the --with-gl-lib-name and --enable-mangling options.
In driOpenDriver, use the GL_LIB_NAME macro instead of hard-coding
"libGL.so.1".
v2: Add an #ifndef/#define for GL_LIB_NAME so that non-autoconf builds will
work.
v3: Fix the library filename in the Makefile.
Signed-off-by: Kyle Brenneman <kbrenneman at nvidia.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
commit 798f260a2f553e339d7f5fc5120bb627893dc740
Author: Kyle Brenneman <kbrenneman at nvidia.com>
Date: Mon Sep 28 11:59:22 2015 -0600
mapi: Make _glapi_get_stub work with "gl" or "mgl" prefix.
When USE_MGL_NAMESPACE is defined, _glapi_get_stub will check for the "m"
prefix before trying to skip it, so that "glFoo" and "mglFoo" are
equivalent.
This should let it work with all the places where something calls
_glapi_get_proc_offset with a hard-coded name that starts with the normal
"gl" prefix.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=55552
Signed-off-by: Kyle Brenneman <kbrenneman at nvidia.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
commit a27f2d991b1723c3349623401ce3c8f26dcdb28b
Author: Kyle Brenneman <kbrenneman at nvidia.com>
Date: Mon Sep 28 11:59:21 2015 -0600
glx: Fix build errors with --enable-mangling (v2)
Rearranged the GLX_ALIAS macro in glextensions.h so that it will pick up
the renames from glx_mangle.h.
Fixed the alias attribute for glXGetProcAddress when USE_MGL_NAMESPACE is
defined.
v2: Add a comment clarifying why GLX_ALIAS needs two macros.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=55552
Signed-off-by: Kyle Brenneman <kbrenneman at nvidia.com>
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 85313ff8ab1e3fad9679e05a97a7fd55ecf87291
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Fri Oct 2 10:08:55 2015 +0300
glsl: validate binding qualifier on block members
Fixes following Piglit test:
member-invalid-binding-qualifier.frag
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit f42466322a3c6f9dacf17caaf2b8f411e41ba7aa
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Wed Sep 30 15:03:15 2015 +0200
glsl: emit row_major matrix's SSBO stores only for components in writemask
When writing to a column of a row-major matrix, each component of the
vector is stored to non-consecutive memory addresses, so we generate
one instruction per component.
This patch skips the disabled components in the writemask, saving some
store instructions plus avoid storing wrong data on each disabled
component.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit a552b77dccacbbf68af3c527273085224b2b4480
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Thu Oct 1 14:54:33 2015 +0300
glsl: error out if non-constant indexing of SSBO arrays with GLSL ES
Fixes a failing subtest in:
ES31-CTS.shader_storage_buffer_object.negative-glsl-compileTime
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit b3f9c5cc0fab6d770d220efd87ba3746c6673875
Author: Daniel Scharrer <daniel at constexpr.org>
Date: Thu Oct 1 14:36:31 2015 +0200
mesa: Add abs input modifier to base for POW in ffvertex_prog
The result of POW for a negative base is undefined. Even when the result
is multiplied by zero (which is the case here whenever the base is
negative), the Inf and NaNs can propagate past that.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91342
Signed-off-by: Daniel Scharrer <daniel at constexpr.org>
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 604ce8253ae796ecf9763f1612e2fff25591cb07
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Aug 25 16:09:46 2015 -0700
i965/fs: Print reg and reg_offset separately for ATTR files.
Reading this output was really confusing. reg represents attribute
slots; reg_offset is the x/y/z/w component (0..3) within a vec4 slot.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 193d29516ddb76f469fea17119493e2b685bc6b7
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Aug 26 03:07:29 2015 -0700
i965/nir: Refactor input/output lowering setup into helpers.
The code for input lowering is going to get significantly more
complicated shortly, so I wanted to pull it out. Vertex shader inputs
are handled nearly identically regardless of vec4/scalar mode, so I
opted to not split that.
I thought about having each function actually do the lowering, but one
pass through nir_lower_io that handles all types (which weren't handled
earlier) is probably more efficient.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 39a1d36a67974dd9fc3c0d834d6a117cdfed8f33
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Aug 12 15:14:35 2015 -0700
nir: Allow nir_lower_io() to only lower one type of variable.
We may want to use different type_size functions for (e.g.) inputs
vs. uniforms. Passing in -1 for mode ignores this, handling all
modes as before.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 1c6689bf03fe500cc1bc55d7c2039c0aa3ae095c
Author: Brian Paul <brianp at vmware.com>
Date: Wed Sep 30 11:48:07 2015 -0600
mesa: fix incorrect error in _mesa_BindTextureUnit()
If the texture object exists, but the Name field is zero, it means
the object was created but never bound to a target. Trying to bind it
in _mesa_BindTextureUnit() should generate GL_INVALID_OPERATION.
Fixes piglit's arb_direct_state_access-bind-texture-unit test.
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit a9408f3ca14f2fb6286bd66bad06ee1bde0d8697
Author: Brian Paul <brianp at vmware.com>
Date: Wed Sep 30 11:37:16 2015 -0600
mesa: remove _mesa_get_tex_unit_err() and fix error handling
This helper was only called from _mesa_BindTextureUnit(). It's simpler
to just inline it.
The error check / code / message in the helper was incorrect. It was
written for glBindTextures(), not glBindTextureUnit(). The correct
error for a bad texture unit number is GL_INVALID_VALUE. The error
message now reports the unit number rather than a GL_TEXTUREi enum.
Fixes a failure in piglit's arb_direct_state_access-bind-texture-unit test.
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit c277fa394087272c79d65fc308d268fc768b91e5
Author: Brian Paul <brianp at vmware.com>
Date: Wed Sep 30 11:29:13 2015 -0600
mesa: consolidate texture binding code
Before, we were doing the actual _mesa_reference_texobj() call and
ctx->Driver.BindTexture() and misc housekeeping in three different
places. This consolidates the common code in a new bind_texture()
function.
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 78f908c54bc65a6433a47244aef45d234d909b3b
Author: Brian Paul <brianp at vmware.com>
Date: Wed Sep 30 08:58:09 2015 -0600
mesa: fix indentation in _mesa_create_nameless_texture()
commit aa249190a5df098c8a22d0e4649c58007d416c8a
Author: Brian Paul <brianp at vmware.com>
Date: Wed Sep 30 08:22:59 2015 -0600
st/mesa: clean up #includes in st_draw.c
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 82e3d8ba8b378467a40690770b7461ce0e1f1ea7
Author: Brian Paul <brianp at vmware.com>
Date: Wed Sep 30 08:22:32 2015 -0600
mesa: clean up #includes in sampler.cpp
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 32a4999ee7a6de0780eb467b9d5e74a2968bdae0
Author: Brian Paul <brianp at vmware.com>
Date: Wed Sep 30 08:22:05 2015 -0600
mesa: clean up #includes in ir_to_mesa.cpp
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit b9b13d873a659967da6bd70ddb57615e5df098bd
Author: Brian Paul <brianp at vmware.com>
Date: Wed Sep 30 08:21:41 2015 -0600
mesa: clean up #includes in uniforms.h
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit e13b5150449fbb2cb172157e59d4f848085c9386
Author: Brian Paul <brianp at vmware.com>
Date: Wed Sep 30 08:21:25 2015 -0600
mesa: clean up #includes in uniform_query.cpp
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 85ea1256207e9812fad1f3142fa20e561427fe8e
Author: Brian Paul <brianp at vmware.com>
Date: Wed Sep 30 08:21:02 2015 -0600
mesa: clean up #includes in pipelineobj.c
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 1a22550725d37923d1304654d9156362bdd43ec5
Author: Brian Paul <brianp at vmware.com>
Date: Wed Sep 30 08:14:04 2015 -0600
mesa: clean up #includes in ff_fragment_shader.cpp
Get rid of "../glsl/" paths. Sort alphabetically.
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 74553240301c60e3520fb55e09391993dac28f5d
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Tue Sep 29 13:34:20 2015 +0200
main: Fix block index when mixing UBO and SSBO blocks
Since we store both in UniformBlocks, we can't just compute the index by
subtracting the array address start, we need to count the number of
buffers of the approriate type.
v2:
- Just fall back to calc_resource_index (Tapani)
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit ca2e16d26ec46e604c76ab72d3ec14a7a8643cc8
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Wed Sep 30 20:38:13 2015 +0300
mesa: use strtok_s for strtok_r on windows
https://msdn.microsoft.com/en-us/library/ftsafwz3.aspx
v2: use _WIN32 instead of _MSC_VER (Brian Paul)
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92183
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 9bd9cf1fa402bf948020ee5d560259a5cfd2a739
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Sep 22 14:42:32 2015 -0700
meta: Handle array textures in scaled MSAA blits
The old code had some significant problems with respect to
sampler2DArray textures. The biggest problem was that some of the code
would use vec3 for the texture coordinate type, and other parts of the
code would use vec2. The resulting shader would not even compile.
Since there were not tests for this path, nobody noticed.
The input to the fragment shader is always treated as a vec3. If the
source data is only vec2, the vertex puller will supply 0 for the .z
component. The texture coordinate passed to the fragment shader is
always a vec2 that comes from the .xy part of the vertex shader input.
The layer, taken from the .z of the vertex shader input is passed
separately as a flat integer. If the generated fragment shader does not
use the layer integer, the GLSL linker will eliminate all the dead code
in the vertex shader.
Fixes the new piglit tests "blit-scaled samples=2 with
gl_texture_2d_multisample_array", etc. on i965.
Note for stable maintainer: This patch may depend on 46037237, and that
patch should be safe for stable.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Cc: Topi Pohjolainen <topi.pohjolainen at intel.com>
Cc: Jordan Justen <jordan.l.justen at intel.com>
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
commit b217e6f0351f185d7181712db2871611de2f89ea
Author: Chad Versace <chad.versace at intel.com>
Date: Fri Sep 25 11:16:13 2015 -0700
i965/miptree: Add PRM references for most struct members (v2)
Add comments that link the driver's miptree structures to the hardware
structures documented in the PRM. This provides sorely needed
orientation to developers new to the miptree code. And for miptree
veterans, this clarifies some of the more obscure miptree data.
For each driver struct field that closely corresponds to a
hardware struct field, add a PRM reference to that hardware field's
name. For example,
struct intel_mipmap_tree {
...
/**
* @brief One of GL_TEXTURE_2D, GL_TEXTURE_2D_ARRAY, etc.
*
* @see RENDER_SURFACE_STATE.SurfaceType
* @see RENDER_SURFACE_STATE.SurfaceArray
* @see 3DSTATE_DEPTH_BUFFER.SurfaceType
*/
GLenum target;
...
};
Also annotate the INTEL_MSAA_LAYOUT_* enums with the name of the PRM
sections that documents the layout.
v2: Replace "2D subimage" with "slice", and define what a "slice" is.
For Ben.
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com> (v1)
Reviewed-by: Ben Widawsky <benjamin.widawsky at intel.com> (v1)
commit f7fe9fb0f19196f74864e0b0f57ac61c066c9d10
Author: Chad Versace <chad.versace at intel.com>
Date: Fri Sep 25 10:04:48 2015 -0700
i965/miptree: Rename align_w,align_h -> halign,valign
The values of intel_mipmap_tree::align_w and ::align_h correspond to the
hardware enums HALIGN_* and VALIGN_*.
See the confusion?
align_h != HALIGN
align_h == VALIGN
Reduce the confusion by renaming the variables to match the hardware
enum names:
git ls-files |
xargs sed -i -e 's/align_w/halign/g' \
-e 's/align_h/valign/g'
Suggested-by: Kenneth Graunke <kenneth at whitecape.org>
Acked-by: Ben Widawsky <benjamin.widawsky at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 56367b0290919651e4c104b3e798cc5588272d3c
Author: Chad Versace <chad.versace at intel.com>
Date: Fri Sep 25 09:52:26 2015 -0700
i965/miptree: Rename intel_miptree_map::mt -> ::linear_mt (v2)
Because that's what it is. It's an untiled, *linear* miptree.
v2:
- Add space after /*.
- Use one comment per function argument.
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Acked-by: Ben Widawsky <benjamin.widawsky at intel.com>
commit b7882ae6777d53b32f1625c6270cdc95e5b7b802
Author: Chad Versace <chad.versace at intel.com>
Date: Fri Sep 25 09:46:19 2015 -0700
i965/miptree: Fix comments for map mode
The comment for intel_miptree_map::mode claimed that it was a bitmask of
GL_MAP_{READ,WRITE,INVALIDATE}_BIT. In reality, the bitmask may include
any of {GL,BRW}_MAP_*_BIT.
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Acked-by: Ben Widawsky <benjamin.widawsky at intel.com>
commit bd191b7cc614f0c74320fff09d84c2cfaa7b8fcd
Author: Chad Versace <chad.versace at intel.com>
Date: Fri Sep 25 09:44:22 2015 -0700
i965/miptree: More comments for BRW_MAP_DIRECT_BIT (v2)
Clarify that this bit extends the set of GL_MAP_*_BIT enums.
Also fix typo of "temporary".
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Acked-by: Ben Widawsky <benjamin.widawsky at intel.com>
commit 651395b6e8332160023ecdddb45b03a313d26077
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Sep 30 09:13:08 2015 -0700
i965: Remove duplicate copy of is_scalar_shader_stage().
Jason open coded this in 60befc63 when cleaning up some ugly code;
using our existing helper tidies it up a bit more.
v2: Drop inline (suggested by Matt).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit a1a3f0961b20907b6948959c1f224bb055bd4f3d
Author: Ville Syrjälä <ville.syrjala at linux.intel.com>
Date: Mon Mar 23 14:47:33 2015 +0200
i915: Remember to call intel_prepare_render() before blitting
Bring over the following fix from i965:
commit fb3d62fe3d4fc40ba4ad9804d8b6f451316c9ae2
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Aug 6 14:36:09 2013 -0700
i965: Remember to call intel_prepare_render() before blitting.
Fixes a crash in the following piglit tests:
bin/fbo-sys-blit -auto
bin/fbo-sys-sub-blit -auto
Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
commit c349031c27b7f66151f07d785625c585e10a92c2
Author: Ville Syrjälä <ville.syrjala at linux.intel.com>
Date: Mon Mar 23 14:47:36 2015 +0200
i915: Fix texcoord vs. varying collision in fragment programs
i915 fragment programs utilize the texture coordinate registers
for both texture coordinates and varyings. Unfortunately the
code doesn't check if the same index might be in use for both.
It just naively uses the index to pick a texture unit, which
could lead to collisions.
Add an extra mapping step to allocate non conflicting texture
units for both uses.
The issue can be reproduced with a pair of simple shaders like
these:
attribute vec4 in_mod;
varying vec4 mod;
void main() {
mod = in_mod;
gl_TexCoord[0] = gl_MultiTexCoord0;
gl_Position = gl_ModelViewProjectionMatrix * gl_Vertex;
}
varying vec4 mod;
uniform sampler2D tex;
void main() {
gl_FragColor = texture2D(tex, vec2(gl_TexCoord[0])) * mod;
}
Fixes many piglit tests on i915:
glsl-link-varyings-2
glsl-orangebook-ch06-bump
interpolation-none-gl_frontcolor-smooth-fixed
interpolation-none-gl_frontcolor-smooth-none
interpolation-none-gl_frontcolor-smooth-vertex
interpolation-none-gl_frontsecondarycolor-smooth-fixed
interpolation-none-gl_frontsecondarycolor-smooth-vertex
interpolation-none-gl_frontsecondarycolor-smooth-none
interpolation-none-other-flat-fixed
interpolation-none-other-flat-none
interpolation-none-other-flat-vertex
interpolation-none-other-smooth-fixed
interpolation-none-other-smooth-none
interpolation-none-other-smooth-vertex
v2 [idr]: Minor formatting tweaks.
Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
commit 9504740f3e6698d860ac93310a33f51f01c10c4f
Author: Ville Syrjälä <ville.syrjala at linux.intel.com>
Date: Mon Mar 23 14:47:24 2015 +0200
i830: Fix collision between I830_UPLOAD_RASTER_RULES and I830_UPLOAD_TEX(0)
I830_UPLOAD_RASTER_RULES and I830_UPLOAD_TEX(0) are trying to occupy
the same bit. Move the texture bits upwards a bit to make room for
I830_UPLOAD_RASTER_RULES.
Now the driver will actually upload the raster rules which is rather
important to get the provoking vertex right. Fixes the appearance
of glxgears teeth on gen2.
Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
commit 7b391142e9da6186221a9eb39977e487f079ef72
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Tue Sep 29 17:04:03 2015 -0700
i965/cs: Upload UBO/SSBO surfaces
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit 83018f5c20a2a1b48f88704a25ebb8410b2f9c71
Author: Rhys Kidd <rhyskidd at gmail.com>
Date: Wed Sep 30 23:18:52 2015 +1000
mesa: Fix format specifier warning in mesa_DispatchComputeIndirect()
Commit 1665d29ee3125743fd6daf3c43fc715f543d5669 introduced an incorrect
format specifier that operates on GLintptr indirect within the function
_mesa_DispatchComputeIndirect().
This patch mitigates the introduced GCC warning:
src/mesa/main/compute.c: In function '_mesa_DispatchComputeIndirect':
src/mesa/main/compute.c:53:7: warning: format '%d' expects argument of type 'int', but argument 3 has type 'GLintptr' [-Wformat=]
_mesa_debug(ctx, "glDispatchComputeIndirect(%d)\n", indirect);
^
v2: Amend for Boyan Ding <boyan.j.ding at gmail.com> feedback.
Signed-off-by: Rhys Kidd <rhyskidd at gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 3948ac19a40663bd00deb84518ac747daa5f401f
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Sep 29 18:06:49 2015 -0700
i965: Get rid of prog_data compare functions
They are no longer used.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit bfdc76c133bb9e91049824b7480f862f142e4195
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Sep 29 18:05:55 2015 -0700
i965/state_cache: Remove the aux_compare fields
They haven't been used since 1bba29ed403e735ba0bf04ed8aa2e571884fcaaf so
there's no good reason to keep them around.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit a4734b34b3928ca6150b8d93f402da54ed69e6e7
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Sep 28 16:57:27 2015 -0700
i965/copy_image: Fix a copy+past error
Reported-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 70e91d61fde239e8ae58148cacd4ff891126e2aa
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Fri Aug 7 21:13:12 2015 +0100
i965: Remove early release of DRI2 miptree
intel_update_winsys_renderbuffer_miptree() will release the existing
miptree when wrapping a new DRI2 buffer, so we can remove the early
release and so prevent a NULL mt dereference should importing the new
DRI2 name fail for any reason. (Reusing the old DRI2 name will result
in the rendering going astray, to a stale buffer, and not shown on the
screen, but it allows us to issue a warning and not crash much later in
innocent code.)
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86281
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit e21bb9e7bdea0f73809759d3c248048eedd79663
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Mon Sep 28 11:47:33 2015 +0200
glsl: assert base_alignment > 0 for records
From GLSL 1.50 spec, section 4.1.8 "Structures":
"Structures must have at least one member declaration."
So the base_alignment should be higher than zero.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit f3afcbecc63ec565a0386cda554d145ca908367d
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Tue Sep 29 16:10:02 2015 +0200
util: use strnlen() in strndup() implementations
If the string being copied is not NULL-terminated the result of
strlen() is undefined.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Neil Roberts <neil at linux.intel.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 023165a734b3bae52a449ad01bc1ea5ba4384ec1
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Tue Sep 15 11:16:29 2015 +0200
i965/vec4/nir: add nir_intrinsic_memory_barrier support
Fix OpenGL ES 3.1 conformance tests: advanced-readWrite-case1-vsfs
and advanced-matrix-vsfs.
v2:
- Fix SHADER_OPCODE_MEMORY_FENCE emission and the allocation of 'tmp'
(Francisco).
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Tested-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit f24e5e68d6bd640da2d9a3ae1cf7898ef9ed2fce
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Wed Sep 16 15:47:34 2015 +0200
glsl: apply shader storage block member rules when adding program resources
From ARB_program_interface_query:
"For an active shader storage block member declared as an array, an
entry will be generated only for the first array element, regardless
of its type. For arrays of aggregate types, the enumeration rules are
applied recursively for the single enumerated array element."
v2:
- Simplify 'if' conditions and return true if it is not a buffer
variable, because these rules only apply to buffer variables (Timothy).
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
commit 4810d02112b7d056d5355ec9fd8953a4e763fd26
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Fri Sep 25 14:49:37 2015 -0700
nir: Don't set dest in SSBO store glsl_to_nir conversion
This matches the function signature created in
lower_ubo_reference_visitor::ssbo_store which has a void return.
Suggested-by: Jason Ekstrand <jason at jlekstrand.net>
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit 476e6d732f76f1ac1c4560ccade7cbc93f985d09
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Sep 23 15:40:33 2015 -0700
nir: Use a system value for gl_PrimitiveIDIn.
At least on Intel hardware, gl_PrimitiveIDIn comes in as a special part
of the payload rather than a normal input. This is typically what we
use system values for. Dave and Ilia also agree that a system value
would be nicer.
At some point, we should change it at the GLSL IR level as well. But
that requires changing most of the drivers. For now, let's at least
make NIR do the right thing, which is easy.
v2: Add a comment about not creating a temporary (suggested by Iago).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit cb758b892a7e62ff1f6187f2ca9ac543ff70a096
Author: Brian Paul <brianp at vmware.com>
Date: Thu Sep 24 09:36:44 2015 -0600
st/mesa: try PIPE_BIND_RENDER_TARGET when choosing float texture formats
For 8-bit RGB(A) texture formats we set the PIPE_BIND_RENDER_TARGET flag
to try to get a hardware format which also supports rendering (for FBO
textures). Do the same thing for floating point formats.
This allows the Redway3D Flat demo to run.
Cc: 10.6 11.0 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit daf23bd4cb944e1d78664b6780a78d021c0cec79
Author: Brian Paul <brianp at vmware.com>
Date: Thu Sep 24 09:34:48 2015 -0600
st/mesa: add some debugging code in st_ChooseTextureFormat()
I've temporarily added code like this many times. Wrap it in a
conditional that can be enabled when needed.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 7147f7098e55e3d2e62516a54c1ff8e77c9052d0
Author: Brian Paul <brianp at vmware.com>
Date: Sat Sep 26 20:22:21 2015 -0600
mesa: clean up #includes in shaderapi.c
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit b24c6d3fefabf456e19b26a0a581ae53eb3d2d19
Author: Brian Paul <brianp at vmware.com>
Date: Sat Sep 26 20:19:40 2015 -0600
mesa: clean up the #includes in shader_query.cpp
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 3bbff1e26ee8bbf63f7a954c3f24d514486939e5
Author: Brian Paul <brianp at vmware.com>
Date: Sat Sep 26 20:14:57 2015 -0600
mesa: remove an extern "C" wrapper in shader_query.cpp
The shaderapi.h header already has the extern "C" wrapper.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 681b4badaedec5c9503887c4afb32485ce22c30e
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Thu Sep 24 01:45:40 2015 -0700
i965/cs: Generate code to load gl_NumWorkGroups
This code also sets cs_prog_data->uses_num_work_groups which is later
used by state setup to indicate that the gl_NumWorkGroups surface
needs to be setup.
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 4c6ddd3397f9ec363342831eab710003996e77a8
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Sat Aug 22 18:51:08 2015 -0700
nir: Convert SYSTEM_VALUE_NUM_WORK_GROUPS to a nir intrinsic
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit f6ae91406966c0fdcfcd628539e34964ae0ab1a6
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Thu Aug 20 15:56:53 2015 -0700
glsl/cs: Add gl_NumWorkGroups as a system value
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 63d7b33f516815ce3f9b3bb1b26a39f1545a4446
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Thu Sep 24 01:29:32 2015 -0700
i965/cs: Setup surface binding for gl_NumWorkGroups
This will only be setup when the prog_data uses_num_work_groups
boolean is set.
At this point nothing will set uses_num_work_groups, but soon code
will set it when emitting code for the intrinsic that loads
gl_NumWorkGroups.
We can't emit this surface information earlier at the start of the
DispatchCompute* call because we may not have generated the program
yet. Until we generate the program, we don't know if the
gl_NumWorkGroups variable is accessed.
We also can't emit the surface as part of the brw_cs_state atom,
because we might not need the surface if gl_NumWorkGroups is not used
by the program.
Lastly, we cannot emit the surface later (after state upload) in the
DispatchCompute* call, because it needs to be run before the
brw_cs_state atom is emitted, since it changes the surface state.
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit d1be9d21265cf4e344a5d78b17cea7ee2c8408a1
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Thu Sep 24 01:20:55 2015 -0700
i965/cs: Add a binding table entry for gl_NumWorkGroups
If glDispatchComputeIndirect is used, then the value for this variable
must be read from the indirect BO.
To allow the same generated code to support indirect and
glDispatchCompute, we will also setup a BO for the number of work
groups using the intel_upload_data mechanism. This will only be
required if the gl_NumWorkGroups variable is accessed.
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit d57a85f32b2242e19c2d20e91af0218d41e1e9fe
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Thu Sep 24 01:06:56 2015 -0700
i965/cs: Store compute invocation information in brw context
We will need this in an atom to setup a surface to read the
gl_NumWorkGroups values from.
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 60cf84dea7dfe2749d774b487079684d6a613afc
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Thu Sep 24 00:26:59 2015 -0700
i965/cs: Re-emit cs_state when surfaces have changed
Unlike rendering (BINDING_TABLE_POINTERS_*S), compute doesn't have a
binding table pointers command. Instead it is part of the
MEDIA_INTERFACE_DESCRIPTOR structure loaded by the brw_cs_state atom.
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 2ec5f3e1d5616f9e5c223a9f48d4b1a0d2568225
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Thu Sep 24 00:25:27 2015 -0700
i965/cs: Re-emit push constants and cs_state on new batches
We need to re-emit push constansts when a new batch is started since
the push constants are stored in the batch. We also need to re-emit
the MEDIA_INTERFACE_DESCRIPTOR (in brw_cs_state) since it is stored in
the batch.
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 1665d29ee3125743fd6daf3c43fc715f543d5669
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Thu Sep 24 00:19:58 2015 -0700
mesa/cs: Add MESA_VERBOSE=api support in DispatchCompute*
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 952366a60e0743ae025edaf370a233d0633edf7b
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Tue Sep 29 16:01:22 2015 +0100
util: Fix strndup prototype on C++.
Trivial.
commit c0722be9f58ef89dae98d8c459ec4f9589f97748
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Mon Aug 3 08:58:20 2015 +0300
mesa: fix ARRAY_SIZE query for GetProgramResourceiv
Patch also refactors name length queries which were using array size
in computation, this has to be done in same time to avoid regression in
arb_program_interface_query-resource-query Piglit test.
Fixes rest of the failures with
ES31-CTS.program_interface_query.no-locations
v2: make additional check only for GS inputs
v3: create helper function for resource name length
so that it gets calculated only in one place
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
commit 12d510ab742baad88d624585938c723ffedbcae7
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Mon Sep 28 12:59:35 2015 +0200
glsl: Fix forward NULL dereference coverity warning
The comment says that it should be impossible for decl_type to be NULL
here, so don't try to handle the case where it is, simply add an assert.
>>> CID 1324977: Null pointer dereferences (FORWARD_NULL)
>>> Comparing "decl_type" to null implies that "decl_type" might be null.
No piglit regressions observed.
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
commit 1dc2db7a4dfb0e88a51a27c2234b6a01dead80bf
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Mon Sep 28 12:59:34 2015 +0200
glsl: Fix null return coverity warning
Add an assert on the result of as_dereference() not being NULL:
>>> CID 1324978: Null pointer dereferences (NULL_RETURNS)
>>> Dereferencing a null pointer "deref_record->record->as_dereference()".
Since we are introducing a new variable to hold the result of
as_dereference(), take the opportunity to rename deref_record_type to
interface_type and just name the new variable interface_deref, which is
less confusing.
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 6bf718fec22f605702c7d15503d4dbc3c2be35e6
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Mon Sep 28 12:59:33 2015 +0200
glsl: Fix unused value warning reported by Coverity
We don't use param in this part of the code, so no point in advancing
the pointer forward:
>>> CID 1324983: Code maintainability issues (UNUSED_VALUE)
>>> Assigning value from "param->get_next()" to "param" here, but that stored value is overwritten before it can be used.
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit bea66d22f2c0e97242c15652376ae4e82779f343
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Mon Sep 28 14:23:34 2015 +0200
util: implement strndup for WIN32
v2:
- Add strndup.h to Makefile.sources (Emil)
- Use calloc instead of malloc (Emil).
- Check if allocation fails (Emil, Jose)
- Add '#pragma once' and include stdlib.h to strndup.h (Jose)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92124
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 7efb2350199f7ea5acbadb76a1a19eda75b45a45
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Fri Sep 11 12:31:10 2015 +0200
glsl: use correct number of uniform blocks in error message
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
commit 6668eb5a451c43ac78a784711cf239fdf7ca75ef
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Fri Sep 11 12:29:37 2015 +0200
mesa: rename gl_shader_program's NumUniformBlocks to NumBufferInterfaceBlocks
Because it counts shader storage blocks too.
v2:
- Use NumBufferInterfaceBlocks instead (Jordan).
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 38004eb17ce9663a4343bae4e783e97e73596e9c
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Fri Sep 11 10:02:56 2015 +0200
main: fix ACTIVE_UNIFORM_BLOCKS value
NumUniformBlocks also counts shader storage blocks.
NumUniformBlocks variable will be renamed in a later patch to avoid
misunderstandings.
v2:
- Modify the condition to use !IsShaderStorage and the list of
uniform blocks (Timothy)
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
commit 589249a792a1db04a3cb41a8e319dabacf3e6123
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Tue Sep 29 00:22:32 2015 +0100
docs: add news item and link release notes for 11.0.2
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit dda02d202efa3cdf34a498af85d9c841c7dd9c37
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Tue Sep 29 00:19:36 2015 +0100
docs: add sha256 checksums for 11.0.2
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit 4c0b48461269d3ede0c5446d86ebe3e81f16788e)
commit 58e02b2a4e2beaed1d173276121bc033063a1988
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Sep 28 20:45:37 2015 +0100
docs: add release notes for 11.0.2
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit 51e0b06d9916e126060c0d218de1aaa4e5a4ce26)
commit 945592f92ca91e21307d10b657835d512bacf8b8
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Fri Jul 24 14:52:01 2015 -0700
i965/gen9: Add a condition for starting pixel in fast copy blit
This condition restricts the use of fast copy blit to cases
where starting pixel of src and dst is oword (16 byte) aligned.
Many piglit tests (if using fast copy blit in Mesa) failed earlier
because I missed adding this condition.Fast copy blit is currently
enabled for use only with Yf/Ys tiling.
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit 1d8cba9b51b7a6e7dbf3f0d3f53b5c232fd0b5b2
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Sep 28 15:18:08 2015 -0400
nouveau: wait to unref the transfer's bo until it's no longer used
The bo will often come from a slab in which case it doesn't matter. But
for larger allocations this will be in its own bo, and we have to make
sure to wait until it's no longer used in order for it to be freed.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org
Tested-by: Marcin Åšlusarz <marcin.slusarz at gmail.com>
commit 3a6b9a7830c3df14ffcfbbf57c82ea08bd59ef04
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Sep 25 19:05:14 2015 -0400
nouveau: delay deleting buffer with unflushed fence
If there is an unflushed fence on the bo, then the resource may still be
used in commands built up in the local pushbuf. Flushing can cause all
sorts of unwanted effects, so just free the bo when the relevant fence
is hit.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org
Tested-by: Marcin Åšlusarz <marcin.slusarz at gmail.com>
commit d4e650b07bc80075f0d088e7d85df9efa45e11bd
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Sep 25 16:34:07 2015 -0400
nouveau: be more careful about freeing temporary transfer buffers
Deleting a buffer does not flush the command stream. Make sure that we
wait for the copies to finish before deleting the temporary bo.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org
Tested-by: Marcin Åšlusarz <marcin.slusarz at gmail.com>
commit 4c5308bbf4fa5c6ac274f6e1ab7c8846a2866976
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Wed Aug 19 16:26:59 2015 -0700
i965: Rename intel_miptree_get_dimensions_for_image()
This function isn't specific to miptrees. So, drop the "miptree"
from function name.
V3: Add a comment explaining how the 1D Array texture height and
depth is interpreted by Intel hardware.
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit 0bfd914f9f02c85a4ad8e6892f1a31e37c14f2b2
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Tue Aug 11 16:36:44 2015 -0700
i965/gen9: Fix {src, dst}_pitch alignment check for XY_FAST_COPY_BLT
I misinterpreted the alignmnet restriction in XY_FAST_COPY_BLT earlier.
Instead of checking pitch for 64KB alignmnet we need to check it for
tile widh alignment.
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit 0fa39bff19dc2fbd3c184bd0e1267c86bd5040d9
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Tue Aug 11 16:31:39 2015 -0700
i965: Fix {src, dst}_pitch alignment check for XY_SRC_COPY_BLT
Current code checks the alignment restrictions only for Y tiling.
From Broadwell PRM vol 10:
"pitch is of 512Byte granularity for Tile-X: This means the tiled-x
surface pitch can be (512, 1024, 1536, 2048...)/4 (in Dwords)."
This patch adds the restriction for X tiling as well.
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit e83b07aa7b124184decd68a64d970e8f408f8725
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Tue Aug 11 16:30:34 2015 -0700
i965: Move conversion of {src, dst}_pitch to dwords outside if/else
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit 485285498f39aa9590d430dee6d52c796531b8c0
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Tue Aug 11 16:26:39 2015 -0700
i965: Delete temporary variable 'src_pitch'
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit bbbc9fd8e5e2a4434c8630eacd7943d59aa73c47
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Thu Jul 9 10:47:17 2015 -0700
i965: Use helper function intel_get_tile_dims() in surface setup
It takes care of using the correct tile width if we later use other
tiling patterns for aux miptree.
V2: Remove the comment about using Yf for aux miptree.
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit 1dc41be9ebd07825836b0ca4b98e00ffc7ecc0ec
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Tue Aug 18 15:47:13 2015 -0700
i965: Use intel_get_tile_dims() to get tile masks
This will require change in the parameters passed to
intel_miptree_get_tile_masks().
V2: Rearrange the order of parameters. (Ben)
Change the name to intel_get_tile_masks(). (Topi)
V3: Use temporary variables in intel_get_tile_masks()
for clarity. Fix mask_y computation.
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit 21fdc59d349eb396b48f0919dfd1a8dc234b96b1
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Tue Aug 18 15:48:56 2015 -0700
i965: Add a helper function intel_get_tile_dims()
V2:
- Do the tile width/height computations in the new helper
function and use it later in intel_miptree_get_tile_masks().
- Change the name to intel_get_tile_dims().
V3: Return the tile_h in number of rows in place of bytes.
Document the units of tile_w, tile_h parameters.
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit 5edd9961c15a80d557ba42f48c97a471b23d9c5e
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Thu Sep 24 10:57:43 2015 +0200
mesa: Use the effective internal format instead for validation
When validating format+type+internalFormat for texture pixel operations
on GLES3, the effective internal format should be used if the one
specified is an unsized internal format. Page 127, section "3.8 Texturing"
of the GLES 3.0.4 spec says:
"if internalformat is a base internal format, the effective internal
format is a sized internal format that is derived from the format and
type for internal use by the GL. Table 3.12 specifies the mapping of
format and type to effective internal formats. The effective internal
format is used by the GL for purposes such as texture completeness or
type checks for CopyTex* commands. In these cases, the GL is required
to operate as if the effective internal format was used as the
internalformat when specifying the texture data."
v2: Per the spec, Luminance8Alpha8, Luminance8 and Alpha8 should not be
considered sized internal formats. Return the corresponding unsize format
instead.
v4: * Improved comments in
_mesa_es3_effective_internal_format_for_format_and_type().
* Splitted patch to separate chunk about reordering of
error_check_subtexture_dimensions() error check, which is not directly
related with this patch.
v5: Dropped the splitted patch because it was actually a work around 3
dEQP tests that are buggy:
dEQP-GLES2.functional.negative_api.texture.texsubimage2d_neg_offset
dEQP-GLES2.functional.negative_api.texture.texsubimage2d_offset_allowed
dEQP-GLES2.functional.negative_api.texture.texsubimage2d_neg_wdt_hgt
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Tested-by: Mark Janes <mark.a.janes at intel.com>
commit c6bf1cd1467ea5d5370394ba99366dd8a59a385c
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Thu Sep 24 10:57:42 2015 +0200
mesa: Move _mesa_base_tex_format() from teximage to glformats files
This function will be needed as part of validating the combination of format,
type and internal format of texture pixel operations, which happens in
glformats files. Specifically, we want to be able to obtain the base format
of a resolved effective internal format, to compare it with the original
internal format passed.
Also, since this function deals solely with GL formats, it fits better in
glformats where the rest of similar format functionality rests.
The function is moved as-is, without any modification.
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Tested-by: Mark Janes <mark.a.janes at intel.com>
commit 15ab968f62dd322ecda6d70b1069f52616fe39bb
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Thu Sep 24 10:57:41 2015 +0200
mesa: Fix order of format+type and internal format checks for glTexImageXD ops
The more specific GLES constrains should be checked after the general
validation performed by _mesa_error_check_format_and_type(). This is also
for consistency with the error checks order of glTexSubImage ops.
v3: The change of order uncovered a bug that regresses a couple of piglit
tests written against OpenGL-ES 1.1 spec, which expects an INVALID_VALUE
instead of the INVALID_ENUM returned by _mesa_error_check_format_and_type()
when an invalid format is passed to glTexImage2D. This version of the patch
accounts for those cases.
Fixes 1 dEQP test:
* dEQP-GLES3.functional.negative_api.texture.teximage2d
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Tested-by: Mark Janes <mark.a.janes at intel.com>
commit 7cdd818d2ae82f0cc81ebbc58ae6c95e6d649ba2
Author: Alexander von Gluck IV <kallisti5 at unixzen.com>
Date: Sat Sep 26 11:49:36 2015 -0500
egl: Fix missing Haiku include path
commit 255a225265bb29fab828e8f0d1b10246718895c2
Author: Alexander von Gluck IV <kallisti5 at unixzen.com>
Date: Sat Sep 26 11:39:09 2015 -0500
state_trackers/hgl: Fix missing include path
commit b61292296bd7e1876fdb64725a783a7e96f6c4c1
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Aug 26 21:59:46 2015 +0300
i965/fs: Fix hang on IVB and VLV with image format mismatch.
IVB and VLV hang sporadically when an untyped surface read or write
message is used to access a surface of format other than RAW, as may
happen when there is a mismatch between the format qualifier of the
image uniform and the format of the actual image bound to the
pipeline. According to the spec this condition gives undefined
results but may not lead to program termination (which is one of the
possible outcomes of the hang). Fix it by checking at runtime whether
the surface is of the right type.
Fixes the "arb_shader_image_load_store.invalid/format mismatch" piglit
subtest.
Reported-by: Mark Janes <mark.a.janes at intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91718
CC: mesa-stable at lists.freedesktop.org
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 2518645f63e2f66d3638180f44a007541928319c
Author: Serge Martin <edb+mesa at sigluy.net>
Date: Sat Sep 19 23:16:10 2015 +0200
clover: Implement clCreateImage?D w/ clCreateImage.
Remplace clCreateImage2D and clCreateImage3D implementation with call
to clCreateImage.
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit f2c52e392bdaa9ce9b9075996eb5efafde142030
Author: Serge Martin <edb+mesa at sigluy.net>
Date: Sat Sep 19 23:16:09 2015 +0200
clover: Implement CL1.2 clCreateImage().
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 92666b90c0db8bb51fd54bcf22db3d288a5556e7
Author: Francisco Jerez <currojerez at riseup.net>
Date: Fri Sep 18 18:42:55 2015 +0200
clover: Move down canonicalization of memory object flags into validate_flags().
This will be used to share the same logic between buffer and image
creation.
v2: Make memory flag set constants local to validate_flags. (Serge
Martin)
commit 2b9248dc58c1aec1fe6e7fd4cb07ee883f70161b
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Fri Sep 25 09:52:45 2015 +0200
docs: mention ARB_shader_storage_buffer_object on 11.1.0 release notes
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
commit e7ae6d9e141489281295352e43facbc1aeb137d9
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Mon Sep 28 13:56:28 2015 +0200
glsl: revert "glsl: atomic counters can be declared as buffer-qualified variables"
This reverts commit 586142658e2927a68c.
The specs are not explicit about any restrictions related to the types allowed
on buffer variables, however, the description of opaque types (like atomic
counters) is in conclict with the purpose of buffer variables:
"The opaque types declare variables that are effectively opaque
handles to other objects. These objects are
accessed through built-in functions, not through direct reading or
writing of the declared variable.
(...)
Opaque variables cannot be treated as l-values;(...)"
Also, Mesa is already disallowing opaque types in interface blocks anyway, so
that commit was not really achieving anything.
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 5bff12ecb403356d7848dc02696c618b68a324f1
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Sep 26 13:45:28 2015 -0400
gallium/util: avoid unreferencing random memory on buffer alloc failure
Found by Coverity
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Albert Freeman <albertwdfreeman at gmail.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 6dd059fefe2c8c8a5337a646ab8772ebad8f811b
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Sep 26 13:37:02 2015 -0400
mesa: don't leak interface_name
Found by Coverity
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
commit e413d2fbc4b37eb552ee42940fb792e504233e51
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Mon Sep 28 11:03:19 2015 +1000
glsl: fix component size calculation for tessellation and geom shaders
Broken in commit abdab88b30ab when adding arrays of arrays support
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit 3c63a2d2f02d9f94f0b633c39508df1269fb7dab
Author: Boyan Ding <boyan.j.ding at gmail.com>
Date: Sun Sep 27 17:15:28 2015 +0800
docs/GL3.txt: fix typo
Signed-off-by: Boyan Ding <boyan.j.ding at gmail.com>
Reviewed-by: Albert Freeman <albertwdfreeman at gmail.com>
commit d6a41b5f70b9071cca8959afab66a6504e7cb7ce
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Sep 25 08:21:57 2015 -0700
i965/gs: Optimize away the EOT write on Gen8+ with static vertex count.
With static vertex counts, the final EOT write doesn't actually write
any data - it's just there to end the thread. Typically, the last
thing before ending the thread will be an EmitVertex() call, resulting
in a URB write. We can just set EOT on that.
Note that this isn't always possible - there might be an intervening
SSBO write/image store, or the URB write may have been in a loop.
shader-db statistics for geometry shaders only:
total instructions in shared programs: 3173 -> 3149 (-0.76%)
instructions in affected programs: 176 -> 152 (-13.64%)
helped: 8
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 08fe5799e61e9251dec163d000709ff33434216d
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Sep 24 23:47:29 2015 -0700
i965/gs: Allow src0 immediates in GS_OPCODE_SET_WRITE_OFFSET.
GS_OPCODE_SET_WRITE_OFFSET is a MUL with a constant src[1] and special
strides. We can easily make the generator handle constant src[0]
arguments by instead generating a MOV with the product of both operands.
This isn't necessarily a win in and of itself - instead of a MUL, we
generate a MOV, which should be basically the same cost. However, we
can probably avoid the earlier MOV to put src[0] into a register.
shader-db statistics for geometry shaders only:
total instructions in shared programs: 3207 -> 3173 (-1.06%)
instructions in affected programs: 3207 -> 3173 (-1.06%)
helped: 11
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit f0a618ee7c26a3dd54292fbc2bfd914b0d680ed9
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Sep 24 18:21:59 2015 -0700
i965: Implement "Static Vertex Count" geometry shader optimization.
Broadwell's 3DSTATE_GS contains new "Static Output" and "Static Vertex
Count" fields, which control a new optimization. Normally, geometry
shaders can output arbitrary numbers of vertices, which means that
resource allocation has to be done on the fly. However, if the number
of vertices is statically known, the hardware can pre-allocate resources
up front, which is more efficient.
Thanks to the new NIR GS intrinsics, this is easy. We just call the
function introduced in the previous commit to get the vertex count.
If it obtains a count, we stop emitting the extra 32-bit "Vertex Count"
field in the VUE, and instead fill out the 3DSTATE_GS fields.
Improves performance of Gl32GSCloth by 5.16347% +/- 0.12611% (n=91)
on my Lenovo X250 laptop (Broadwell GT2) at 1024x768.
shader-db statistics for geometry shaders only:
total instructions in shared programs: 3227 -> 3207 (-0.62%)
instructions in affected programs: 242 -> 222 (-8.26%)
helped: 10
v2: Don't break non-NIR paths (just skip this optimization).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit bcef2abad7cf255b6ac112b9ebf0ff75e491c968
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Sep 24 20:58:05 2015 -0700
i965: Move GS_THREAD_END mlen calculations out of the generator.
The visitor was setting a mlen that was wrong for Broadwell, but the
generator was ignoring it and doing the right thing regardless. We may
as well move the logic fully into the visitor. This will be useful in
the next commit as well.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 02530c5dc5dc88078f41fb134c7e0e3833c9f772
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Sep 24 17:01:23 2015 -0700
nir: Add a function to count the number of vertices a GS emits.
Some hardware (such as Broadwell) can run geometry shaders more
efficiently when the number of vertices emitted is statically known.
This pass provides a way to obtain the constant vertex count, or
-1 indicating that the vertex count is unknown/non-constant.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit df221f65e26199a74bc259d3f94e70637b843afa
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Aug 29 00:33:10 2015 -0700
i965: Simplify handling of VUE map changes.
The old code was disasterously complex - spread across multiple atoms
which may not even run, inspecting the dirty bits to try and decide
whether it was necessary to do checks...storing VS information in
brw_context...extra flagging...
This code tripped me and Carl up very badly when working on the
shader cache code. It's very fragile and hard to maintain.
Now that geometry shaders only depend on their inputs and don't have
to worry about the VS VUE map, we can dramatically simplify this:
just compute the VUE map coming out of the geometry shader stage
in brw_upload_programs. If it changes, flag it. Done.
v2: Also check vue_map.separable.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit 6301af22bb80b2c177539074e3b2c68e65c15d41
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Aug 29 00:01:15 2015 -0700
i965/gs: Remove the dependency on the VS VUE map.
Because we only support geometry shaders in core profile, we can safely
ignore any driver-extending of VS outputs.
Those are:
- Legacy userclipping (doesn't exist in core profile)
- Edgeflag copying (Gen4-5 only, no GS support)
- Point coord replacement (Gen4-5 only, no GS support)
- front/back color hacks (Gen4-5 only, no GS support)
v2: Rebase; leave a comment about why SSO works.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit 99df02ca26f6127c8fa24d38a8a069ac6159356a
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Sep 9 16:21:56 2015 -0700
i965: Don't re-layout varyings for separate shader programs.
Previously, our VUE map code always assigned slots to varyings
sequentially, in one contiguous block.
This was a bad fit for separate shaders - the GS input layout depended
or the VS output layout, so if we swapped out vertex shaders, we might
have to recompile the GS on the fly - which rather defeats the point of
using separate shader objects. (Tessellation would suffer from this
as well - we could have to recompile the HS, DS, and GS.)
Instead, this patch makes the VUE map for separate shaders use a fixed
layout, based on the input/output variable's location field. (This is
either specified by layout(location = ...) or assigned by the linker.)
Corresponding inputs/outputs will match up by location; if there's a
mismatch, we're allowed to have undefined behavior.
This may be less efficient - depending what locations were chosen, we
may have empty padding slots in the VUE. But applications presumably
use small consecutive integers for locations, so it hopefully won't be
much worse in practice.
3% of Dota 2 Reborn shaders are hurt, but only by 2 instructions.
This seems like a small price to pay for avoiding recompiles.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit 1e5180316cd62c8c8aa46399ab6a17ad9604d48f
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Sep 9 16:09:35 2015 -0700
i965/vue: Make assign_vue_map() take an explicit slot.
Our plan of assigning consecutive slots doesn't work properly for
separate shader objects - at least, if we want to avoid recompiling them
whenever the interface changes.
As a first step, make assign_vue_map take an explicit slot parameter,
rather than implicitly incrementing it.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit 268008f98c3810b9f276df985dc93efc0c49f33e
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Sep 9 20:21:59 2015 -0700
i965: Initialize unused VUE map slots to BRW_VARYING_SLOT_PAD.
Nothing actually relies on unused slots being initialized to
BRW_VARYING_SLOT_COUNT. Soon, we're going to have VUE maps with holes
in them, at which point pre-filling with BRW_VARYING_SLOT_PAD make a lot
more sense.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit 39d4b553a87228fd93bfdd7100d0687e55aec4b7
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Sep 9 20:23:04 2015 -0700
i965: Fix BRW_VARYING_SLOT_PAD handling in the scalar VS backend.
We can't just break for padding slots. Instead, treat them like
unwritten output variables, so we handle flushing and incrementing
urb_offset correctly.
Paul introduced the concept of padding slots back in 2011, but we've
never actually used them for anything. So it's unsurprising that the
scalar VS backend didn't handle them quite right.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit 511a86383b9d6490788a15cca2df791c6d63bfd7
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Tue Sep 15 08:18:39 2015 +0200
main/tests: Enable glShaderStorageBlockBinding() check in dispatch_sanity test
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit d2d4f00a2c0c356b6abfc7837a834eedd3178218
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Sep 26 14:25:19 2015 +0100
docs: add news item and link release notes for 11.0.1
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 5d08669e2f3189ca6f7c4bfdfe04a3d5816dfaa1
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Sep 26 14:08:52 2015 +0100
docs: add sha256 checksums for 11.0.1
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit 7f1a77ae664cca29208edc32ff82dc7ff4faa02b)
commit aeec9949544d238dcf9e2c6cdbd77fc770c5068e
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Sep 26 13:32:07 2015 +0100
docs: add release notes for 11.0.1
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit bcb9e1d26ba4198359300b50e5c188977cef932e)
commit abdab88b30ab2eb78cf20fd91361f820e1f3e06b
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Sun May 4 21:13:25 2014 +1000
glsl: calculate component size for arrays of arrays when varying packing disabled
Signed-off-by: Timothy Arceri <t_arceri at yahoo.com.au>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 1d401f9ce48f85b4340fcd4a591222aa165910f1
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Wed May 27 21:33:45 2015 +1000
glsl: validate binding qualifier for AoA
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 9bad7afbc2ca6003da9a19c486b81d6ed0b8b0df
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Wed May 27 21:31:59 2015 +1000
glsl: add helper for calculating size of AoA
V2: return 0 if not array rather than -1
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 776a3845d6325578d51eea6e7d91ffb475862fc8
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Sat Jul 18 10:51:51 2015 +1000
glsl: clean-up link uniform code
These changes are also needed to allow linking of
struct and interface arrays of arrays.
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
commit 9932142192f848ae9dbc644551653547640346b4
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Sep 24 23:50:01 2015 +0200
radeonsi: add scratch buffer to the buffer list when it's re-allocated
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
Cc: mesa-stable at lists.freedesktop.org
commit 1e97b41893a4f53a71ee141a5e8a046fed7b49cd
Author: Leo Liu <leo.liu at amd.com>
Date: Fri Sep 18 15:51:26 2015 -0400
radeon/vce: fix vui time_scale zero error
if app pass 0 as frame_rate_num, it should not be encoded to the VUI.
Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
commit 1dd943d7fb5bd374e871436ccf6546327687c761
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu Jul 30 11:25:27 2015 -0700
mesa: Add locking to programs.
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 3c57a102ebd2efc427a59bf8eb441b4e5dec8553
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Jun 12 09:07:09 2015 -0700
mesa: Add locking to sampler objects.
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit d4b0e0b717b698682700bf1cd9d448043a57701d
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Jun 10 13:31:06 2015 -0700
mesa: Remove debugging code from _mesa_reference_*.
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit c8dc04d4c00ed45bfe5f7acb34b0d2f6ab8b7f8d
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Jun 29 10:25:41 2015 -0700
c11/threads: Assert that mtx is non-NULL and check return values.
Passing NULL to C11 threads functions isn't safe, so there's no need for
our implementation to handle it. Cuts about 1k of .text.
text data bss dec hex filename
5009514 198440 26328 5234282 4fde6a i965_dri.so before
5008346 198440 26328 5233114 4fd9da i965_dri.so after
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 266d05a3a0651ac954c91aea12c870940e8a9820
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Fri Sep 25 09:56:39 2015 +0300
glsl: fix packed varyings interface type and add default case
fixes Piglit test:
arb_program_interface_query/linker/query-varyings.shader_test
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit e92c35a8724efd36a35ac9106e5977c5ec2cb332
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jul 29 16:01:24 2015 +0200
glsl: Mark as active all elements of shared/std140 block arrays
Commit 1ca25ab (glsl: Do not eliminate 'shared' or 'std140' blocks
or block members) considered as active 'shared' and 'std140' uniform
blocks and uniform block arrays, but did not include the block array
elements. Because of that, it was possible to have an active uniform
block array without any elements marked as used, making the assertion
((b->num_array_elements > 0) == b->type->is_array())
in link_uniform_blocks() fail.
Fixes the following 5 dEQP tests:
* dEQP-GLES3.functional.ubo.random.nested_structs_instance_arrays.18
* dEQP-GLES3.functional.ubo.random.nested_structs_instance_arrays.24
* dEQP-GLES3.functional.ubo.random.nested_structs_arrays_instance_arrays.19
* dEQP-GLES3.functional.ubo.random.all_per_block_buffers.49
* dEQP-GLES3.functional.ubo.random.all_shared_buffer.36
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83508
Tested-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 065e7d37f16814646dfd1c95c15a73605042e277
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Wed May 13 13:37:42 2015 +0200
docs: Mark ARB_shader_storage_buffer_object as done for i965
v2:
- Mark it too for GLES 3.1
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 614b5307fd485a62205b0ceb05657dd862c1f036
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Wed Mar 18 07:36:24 2015 +0100
i965: Enable ARB_shader_storage_buffer_object extension for gen7+
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 5b080e3ddfa9e2241ecff3b0220785fbfe39fb08
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Tue Jul 14 12:23:42 2015 +0200
mesa: enable ARB_shader_storage_buffer_object extension for GLES 3.1
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 10b5c6491f60d7cf119554f7d8e797b896707335
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Wed Apr 22 16:11:13 2015 +0200
mesa: Add getters for the GL_ARB_shader_storage_buffer_object max constants
v2:
- Add tessellation shader constants support
v3:
- Add GLES 3.1 support.
v4:
- Move the getters to the proper place
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 91191af6d6b5579dd1bc1a63b42f9ca416623c7e
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Mon Apr 20 16:10:44 2015 +0200
glapi: add ARB_shader_storage_block_buffer_object
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 26011fa22a44e539d262b050f0c5b97a7a16a466
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Tue Apr 21 08:23:36 2015 +0200
main/tests: add ARB_shader_storage_buffer_object tokens to enum_strings
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 9b477ad49d3f82503a1b8ba23dedfc05cd848fe8
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Wed May 6 08:11:02 2015 +0200
main: Add SHADER_STORAGE_BLOCK and BUFFER_VARIABLE support for ARB_program_interface_query
Including TOP_LEVEL_ARRAY_SIZE and TOP_LEVEL_ARRAY_STRIDE queries.
v2:
- Use std430_array_stride() to get top level array stride following std430's rules.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 0f18945cb612493d787377d8cbb138c18738f683
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Tue Apr 28 14:25:56 2015 +0200
glsl: Do not allow reads from write-only buffer variables
The error location won't be right, but fixing that would require to check
for this as we process each type of AST node that can involve a variable
read.
v2:
- Limit the check to buffer variables, image variables have different
semantics involved.
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 995a719499d4bd97b27f1e8c7b506202257007b6
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Wed Aug 5 10:30:46 2015 +0200
glsl: Do not allow assignments to read-only buffer variables
v2:
- Merge the error check for the readonly qualifier with the already
existing check for variables flagged as readonly (Timothy).
- Limit the check to buffer variables, image variables have different
semantics involved (Curro).
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 6ef82f039c6fc82dc0910e842a47c4a69ab44e12
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Fri May 8 09:41:58 2015 +0200
glsl: Allow memory qualifiers on shader storage buffer blocks
v2:
- Memory qualifiers on shader storage buffer objects do not come in the form
of layout qualifiers, they are block-level qualifiers.
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit f1b647fdd1028bf475ed258c4dd8b833339ec796
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Tue Apr 28 12:09:58 2015 +0200
glsl: Apply memory qualifiers to buffer variables
v2:
- Save memory qualifier info in the top level members of a shader
storage block.
- Add a checks to record_compare() which is used when comparing
shader storage buffer declarations in different shaders.
- Always report an error for incompatible readonly/writeonly
definitions, whether they are present at block or field level.
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit f4c8c01a3db984a08dc02b72c2904b0532e0847f
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Tue Apr 28 11:27:24 2015 +0200
glsl: Allow use of memory qualifiers with ARB_shader_storage_buffer_object.
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 3b2037f88c974ce6b194f099db32716f152b15e7
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Thu May 14 07:39:52 2015 +0200
glsl: fix UNIFORM_BUFFER_START or UNIFORM_BUFFER_SIZE query when no buffer object is bound
According to ARB_uniform_buffer_object spec:
"If the parameter (starting offset or size) was not specified when the
buffer object was bound (e.g. if bound with BindBufferBase), or if no
buffer object is bound to <index>, zero is returned."
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 2e16dd1350703865104253a9d871e4c0a3257933
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Tue Apr 28 10:08:17 2015 +0200
mesa: Add queries for GL_SHADER_STORAGE_BUFFER
These handle querying the buffer name attached to a giving binding point
as well as the start offset and size of that buffer.
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 4b7b1cf3c0b1682d5ae8983df2bbf5dea50081cd
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Tue Apr 21 16:58:29 2015 +0200
mesa: add glShaderStorageBlockBinding()
Defined in ARB_shader_storage_buffer_object extension.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit a07d0c26574203415da343718d906375accf95b3
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Fri Apr 24 12:34:00 2015 +0200
glsl: First argument to atomic functions must be a buffer variable
v2:
- Add ssbo_in the names of the static functions so it is clear that this
is specific to SSBO atomics.
v3:
- Move the check after the loop (Kristian Høgsberg)
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 5ef169034c77ede86546d8dc42f7f22abcd6faa0
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Fri Aug 7 11:31:13 2015 +0200
i965/nir/vec4: Implement nir_intrinsic_ssbo_atomic_*
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 14af6f4698a9f60c080b9adda4d3b4c45b157bd7
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Mon Jun 1 09:41:47 2015 +0200
i965/nir/fs: Implement nir_intrinsic_ssbo_atomic_*
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 9d5c0be5d518a0ac7381ebe40b1fa2bef9839bdf
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Mon Jun 1 09:40:39 2015 +0200
nir: Implement lowered SSBO atomic intrinsics
The original GLSL IR intrinsics have been lowered to an internal
version that accepts a block index and an offset instead of a
SSBO reference.
v2 (Connor):
- Document the sources used by the atomic intrinsics.
Reviewed-by: Connor Abbott <connor.w.abbott at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit d2719b6e4f6bdbbd29ac66903d3d9dad9bd01386
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Wed Jul 8 15:59:05 2015 +0200
glsl: lower SSBO atomic intrinsics
The first argument to SSBO atomics is a reference to a SSBO buffer variable
so we want to compute its block index and offset and provide these values
to an internal version of the intrinsic that takes them instead of the
buffer variable reference.
v2:
- Support single components of integer vectors to be passed in as arguments.
- Get interface packing information from interface's type.
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit da659087b9620805c155c3954f560995ed96d5b4
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Tue Sep 1 11:57:07 2015 +0200
glsl: use ir_rvalue instead of ir_dereference in auxiliary functions
In a later commit we will need to handle ir_swizzle nodes too, which are
not an ir_dereference. That can happen, for example, when we pass a
component of an integer vector as argument to any of the SSBO atomic
functions.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit ea0a1f5beb22982a886ba862ba95f92c9e35165a
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Thu Apr 23 11:21:54 2015 +0200
glsl: Add atomic functions from ARB_shader_storage_buffer_object
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 2cacebaad3da88853e9b0d19522d24e11a7f4f91
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Thu Apr 23 11:06:12 2015 +0200
glsl: Rename atomic counter functions
Shader Storage Buffer Object will add new atomic functions that are not
associated with counters, so better have atomic counter-specific functions
explicitly include the word "counter" in their names.
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 586142658e2927a68ce02c44d3bdcaa628cac717
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Wed Sep 23 09:04:53 2015 +0200
glsl: atomic counters can be declared as buffer-qualified variables
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 475d9c32d1331eb330c8594ed6f84e668157500e
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Tue May 19 09:02:06 2015 +0200
nir/glsl_to_nir: ignore an instruction's dest if it hasn't any
Reviewed-by: Connor Abbott <connor.w.abbott at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit e3f9c7829c609e8a32da9f36c9829843f2204a37
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Thu Sep 10 12:01:02 2015 +0200
i965/nir/vec4: Implement nir_intrinsic_load_ssbo
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 5b186aafe7a8d3f96a99ad2fddd2bff99d99e923
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Mon Jun 1 09:28:29 2015 +0200
i965/nir/fs: Implement nir_intrinsic_load_ssbo
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit e59ae238b606af0f3ec5c722ac2d1495caed091a
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Thu Jul 9 10:29:18 2015 +0200
nir: Implement __intrinsic_load_ssbo
v2:
- Fix ssbo loads with boolean variables.
v3:
- Simplify the changes (Kristian)
Reviewed-by: Connor Abbott <connor.w.abbott at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 3e70c968de363168fc491ca673a4798284a10c44
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Wed Sep 23 08:48:21 2015 +0200
nir: modify the instruction insertion in nir_visitor::visit(ir_call *ir)
This patch moves nir_instr_insert_after_cf_list call into each case
in the intrinsics switch at nir_visitor::visit(ir_call *ir) and
define a nir_dest variable which will be used when handling
ir->return_deref after the switch.
This patch simplifies the code for nir_intrinsic_load_ssbo
implementation changes we are going to do next.
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 922b3d1bb16b4b6b292cb159e5fe3d0615ca725c
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Thu Sep 10 12:00:04 2015 +0200
i965/nir/vec4: Implement nir_intrinsic_store_ssbo
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 337dad8ceeb4f313a47b4ddb31805f355c3fc3a5
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Mon Jun 1 09:26:01 2015 +0200
i965/nir/fs: Implement nir_intrinsic_store_ssbo
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 9bb7d9ecf881a10f198fba2c52ffb8bf3d557d6a
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Thu Jul 9 10:26:42 2015 +0200
nir: Implement __intrinsic_store_ssbo
v2 (Connor):
- Make the STORE() macro take arguments for the extra sources (and their
size) and any extra indices required.
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit f17c6b90660f4e156e76f4fa333af86cda2a0125
Author: Francisco Jerez <currojerez at riseup.net>
Date: Sat Aug 1 17:15:36 2015 +0300
i965/vec4: Import surface message builder functions.
Implement helper functions that can be used to construct and send
untyped and typed surface read, write and atomic messages to the
shared dataport unit.
v2: Split from the FS implementation.
v3: Rewrite to avoid evil array_reg, emit_collect and emit_zip.
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit d5503ce39ffb056de8d3c9c78870aa7f1b3432d2
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Apr 29 02:12:27 2015 +0300
i965/vec4: Import helpers to convert vectors into arrays and back.
These functions handle the conversion of a vec4 into the form expected
by the dataport unit in message and message return payloads. The
conversion is not always trivial because some messages don't support
SIMD4x2 for some generations, in which case a strided copy may be
necessary.
v2: Split from the FS implementation.
v3: Rewrite to avoid evil array_reg, emit_collect and emit_zip.
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 402cb7ce13da9319c96b585c1f39810a3719fae8
Author: Francisco Jerez <currojerez at riseup.net>
Date: Fri Apr 24 17:42:55 2015 +0300
i965/vec4: Introduce VEC4 IR builder.
See "i965/fs: Introduce FS IR builder." for the rationale.
v2: Drop scalarizing VEC4 builder.
v3: Take a backend_shader as constructor argument. Improve handling
of debug annotations and execution control flags. Rename "instr"
variable. Initialize cursor to NULL by default and add method to
explicitly point the builder at the end of the program.
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 203cd1bf28b88e041a693c867b4dd705236b0d5f
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Tue Jun 23 08:53:36 2015 +0200
glsl: shader storage blocks use different max block size values than uniforms
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit eb9a9b62b17d00f6536357a4de254899ae4ed2c7
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Fri May 15 12:26:42 2015 +0200
glsl: ignore buffer variables when counting uniform components
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 138e4ae8aee3c13e83c732ba0f6d705e8001050c
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Wed Apr 22 16:58:45 2015 +0200
glsl: number of active shader storage blocks must be within allowed limits
Notice that we should differentiate between shader storage blocks and
uniform blocks, since they have different limits.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit a7b4ab45d08d8469daefb9f2af34ad6860b9fc3b
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Tue Apr 21 12:12:05 2015 +0200
glsl: a shader storage buffer must be smaller than the maximum size allowed
Otherwise, generate a link time error as per the
ARB_shader_storage_buffer_object spec.
v2:
- Fix error message (Jordan)
v3:
- Move std140_size() changes to its own patch (Kristian)
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit e854a9800120ac0b1930da27f39207a35a637779
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Mon Apr 13 09:50:53 2015 +0200
glsl: add std430 interface packing support to ssbo related operations
v2:
- Get interface packing information from interface's type, not the
variable type.
- Simplify is_std430 condition in emit_access() for readability (Jordan)
- Add a commment explaing why array of three-component vector case is
different in std430 than the rest of cases.
- Add calls to std430_array_stride().
v3:
- Simplify size_mul change for std430's case (Jordan)
- Fix commit log lines length (Jordan)
- Pass 'packing' instead of 'is_std430' to emit_access() (Kristian)
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 1be180b941ac9e0652a6b2d19713ddccd8a5151f
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Fri Sep 4 17:53:48 2015 +0200
glsl: Add std430 support to program_resource_visitor's member functions
They are used to calculate the offset, array stride of uniform/shader
storage buffer variables. Take into account this info to get the right
value for std430.
v2:
- Fix commit log line length and indention. (Jordan)
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 8f0167c65b2df73cf2ef094358ba162fe0028d14
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Mon Aug 31 07:45:53 2015 +0200
glsl: Add parser/compiler support for std430 interface packing qualifier
v2:
- Fix a missing check in has_layout()
v3:
- Mention shader storage block in error message for layout qualifiers
(Kristian).
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 35476c2bae5d59adf5fcfce8c83958ed076264e5
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Mon Aug 31 07:44:47 2015 +0200
glsl: Add std430 related member functions to glsl_type class
They are used to calculate size, base alignment and array stride values
for a glsl_type following std430 rules.
v2:
- Paste OpenGL 4.3 spec wording as it mentions stride of array. (Jordan)
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit a40f917c4b0100a7ec9a97a12ce0959f83a3f61b
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Thu Sep 3 12:00:16 2015 +0200
glsl: allow default qualifiers for shader storage block definitions
This kind of definitions:
layout(xxx) buffer;
was not supported by commit 84fc5fece006.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 3763a0e0a740ccbb5d8e0912361a7ed97111751c
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Thu Sep 10 10:00:12 2015 +0200
glsl: Move interface block processing to glsl_parser_extras.cpp
No functional changes.
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 9c1f10b1bc548a00482a0b6b789c4cdb12f5302e
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Thu Sep 3 09:47:56 2015 +0200
glsl: ignore default qualifier declarations when checking for duplicate layout qualifiers
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 130031168de44e38e84000f279951ef70a99cb66
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Wed Sep 2 15:58:01 2015 +0200
glsl: layout qualifier can appear more than once since OpenGL 4.20
Also if GL_ARB_shading_language_420pack extension is enabled.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 5bb5eeea008a01f5bc44570915ea4b7ac432cef9
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Fri Apr 24 07:02:19 2015 +0200
i965/wm: surfaces should have the API buffer size, not the drm buffer size
The returned drm buffer object has a size multiple of 4096 but that should not
be exposed to the API user, which is working with a different size.
As far as I can see this problem is only visible in the calculation of the
length of unsized arrays used in SSBOs, as the implementation of this needs
to query the underlying buffer size via a message.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit eaa6f01c8d0c49d8ae637d8104163da9c45526ca
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Thu Apr 16 13:18:01 2015 +0200
i965/wm: emit null buffer surfaces when null buffers are attached
Otherwise we can expect odd things to happen if, for example, we ask
for the size of the attached buffer from shader code, since that
might query this value from the surface we uploaded and get random
results.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit f5dd2c182275a9de57e5186491012c402a6248e0
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Mon Jun 1 09:45:51 2015 +0200
i965/fs/nir: implement nir_intrinsic_get_buffer_size
v2:
- Remove inst->regs_written assignment as the instruction only
writes to one register.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit b23eb643ebab9ef250ce026a7e2f651de9be10f6
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Mon Apr 13 16:55:49 2015 +0200
i965/fs: Implement FS_OPCODE_GET_BUFFER_SIZE
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 65d7f5fe9f4284f7de867b4c412f086c6dcca176
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Wed Aug 26 12:21:54 2015 +0200
i965/vec4/nir: implement nir_intrinsic_get_buffer_size
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 6485880232df46c0cdded0b063b8841a7855bd32
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Fri Aug 28 09:39:49 2015 +0200
i965/vec4: Implement VS_OPCODE_GET_BUFFER_SIZE
Notice that Skylake needs to include a header in the sampler message
so it will need some tweaks to work there.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 003ce30e36b1a0757053a1f1407cdd314a32db10
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Mon Jun 1 09:44:55 2015 +0200
nir: Implement ir_unop_get_buffer_size
This is how backends provide the buffer size required to compute
the size of unsized arrays in the previous patch
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 750c694474776fd545262aaf3190ccd92d6bb0ec
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Wed Jul 8 17:42:14 2015 +0200
glsl: implement unsized array length
v2:
- Reduce the number of lines over 80 character line width
limit. (Thomas Hellan)
v3:
- Inject the formula to compute the array length in the IR, backends
only need to provide the buffer size (Curro)
- Create an auxiliary function to simplify code (Jordan Justen)
- Rename variables (Jordan Justen)
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 273f61a0051a794d1a39d70fb1dbf46a3ca3c63f
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Mon Apr 13 16:17:07 2015 +0200
glsl: Add parser/compiler support for unsized array's length()
The unsized array length is computed with the following formula:
array.length() =
max((buffer_object_size - offset_of_array) / stride_of_array, 0)
Of these, only the buffer size needs to be provided by the backends, the
frontend already knows the values of the two other variables.
This patch identifies the cases where we need to get the length of an
unsized array, injecting ir_unop_ssbo_unsized_array_length expressions
that will be lowered (in a later patch) to inject the formula mentioned
above.
It also adds the ir_unop_get_buffer_size expression that drivers will
implement to provide the buffer length.
v2:
- Do not define a triop that will force backends to implement the
entire formula, they should only need to provide the buffer size
since the other values are known by the frontend (Curro).
v3:
- Call state->has_shader_storage_buffer_objects() in ast_function.cpp instead
of using state->ARB_shader_storage_buffer_object_enable (Tapani).
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 1440d2a6833902d9c966fe8ad7db46a7f787391c
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Mon Sep 21 09:09:11 2015 +0200
glsl: Add unsized array support to glsl_type::std140_size()
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 68f5a4e6d2c5bec39b425a41eac6b190a8a7d14a
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Tue Sep 22 11:05:28 2015 +0200
glsl: fix indention in glsl_types.cpp
No functional changes.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit f3f64cd0c4b9cf3363056ddc9c4d7616614ce829
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Wed Mar 18 15:32:03 2015 +0100
glsl: add support for unsized arrays in shader storage blocks
They only can be defined in the last position of the shader
storage blocks.
When an unsized array is used in different shaders, it might be
converted in different sized arrays, avoid get a linker error
in that case.
v2:
- Rework error condition and error messages (Timothy Arceri)
v3:
- Move OpenGL ES check to its own patch.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit f45d39f6afc436ee4c68a21382933b2b39879eef
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Tue Aug 25 08:02:46 2015 +0200
glsl: return error if unsized arrays are found in OpenGL ES
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 6335c7923683ecf37bcd59007a144aa37c857343
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Thu Apr 9 09:14:38 2015 +0200
i965/fs: Do not split buffer variables
Buffer variables are the same as uniforms, only that read/write, so we want
the same treatment.
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 2773a7cf1d929729de04abf516ce5bf9eac77834
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Thu Apr 9 10:33:30 2015 +0200
i965: handle visiting of ir_var_shader_storage variables
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 37da6a2acd549d145b1691bb1f6bab87b65c92a6
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Mon Mar 23 13:48:43 2015 +0100
i965: Upload Shader Storage Buffer Object surfaces
Since these are a special kind of UBOs we emit them together reusing the
same infrastructure, however, we use a RAW surface so we can reuse
existing untyped read/write/atomic messages which include a pixel mask
header that we need to set to obtain correct behavior with helper
invocations of the fragment shader.
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit bdbabc57e302b73e2db30f6d46918afb2b442c7b
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Thu Mar 19 12:11:39 2015 +0100
i965: Set MaxShaderStorageBuffers for compute shaders
v2:
- Set it after the driver's MaxShaderStorageBuffers value assignment.
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 36f392c4ef5fd8793127132f9b4465249e92c9ce
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Tue Jun 9 09:16:33 2015 +0200
i965: set ARB_shader_storage_buffer_object related constant values
v2:
- Add tessellation shader constants assignment
v3:
- Set MaxShaderStorageBufferBindings to 36.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit dfdeb94a5aedf838fe1f180fd68a7b5b2a3d7e99
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Thu Mar 19 11:07:19 2015 +0100
i965: Implement DriverFlags.NewShaderStorageBuffer
We use the same dirty state for SSBOs and UBOs because they share the
same infrastructure.
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 332ff009ffcbdad2402f089060623c0a86fa253c
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Thu Mar 19 11:27:21 2015 +0100
i965: Use 64-byte offset alignment for shader storage buffers
This should be a cacheline (64 bytes) so that we can safely have the
CPU and GPU writing the same SSBO on non-cachecoherent systems (our
Atom CPUs). With UBOs, the GPU never writes, so there's no
problem. For an SSBO, the GPU and the CPU can be updating disjoint
regions of the buffer simultaneously and that will break if the
regions overlap the same cacheline.
v2:
- Use cacheline size (64 bytes) instead of 16 bytes (Kristian).
- Update commit log and add a comment in the code explaining
why we use cacheline size (Ben).
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 4cf908f9cbaac5563dd3ff355399e2b56addbca4
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Thu Sep 3 13:58:25 2015 +0200
mesa: set MAX_SHADER_STORAGE_BUFFERS to 16.
v2:
- Set the value to 16 and drop the comment. (Kristian)
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 4639cea2921669527eb43dcb49724c05afb27e8e
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Fri Sep 4 11:30:34 2015 +0300
glsl: add packed varyings to program resource list
This makes sure that user is still able to query properties about
variables that have gotten packed by lower_packed_varyings pass.
Fixes following OpenGL ES 3.1 test:
ES31-CTS.program_interface_query.separate-programs-vertex
v2: fix 'name included in packed list' check (Ilia Mirkin)
v3: iterate over instances of name using strtok_r (Ilia Mirkin)
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Marta Lofstedt <marta.lofstedt at intel.com>
commit a6b55beb78501e3447c55a2d3a4e4b5d6950b86c
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Fri Sep 4 11:22:15 2015 +0300
mesa: add packed_varyings list to gl_shader
This is required to store information about packed varyings, currently
these variables get lost and cannot be retrieved later in sensible way
for program interface queries. List will be utilized by next patch.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Marta Lofstedt <marta.lofstedt at intel.com>
commit ebbe6cdad7ab082d2b191fe6c7c0eaa6921d55de
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Thu Sep 17 16:25:24 2015 -0700
i965/cs: Implement DispatchComputeIndirect support
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit d11d018ce38b76a580242d64e61e8e30dad035e8
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Thu Sep 17 11:14:45 2015 -0700
mesa/cs: Implement glDispatchComputeIndirect
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 12cf91db0236291ebaff71f602d929064b1ec096
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Thu Sep 17 10:10:07 2015 -0700
mesa/cs: Support GL_DISPATCH_INDIRECT_BUFFER
v2:
* Use _mesa_has_compute_shaders (Ilia)
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 4a1ba7e6bd3ddcab4647a1382d14165a08c0d3b0
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Thu Sep 17 10:05:22 2015 -0700
mesa/cs: Add _mesa_validate_DispatchCompute
Move API validation to _mesa_validate_DispatchCompute in
api_validate.c.
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 19604d30e1351868f7f54847c91ffec7b3fcd27e
Author: Roland Scheidegger <sroland at vmware.com>
Date: Sun Sep 20 01:33:17 2015 +0200
mesa: fix mipmap generation for immutable, compressed textures
If the immutable compressed texture didn't have the full mip pyramid,
this didn't work, because it tried to generate mip levels for non-existing
levels. _mesa_prepare_mipmap_level() would correctly handle this by returning
FALSE if the mip level didn't exist, however we actually created the
non-existing mip level right before that because we used _mesa_get_tex_image()
before calling _mesa_prepare_mipmap_level(). It would then proceed to crash
(we allocated the mip level, which is a bad idea on an immutable texture,
but didn't initialize the values, leading to assertion failures or segfaults).
Fix this by using _mesa_select_tex_image() instead and call it after
_mesa_prepare_mipmap_level(), as that function will allocate missing mip levels
for non-immutable textures already.
This fixes a (2 year old) crash with astromenace which was hack-fixed in ubuntu
packages instead: http://bugs.debian.org/718680 (I guess most apps do full mip
chains - I believe this app not doing it is actually unintentional, always one
level less than full mip chain...).
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit d6bb46bbe8e4ef90dedc5a04c7434a8113c10a8b
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Sep 23 18:06:19 2015 -0700
glsl: Expose gl_MaxTess{Control,Evaluation}AtomicCounters.
... with only ARB_shader_atomic_counters.
I expected to see interactions with ARB_tessellation_shader in the
ARB_shader_atomic_counters spec, but they do not exist. It seems that we
should unconditionally expose these variables in the presence of
ARB_shader_atomic_counters:
gl_MaxTessControlAtomicCounters
gl_MaxTessEvaluationAtomicCounters
This partially reverts commit da7adb99e8. The commit also affected
gl_MaxTessControlImageUniforms and gl_MaxTessEvaluationImageUniforms
similarly but the ARB_shader_image_load_store spec does list an
interaction with ARB_tessellation_shader.
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92095
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 7fee23569b0e3a4d4636a83fb6751ee82987ec5f
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Wed Sep 23 19:22:17 2015 +0200
i965/vec4: check swizzle before discarding a uniform on a 3src operand
Without this commit, copy propagation is discarded if it involves
a uniform with an instruction that has 3 sources. But 3 sourced
instructions can access scalar values.
For example, this is what vec4_visitor::fix_3src_operand() is already
doing:
if (src.file == UNIFORM && brw_is_single_value_swizzle(src.swizzle))
return src;
Shader-db results (unfiltered) on NIR:
total instructions in shared programs: 6259650 -> 6241985 (-0.28%)
instructions in affected programs: 812755 -> 795090 (-2.17%)
helped: 7930
HURT: 0
Shader-db results (unfiltered) on IR:
total instructions in shared programs: 6445822 -> 6441788 (-0.06%)
instructions in affected programs: 296630 -> 292596 (-1.36%)
helped: 2533
HURT: 0
v2:
- Updated commit message, using Matt Turner suggestions
- Move the check after we've created the final value, as Jason
Ekstrand suggested
- Clean up the condition
v3:
- Move the check back to the original place, to keep things
tidy, as suggested by Jason Ekstrand
v4:
- Fixed missing is_single_value_swizzle() as pointed by Jason Ekstrand
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 1d040160f861955a14728bea48e697cfaed8e045
Author: Mauro Rossi <issor.oruam at gmail.com>
Date: Wed Sep 23 22:30:55 2015 +0200
android: radeonsi: fix sid_tables.h missing LOCAL_MODULE_CLASS
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit ebcc886d87e465f7bd3a172f9ff4dc825c238c5c
Author: Benjamin Bellec <b.bellec at gmail.com>
Date: Fri Sep 4 20:27:22 2015 +0200
gallium/radeon: remove the percentage symbol from HUD temperature
The HUD adds '%' if max == 100.
Signed-off-by: Benjamin Bellec <b.bellec at gmail.com>
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit 7bbce21e458d912279159aa6ac122768c6c06551
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Sep 10 18:48:12 2015 +0200
gallium/u_blitter: handle allocation failures
Cc: 11.0 <mesa-stable at lists.freedesktop.org>
Acked-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit ae418a7b5640aadb625bb7a7d6e4aa0a98ccb77f
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Sep 10 19:25:14 2015 +0200
radeonsi: handle dummy constant buffer allocation failure
Cc: 11.0 <mesa-stable at lists.freedesktop.org>
Acked-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit b737d9c1dce073aa36b21c33cb30fbae89c38153
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Sep 10 18:42:22 2015 +0200
radeonsi: don't forget to update scratch relocations for LS, HS, ES shaders
Cc: 11.0 <mesa-stable at lists.freedesktop.org>
Acked-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit d556346b3590e8d5601c0831577f08e7b1ccecec
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Sep 10 18:40:51 2015 +0200
radeonsi: skip drawing if updating the scratch buffer fails
Cc: 11.0 <mesa-stable at lists.freedesktop.org>
Acked-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 1f99b0be7e4e300c2b1761437f740a604ab036bc
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Sep 10 18:33:10 2015 +0200
radeonsi: skip drawing if PS fails to compile or upload
Cc: 11.0 <mesa-stable at lists.freedesktop.org>
Acked-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 237d7cccce15b91590afa90020ff71324217fdb9
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Sep 10 18:32:22 2015 +0200
radeonsi: skip drawing if VS, TCS, TES, GS fail to compile or upload
Cc: 11.0 <mesa-stable at lists.freedesktop.org>
Acked-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 9b6d9dd7d8d2779e2bd08787c26f51512b84f6d2
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Sep 10 18:31:33 2015 +0200
radeonsi: handle fixed-func TCS shader create failure
Cc: 11.0 <mesa-stable at lists.freedesktop.org>
Acked-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 5dbadb02572f875f5d2f22327eab6b93de61337c
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Sep 10 18:30:41 2015 +0200
radeonsi: handle shader precompile failures
Cc: 11.0 <mesa-stable at lists.freedesktop.org>
Acked-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 263f5a2cf97e455e48dbd7728cb0ac10fd699746
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Sep 10 18:27:53 2015 +0200
radeonsi: skip drawing if GS ring allocations fail
Cc: 11.0 <mesa-stable at lists.freedesktop.org>
Acked-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 22d3ccf5a814bfc768e373d0c983a356f4e4efe3
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Sep 10 18:27:53 2015 +0200
radeonsi: skip drawing if the tess factor ring allocation fails
Cc: 11.0 <mesa-stable at lists.freedesktop.org>
Acked-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 5c219ab55239ceef3285262ff68a502e419061e0
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Sep 10 18:16:26 2015 +0200
radeonsi: add malloc fail paths to si_create_shader_state
Cc: 11.0 <mesa-stable at lists.freedesktop.org>
Acked-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 394d67a58f949245e8b3fad400e9efaa5829ec84
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Sep 10 18:15:40 2015 +0200
radeonsi: report alloc failure from si_shader_binary_read
Cc: 11.0 <mesa-stable at lists.freedesktop.org>
Acked-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit dea834e639715caa9517a695a3fb04d5de9aa069
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Sep 10 18:14:36 2015 +0200
gallium/radeon: add a fail path for depth MSAA texture readback
Cc: 11.0 <mesa-stable at lists.freedesktop.org>
Acked-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit f95e695059c428a21a1e1a27d5cd5ccce2a97b0e
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Sep 10 17:54:41 2015 +0200
gallium/radeon: handle buffer alloc failures in r600_draw_rectangle
Cc: 11.0 <mesa-stable at lists.freedesktop.org>
Acked-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 282b3780123bace557fc90127bd35b075ea0873e
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Sep 10 17:53:28 2015 +0200
gallium/radeon: handle buffer_map staging buffer failures better
Cc: 11.0 <mesa-stable at lists.freedesktop.org>
Acked-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit cd27ff6a0f85ca35f0f7f2fa7971692e0028e2ed
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Sep 10 17:42:31 2015 +0200
radeonsi: handle constant buffer alloc failures
Cc: 11.0 <mesa-stable at lists.freedesktop.org>
Acked-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 29dff6f67656c8e6e09249cc76b6efa0c03353a7
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Sep 10 17:42:31 2015 +0200
radeonsi: handle index buffer alloc failures
Cc: 11.0 <mesa-stable at lists.freedesktop.org>
Acked-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit f3a081953393c7d40bd8df9ec22a2551d01098f5
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Sep 23 02:33:24 2015 +0200
st/mesa: fix front buffer regression after dropping st_validate_state in Blit
Broken by: d082c5324914212f76e45be497229c7a0681f706
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92072
Cc: 10.6 11.0 <mesa-stable at lists.freedesktop.org>
Tested-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 21c1c7ff81cb3cca9c1f5d907fe6c17219b5a137
Author: Kristian Høgsberg Kristensen <krh at bitplanet.net>
Date: Thu Sep 24 10:51:10 2015 -0700
wayland: Add copyright notice for wayland-egl.c
Signed-off-by: Kristian Høgsberg Kristensen <krh at bitplanet.net>
commit 2ea16966ae66d4dd5c5dcb996d7996d9c734bbee
Author: Kristian Høgsberg Kristensen <krh at bitplanet.net>
Date: Wed Sep 23 16:57:47 2015 -0700
i965: Respect stride and subreg_offset for ATTR registers
When we assign hw regs to attributes, we don't incorporate the stride
and subreg_offset from the fs_reg. It's rarely used, but the integer
multiplication lowering uses unusual stride and subreg_offset
combination breaks when one source is an attribute.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91970
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Kristian Høgsberg Kristensen <krh at bitplanet.net>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 200aee424790f3167fcb175f4798af27783fe364
Author: Brian Paul <brianp at vmware.com>
Date: Fri Aug 28 00:42:00 2015 -0600
mesa: rework Driver.CopyImageSubData() and related code
Previously, core Mesa's _mesa_CopyImageSubData() created temporary textures
to wrap renderbuffer sources/destinations. This caused a bit of a mess in
the Mesa/gallium state tracker because we had to basically undo that
wrapping.
Instead, change ctx->Driver.CopyImageSubData() to take both gl_renderbuffer
and gl_texture_image src/dst pointers (one being null, the other non-null)
so the driver can handle renderbuffer vs. texture as needed.
For the i965 driver, we basically moved the code that wrapped textures
around renderbuffers from copyimage.c down into the met and driver code.
The old code in copyimage.c also made some questionable calls to
_mesa_BindTexture(), etc. which weren't undone at the end.
v2 (Jason Ekstrand): Rework the intel bits
v3 (Brian Paul): Update the temporary st_CopyImageSubData() function.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Tested-by: Kai Wasserbäch <kai at dev.carbon-project.org>
Tested-by: Nick Sarnie <commendsarnex at gmail.com>
commit c8cb5ed93c8e7343390f188bbf1a8459380a5739
Author: Thomas Hellstrom <thellstrom at vmware.com>
Date: Thu Sep 17 03:22:53 2015 -0700
st/xa: Fixups for PIPE_FORMAT_R8_UNORM A8 usage v2.
Check for PIPE_FORMAT_R8_UNORM when setting up the copy shader.
Also re-enable the dest alpha blending with A8 destination that
actually turned out to be correct.
Verified using rendercheck that the composite operators
overreverse, in, out, atop, atopreverse and xor seem to work fine
with a8 destiation.
v2: Fix a copy-paste error.
Reported-by: Jose Fonseca <jfonseca at vmware.com>
Signed-off-by: Thomas Hellstrom <thellstrom at vmware.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 1614c39a8fc205d7b1cb5b16737c233fbcc5b678
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Sep 23 00:30:23 2015 -0400
st/mesa: keep track of saturated writes when eliminating dead code
It doesn't matter whether a write is saturated or not, in another
implementation it might even have been a separate opcode. This code was
most likely copied from the copy-propagation pass (where one does have
to distinguish saturation).
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 827d7948340f4cbc7de2d02971e4f36fbd52f7a8
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Wed Sep 23 11:12:57 2015 +1000
glsl: correctly detect inactive UBO arrays
Previously the code was trying to get the packing type from the array not the
interface.
Cc: Ian Romanick <ian.d.romanick at intel.com>
Cc: Antia Puentes <apuentes at igalia.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit 71e187430cdd1d82972554d7f9e994a41847bea1
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Aug 13 15:39:40 2015 -0400
i965: add ARB_texture_barrier support
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 31a36ffbc81a4dd79b91bf0fc59f0e5f8d44dbd7
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Sep 3 01:01:29 2015 -0700
i965/gs: Fix extra level of indentation left by the previous commit.
I left a bunch of code indented a level in the previous patch to make
the diff easier to read. But now we should fix that.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit df31c1850d14729e27513ae733110a668f6b6e95
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Aug 5 09:16:59 2015 -0700
i965/gs: Use new NIR intrinsics.
By performing the vertex counting in NIR, we're able to elide a ton of
useless safety checks around every EmitVertex() call:
total instructions in shared programs: 3952 -> 3720 (-5.87%)
instructions in affected programs: 3491 -> 3259 (-6.65%)
helped: 11
HURT: 0
Improves performance in Gl32GSCloth by 0.671742% +/- 0.142202% (n=621)
on Haswell GT3e at 1024x768.
This should also make it easier to implement Broadwell's "Static Vertex
Count" feature someday.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 542d40d698a698dc656c7a64ddcea07060707555
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue May 12 01:05:29 2015 -0700
nir: Add new GS intrinsics that maintain a count of emitted vertices.
This patch also introduces a lowering pass to convert the simple GS
intrinsics to the new ones. See the comments above that for the
rationale behind the new intrinsics.
This should be useful for i965; it's a generic enough mechanism that I
could see other drivers potentially using it as well, so I don't feel
too bad about putting it in the generic code.
v2:
- Use nir_after_block_before_jump for the cursor (caught by Jason
Ekstrand - I'd mistakenly used nir_after_block when rebasing this
code onto the new NIR control flow API).
- Remove the old emit_vertex intrinsic at the end, rather than in
the middle (requested by Jason).
- Use state->... directly rather than locals (requested by Jason).
- Report progress from nir_lower_gs_intrinsics() (requested by me).
- Remove "Authors:" section from file comment (requested by
Michael Schellenberger Costa).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 0a040975ec1d27b62c6f8bf16093df3de898e9b3
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Sep 21 13:21:10 2015 -0700
nir: Add unit tests for control flow graphs.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Acked-by: Jason Ekstrand <jason.ekstrand at intel.com>
Acked-by: Connor Abbott <cwabbott0 at gmail.com>
commit fbaa1b19d7accc5de95d6804525aad5b95abba72
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Sep 19 04:40:07 2015 -0700
nir/cf: Fix dominance metadata in the dead control flow pass.
The NIR control flow modification API churns the block structure,
splitting blocks, stitching them back together, and so on. Preserving
information about block dominance is hard (and probably not worthwhile).
This patch makes nir_cf_extract() throw away all metadata, like we do
when adding/removing jumps.
We then make the dead control flow pass compute dominance information
right before it uses it. This is necessary because earlier work by the
pass may have invalidated it.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 6560838703431f89c47d68822758bc76fd34c355
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Sep 1 22:56:29 2015 -0700
nir/cf: Fix unlink_block_successors to actually unlink the second one.
Calling unlink_blocks(block, block->successors[0]) will successfully
unlink the first successor, but then will shift block->successors[1]
down to block->successor[0]. So the successors[1] != NULL check will
always fail.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 024e5ec9777c38f8c05be6678a9f51b145a00236
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Sep 18 13:11:56 2015 -0700
nir/cf: Alter block successors before adding a fake link.
Consider the case of "while (...) { break }". Or in NIR:
block block_0 (0x7ab640):
...
/* succs: block_1 */
loop {
block block_1:
/* preds: block_0 */
break
/* succs: block_2 */
}
block block_2:
Calling nir_handle_remove_jump(block_1, nir_jump_break) will remove the break.
Unfortunately, it would mangle the predecessors and successors.
Here, block_2->predecessors->entries == 1, so we would create a fake
link, setting block_1->successors[1] = block_2, and adding block_1 to
block_2's predecessor set. This is illegal: a block cannot specify the
same successor twice. In particular, adding the predecessor would have
no effect, as it was already present in the set.
We'd then call unlink_block_successors(), which would delete the fake
link and remove block_1 from block_2's predecessor set. It would then
delete successors[0], and attempt to remove block_1 from block_2's
predecessor set a second time...except that it wouldn't be present,
triggering an assertion failure.
The fix appears to be simple: simply unlink the block's successors and
recreate them to point at the correct blocks first. Then, add the fake
link. In the above example, removing the break would cause block_1 to
have itself as a successor (as it becomes an infinite loop), so adding
the fake link won't cause a duplicate successor.
v2: Add comments (requested by Connor Abbott) and fix commit message.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 0991b2eb3535f9af289149c9e63c38b56cb4b549
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Sep 22 18:04:14 2015 -0700
nir/cf: Conditionally do block_add_normal_succs() in unlink_jump();
There is a bug where we mess up predecessors/successors due to the
ordering of unlinking/recreating edges/adding fake edges. In order to
fix that, I need everything in one routine.
However, calling block_add_normal_succs() isn't safe from
cleanup_cf_node() - it would crash trying to insert phi undefs.
So unfortunately I need to add a parameter.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 9674c76c0e473a3edbc45f935ea88afd64024325
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Sep 3 00:33:50 2015 -0700
nir/cf: Don't break outer-block successors in split_block_beginning().
Consider the following NIR:
block block_0;
/* succs: block_1 block_2 */
if (...) {
block block_1;
...
} else {
block block_2;
}
Calling split_block_beginning() on block_1 would break block_0's
successors: link_block() sets both successors of a block, so calling
link_block(block_0, new_block, NULL) would throw away the second
successor, leaving only /* succ: new_block */. This is invalid: the
block before an if statement must have two successors.
Changing the call to link_block(pred, new_block, pred->successors[0])
would correctly leave both successors in place, but because unlink_block
may shift successor[1] to successor[0], it may not preserve the original
order. NIR maintains a convention that successor[0] must point to the
"then" block, while successor[1] points to the "else" block, so we need
to take care to preserve this ordering.
This patch creates a new function that swaps out one successor for
another, preserving the ordering. It then uses this to fix the issue.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit e2637db618b868682e1c996b3c6394c2e82963f1
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Sep 3 00:31:19 2015 -0700
nir/cf: Make a helper function for removing a predecessor.
I need to do this in a second place, and I'd rather make a helper
function than cut and paste the code.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 6a67ede6b33cfb3bc35d09dcd25a731cba3b7780
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Sep 3 01:29:38 2015 -0700
nir: Validate that a block doesn't have two identical successors.
This is invalid, and causes disasters if we try to unlink successors:
removing the first will work, but removing the second copy will fail
because the block isn't in the successor's predecessor set any longer.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 8dcbca59572a856ca554af9ab3f52120b6f2a929
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Sep 22 21:32:06 2015 -0700
nir/lower_vec_to_movs: Don't emit unneeded movs
It's possible that, if a vecN operation is involved in a phi node, that we
could end up moving from a register to itself. If swizzling is involved,
we need to emit the move but. However, if there is no swizzling, then the
mov is a no-op and we might as well not bother emitting it.
Shader-db results on Haswell:
total instructions in shared programs: 6262536 -> 6259558 (-0.05%)
instructions in affected programs: 184780 -> 181802 (-1.61%)
helped: 838
HURT: 0
Reviewed-by: Eduardo Lima Mitev <elima at igalia.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 65e80ce5b565953ffb07586790eeea51199ca9cf
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Sep 22 21:11:23 2015 -0700
nir/lower_vec_to_movs: Properly handle source modifiers on vecN ops
I don't know of any piglit tests that are currently broken. However, there
is nothing stopping a vecN instruction from getting source modifiers and
lower_vec_to_movs is run after we lower to source modifiers.
Reviewed-by: Eduardo Lima Mitev <elima at igalia.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit aae0c88797e7e44c55873b3e97cceed5c6e6cded
Author: Ville Syrjälä <ville.syrjala at linux.intel.com>
Date: Mon Mar 23 14:47:28 2015 +0200
i915: Make hw_prim[] const
The table used to map the GL primitive to the hw primitive never
changes so make it const.
Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 84fec757de2f8c6ba47f2f56077993d62538711a
Author: Ville Syrjälä <ville.syrjala at linux.intel.com>
Date: Mon Mar 23 14:47:23 2015 +0200
t_dd_dmatmp: Make the render_tab[]s const
These tables hold function pointers and they never change so
make them const.
Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit abbaf3301f2405adf61d2804706c00a391a1336e
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Sep 14 17:57:15 2015 -0700
mesa: Remove unused HAVE_TRI_STRIP_1 defines
Defined to 0 in a few places, but it's not used anywhere.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit d830965057bc01734dcca415969ebb6950f2e58c
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Sep 14 17:29:50 2015 -0700
t_dd_dmatmp: Constify dmasz
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 8e9968f184dd1f9727d1095aa45936d5c6ec9f16
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Sep 14 17:26:10 2015 -0700
t_dd_dmatmp: Silence comparison between signed and unsigned integer expression warnings
../../../../../src/mesa/tnl_dd/t_dd_dmatmp.h:83:28: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
nr = MIN2(currentsz, count - j);
^
../../../../../src/mesa/tnl_dd/t_dd_dmatmp.h:83:55: warning: signed and unsigned type in conditional expression [-Wsign-compare]
nr = MIN2(currentsz, count - j);
^
../../../../../src/mesa/tnl_dd/t_dd_dmatmp.h:116:25: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
nr = MIN2(currentsz, count - j);
^
../../../../../src/mesa/tnl_dd/t_dd_dmatmp.h:116:52: warning: signed and unsigned type in conditional expression [-Wsign-compare]
nr = MIN2(currentsz, count - j);
^
../../../../../src/mesa/tnl_dd/t_dd_dmatmp.h:140:25: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
nr = MIN2(currentsz, count - j);
^
../../../../../src/mesa/tnl_dd/t_dd_dmatmp.h:140:52: warning: signed and unsigned type in conditional expression [-Wsign-compare]
nr = MIN2(currentsz, count - j);
^
../../../../../src/mesa/tnl_dd/t_dd_dmatmp.h: In function 'intel_render_line_loop_verts':
../../../../../src/mesa/tnl_dd/t_dd_dmatmp.h:174:28: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
nr = MIN2(currentsz, count - j);
^
../../../../../src/mesa/tnl_dd/t_dd_dmatmp.h:174:55: warning: signed and unsigned type in conditional expression [-Wsign-compare]
nr = MIN2(currentsz, count - j);
^
../../../../../src/mesa/tnl_dd/t_dd_dmatmp.h:224:25: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
nr = MIN2(currentsz, count - j);
^
../../../../../src/mesa/tnl_dd/t_dd_dmatmp.h:224:52: warning: signed and unsigned type in conditional expression [-Wsign-compare]
nr = MIN2(currentsz, count - j);
^
../../../../../src/mesa/tnl_dd/t_dd_dmatmp.h:255:25: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
nr = MIN2(currentsz, count - j);
^
../../../../../src/mesa/tnl_dd/t_dd_dmatmp.h:255:52: warning: signed and unsigned type in conditional expression [-Wsign-compare]
nr = MIN2(currentsz, count - j);
^
../../../../../src/mesa/tnl_dd/t_dd_dmatmp.h:281:25: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
nr = MIN2(currentsz, count - j + 1);
^
../../../../../src/mesa/tnl_dd/t_dd_dmatmp.h:281:56: warning: signed and unsigned type in conditional expression [-Wsign-compare]
nr = MIN2(currentsz, count - j + 1);
^
../../../../../src/mesa/tnl_dd/t_dd_dmatmp.h: In function 'intel_render_poly_verts':
../../../../../src/mesa/tnl_dd/t_dd_dmatmp.h:313:28: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
nr = MIN2(currentsz, count - j + 1);
^
../../../../../src/mesa/tnl_dd/t_dd_dmatmp.h:313:59: warning: signed and unsigned type in conditional expression [-Wsign-compare]
nr = MIN2(currentsz, count - j + 1);
^
../../../../../src/mesa/tnl_dd/t_dd_dmatmp.h:365:28: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
nr = MIN2(currentsz, count - nr);
^
../../../../../src/mesa/tnl_dd/t_dd_dmatmp.h:365:56: warning: signed and unsigned type in conditional expression [-Wsign-compare]
nr = MIN2(currentsz, count - nr);
^
../../../../../src/mesa/tnl_dd/t_dd_dmatmp.h:83:28: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
nr = MIN2(currentsz, count - j);
^
../../../../../src/mesa/tnl_dd/t_dd_dmatmp.h:83:55: warning: signed and unsigned type in conditional expression [-Wsign-compare]
nr = MIN2(currentsz, count - j);
^
../../../../../src/mesa/tnl_dd/t_dd_dmatmp.h:116:25: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
nr = MIN2(currentsz, count - j);
^
../../../../../src/mesa/tnl_dd/t_dd_dmatmp.h:116:52: warning: signed and unsigned type in conditional expression [-Wsign-compare]
nr = MIN2(currentsz, count - j);
^
../../../../../src/mesa/tnl_dd/t_dd_dmatmp.h:140:25: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
nr = MIN2(currentsz, count - j);
^
../../../../../src/mesa/tnl_dd/t_dd_dmatmp.h:140:52: warning: signed and unsigned type in conditional expression [-Wsign-compare]
nr = MIN2(currentsz, count - j);
^
../../../../../src/mesa/tnl_dd/t_dd_dmatmp.h: In function 'radeon_dma_render_line_loop_verts':
../../../../../src/mesa/tnl_dd/t_dd_dmatmp.h:174:28: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
nr = MIN2(currentsz, count - j);
^
../../../../../src/mesa/tnl_dd/t_dd_dmatmp.h:174:55: warning: signed and unsigned type in conditional expression [-Wsign-compare]
nr = MIN2(currentsz, count - j);
^
../../../../../src/mesa/tnl_dd/t_dd_dmatmp.h:224:25: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
nr = MIN2(currentsz, count - j);
^
../../../../../src/mesa/tnl_dd/t_dd_dmatmp.h:224:52: warning: signed and unsigned type in conditional expression [-Wsign-compare]
nr = MIN2(currentsz, count - j);
^
../../../../../src/mesa/tnl_dd/t_dd_dmatmp.h:255:25: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
nr = MIN2(currentsz, count - j);
^
../../../../../src/mesa/tnl_dd/t_dd_dmatmp.h:255:52: warning: signed and unsigned type in conditional expression [-Wsign-compare]
nr = MIN2(currentsz, count - j);
^
../../../../../src/mesa/tnl_dd/t_dd_dmatmp.h:281:25: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
nr = MIN2(currentsz, count - j + 1);
^
../../../../../src/mesa/tnl_dd/t_dd_dmatmp.h:281:56: warning: signed and unsigned type in conditional expression [-Wsign-compare]
nr = MIN2(currentsz, count - j + 1);
^
../../../../../src/mesa/tnl_dd/t_dd_dmatmp.h: In function 'radeon_dma_render_poly_verts':
../../../../../src/mesa/tnl_dd/t_dd_dmatmp.h:313:28: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
nr = MIN2(currentsz, count - j + 1);
^
../../../../../src/mesa/tnl_dd/t_dd_dmatmp.h:313:59: warning: signed and unsigned type in conditional expression [-Wsign-compare]
nr = MIN2(currentsz, count - j + 1);
^
../../../../../src/mesa/tnl_dd/t_dd_dmatmp.h:365:28: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
nr = MIN2(currentsz, count - nr);
^
../../../../../src/mesa/tnl_dd/t_dd_dmatmp.h:365:56: warning: signed and unsigned type in conditional expression [-Wsign-compare]
nr = MIN2(currentsz, count - nr);
^
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit d663d8f5d4088407af982577be075fe7e79d4e3d
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Sep 14 17:12:06 2015 -0700
t_dd_dmatmp: Use stdbool.h
No piglit regressions on i915 (G33) or radeon (Radeon 7500).
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit b7259fc6b0c3a94d2ddbea74470e551c877fc324
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Sep 14 17:10:05 2015 -0700
t_dd_dmatmp: General indentation and formatting fixes
No piglit regressions on i915 (G33) or radeon (Radeon 7500).
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 57ae5c237d65b7283964f61779fcb07096da8b5b
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Sep 14 17:04:33 2015 -0700
t_dd_dmatmp: Indentation and formatting fixes after HAVE_ELTS change
No piglit regressions on i915 (G33) or radeon (Radeon 7500).
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 25b42f13bd762119eb1dae565e999c1bd52f7c2d
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Sep 14 16:57:32 2015 -0700
t_dd_dmatmp: Remove HAVE_ELTS support
Two drivers use this file, and neither supports ELTs.
No piglit regressions on i915 (G33) or radeon (Radeon 7500).
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 1f374958fdc02050e9d3c0f2dfd0b87702470fb7
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Sep 14 14:35:51 2015 -0700
t_dd_dmatmp: Indentation and formatting fixes after HAVE_TRI_FANS change
No piglit regressions on i915 (G33) or radeon (Radeon 7500).
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 03c3208c185c29dd26446ffa5bae8f05f51d3f1b
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Sep 14 14:31:09 2015 -0700
t_dd_dmatmp: Require HAVE_TRI_FANS
Two drivers use this file, and both support triangle fans.
No piglit regressions on i915 (G33) or radeon (Radeon 7500).
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 2e19ed3cb54cb33e8d772bfde78cc1d33dc0853b
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Sep 14 14:29:31 2015 -0700
t_dd_dmatmp: Indentation and formatting fixes after HAVE_TRI_STRIPS change
v2: Fix '- nr' typo noticed by Marius.
No piglit regressions on i915 (G33) or radeon (Radeon 7500).
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Brian Paul <brianp at vmware.com> [v1]
commit fd97a055083a8927d1f6458b9015a202f43f8f01
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Sep 14 14:23:44 2015 -0700
t_dd_dmatmp: Require HAVE_TRI_STRIPS
Two drivers use this file, and both support triangle strips.
No piglit regressions on i915 (G33) or radeon (Radeon 7500).
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 22b73f3c2a09375c49bd6202dabdbff368351315
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Sep 14 14:19:44 2015 -0700
t_dd_dmatmp: Require HAVE_TRIANGLES
Two drivers use this file, and both support triangles.
No piglit regressions on i915 (G33) or radeon (Radeon 7500).
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit dcd8e49962b550f8854fff20e0369dae5550f640
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Sep 14 14:14:08 2015 -0700
t_dd_dmatmp: Indentation and formatting fixes after HAVE_LINE_STRIPS change
No piglit regressions on i915 (G33) or radeon (Radeon 7500).
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 1ecdf956ac699aee5e8c62887a40608accb0ac94
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Sep 14 14:08:40 2015 -0700
t_dd_dmatmp: Require HAVE_LINE_STRIPS
Two drivers use this file, and both support line strips.
No piglit regressions on i915 (G33) or radeon (Radeon 7500).
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 1ab8a69a3b7e2846a602f14aa6e4dd5994be1615
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Sep 14 14:51:46 2015 -0700
t_dd_dmatmp: Indentation and formatting fixes after HAVE_LINES change
No piglit regressions on i915 (G33) or radeon (Radeon 7500).
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit b8461e03f01167a8bafe7fa9f12ff0ec246533b4
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Sep 14 12:46:21 2015 -0700
t_dd_dmatmp: Require HAVE_LINES
Two drivers use this file, and both support lines.
No piglit regressions on i915 (G33) or radeon (Radeon 7500).
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 265624c5af6f7eaa18bc81cc8aa8aeb0f5801861
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Sep 14 12:41:33 2015 -0700
t_dd_dmatmp: Indentation and formatting fixes after HAVE_QUADS change
No piglit regressions on i915 (G33) or radeon (Radeon 7500).
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 4ecc387a935d2364c5be02cbf7a72b0a05fa419a
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Sep 14 12:38:19 2015 -0700
t_dd_dmatmp: Remove HAVE_QUADS support
Two drivers use this file, and neither supports quads.
No piglit regressions on i915 (G33) or radeon (Radeon 7500).
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 249ba09f59af870dc55eacede5b1e164873c397d
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Sep 14 12:36:33 2015 -0700
t_dd_dmatmp: Remove HAVE_QUAD_STRIPS support
Two drivers use this file, and neither supports quad strips.
No piglit regressions on i915 (G33) or radeon (Radeon 7500).
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 25543d8ec506ef32599af6f5e0dd735e01b39909
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Sep 14 11:59:22 2015 -0700
t_dd_dmatmp: Use addition instead of subtraction in loop bounds
This is used everywhere else in this file because it avoids problems
when count is zero (due to trimming).
No piglit regressions on i915 (G33) or radeon (Radeon 7500).
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38109
Reviewed-by: Brian Paul <brianp at vmware.com>
Cc: Marius Predut <marius.predut at intel.com>
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
commit c0b3b2f7603eab210acdb2e654e5411fe912ca34
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Sep 14 11:56:20 2015 -0700
t_dd_dmatmp: Pull out common 'count -= count & 3' code
This was missing in the HAVE_TRIANGLES path, and that could cause
incorrect rendering.
No piglit regressions on i915 (G33) or radeon (Radeon 7500).
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38109
Reviewed-by: Brian Paul <brianp at vmware.com>
Cc: Marius Predut <marius.predut at intel.com>
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
commit 0d475ee2b989ac1697720ca391913e9158156bdc
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Sep 14 11:50:28 2015 -0700
t_dd_dmatmp: Use '& 3' instead of '% 4' everywhere
No piglit regressions on i915 (G33) or radeon (Radeon 7500).
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
commit fad8d54de7e7f908cb0d06f0b54af8440e689928
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Sep 14 11:46:50 2015 -0700
t_dd_dmatmp: Clean up improper code formatting from previous patch
No piglit regressions on i915 (G33) or radeon (Radeon 7500).
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
commit d7bf7969b90f66ee614f2d2225f3a821d5396a89
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Sep 14 11:37:12 2015 -0700
t_dd_dmatmp: Make "count" actually be the count
The value passed in count previously was "vertex after the last vertex
to be processed." Calling that "count" was misleading and kind of mean.
Looking at the code, many functions immediately do "count-start" to get
back the true count. That's just silly.
If it is better for the loops to be 'for (j = start; j < (start +
count); j++)', GCC will do that transformation.
NOTE: There is some strange formatting left by this patch. That was
done to make it more obvious that the before and after code is
equivalent. These will be fixed in the next patch.
No piglit regressions on i915 (G33) or radeon (Radeon 7500).
v2: Fix a remaining (count-start) in render_quad_strip_verts.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Brian Paul <brianp at vmware.com> [v1]
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
commit f2e75ac88a92ab2180de576aca298929cfce03f2
Author: Antia Puentes <apuentes at igalia.com>
Date: Tue Sep 22 18:17:45 2015 +0200
i965/vec4: Don't coalesce regs in Gen6 MATH ops if reswizzle/writemask needed
Gen6 MATH instructions can not execute in align16 mode, so swizzles or
writemasking are not allowed.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92033
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit cf439951b791827677e96d29e209b5fc08d07a2e
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Tue Feb 24 19:02:56 2015 +0100
mesa: Fix GL_FRAMEBUFFER_ATTACHMENT_OBJECT_TYPE for default framebuffer.
From section 9.2. Binding and Managing Framebuffer Objects:
"Upon successful return from Get*FramebufferAttachmentParameteriv, if
pname is FRAMEBUFFER_ATTACHMENT_OBJECT_TYPE, then params will contain
one of NONE, FRAMEBUFFER_DEFAULT, TEXTURE, or RENDERBUFFER, identifying
the type of object which contains the attached image."
And then it clarifies further:
"If the value of FRAMEBUFFER_ATTACHMENT_OBJECT_TYPE is NONE, then
either no framebuffer is bound to target; or the default framebuffer is
bound, attachment is DEPTH or STENCIL, and the number of depth or stencil
bits, respectively, is zero"
Currently, if the default framebuffer is bound, we always return
GL_FRAMEBUFFER_DEFAULT for FRAMEBUFFER_ATTACHMENT_OBJECT_TYPE, but
according to the spec, when GL_DEPTH or GL_STENCIL attachments are
the ones being queried, we should return GL_NONE if they don't exist.
Fixes the following dEQP test:
dEQP-GLES3.functional.state_query.fbo.framebuffer_attachment_x_size_initial
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Cc: "10.6" <mesa-stable at lists.freedesktop.org>
commit 89524e717147053fe9da6e30daa0aaffcd29d26d
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Tue Sep 22 14:34:11 2015 +0300
glsl: bail out early in _mesa_ShaderSource if no shaderobj
Patch fixes a crash in conformance test that tries out different
invalid arguments for glShaderSource and glGetShaderSource:
ES2-CTS.gtf.GL.glGetShaderSource.getshadersource_programhandle
This is a regression from commit:
04e201d0c02cd30ace5c6fe80e9f021ebb733682
Additions in v2 also fix following failing deqp test:
dEQP-GLES[2|3].functional.negative_api.shader.shader_source
v2: cleanup function, do check earlier (Iago Toral)
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 10da96887c785930c2553b2d5bde91e52b8b034a
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Sep 21 13:58:19 2015 -0700
i965/vec4: Detect and delete useless MOVs.
With NIR:
instructions in affected programs: 111508 -> 109193 (-2.08%)
helped: 507
Without NIR:
instructions in affected programs: 28763 -> 28474 (-1.00%)
helped: 186
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit e7496fed2a2428b704b8aeab5f42df8e6a2f7ae1
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Sep 22 16:57:03 2015 -0700
prog_to_nir: Use nir_op_dph
Shader-db results on HSW:
instructions in affected programs: 72 -> 56 (-22.22%)
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 999ff3c77d5d978224ee01ca19121e15698c2c6a
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Sep 22 17:29:49 2015 -0700
nir/lower_alu_to_scalar: Add support for nir_op_fdph
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 2e5423ad6345e027bb40c75ffc0e9e64843b9c05
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Sep 22 16:55:42 2015 -0700
i965/vec4: Add support for fdph_replicated
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit e5a9346d0046b0a78620687e75239b30e3876662
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Sep 22 16:54:27 2015 -0700
nir: Add fdph and fdph_replicated opcodes
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 0f9bf647705db48a88c700bfa7ca3d4a9f6b4f56
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Sep 22 17:16:59 2015 -0700
nir/lower_alu_to_scalar: Return after lower_reduction
We don't use any of the code after the switch anyway. Since we check for
num_components == 1 and early-return, it doesn't get executed so
everything's ok. However, it makes it much clearer what's going on if we
simply do an early return.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 2b79db2c0216075f5047fe3723d100fd70fc59c7
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Sep 22 17:14:45 2015 -0700
nir/lower_alu_to_scalar: Use the builder
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit f5991ebf3418c48486bda072ad7aba247bc21923
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Tue Sep 9 21:15:09 2014 +1200
i965: Add defines for tessellation stages
v2 (Ken):
- Squash together commits for HS, DS, and TE, as well as fixes.
- Add INTEL_MASK variants so we can use SET_FIELD if we want.
- Rename GEN7_HS_INSTANCE_CONTROL to GEN7_HS_INSTANCE_COUNT to match
the documentation.
- Add some more fields from the PRMs.
- Add Broadwell variants.
Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
commit 8ae8feca844c953510e94f116be2fc37fb14ffe0
Author: Grazvydas Ignotas <notasas at gmail.com>
Date: Wed Sep 23 01:50:31 2015 +0300
r600g: update num_dw in scissor_enable workaround
"r600g: apply disable workaround on all scissors" forgot to update
num_dw, fix it.
Fixes: fbb423b433 "r600g: apply disable workaround on all scissors"
Reported-and-tested-by: Markus Trippelsdorf <markus at trippelsdorf.de>
Signed-off-by: Grazvydas Ignotas <notasas at gmail.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 1bd89db921105dbe76047144b4719d4617aee1d8
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Wed Sep 16 17:19:50 2015 +0200
i965/vec4: refactor brw_vec4_copy_propagation.
Now it is more similar to brw_fs_copy_propagation, with three
clear stages:
1) Build up the value we are propagating as if it were the source of a
single MOV:
2) Check that we can propagate that value
3) Build the final value
Previously everything was somewhat messed up, making the
implementation on some specific cases, like knowing if you can
propagate from a previous instruction even with type mismatches, even
messier (for example, with the need of maintaining more of one
has_source_modifiers). The refactoring clears stuff, and gives
support to this mentioned use case without doing anything extra
(for example, only one has_source_modifiers is used).
Shader-db results for vec4 programs on Haswell:
total instructions in shared programs: 1683842 -> 1669037 (-0.88%)
instructions in affected programs: 739837 -> 725032 (-2.00%)
helped: 6237
HURT: 0
v2: using 'arg' index to get the from inst was wrong
v3: rebased against last change on the previous patch of the series
v4: don't need to track instructions on struct copy_entry, as we
only set the source on a direct copy
v5: change the approach for a refactoring
v6: tweaked comments
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 4a03066e5a23058d8cf5a3c34b889ec484c36034
Author: Brian Paul <brianp at vmware.com>
Date: Mon Sep 21 09:03:45 2015 -0600
st/mesa: remove st_bind_framebuffer()
The function was a no-op and if the ctx->Driver.BindFramebuffer pointer
is null, Mesa won't try to use it.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit b590ffd0f95bfe5ff7d44412e4916bba40630be9
Author: Brian Paul <brianp at vmware.com>
Date: Thu Sep 17 09:49:07 2015 -0600
mesa: const-qualify _mesa_is_legal_tex_storage_format ctx param
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit acee1a322d0a483aa155ff05cfaa124e84865656
Author: Brian Paul <brianp at vmware.com>
Date: Thu Sep 17 09:47:36 2015 -0600
mesa: const-qualify _mesa_base_tex_format() ctx param
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 4879b766015eebd01911b40df8bef10081b8fce3
Author: Brian Paul <brianp at vmware.com>
Date: Thu Sep 17 09:45:42 2015 -0600
mesa: const-qualify buffer_object_subdata_range_good() bufObj parameter
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 76dbab0a694d221ce0ea51d8c0b83a4529c42d29
Author: Brian Paul <brianp at vmware.com>
Date: Thu Sep 17 09:45:20 2015 -0600
mesa: whitespace, comment fixes in texstorage.c
commit 419210005a84f1f26da353b945b3f783d53fa56a
Author: Marta Lofstedt <marta.lofstedt at intel.com>
Date: Wed Aug 19 20:25:24 2015 +0200
mesa/es3.1: Enable GL_ARB_vertex_attrib_binding functionality for GLES 3.1
Signed-off-by: Marta Lofstedt <marta.lofstedt at intel.com>
commit cf293e518ebd847cb28e03d4378679c47548206d
Author: Marta Lofstedt <marta.lofstedt at intel.com>
Date: Wed Aug 19 20:25:23 2015 +0200
mesa/es3.1: Allow query of Vertex bindings for GLES 3.1
Signed-off-by: Marta Lofstedt <marta.lofstedt at intel.com>
commit 6c3de8996fbe9447e092cc75ccdd6f720fabaf4d
Author: Marta Lofstedt <marta.lofstedt at intel.com>
Date: Wed Aug 19 20:25:22 2015 +0200
mesa/es3.1 : Align OpenGL ES 3.1 glBindVertexBuffer error handling with OpenGL Core
According to OpenGL ES 3.1 specification 10.3.1:
"An INVALID_OPERATION error is generated if buffer is not zero
or a name returned from a previous call to GenBuffers,
or if such a name has since been deleted with DeleteBuffers."
This error check was previously limited to OpenGL Core.
Signed-off-by: Marta Lofstedt <marta.lofstedt at intel.com>
commit 7f8815bcb9af9b4b374ad7bd6e7cfa7529a6c980
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Mon Sep 7 15:08:13 2015 +0300
i965: fix textureGrad for cubemaps
Fixes bugs exposed by commit
2b1cdb0eddb73f62e4848d4b64840067f1f70865 in:
ES3-CTS.gtf.GL3Tests.shadow.shadow_execution_frag
No regressions observed in deqp, CTS or Piglit.
v2: address review feedback from Iago Toral:
- move rho calculation to else branch
- optimize dx and dy calculation
- fix documentation inconsistensies
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogovin at intel.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91114
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
commit 5cede90f6269d517a420856cced705c2d2cc7ef6
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Sep 17 13:18:41 2015 -0700
nir: Report progress from nir_normalize_cubemap_coords().
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit d7ffd90ecb1e91fc3e0c816c06c71a2743d48276
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Sep 17 13:08:03 2015 -0700
nir: Add braces around multi-line loop.
This was correct but not our usual style.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 0a1adaf11d051b71b4c46aabee2e5342f2d6aef3
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Sep 17 13:00:58 2015 -0700
nir: Report progress from nir_lower_system_values().
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit dc18b9357b553a972ea439facfbc55e376f1179f
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Sep 17 12:33:36 2015 -0700
nir: Report progress from nir_split_var_copies().
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit cfae0f8a3ae98ae10bcf9e4f1429f66165a17d95
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Sep 17 12:29:49 2015 -0700
nir: Report progress from nir_lower_locals_to_regs().
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 1adde5b87e43b1512c0744c412d51cbc0078329b
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Sep 17 10:57:14 2015 -0700
nir: Report progress from nir_remove_dead_variables().
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 9f5e7ae9d83ce6de761936b95cd0b7ba4c1219c4
Author: Jason Ekstrand <jason at jlekstrand.net>
Date: Wed Sep 9 17:50:09 2015 -0700
nir: Report progress from lower_vec_to_movs().
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 967a5ddb88d248aa317964c9b0951332b2494aab
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Sep 17 08:38:10 2015 -0700
nir: Report progress from nir_lower_globals_vars_to_local().
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 60befc63470a9cf1ac59ca74cd0a8164a25db09e
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Sep 21 11:18:23 2015 -0700
i965: Clean up GLSL compiler option setup
The only functional change here is that we now set EmitNoIndirectOutput and
EmitNoIndirectTemp for compute shaders. Compute shaders don't have outputs
per-se and we should have been setting EmitNoIndirectTemp all along.
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 6dfc5e28f7d08094210d8cecd3ed4a5b393dafe9
Author: Jeremy Huddleston <jeremyhu at freedesktop.org>
Date: Sat Aug 29 14:51:45 2015 -0700
configure.ac: Add support to enable read-only text segment on x86.
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
Bugzilla: https://bugs.gentoo.org/240956
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit c1e38ad37042b0ec261eb0ba5631b7ff0ee7a9da
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Thu Sep 10 16:59:12 2015 -0700
i965/skl: Use larger URB size where available.
All SKL SKUs except the lowest one which has half the L3 size actually have 384K
of URB per slice.
For once, I can explain how this mistake was made and how it was missed in
review... Historically when we enable a platform and put the production sizes,
you can simply look at the "smallest" SKU and see what its URB size is (and we
assumed it was the 1 slice variant). Since on newer platforms the URB sizes are
scaled automatically by HW, this was sufficient. On SKL, this is a bit different
as the lowest SKU actually has half of the L3 fused off. GT2 is the 1 slice (not
GT1) variant and it has 384K.
There are no Jenkins tests fixed (or regressions) and we don't expect any fixes
here because you can always run with less URB size.
Thanks to Sarah for bringing this to my attention.
Cc: Sarah Sharp <sarah.a.sharp at intel.com>
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 46362db4a6bb6db64727d3adcb16ca8f32aa70fb
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Sep 21 08:22:12 2015 -0700
nir/builder: Don't use designated initializers
Designated initializers are not allowed in C++ (not even C++11). Since
nir_lower_samplers is now using nir_builder, and nir_lower_samplers is in
C++, this breaks the build on some compilers. Aparently, GCC 5 allows it
in some limited extent because mesa still builds on my system without this
patch.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92052
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit d513388c8aa1ef4edb937e97a75b953f1abe16f3
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Sep 10 16:53:08 2015 -0700
nir: Move system value -> intrinsic mapping into nir.c
This way they're right next to the map going the other direction.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit de7ffdb38343b7f9292184ca827987de9852c80c
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Sep 17 16:12:17 2015 +0100
nir: rename nir_lower_samplers.c{pp,}
With the only C++ function having its own wrapper we can 'demote' this
file to a normal C one. This allows us to get rid of extern C { #include
<foo.h> } 'hacks'. Plus some of the headers may use C99 initializers,
which are not supported by the ISO standard.
This may cause build issue on incremental builds. If so run the
following:
sed -i -e 's|samplers\.cpp|samplers.c|' src/glsl/nir/.deps/nir_lower_samplers.Plo
Fixes: ef8eebc6ad5(nir: support indirect indexing samplers in struct arrays)
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reported-by: Gottfried Haider <gottfried.haider at gmail.com>
Tested-by: Gottfried Haider <gottfried.haider at gmail.com>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
commit d130cda4531602185dcf7cafe217c9b7abdba954
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Sep 17 15:57:26 2015 +0100
nir: add C wrapper around glsl_type::record_location_offset
This will allow us to convert nir_lower_sampler.cpp to C.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Tested-by: Gottfried Haider <gottfried.haider at gmail.com>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
commit bdb1faf44eac0128baaab62bd4c425c7c3424299
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Sep 17 16:03:48 2015 +0100
nir: move stdio.h inclusion before extern C
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Tested-by: Gottfried Haider <gottfried.haider at gmail.com>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
commit c1070550c289d48ef389aeb8c564d1abd1123ad1
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Sep 21 07:42:27 2015 -0700
i965: Fix MRF register number assertions for compr4.
compr4 is represented by setting the high bit on the MRF number.
We need to mask it out before sanity checking the register number.
Fixes ~8000 assert fails on Ironlake and G45.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92066
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
commit 72ebd532a163fd92d96a94a4260da1bfb75a62c8
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Sep 18 19:08:35 2015 -0400
radeonsi: implement TXQS support
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Tested-by: Fredrik Bruhn <f at unibap.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 7d5162bdc0850c80f4b9427a2aac6b42c7dcceaa
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Sep 19 16:19:26 2015 -0400
radeonsi: load fmask ptr relative to the resources array
res_ptr already contains the resource values. fmask_ptr needs to be
looked up relative to the start of the resource params.
Note that this only affects indirect loads of MS sampler arrays.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
commit 5d23ce2f15bda866990750b49d7860144dff2e68
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Thu Sep 17 13:43:52 2015 +0200
i965/vec4: Use MRF registers 21-23 for spilling in gen6
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 6789a32075774fc332eb7432910c7fbc21ee2026
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Tue Sep 15 16:33:48 2015 +0200
i965/fs: Use MRF registers 21-23 for spilling in gen6
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit f50645d05c6dffa6463856ded0b8461ac9d24535
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Tue Sep 15 16:00:26 2015 +0200
i965: Turn BRW_MAX_MRF into a macro that accepts a hardware generation
There are some bug reports about shaders failing to compile in gen6
because MRF 14 is used when we need to spill. For example:
https://bugs.freedesktop.org/show_bug.cgi?id=86469
https://bugs.freedesktop.org/show_bug.cgi?id=90631
Discussion in bugzilla pointed to the fact that gen6 might actually have
24 MRF registers available instead of 16, so we could use other MRF
registers and avoid these conflicts (we still need to investigate why
some shaders need up to MRF 14 anyway, since this is not expected).
Notice that the hardware docs are not clear about this fact:
SNB PRM Vol4 Part2's "Table 5-4. MRF Registers Available in Device
Hardware" says "Number per Thread" - "24 registers"
However, SNB PRM Vol4 Part1, 1.6.1 Message Register File (MRF) says:
"Normal threads should construct their messages in m1..m15. (...)
Regardless of actual hardware implementation, the thread should
not assume th at MRF addresses above m15 wrap to legal MRF registers."
Therefore experimentation was necessary to evaluate if we had these extra
MRF registers available or not. This was tested in gen6 using MRF
registers 21..23 for spilling and doing a full piglit run (all.py) forcing
spilling of everything on the FS backend. It was also tested by doing
spilling of everything on both the FS and the VS backends with a piglit run
of shader.py. In both cases no regressions were observed. In fact, many of
these tests where helped in the cases where we forced spilling, since that
triggered the same underlying problem described in the bug reports. Here are
some results using INTEL_DEBUG=spill_fs,spill_vec4 for a shader.py run on
gen6 hardware:
Using MRFs 13..15 for spilling:
crash: 2, fail: 113, pass: 6621, skip: 5461
Using MRFs 21..23 for spilling:
crash: 2, fail: 12, pass: 6722, skip: 5461
This patch sets the ground for later patches to implement spilling
using MRF registers 21..23 in gen6.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 085861083638ec782c17d3aa72ab46f1a0099935
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Wed Sep 16 09:08:19 2015 +0200
i965: Move MRF register asserts out of brw_reg.h
In a later patch we will make BRW_MAX_MRF return a different value depending
on the hardware generation, but it is inconvenient to add a gen parameter
to the brw_reg functions only for the assertions, so move these to places where
we have the hardware generation available.
Ken suggested to add the asserts to brw_set_src0 and brw_set_dest since that
would make sure that we catch all uses of MRF registers, even those coming
from modules that generate native code directly, like blorp. Unfortunately,
this is very late in the process which can make things harder to debug, so add
asserts to the generator as well.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit d48ac93066190077510d635e71631b6574261d08
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Fri Sep 18 08:15:52 2015 +0200
i965: Maximum allowed size of SEND messages is 15 (4 bits)
Until now we only used MRFs 1..15 for regular SEND messages, so the
message length could not possibly exceed the maximum size. Soon we'll
allow to use MRF registers 1..23 in gen6, so we need to be careful
not to build messages that can go beyond the limit. That could occur,
specifically, when building URB write messages, which we may need to
split in chunks due to their size. Previously we would simply go and
create a new message when we reached MRF 13 (since 13..15 were
reserved for spilling), now we also want to check the size of the
message explicitly.
Besides adding that condition to split URB write messages properly,
this patch also adds asserts in the generator. Notice that
brw_inst_set_mlen already asserts for this, but asserting in the
generators is easy and can make debugging easier in some cases.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit b65f91dd3285ca0daee658cdf9ac41caaad2f1fb
Author: Rob Clark <robclark at freedesktop.org>
Date: Sun Sep 20 14:02:29 2015 -0400
nir/print: fix coverity error
Not something actually hit in real life (now state is never non-null,
but only case state->syms is null is if nir_print_instr() path). But it
was something I overlooked the first time, so might as well fix it.
*** CID 1324642: Null pointer dereferences (REVERSE_INULL)
/src/glsl/nir/nir_print.c: 299 in print_var_decl()
293
294 fprintf(fp, " (%s, %u)", loc, var->data.driver_location);
295 }
296
297 fprintf(fp, "\n");
298
>>> CID 1324642: Null pointer dereferences (REVERSE_INULL)
>>> Null-checking "state" suggests that it may be null, but it has already been dereferenced on all paths leading to the check.
299 if (state) {
300 _mesa_set_add(state->syms, name);
301 _mesa_hash_table_insert(state->ht, var, name);
302 }
303 }
304
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 6ba291db4ba4f03ac94560eaae861bc162ac838e
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Fri Sep 18 10:30:12 2015 +0200
i965/vec4/nir: Remove all "this->" snippets
For consistency, either we have all class members dereferenced, or none.
In this case, very few are so lets get rid of them all.
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 8f6fd57db2275df8f86a5a173575b7d807508625
Author: Marcin Åšlusarz <marcin.slusarz at gmail.com>
Date: Sun Sep 20 13:40:10 2015 +0200
dri/common: fix gbm-symbols-check regression
Broken by commit c228514c72cb2fd5fb9e510808e29204fc9e7ae1
"dri/common: use sysconfdir when looking for drirc".
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92054
Signed-off-by: Marcin Åšlusarz <marcin.slusarz at gmail.com>
commit 1e01db0fa990a71c3cf1434324bc88bf579c5ee3
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sun Sep 20 11:59:24 2015 +0100
docs: add news item and link release notes for 10.6.8
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 278a32374c8451129c004adcc13fe368e4f4e708
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sun Sep 20 11:55:41 2015 +0100
docs: add sha256 checksums for 10.6.8
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit 02387926addc62198c9b684f4f51f7cbe06b3e25)
commit 72d407da1028beba976beb725f92e294a5d2f256
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sun Sep 20 11:05:07 2015 +0100
docs: add release notes for 10.6.8
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit 91c6302734574e91424a7ccb52b6368b712366cc)
commit 99b1f4751f97631011b64fabcb57acf6beae01ac
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Thu Aug 27 16:29:06 2015 -0700
mesa/teximage: reuse compressed format utility functions for base_format
Reuse utility functions instead of reimplementing the same logic.
* _mesa_is_compressed_format() performs the required checking to
determine format support in the current context.
* _mesa_gl_compressed_format_base_format() returns the base format.
As a side effect, we now check that we're in a desktop context when
determining support for the FXT1 and RGTC formats. This is in agreement
with our extension table and the glext headers.
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
commit db2777091d70c7abd28e0a8aac16b4a416e42e81
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Thu Aug 27 16:25:48 2015 -0700
mesa/texcompress: add compressed formats to base format utility function
Add S3TC and PALETTE formats.
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
commit 29835fe19e0ca73a8017427498056ff7eb713cdd
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Wed Aug 26 16:36:11 2015 -0700
mesa/glformats: refactor compressed format support function
Instead of case statements, use _mesa_get_format_layout() to
determine if a GL format is part of a family of compressed formats.
v2. restrict LATC formats to API_OPENGL_COMPAT (Ilia).
rename the variable mFormat to m_format.
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
commit 31a5135cd793951191c4a2fb86a50253a9931454
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Wed Aug 26 16:25:44 2015 -0700
mesa/formats: add MESA_LAYOUT_LATC
This enables us to predicate statments on a compressed format being
a type of LATC format. Also, remove the comment that lists the enum
(it was getting a tad long).
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
commit c228514c72cb2fd5fb9e510808e29204fc9e7ae1
Author: Marcin Åšlusarz <marcin.slusarz at gmail.com>
Date: Sat Sep 19 19:17:34 2015 +0200
dri/common: use sysconfdir when looking for drirc
Useful when locally installed mesa has more quirks than the system one.
Signed-off-by: Marcin Åšlusarz <marcin.slusarz at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 9ffc1049cae07e4e2d2dc8f4d1f5f113b4b1fdc4
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Sep 17 13:35:33 2015 -0400
freedreno/ir3: use nir two-sided-color lowering
With this, we completely switch over to nir lowering passes instead of
tgsi_lowering. So one step closer to supporting direct glsl or spirv to
nir support for freedreno a3xx/a4xx.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit e13ed3ffb4d5267e7b79eece448abf1db1438ea1
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Sep 17 13:17:08 2015 -0400
nir: add two-sided-color lowering pass
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit e4dfcdcbecee9d11709e85524222d748d0e27112
Author: Rob Clark <robclark at freedesktop.org>
Date: Fri Sep 18 13:23:36 2015 -0400
nir/build: add nir_vec() helper
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit c71cb670ba786a4bc443d23e6aa4b866e069dcd2
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Sep 16 13:42:21 2015 -0400
freedreno/ir3: lower txp/clamp in NIR
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 3745c38425b3e1da5c94a5f900eb5fdc44da9439
Author: Rob Clark <robclark at freedesktop.org>
Date: Fri Sep 18 10:44:27 2015 -0400
nir/lower_tex: add support to clamp texture coords
Some hardware needs to clamp texture coordinates to [0.0, 1.0] in the
shader to emulate GL_CLAMP. This is added to lower_tex_proj since, in
the case of projected coords, the clamping needs to happen *after*
projection.
v2: comments/suggestions from Ilia and Eric, use txs to get texture size
and clamp RECT textures to their dimensions rather than [0.0, 1.0] to
avoid having to lower RECT textures to 2D.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 1ce8060c25c7f2c7a54159fab6a6974c0ba182a8
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Sep 16 16:49:14 2015 -0400
nir/lower_tex: support for lowering RECT textures
v2: comments/suggestions from Ilia and Eric, split out get_texture_size()
helper so we can use it in the next commit for clamping RECT textures.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit faf5f174ddbc7680f6947ceababb94fdb552bcdb
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Sep 16 12:56:58 2015 -0400
nir/lower_tex: support projector lowering per sampler type
Some hardware, such as adreno a3xx, supports txp on some but not all
sampler types. In this case we want more fine grained control over
which texture projectors get lowered.
v2: split out nir_lower_tex_options struct to make it easier to
add the additional parameters coming in the following patches
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit f83ba7bc41a381a0e52c456431dbe1a15176ffb4
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Sep 16 12:53:12 2015 -0400
nir/lower_tex: split out project_src() helper
Split this out to reduce noise in later patches.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit d9b9ff76f17ee36b87b2722fa2a19e1d9f036c26
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Sep 17 07:54:35 2015 -0400
nir: rename nir_lower_tex_projector
Since the following patches will add additional tex-lowering related
functionality, which doesn't make sense to split out into a separate
pass (as they would require duplication of the projector lowering
logic), let's give this pass a more generic name.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 06d31dceae611b7d5c11442aa9bf8178067bcb62
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Wed Sep 16 10:26:55 2015 +0200
i965/vec4: Change types as needed to propagate source modifiers using current instruction
SEL and MOV instructions, as long as they don't have source modifiers, are
just copying bits around. So those kind of instruction could be propagated
even if there are type mismatches. This is needed because NIR generates
integer SEL and MOV instructions whenever it doesn't know what else to
generate.
This commit adds support for copy propagation using current instruction
as reference.
Equivalent to commit 472ef9 but for vec4.
v2: include check for saturate, as Jason Ekstrand suggested
v3: check that the dst.type and the src type are the same, in order to
solve (among others) the following deqp regression with v2:
dEQP-GLES3.functional.shaders.operator.unary_operator.minus.lowp_uint_vertex
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit f7ca52dd6d8b4b0fcdf01d8def5edf913ece6861
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Fri Sep 18 11:02:34 2015 +0200
i965/fs: Fix comparison between signed and unsigned integer expressions
brw_fs_visitor.cpp: In member function 'void fs_visitor::emit_urb_writes()':
brw_fs_visitor.cpp:977:58: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit afa1efdc8522d987e3af7c7a6272021caa33eb82
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Tue Sep 15 09:17:20 2015 +0300
mesa: fix errors when reading depth with glReadPixels
OpenGL ES 3.0 spec 3.7.2 "Transfer of Pixel Rectangles" specifies
DEPTH_COMPONENT, UNSIGNED_INT as a valid couple, validation for
internal format is checked by is_float_depth().
Fix regression caused by 81d2fd91a90e5b2fd9fd74792a7a7c329f0e4d29 in:
ES3-CTS.gtf.GL3Tests.packed_pixels.packed_pixels
Test uses GL_DEPTH_COMPONENT, UNSIGNED_INT only when GL_NV_read_depth
extension is present.
v2: change check in _mesa_error_check_format_and_type to be explicit
for ES 2.0+, desktop OpenGL does not allow this behaviour + uses
this function for both glReadPixels and glDrawPixels validation.
(No Piglit regressions seen with v2.)
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com> [v1]
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92009
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
commit 2e4ab489b5963e57df01fa20bb95d67139de8b75
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Sep 17 21:07:41 2015 -0400
nir/builder: fix c++11 compiler warning
Fixes:
In file included from nir/nir_lower_samplers.cpp:27:0:
nir/nir_builder.h: In function 'nir_ssa_def* nir_channel(nir_builder*, nir_ssa_def*, int)':
nir/nir_builder.h:222:37: warning: narrowing conversion of 'c' from 'int' to 'unsigned int' inside { } is ill-formed in C++11 [-Wnarrowing]
unsigned swizzle[4] = {c, c, c, c};
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 7c72f593adc0bbe9570236636abf64b4fc18d88d
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Sep 17 21:06:11 2015 -0400
nir: really actually fix comment this time
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 5305603b9de52e59b9c5eec440f90a12cafa91a1
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Sep 17 18:18:45 2015 -0400
nir/print: print variable names
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
commit ba78260b0fbd291618df63bc7a54be0a36148b40
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Sep 17 18:18:19 2015 -0400
nir: some comment fixups
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
commit c70ed861722c45753ae9a24cf4c00643f0640e2f
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Sep 16 13:57:26 2015 -0400
freedreno/ir3: add --gpu arg to cmdline compiler
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit c970ec0577649e2f1b0532c2a62e279b784f8687
Author: Rob Clark <robclark at freedesktop.org>
Date: Sat Sep 12 11:15:32 2015 -0400
freedreno/a4xx: wire up ucp support
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 91ec210ea8e35af8a7b30fa599b67b1faa55f34c
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Sep 10 16:09:13 2015 -0400
freedreno/ir3: add support for ucp
Use nir_lower_clip pass for adding the VS/FS instructions to handle
user-clip-planes and CLIPDIST. Wire up support for load_user_clip_plane
intrinsic to fetch ucp[plane] values as driver-params (passed as const's
to the shader).
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 509e0c4505813ebeaad1c95822156ed2df627487
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Sep 9 14:57:15 2015 -0400
nir: add lowering stage for user-clip-planes / clipdist
The vertex shader lowering adds calculation for CLIPDIST, if needed
(ie. user-clip-planes), and the frag shader lowering adds conditional
kills based on CLIPDIST value (which should be treated as a normal
interpolated varying by the driver).
Note that this won't quite do the right thing in the face of MSAA plus
user-clip-planes, since all the samples would be killed or not (rather
than potentially only a portion of them). But it's better than no UCP
support at all for drivers that don't have this in hw.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 53671a37238fd34f08d91d5d079d26437f21a473
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Aug 27 17:42:40 2015 -0400
nir: add sysval for user-clip-planes
For lowering user-clip-planes, we need a way to pass the enabled/used
user-clip-planes in to shader.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
commit c4572b7dfe7a4ae9dc6e900f89786fa9cf7769df
Author: Rob Clark <robclark at freedesktop.org>
Date: Fri Sep 11 17:20:48 2015 -0400
freedreno/ir3: convert from tgsi semantic/index to varying-slot
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 4a121e1a90dc34677d9a68e8877dfe53f1e889a2
Author: Rob Clark <robclark at freedesktop.org>
Date: Fri Sep 11 17:01:23 2015 -0400
glsl: add SYSTEM_VALUE_VERTEX_CNT
Used internally in freedreno/ir3 to calc stream-out position. Seems
like a generic enough way to implement stream-out (using str instrs),
plus it avoids compiler warnings by sneaking in a non-enum value in
switch statements.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit e523f69b1d2f0cb3ff7659e3c55b9a2e40240c9c
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Sep 10 17:25:18 2015 -0400
freedreno/ir3: switch to shader_enums.h interp constants
A small step towards un-TGSI'ifying ir3.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit e844e1007d3baac09ff2cc78879d6974be18ecaf
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Sep 16 22:17:18 2015 -0400
nv50,nvc0: flush texture cache in presence of coherent bufs
This fixes the newly-added arb_texture_buffer_object-bufferstorage
piglit test.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
commit 323c91250682ac931941047f282a613c74b1ba26
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Tue Sep 15 01:32:40 2015 -0400
nv50,nvc0: detect underlying resource changes and update tic
When updating texture buffers, we might end up replacing the whole
buffer. Check that the tic address matches the resource address, and if
not, update the tic and reupload it.
This fixes:
arb_direct_state_access-texture-buffer
arb_texture_buffer_object-data-sync
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
commit 8d3b92af21afb58b6a65e18bb05785d7aae72c27
Author: Boyan Ding <boyan.j.ding at gmail.com>
Date: Sun Aug 30 15:07:33 2015 +0800
vc4: Try to pair up instructions when only one of them has PM bit
Instructions with difference in PM field can actually be paired up if
the one without PM doesn't do packing/unpacking and non-NOP
packing/unpacking operations from PM instruction aren't added to the
other without PM.
total instructions in shared programs: 48209 -> 47460 (-1.55%)
instructions in affected programs: 11688 -> 10939 (-6.41%)
Signed-off-by: Boyan Ding <boyan.j.ding at gmail.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit fc11dbe13f3470ff2a4cb91c6b063db2456664da
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Sep 8 16:45:57 2015 -0700
i965/vec4: Use nir_move_vec_src_uses_to_dest
The idea here is not that it gives register coalescing a little bit of a
helping hand. It doesn't actually fix the coalescing problems, but it
seems to help a good bit.
Shader-db results for vec4 programs on Haswell:
total instructions in shared programs: 1746280 -> 1683959 (-3.57%)
instructions in affected programs: 1259166 -> 1196845 (-4.95%)
helped: 11363
HURT: 148
v2 (Jason Ekstrand):
- Run nir_move_vec_src_uses_to_dest after going out of SSA
- New shader-db numbers
Reviewed-by: Eduardo Lima Mitev <elima at igalia.com>
commit a6c467d6c574baf6636814b51f1dafe2557e22f6
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Sep 8 15:18:01 2015 -0700
nir: Add a pass to rewrite uses of vecN sources to the vecN destination
v2 (Jason Ekstrand):
- Handle non-SSA sources and destinations
Reviewed-by: Eduardo Lima Mitev <elima at igalia.com>
commit ddffe30f404b7dffef2b90879023433ecc7df3e3
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Sep 14 12:25:28 2015 -0700
nir: Add comments to nir_index_instrs and nir_index_ssa_defs
The provided indices have the very nice property that if A dominates B then
A->index <= B->index. We should document that somewhere.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 8ecaef967d6f2775bf7114d857baf3aaa13643a7
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Sep 8 16:43:51 2015 -0700
nir: Add a generic instruction index
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit bd016a2601a741799bc76734deae0cb9ebcb2b8f
Author: Ulrich Weigand <uweigand at de.ibm.com>
Date: Tue Sep 15 15:23:26 2015 +0200
mesa: Fix texture compression on big-endian systems
Various pieces of code to create compressed textures will first
generate an uncompressed RGBA texture into a temporary buffer,
and then read from that buffer while creating the final compressed
texture in the requested format.
The code reading from the temporary buffer assumes the buffer is
formatted as an array of bytes in RGBA order. However, the buffer
is filled using a _mesa_texstore call with MESA_FORMAT_R8G8B8A8_UNORM
format -- this is defined as an array of *integers* holding the
RGBA values in packed format (least-significant to most-significant).
This means incorrect bytes are accessed on big-endian systems.
This patch fixes this by using the MESA_FORMAT_A8B8G8R8_UNORM format
instead on big-endian systems when filling the buffer. This fixes
about 100 piglit test case failures on s390x for me.
Signed-off-by: Ulrich Weigand <ulrich.weigand at de.ibm.com>
Tested-by: Oded Gabbay <oded.gabbay at gmail.com>
Cc: "10.6" "11.0" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied at gmail.com>
commit 7e2865064916b85243788fc69040bb981f53c4f9
Author: Thomas Hellstrom <thellstrom at vmware.com>
Date: Wed Sep 16 05:53:13 2015 -0700
st/xa: Use PIPE_FORMAT_R8_UNORM when available
XA has been using L8_UNORM for a8 and yuv component surfaces.
This commit instead makes XA prefer R8_UNORM since it's assumed to have a
higher availability.
Also neither of these formats are suitable as destination formats using
destination alpha blending, so reject those operations.
Signed-off-by: Thomas Hellstrom <thellstrom at vmware.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit ba02f7a3b6a0e4314753a8e5080db61241563f9c
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Tue Sep 1 13:53:44 2015 +0300
mesa: return initial value for VALIDATE_STATUS if pipe not bound
From OpenGL 4.5 Core spec (7.13):
"If pipeline is a name that has been generated (without subsequent
deletion) by GenProgramPipelines, but refers to a program pipeline
object that has not been previously bound, the GL first creates a
new state vector in the same manner as when BindProgramPipeline
creates a new program pipeline object."
I interpret this as "If GetProgramPipelineiv gets called without a
bound (but valid) pipeline object, the state should reflect initial
state of a new pipeline object." This is also expected behaviour by
ES31-CTS.sepshaderobjs.PipelineApi conformance test.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Marta Lofstedt <marta.lofstedt at intel.com>
commit d9689be5c67e71518ef8687fd7fc4bc6df25b93f
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Tue Sep 1 13:53:43 2015 +0300
mesa: return initial value for PROGRAM_SEPARABLE when not linked
From OpenGL ES 3.1 spec (7.12):
"Most properties set within program objects are specified not to
take effect until the next call to LinkProgram or ProgramBinary.
Some properties further require a successful call to either of
these commands before taking effect. GetProgramiv returns the
properties currently in effect for program, which may differ from
the properties set within program since the most recent call to
LinkProgram or ProgramBinary, which have not yet taken effect. If
there has been no such call putting changes to pname into effect,
initial values are returned."
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Marta Lofstedt <marta.lofstedt at intel.com>
commit 8f1ae9abeba6b6eaf0c14f4c78c674e5afbc38aa
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Mon Sep 14 10:46:01 2015 +0300
mesa: enable query of PROGRAM_PIPELINE_BINDING for ES 3.1
Specified in OpenGL ES 3.1 spec, Table 23.32: Program Object State.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Marta Lofstedt <marta.lofstedt at intel.com>
commit ef8eebc6ad5d86e524426f0755c0f7d0b4c0cd3e
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Wed Aug 26 22:18:36 2015 +1000
nir: support indirect indexing samplers in struct arrays
As a bonus we get indirect support for arrays of arrays for free.
V5: couple of small clean-ups suggested by Jason.
V4: fix struct member location caclulation, use nir_ssa_def rather than
nir_src for the indirect as suggested by Jason
V3: Use nir_instr_rewrite_src() with empty src rather then clearing
the use_link list directly for the old indirects as suggested by Jason
V2: Fixed validation error in debug build
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 0ad44ce3735aa39391ab866c6a692eb76115b8c1
Author: Timothy <t_arceri at yahoo.com.au>
Date: Sat Sep 12 07:33:27 2015 +1000
glsl: add helper for calculating offsets for struct members
V2: update comments
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 12af915e27e4f10bc4c29f1cc8119b28ba27d874
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Tue Sep 1 15:52:10 2015 +1000
glsl: make variables private
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit dcd9cd03837545055ce2a315e7e8840cc3254d1a
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Sun Aug 30 12:50:34 2015 +1000
glsl: store uniform slot id in var location field
This will allow us to access the uniform later on without resorting to
building a name string and looking it up in UniformHash.
V3: remove line wrap change from this patch
V2: store slot number for all non-UBO uniforms to make code more
consitent, renamed explicit_binding to explicit_location and added
comment about what it does. Store the location at every shader stage.
Updated data.location comments in ir/nir.h.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 9788700caf61ff8beee5fd836f5efd98a931a976
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Wed Sep 2 11:29:11 2015 +1000
glsl: assign hidden uniforms their slot id earlier
This is required so that the next patch can safely assign the slot id
to the var.
The ids are now assigned in the order we want before allocating storage
so there is no need to sort the storage array and move things around.
V2: rename variable to make code easier to follow as suggested by Jason
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 874a0217fd8bba83b0bc2448f5156fdb82f77d7c
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Sun Aug 30 12:49:46 2015 +1000
glsl: order indices for samplers inside a struct array
This allows the correct offset to be easily calculated for indirect
indexing when a struct array contains multiple samplers, or any crazy
nesting.
The indices for the folling struct will now look like this:
Sampler index: 0 Name: s[0].tex
Sampler index: 1 Name: s[1].tex
Sampler index: 2 Name: s[0].si.tex
Sampler index: 3 Name: s[1].si.tex
Sampler index: 4 Name: s[0].si.tex2
Sampler index: 5 Name: s[1].si.tex2
Before this change it looked like this:
Sampler index: 0 Name: s[0].tex
Sampler index: 3 Name: s[1].tex
Sampler index: 1 Name: s[0].si.tex
Sampler index: 4 Name: s[1].si.tex
Sampler index: 2 Name: s[0].si.tex2
Sampler index: 5 Name: s[1].si.tex2
struct S_inner {
sampler2D tex;
sampler2D tex2;
};
struct S {
sampler2D tex;
S_inner si;
};
uniform S s[2];
V3: Update comments with suggestions from Jason
V2: rename struct array counter to have better name
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit b5df52b1128049bf688cace6e581a16d5f1ad5bb
Author: Dave Airlie <airlied at gmail.com>
Date: Thu Sep 17 06:55:31 2015 +1000
Revert "mesa/extensions: restrict GL_OES_EGL_image to GLES"
This reverts commit 48961fa3ba37999a6f8fd812458b735e39604a95.
glamor/Xwayland use this, the spec saying something when it
was written, and the fact that the comment says Mesa relies on it
hasn't changed.
I also don't have a copy of this patch in my mail archive, which
seems wierd, did it get posted to mesa-dev?
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit f5b26b47444bac7334a3351d1f08d83d4545869c
Author: Eric Anholt <eric at anholt.net>
Date: Wed Sep 16 15:51:00 2015 -0400
vc4: Only build in simulator mode if we find pkg-config for it.
This will let other developers build it x86 for build-testing purposes.
commit 37d0becfd91c0bb8202dd6994b6bba7e5d761990
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Sep 16 14:19:21 2015 -0400
freedreno/a3xx: use NUM_USER_CLIP_PLANES helper instead of magic number
Use the helper from the newly-updated generated header file.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 545a3cbb011e0e7722c2accb330c0994aea5cc38
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Sep 14 01:59:01 2015 -0400
freedreno/a3xx: fix blending of L8 format
Even though luminance formats don't have alpha, we still want the alpha
output to go to the blender. This fixes the luminance blending tests.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
commit ee6b95c82c3dbfad07e75ecdfd993e60fec2ac4f
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Sep 13 19:50:45 2015 -0400
freedreno/a3xx: add support for dual-source blending
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit cfa980f49356eb2d94178f8cc9d67d01b4e3d695
Author: Eric Anholt <eric at anholt.net>
Date: Wed Sep 9 13:23:55 2015 -0400
vc4: convert from tgsi semantic/index to varying-slot
(originally part of previous patch, split out to separate patch by Rob)
v2: squash in some fixes from Eric
v3: Another fix from Eric for point coords.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 8fd3e53f3dc40e4013348e63a0cc7a2787410899
Author: Eric Anholt <eric at anholt.net>
Date: Tue Aug 4 14:28:02 2015 -0700
gallium/ttn: Convert to using VARYING_SLOT_* / FRAG_RESULT_*.
This avoids exceeding the size of the .index bitfield since it got
truncated, and should make our NIR look more like the NIR that the rest of
the NIR developers are working on.
v2: split out vc4 updates, first patch uses varying_slot_to_tgsi_semantic()
helper, and second patch does the actual conversion.
v3: add frag_result_to_tgsi_semantic() helper and don't try to map
frag_results to semantic name/index as if they were varying_slot's
v4: use VERT_ATTRIB_ for VS inputs
v5: Fix vc4 build.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 7a275fcda8ffa3d69b7be6f356469f4af272a6ad
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Tue Sep 15 19:39:25 2015 -0400
nv50, nvc0: fix max texture buffer size to 128M elements
This is what the hardware supports, there never was any sort of 64K
limit.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
commit eb081681df248750727a8a76436760d617b4a6a9
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Tue Sep 15 19:32:10 2015 -0400
st/mesa: avoid integer overflows with buffers >= 512MB
This fixes failures with the newly-submitted max-size texture buffer
piglit test for GPUs exposing >= 128M max texels.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Glenn Kennard <glenn.kennard at gmail.com>
commit 1aff899a874abddc2d79e595242a233e874e4a96
Author: Brian Paul <brianp at vmware.com>
Date: Tue Sep 15 14:28:38 2015 -0600
mesa: move GL_APPLE_object_purgeable functions to new file
Move this code out of bufferobj.c since it's not strongly connected to
buffer objects.
Acked-by: Matt Turner <mattst88 at gmail.com>
commit 8faed71830302bbc640af9ef120bba276043a0a9
Author: Brian Paul <brianp at vmware.com>
Date: Tue Sep 15 14:04:58 2015 -0600
mesa: remove trailing whitespace in bufferobj.c
Trivial.
commit edc01c6704b39619ba3856ad801584611869a9d8
Author: Brian Paul <brianp at vmware.com>
Date: Tue Sep 15 14:03:04 2015 -0600
mesa: whitespace, line wrap fixes in varray.c
Trivial.
commit aecbc93f2d1ff9de4e03a2b216e86dcb9a4ce414
Author: Rob Clark <robclark at freedesktop.org>
Date: Tue Sep 15 18:55:48 2015 -0400
nir/print: print symbolic names from shader-enum
v2: split out moving of FILE *fp into state structure into it's own
(more complete patch) to reduce the noise in this one
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 840df72f9336994b2ca9dde981ec75fe10811a4e
Author: Rob Clark <robclark at freedesktop.org>
Date: Tue Sep 15 18:50:41 2015 -0400
nir/print: bit of state refactoring
Rename print_var_state to print_state, and stuff FILE ptr into the state
object. This avoids passing around an extra parameter everywhere.
v2: even more extensive conversion.. use state *everywhere* instead of
FILE ptr, and convert nir_print_instr() to use state as well
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit f2533f2f8cc059e6d239e414f410483a53970cd3
Author: Rob Clark <robclark at freedesktop.org>
Date: Fri Sep 11 12:48:05 2015 -0400
glsl: shader-enum to name debug fxns
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 5bb41d9094b3c9bdf0669fd55418981ed83347e3
Author: Rob Clark <robclark at freedesktop.org>
Date: Fri Sep 4 11:35:33 2015 -0400
freedreno: one screen to rule them all
Similar to fee0686c21c631d96d6042741267a3c218c23ffc, but in this case to
ensure that drm_gralloc and libGLES_mesa are sharing a single screen.
Bumps libdrm_freedreno version dependency, as it requires the new
fd_device_fd() API.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit b3958f9f8387b5967530ff77a08120074042c8e5
Author: Rob Clark <robclark at freedesktop.org>
Date: Mon Sep 14 11:54:05 2015 -0400
freedreno/ir3: use NIR to lower ffract instead of tgsi_lowering
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit d9efe40dc924b8bfd93c0572bd70c0585f823628
Author: Rob Clark <robclark at freedesktop.org>
Date: Mon Sep 14 11:13:19 2015 -0400
nir: add lowering for ffract
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 47e18a595731c054ac254e26066e6dea804f34e8
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Tue Sep 15 14:01:17 2015 -0700
i965/fs: The barrier send uses only 1 payload register
When preparing the barrier payload, the instructions should operate in
simd8 mode since we only use 1 payload register.
fs_inst::regs_read is also updated to indicate that it only reads one
register for SHADER_OPCODE_BARRIER.
These issues were flagged by:
commit cadd7dd384b33a779d46bd664f456bed4a21a5b7
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Jul 2 15:41:02 2015 -0700
i965/fs: Add a very basic validation pass
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit cb503c322754dd9dba016e703cf8b30177ed157b
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Sep 15 12:09:06 2015 -0700
nir/builder: Use a normal temporary array in nir_channel
C++ gets cranky if we take references of temporaries. This isn't a problem
yet in master because nir_builder is never used from C++. However, it will
be in the future so we should fix it now.
Reviewed-by: Rob Clark <robclark at freedesktop.org>
commit 18385bc3ac867bf7fb4070fe0f90bdf8e3e515a4
Author: Rob Clark <robclark at freedesktop.org>
Date: Mon Sep 14 15:15:06 2015 -0400
freedreno/a4xx: more texture formats
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit d85267c4bb5416dc3fbac7798b4bb68247340508
Author: Rob Clark <robclark at freedesktop.org>
Date: Tue Sep 15 17:25:47 2015 -0400
freedreno/a4xx: border-color support
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit f8222724f539b9e16affc0f4ddd95cfda27293a5
Author: Rob Clark <robclark at freedesktop.org>
Date: Tue Sep 15 17:25:25 2015 -0400
freedreno/a4xx: wire up texture clamp lowering
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 9124a49d54af5d7bd8230af4ba3eebfb167a7655
Author: Rob Clark <robclark at freedesktop.org>
Date: Tue Sep 15 09:23:21 2015 -0400
freedreno: helper for a3xx/a4xx border-colors
Both use the same layout for the buffer containing border-color values,
so rather than duplicating the logic in a4xx, split it out into a
helper.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 76977222af3dcf6c0915830c7b7af06505f8cd9a
Author: Rob Clark <robclark at freedesktop.org>
Date: Mon Sep 14 16:59:36 2015 -0400
freedreno: update generated headers
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 29348631fe7bf732a38856ea842cfc7aa2263468
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Sep 9 17:18:55 2015 -0700
nir/lower_vec_to_movs: Coalesce into destinations of fdot instructions
Now that we have a replicating fdot instruction, we can actually coalesce
into the destinations of vec4 instructions. We couldn't really do this
before because, if the destination had to end up in .z, we couldn't
reswizzle the instruction. With a replicated destination, the result ends
up in all channels so we can just set the writemask and we're done.
Shader-db results for vec4 programs on Haswell:
total instructions in shared programs: 1747753 -> 1746280 (-0.08%)
instructions in affected programs: 143274 -> 141801 (-1.03%)
helped: 667
HURT: 0
It turns out that dot-products matter...
Reviewed-by: Eduardo Lima Mitev <elima at igalia.com>
commit a88ce0c1c4c1f77209b71d5a6858f952642f385a
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Sep 10 11:08:15 2015 -0700
i965/vec4: Use the replicated fdot instruction in NIR
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Eduardo Lima Mitev <elima at igalia.com>
commit 47739c7df430664c3a998163a1e8a4a5e1901691
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Sep 10 10:51:46 2015 -0700
nir: Add a fdot instruction that replicates the result to a vec4
Fortunately, nir_constant_expr already auto-splats if "dst" never shows up
in the constant expression field so we don't need to do anything there.
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Eduardo Lima Mitev <elima at igalia.com>
commit 2458ea95c5676807a064f24ec720f12506975402
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Sep 9 14:40:06 2015 -0700
nir/lower_vec_to_movs: Coalesce movs on-the-fly when possible
The old pass blindly inserted a bunch of moves into the shader with no
concern for whether or not it was really needed. This adds code to try and
coalesce into the destination of the instruction providing the value.
Shader-db results for vec4 shaders on Haswell:
total instructions in shared programs: 1754420 -> 1747753 (-0.38%)
instructions in affected programs: 231230 -> 224563 (-2.88%)
helped: 1017
HURT: 2
This approach is heavily based on a different patch by Eduardo Lima Mitev
<elima at igalia.com>. Eduardo's patch did this in a separate pass as opposed
to integrating it into nir_lower_vec_to_movs.
Reviewed-by: Eduardo Lima Mitev <elima at igalia.com>
commit 2b2f1f16a04dfba4e02a7f331befb5bd94d4a1be
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Sep 9 14:47:28 2015 -0700
nir/lower_vec_to_movs: Get rid of start_idx and swizzle compacting
Previously, we did this thing with keeping track of a separate start_idx
which was different from the iteration variable. I think this was a relic
of the way that GLSL IR implements writemasks. In NIR, if a given bit in
the writemask is unset then that channel is just "unused", not missing. In
particular, a vec4 operation with a writemask of 0xd will use sources 0, 2,
and 3 and leave source 1 alone. We can simplify things a good deal (and
make them correct) by removing this "compacting" step.
Reviewed-by: Eduardo Lima Mitev <elima at igalia.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit c951bb83056724df02ba7e6fe2dfa720c0f45c1f
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Sep 9 13:55:39 2015 -0700
i965/vec4_nir: Use partial SSA form rather than full non-SSA
We made this switch in the FS backend some time ago and it seems to make a
number of things a bit easier. In particular, supporting SSA values takes
very little work in the backend and allows us to take advantage of the
majority of the SSA information even after we've gotten rid of Phi nodes.
Reviewed-by: Eduardo Lima Mitev <elima at igalia.com>
commit c3f8cde964f9850c86469a06d5eedf4e783cbf5c
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Sep 9 13:42:14 2015 -0700
nir/lower_vec_to_movs: Handle partially SSA shaders
v2 (Jason Ekstrand):
- Use nir_instr_rewrite_dest
- Pass the impl directly into lower_vec_to_movs_block
Reviewed-by: Eduardo Lima Mitev <elima at igalia.com>
commit b7eeced3c724bf5de05290551ced8621ce2c7c52
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Sep 9 12:58:58 2015 -0700
nir/lower_vec_to_movs: Pass the shader around directly
Previously, we were passing the shader around, we were just calling it
"mem_ctx". However, the nir_shader is (and must be for the purposes of
mark-and-sweep) the mem_ctx so we might as well pass it around explicitly.
Reviewed-by: Eduardo Lima Mitev <elima at igalia.com>
commit cadd7dd384b33a779d46bd664f456bed4a21a5b7
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Jul 2 15:41:02 2015 -0700
i965/fs: Add a very basic validation pass
Currently the validation pass only validates that regs_read and
regs_written are consistent with the sizes of VGRF's. We can add more as
we find it to be useful.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 0c6df7a1cb593666636aed660e90be0c6aca4591
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Sep 14 15:36:24 2015 -0700
i965/fs_surface_builder: Only apply predicate to components that exist
In certain conditions, we have to do bounds-checking in the shader for
image_load_store. The way this works for image loads is that we do a
predicated load and then emit a series of selects, one per component,
that gives us 0 or the loaded value depending on whether or not you're
in bounds. However, we were hard-coding 4 components which may not be
correct. Instead, we should be using size which is the number of
components read.
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 51824000541d8df9f870cbe0823a3835c9403bff
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Sep 14 14:18:13 2015 -0700
i965/fs: Only read output_components many components when writing an output
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit f55836f5671de5381a609c8d45601e2a92c803ce
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Sep 14 15:09:00 2015 -0700
i965/fs: Set output_components for lowered clip distance outputs
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 82007936491d5fb99cdc5ea18c076e8a896a4a1e
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Thu Aug 27 16:05:22 2015 -0700
mesa/teximage: restrict GL_ETC1_RGB8_OES support to GLES
According to the extensions table and our glext headers,
OES_compressed_ETC1_RGB8_texture is only supported in
GLES1 and GLES2. Since we may give users a GLES3 context
when a GLES2 context is requested, we also allow this
extension for GLES3 as well.
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
commit 48961fa3ba37999a6f8fd812458b735e39604a95
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Thu Sep 10 10:48:46 2015 -0700
mesa/extensions: restrict GL_OES_EGL_image to GLES
Driver vendors do this as well. The extension specification
lists GLES 1.1 or 2.0 as requirements.
Reviewed-by: Chad Versace <chad.versace at intel.com>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
commit fe796a18319d791f3ed3865761452474b1c0477f
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Thu Aug 27 16:05:22 2015 -0700
mesa/extensions: restrict luminance alpha formats to API_OPENGL_COMPAT
According the GL 3.1 spec, luminance alpha formats are deprecated.
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
commit edfb7ed1099cc8b6bebc2f1cb0b7b71bdcdbedeb
Author: Thomas Hellstrom <thellstrom at vmware.com>
Date: Mon Sep 14 23:40:07 2015 -0700
gallium/svga: Enable PIPE_FORMAT_L8_UNORM for vgpu10
It's extensively used by XA for a8- and planar yuv component surfaces.
This fixes broken XA yuv blits using vgpu10 contexts.
Signed-off-by: Thomas Hellstrom <thellstrom at vmware.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit a1ac742f709089eabad59b4da484799091203d91
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Sep 10 14:41:38 2015 +0100
egl/dri2: don't leak the fd on dri2_terminate
Currently the check was incorrect as it did not consider the (unlikely)
case of fd == 0. In order to fix this we should first correctly
initialize it to -1, as the swrast implementations leave it set to zero
(props to calloc()).
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Boyan Ding <boyan.j.ding at gmail.com>
commit bd5bcb5b8ca043a3908d7a70ab1193efc1db278d
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Sep 7 09:53:53 2015 +0100
egl/dri2/drm: compact existing device mgmt
Move the fcntl(dupfd_cloexec) to the else branch where it belongs.
Otherwise it's not immediately obvious that the code is hit, only when
an existing device is used.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Boyan Ding <boyan.j.ding at gmail.com>
commit e4f0d26c8c3c092a09fb65184ab080de4e38373e
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Jul 15 09:00:41 2015 -0700
egl/dri2: Close file descriptor on error.
v2: [Emil Velikov]
Rework the error path to a common goto, close only if we own the fd.
v3; [Emil Velikov]
Always close the fd (we either opened the device or dup'd) (Boyan, Ian)
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Boyan Ding <boyan.j.ding at gmail.com>
commit 4bf151e66279da00655cec02aadb52c9c6583213
Author: Ray Strode <rstrode at redhat.com>
Date: Fri Aug 28 14:50:21 2015 -0400
gbm: convert gbm bo format to fourcc format on dma-buf import
At the moment if a gbm buffer is imported and the gbm buffer
has an old-style GBM_BO_FORMAT format, the import will crash,
since it's passed directly to DRI functions that expect
a fourcc format (as provided by the newer GBM_FORMAT
definitions)
This commit addresses the problem in two ways:
1) it prevents invalid formats from leading to a crash by
returning EINVAL if the image couldn't be created
2) it translates GBM_BO_FORMAT formats into the comparable
GBM_FORMAT formats.
Reference: https://bugzilla.gnome.org/show_bug.cgi?id=753531
CC: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit a26e82b81dc3cebf13c8fd418d87977f2ab2dbb5
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Mon Sep 14 20:16:25 2015 +0200
docs: document INTEL_DEBUG 'optimizer' envvar
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit a548c75e31b4146d55133cb8c57a82117c196584
Author: Kristian Høgsberg Kristensen <krh at bitplanet.net>
Date: Fri Sep 4 17:09:40 2015 -0700
i965: Move perf_debug code to brw_codegen_*_prog()
We're trying to avoid a libdrm dependency in the core compiler, so let's
move the perf_debug code one level up from the brw_*_emit() helpers to
the brw_codegen_*_prog() helpers.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Signed-off-by: Kristian Høgsberg Kristensen <krh at bitplanet.net>
commit 84f2ed2cfdab45aa949aa6affe46cfe2944759c1
Author: Kristian Høgsberg Kristensen <krh at bitplanet.net>
Date: Fri Sep 4 16:55:03 2015 -0700
i965: Move brw_fs_precompile() to brw_wm.c
All other precompile functions live in the brw_<stage>.c files, make fs
follow the convention.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Signed-off-by: Kristian Høgsberg Kristensen <krh at bitplanet.net>
commit dc70c86b9b485cb5006a55cc2efd1f154dbfd469
Author: Kristian Høgsberg Kristensen <krh at bitplanet.net>
Date: Fri Sep 4 16:35:34 2015 -0700
i965: Move compute shader code around
This moves the compute shader code around in order to make the way the
code is split up more consistent. There should be no functional changes.
Typically we have a few files per stage:
brw_vs.c, brw_wm.c brw_gs.c:
code to drive code generation and implement precompiling and
cache search.
genX_<stage>_state.c
gen specific implementation of the state emission for the shader
stage.
The brw_*_emit() functions are all in the same files as the visitor
classes they use (with the exception of VS, which may use either vec4 or
fs).
To make compute follow this convention, we move the brw_cs_emit()
function into brw_fs.cpp. We can then rename brw_cs.cpp to brw_cs.c and
do this in C like the other similar files. Finally, move state setup
and atoms to gen7_cs_state.c.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Signed-off-by: Kristian Høgsberg Kristensen <krh at bitplanet.net>
commit 64e25167ed284619dacab42fdada0bb0fea71321
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Fri Jul 24 15:53:58 2015 -0700
meta: Abort meta pbo path if TexSubImage need signed unsigned conversion
See similar fix for Readpixels in mesa commit 0d20790. Jason suggested
we need that for TexSubImage as well.
Cc: <mesa-stable at lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 5877a594d54fdd2b3aa329f4d35b3491a7ee8a33
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Sep 10 23:58:17 2015 -0400
nvc0/ir: start offset at texBindBase for txq, like regular texturing
Curiously this has no actual effect. I think it's because the first 8
textures are bound in multiple slots for some reason. However seems
prudent to use these the same way as regular texturing, esp in the case
where there are more than 8 textures bound.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 64aee8fe9f28646ceb5b9b62db5766365d6da5c7
Author: Eric Anholt <eric at anholt.net>
Date: Mon Sep 14 11:21:07 2015 -0400
vc4: Fix build from recent NIR cleanups.
commit b8d2263c83d29f4626ac0fe0316978aa6262aefb
Author: Antia Puentes <apuentes at igalia.com>
Date: Mon Sep 14 09:50:59 2015 +0200
i965/vec4_nir: Load constants as integers
Loads constants using integer as their register type, like it is
done in FS backend.
No shader-db changes in HSW.
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91716
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 79f1a7ae28c37f77e08e550cd077959a2a1f8341
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Aug 5 15:57:33 2015 +0200
i965/vec4: Fix saturation errors when coalescing registers
If the register types do not match and the instruction
that contains the final destination is saturated, register
coalescing generated non-equivalent code.
This did not happen when using IR because types usually
matched, but it is visible in nir-vec4.
For example,
mov vgrf7:D vgrf2:D
mov.sat m4:F vgrf7:F
is coalesced to:
mov.sat m4:D vgrf2:D
The patch prevents coalescing in such scenario, unless the
instruction we want to coalesce into is a MOV (without type
conversion implied). In that case, the patch sets the register
types to the type of the final destination.
Shader-db results in HSW (only vec4 instructions shown):
total instructions in shared programs: 1754415 -> 1754416 (0.00%)
instructions in affected programs: 74 -> 75 (1.35%)
helped: 0
HURT: 1
GAINED: 0
LOST: 0
Only one extra instruction in one of the shaders, that comes from
eliminating a saturation error by preventing register coalesce.
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit d1bce52e13bbade24b9fb700ee83e98a8af248c8
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Mon Sep 14 08:50:51 2015 +0300
docs: cleanups + mark some work as done
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit f0b9d532626a88357da0bc862fa40c35aaecf449
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Sep 14 01:07:05 2015 -0400
docs: only astc ldr required for ES3.2, not hdr
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 67d2d3ba433a43bbf03b80c1d7e140e1fc9de2f6
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Sep 10 21:44:45 2015 -0400
st/mesa: emit TXQS, support ARB_shader_texture_image_samples
The image component of the ext is a no-op since there is no image support
in gallium (yet).
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit ec3fe42b3a7c8d8a33d66aa7e3a43330b9c3c926
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Sep 10 22:33:34 2015 -0400
r600g: add support for TXQS tgsi opcode
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Glenn Kennard <glenn.kennard at gmail.com>
commit 4294db90b1804dd213b0b4b3ff4eb46a5c390c76
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Sep 10 22:07:27 2015 -0400
nv50/ir: add support for TXQS tgsi opcode
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit f46a53ffa50f186df347a181ca336fc3e9f96eaf
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Sep 11 17:29:49 2015 -0400
gallium: add PIPE_CAP_TGSI_TXQS to let st know if TXQS is supported
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Glenn Kennard <glenn.kennard at gmail.com>
commit d173c5e77d239618e9609788e3d23ac9180a58a5
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Sep 10 21:37:23 2015 -0400
tgsi: add a TXQS opcode to retrieve the number of texture samples
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
commit c4cf824658da283cf350fd6833d50dff9de4a1ad
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Mon Aug 17 16:32:42 2015 -0700
glsl/cs: Initialize gl_LocalInvocationIndex in main()
We initialize gl_LocalInvocationIndex based on the extension spec
formula:
gl_LocalInvocationIndex =
gl_LocalInvocationID.z * gl_WorkGroupSize.x * gl_WorkGroupSize.y +
gl_LocalInvocationID.y * gl_WorkGroupSize.x +
gl_LocalInvocationID.x;
https://www.opengl.org/registry/specs/ARB/compute_shader.txt
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 6823e12d5aa4646fc8ef0e32455104ba47f80a38
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Mon Aug 17 15:49:44 2015 -0700
glsl/cs: Exclude gl_LocalInvocationIndex from builtin variable stripping
We lower gl_LocalInvocationIndex based on the extension spec formula:
gl_LocalInvocationIndex =
gl_LocalInvocationID.z * gl_WorkGroupSize.x * gl_WorkGroupSize.y +
gl_LocalInvocationID.y * gl_WorkGroupSize.x +
gl_LocalInvocationID.x;
https://www.opengl.org/registry/specs/ARB/compute_shader.txt
We need to set this variable in main(), even if gl_LocalInvocationIndex
is not referenced by the shader. (It may be used by a linked shader.)
Therefore, we can't eliminate it as a dead variable.
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 2b6cc0395be4c3eb1c60c0d7a413e368b5ae3dbf
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Mon Aug 17 14:35:44 2015 -0700
glsl/cs: Initialize gl_GlobalInvocationID in main()
We initialize gl_GlobalInvocationID based on the extension spec
formula:
gl_GlobalInvocationID =
gl_WorkGroupID * gl_WorkGroupSize + gl_LocalInvocationID
https://www.opengl.org/registry/specs/ARB/compute_shader.txt
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Cc: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit c4d049f64603d934aed2a75cac86d4a3d4adadb7
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Mon Aug 17 12:22:34 2015 -0700
glsl: Move link_get_main_function_signature to a common location
Also rename to _mesa_get_main_function_signature.
We will call it near the end of compilation to insert some code into
main for initializing some compute shader global variables.
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Eduardo Lima Mitev <elima at igalia.com>
commit 34e187ec38cee78fbc0e1d1a09a99160fbdf7a9f
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Mon Aug 17 12:30:25 2015 -0700
glsl/cs: Don't strip gl_GlobalInvocationID and dependencies
We lower gl_GlobalInvocationID based on the extension spec formula:
gl_GlobalInvocationID =
gl_WorkGroupID * gl_WorkGroupSize + gl_LocalInvocationID
https://www.opengl.org/registry/specs/ARB/compute_shader.txt
We need to set this variable in main(), even if gl_GlobalInvocationID
is not referenced by the shader. (It may be used by a linked shader.)
Therefore, we can't eliminate these as dead variables.
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit c5743a5d7fa62a339222ceb96d568a525d77fe0c
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Fri Mar 13 11:39:53 2015 -0700
i965/nir: Support gl_WorkGroupID variable
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 4e454cb7c6dd189b433acd98c9595e464e0432b4
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Fri Oct 10 08:28:24 2014 -0700
i965/cs: Initialize gl_WorkGroupID variable from payload
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 4f178f0d8b7b4c410a1ac5532a26dfa51d3a72f1
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Fri Mar 13 11:37:03 2015 -0700
nir: Add gl_WorkGroupID system variable
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit f5bb5a1bf180b80a4fee12d60e97ac4c6f80876c
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Fri Oct 10 08:28:24 2014 -0700
glsl/cs: Add gl_WorkGroupID variable
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 49f999b9cb6ecb32cb27d10b47d234a176ae4c77
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Fri Mar 13 11:34:48 2015 -0700
i965/nir: Support gl_LocalInvocationID variable
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 43624361df1d5647665db793a38e229d89dfb851
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Fri Nov 21 19:14:41 2014 -0800
i965/cs: Initialize gl_LocalInvocationID from payload
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit b94b57f7c540e55d25e1cfd7392fc030022a4933
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Fri Oct 10 08:33:23 2014 -0700
i965/cs: Initialize gl_LocalInvocationID in push constant data
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit c7161a3c3559f0450a90bb1228c74e8fdc9c939b
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Fri Nov 21 18:47:49 2014 -0800
i965/cs: Reserve local invocation id in payload regs
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 62e011d593008e61ddcba3c32b5710505f4974e6
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Fri Mar 13 11:32:43 2015 -0700
nir: Add gl_LocalInvocationID variable
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit bf8d6e501c58b3d6c06056b663ec99b9c7eeb9cf
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Fri Oct 10 08:28:24 2014 -0700
glsl/cs: Add gl_LocalInvocationID variable
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 08ceb5e076328bf6ccceed3a8e5de205dcaf63b0
Author: Krzesimir Nowak <qdlacz at gmail.com>
Date: Sat Sep 12 08:17:00 2015 -0600
softpipe: Change faces type to uint
This is to avoid needless float<->int conversions, since all
face-related computations are made on integers. Spotted by Emil
Velikov.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 59519c2283e91ce4b8c2028673d6d8dc4ee5138f
Author: Rob Clark <robclark at freedesktop.org>
Date: Sun Sep 13 11:22:51 2015 -0400
freedreno/ir3: fix compile warn after 1807a08e
New enum to add to switch so compiler doesn't complain.
commit 1807a08e4f35b014f2a80d1e88dd74a9f096d7a5
Author: Ilia Mirkin <imirkin at alum.mit.edu>
AuthorDate: Thu Aug 27 23:05:03 2015 -0400
Commit: Ilia Mirkin <imirkin at alum.mit.edu>
CommitDate: Thu Sep 10 17:38:33 2015 -0400
nir: add nir_texop_texture_samples and convert from glsl
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit bf45a7d28e7934463ee465b613a9101259520e13
Author: Rob Clark <robclark at freedesktop.org>
Date: Sun Sep 13 11:21:28 2015 -0400
freedreno/ir3: fix compile break after a4aa25be
Following commit dropped the unused memctx arg:
commit a4aa25be1e0a27b1a6a6b0bcf576beb9dfe1ea7a
Author: Jason Ekstrand <jason.ekstrand at intel.com>
AuthorDate: Wed Sep 9 13:24:35 2015 -0700
Commit: Jason Ekstrand <jason.ekstrand at intel.com>
CommitDate: Fri Sep 11 09:21:20 2015 -0700
nir: Remove the mem_ctx parameter from ssa_def_rewrite_uses
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit b88aeff4f51e8a505a8c5e5905d80ae3b75ed3ef
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Sep 10 16:06:05 2015 -0400
nir: add nir_channel() to get at single components of vec's
Rather than make yet another copy of channel(), let's move it into nir.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 86358e949eaa13c075338901024d0e1009fa7e99
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Sep 9 18:28:55 2015 -0400
tgsi/scan: add support to figure out max nesting depth
Sometimes a useful thing for compilers (or, for example, tgsi_to_nir) to
know. And pretty trivial for scan to figure this out for us.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit d6fbcf6ee28c273b37bf293aea5faf77253029a3
Author: Kai Wasserbäch <kai at dev.carbon-project.org>
Date: Sat Sep 12 10:39:50 2015 +0200
r600: Fix llvm build since const buffer changes
In commit f9caabe8f1bff86d19b53d9ecba5c72b238d9e23:
One place in r600_llvm.c was forgotten when replacing
R600_UCP_CONST_BUFFER with R600_BUFFER_INFO_CONST_BUFFER.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91985
Signed-off-by: Kai Wasserbäch <kai at dev.carbon-project.org>
Signed-off-by: Dave Airlie <airlied at gmail.com>
commit 1037e0a84f61f4b1815093bcfd548d4b58ca106f
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Sep 10 16:19:42 2015 -0700
i965/vec4: Don't reswizzle hardware registers
Cc: "11.0 10.6" <mesa-stable at lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91719
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit dd7290cf59206c49f1a322d53baa9957b13d2949
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Sep 10 16:19:22 2015 -0700
i965/emit: Add assertions for accumulator restrictions
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 7852a44e3c460d26ebcd2a9ee66309cfa8c68001
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Sep 12 13:50:33 2015 +0100
docs: add news item and link release notes for 11.0.0
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit c34ed462175062787ab99346ff36f79995f32ac0
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Sep 12 13:32:56 2015 +0100
docs: add sha256 checksums for 11.0.0
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit c4bae5792bb5515da42e23f166f5ba5d68f79615)
commit 09223bfa9b81cf501ae9c194d7305a3c8bc5d402
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Sep 12 10:33:49 2015 +0100
docs: Update 11.0.0 release notes
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit 4f1e500150be2e82a2d7eb954f7198cc0c5cbec1)
commit ce34048b575240347f8426c541971d00c810d3c9
Author: Glenn Kennard <glenn.kennard at gmail.com>
Date: Fri Sep 11 12:42:23 2015 +0200
r600: Enable fp64 on chips with native support
Cypress/Cayman/Aruba, earlier r6xx/r7xx chips only support a subset
of the needed fp64 ops, and don't do GL4 anyway.
Signed-off-by: Glenn Kennard <glenn.kennard at gmail.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit d2ca9afd5da2a0228bbf7a9af5a2bb94424441c9
Author: Glenn Kennard <glenn.kennard at gmail.com>
Date: Fri Sep 11 12:42:22 2015 +0200
r600g: Support I2D/U2D/D2I/D2U
Only for Cypress/Cayman/Aruba, older chips have only partial fp64 support.
Uses float intermediate values so only accurate for int24 range, which
matches what the blob does.
Signed-off-by: Glenn Kennard <glenn.kennard at gmail.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit f9caabe8f1bff86d19b53d9ecba5c72b238d9e23
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Sep 11 04:43:53 2015 +0100
r600g: lower number of driver const buffers
I'm going to want a driver constant buffer for tess to coordinate
LDS storage, so before I go tackling that I decided to merge the
clip/samplepos and texture info buffers into one. So I can steal
the spare one.
This creates a single constant buffer between the two, with
clip/samplepos taking up a reserved 128 bytes at the start.
Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Reviewed-by: Glenn Kennard <glenn.kennard at gmail.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 0337a9b2af6cb72eb2ca3ee2e17d5e06ea7aeacd
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Sep 11 03:11:43 2015 +0100
r600: define some values for the fetch constant offsets.
This just puts these in one place and #defines them.
Reviewed-by: Glenn Kennard <glenn.kennard at gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 2e7e3fe55f1ff9714e4d83cc9db7cbd36e149da5
Author: Thomas Helland <thomashelland90 at gmail.com>
Date: Wed Aug 12 15:07:57 2015 +0200
docs: Update with GLES3.2 entries and status
V2: -Change to "not started" for most entries
-Add status for multisample_2d_array
-Change shader_multisample_interpolation to "not_stared"
V3 (idr): Move the GLES 3.2 section after the "Additional functions"
section from GLES 3.1. Note that GL_KHR_texture_compression_astc_hdr is
done for i965 on gen9+ hardware. Note that GL_OES_shader_io_blocks is
based on some features from GLSL 1.50.
Signed-off-by: Thomas Helland <thomashelland90 at gmail.com>
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com> [v2]
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 2135aba8d99d5b0b5f73d97d4aac6a25d69de57c
Author: Krzesimir Nowak <krzesimir at kinvolk.io>
Date: Fri Sep 11 20:07:42 2015 +0200
softpipe: Constify variables
This commit makes a lot of variables constant - this is basically done
by moving the computation to variable definition. Some of them are
moved into lower scopes (like in img_filter_2d_ewa).
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit 231687c19b3c6ab4f5bead7469b7b27fdbda6d43
Author: Krzesimir Nowak <krzesimir at kinvolk.io>
Date: Fri Sep 11 20:07:41 2015 +0200
softpipe: Constify sp_tgsi_sampler
Add a small inline function doing the casting - this is to make sure
we don't do a cast from some completely unrelated type. This commit
does not make tgsi_sampler parameters const in vfuncs themselves for
now - probably llvmpipe would need looking at before making such a
change.
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit ac23116de56e163a3815626277f9c3691bb56831
Author: Krzesimir Nowak <krzesimir at kinvolk.io>
Date: Fri Sep 11 20:07:40 2015 +0200
softpipe: Constify sampler and view parameters in mip filters
Those functions actually could always take them as constants.
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit ea764baa61bec5b4ae15cf0d5928e3643061807d
Author: Krzesimir Nowak <krzesimir at kinvolk.io>
Date: Fri Sep 11 20:07:39 2015 +0200
softpipe: Constify sampler and view parameters in img filters
Those functions actually could always take them as constants.
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit ba72e6cfb8248ae0d8b3cf5ebf9add7c49f45743
Author: Krzesimir Nowak <krzesimir at kinvolk.io>
Date: Fri Sep 11 20:07:38 2015 +0200
tgsi, softpipe: Constify tgsi_sampler in query_lod vfunc
A followup from previous commit - since all functions called by
query_lod take pointers to const sp_sampler_view and const sp_sampler,
which are taken from tgsi_sampler subclass, we can the tgsi_sampler as
const itself now.
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit ea0fecd1a3f46439c602e04870b34e6f27ad5b2e
Author: Krzesimir Nowak <krzesimir at kinvolk.io>
Date: Fri Sep 11 20:07:37 2015 +0200
softpipe: Constify some sampler and view parameters
This is to prepare for making tgsi_sampler parameter in query_lod a
const too. These functions do not modify anything in either sampler or
view anymore.
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit 4ca2896e8ea1908ea5a0d5bffe8a1b42145a6f72
Author: Krzesimir Nowak <krzesimir at kinvolk.io>
Date: Fri Sep 11 20:07:36 2015 +0200
softpipe: Move the faces array from view to filter_args
With that, sp_sampler_view instances are not abused anymore as a local
storage, so we can later make them constant.
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit ca11c3c0a4726d4f51436d714ef81ef9a01348ea
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Sep 9 16:03:10 2015 -0700
nir/from_ssa: Use instr_rewrite_dest
Reviewed-by: Eduardo Lima Mitev <elima at igalia.com>
commit cee29220e312f7c76a07343e501fa6a1c5f3d1aa
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Sep 9 15:58:25 2015 -0700
nir: Add a function for rewriting instruction destinations
Reviewed-by: Eduardo Lima Mitev <elima at igalia.com>
commit 106a3b2cc33c53ab16ffedc51248b04dd995dc17
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Sep 9 15:58:08 2015 -0700
nir: Only unlink sources that are actually valid
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
commit a4aa25be1e0a27b1a6a6b0bcf576beb9dfe1ea7a
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Sep 9 13:24:35 2015 -0700
nir: Remove the mem_ctx parameter from ssa_def_rewrite_uses
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
commit 8c8fc5f8336c8c79e5890265ae6c03271aa94075
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Sep 9 13:18:29 2015 -0700
nir: Fix a bunch of ralloc parenting errors
As of a10d4937, we would really like things associated with an instruction
to be allocated out of that instruction and not out of the shader. In
particular, you should be passing the instruction that will ultimately be
holding the source into nir_src_copy rather than an arbitrary memory
context.
We also change the prototypes of nir_dest_copy and nir_alu_src/dest_copy to
explicitly take an instruction so we catch this earlier in the future.
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
commit 794355e77167291a3acc8d42249c760c24f54f38
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Sep 10 13:56:08 2015 -0700
nir/lower_outputs_to_temporaries: Reparent the output name
We copy the output, make the old output the temporary, and give the
temporary a new name. The copy keeps the pointer to the old name. This
works just fine up until the point where we lower things to SSA and delete
the old variable and, with it, the name. Instead, we should re-parent to
the copy.
Reviewed-by: Eduardo Lima Mitev <elima at igalia.com>
commit d4e29af2344c06490913efc35430f93a966061bb
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Fri Sep 11 12:21:13 2015 +0200
i965/vec4: check writemask when bailing out at register coalesce
opt_register_coalesce stopped to check previous instructions to
coalesce with if somebody else was writing on the same
destination. This can be optimized to check if somebody else was
writing to the same channels of the same destination using the
writemask.
Shader DB results (taking into account only vec4):
total instructions in shared programs: 1781593 -> 1734957 (-2.62%)
instructions in affected programs: 1238390 -> 1191754 (-3.77%)
helped: 12782
HURT: 0
GAINED: 0
LOST: 0
v2: removed some parenthesis, fixed indentation, as suggested by
Matt Turner
v3: added brackets, for consistency, as suggested by Eduardo Lima
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 2c52c794d727e535c1baca671a7c1e5b38dffb00
Author: Brian Paul <brianp at vmware.com>
Date: Thu Sep 10 12:26:18 2015 -0600
tgsi,softpipe: capitalize the tgsi_sampler_control enum values
We use capitalized enum values everywhere else.
This improves understanding a bit too.
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit b811085b797c79396e59372085293a82fabcf069
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Aug 18 02:07:47 2015 -0700
nir: Store some geometry shader data in nir_shader.
This makes it possible for NIR shaders to know the number of output
vertices and the number of invocations. Drivers could also access
these directly without going through gl_program.
We should probably add InputType and OutputType here too, but currently
those are stored as GL_* enums, and I wanted to avoid using those in
NIR, as I suspect Vulkan/SPIR-V will use different enums. (We should
probably make our own.)
We could add VerticesIn, but it's easily computable from the input
topology, so I'm not sure whether it's worth it. It's also currently
not stored in gl_shader (only gl_shader_program), which would require
changes to the glsl_to_nir interface or require us to store it there.
This is a bit of duplication of data...ideally, we would factor these
substructs out of gl_program, gl_shader_program, and nir_shader, creating
a gl_geometry_info class...but it would need to go in a new place (in
src/glsl?) that isn't mtypes.h nor nir.h.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit cb2b118e4017b1cd90dcc02e688d859b2709465e
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue May 12 01:53:24 2015 -0700
nir/builder: Add nir_load_var() and nir_store_var() helpers.
These provide a convenient way to do simple variable loads and stores.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 4654439fdd766f79a78fe0d812fd916f5815e7e6
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Nov 11 23:16:13 2014 -0800
glsl: Use hash tables for opt_constant_propagation() kill sets.
Cuts compile/link time of the fragment shader in #91857 by 19%
(16.28 -> 13.05).
I didn't bother with the acp sets because they're smaller, but it
might be worth doing as well.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91857
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
Tested-by: Tapani Pälli <tapani.palli at intel.com>
commit e20f30eb5181cddf8286d2247cfaf7e0fac7e417
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Sep 5 00:51:33 2015 -0700
i965: Use hash tables for brw_fs_vector_splitting().
Cuts compile/link time of the fragment shader in #91857 by 25%
(21.64 -> 16.28).
v2: Drop unnecessary _mesa_hash_table_destroy call, and use
refs.ht->entries == 0 rather than ad-hoc checking (suggested by
Timothy Arceri).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91857
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
Tested-by: Tapani Pälli <tapani.palli at intel.com>
commit 2fc0ce293ac58237f02cc5dd2eee4e35abea06b5
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Sep 5 00:22:57 2015 -0700
glsl: Use hash tables in opt_constant_variable().
Cuts compile/link time of the fragment shader in bug #91857 by 31%
(31.79 -> 21.64). It has over 8,000 variables so linked lists are
terrible.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91857
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
Tested-by: Tapani Pälli <tapani.palli at intel.com>
commit 4603723722127e707a5c1fa28736ee932f326846
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Sep 9 10:27:04 2015 -0700
meta: Use result of texture coordinate clamping operation
Previously the result of the complicated clamp() expression just dropped
on the floor: clamp does not modify any of its parameters. Looking at
the surrounding code, I believe this is supposed to modify the value of
tex_coord.
This change (along with a change to avoid the use of
brw_blorp_framebuffer) does not affect any existing piglit tests. I'm
not sure what this clamp is trying to accomplish, so I'm not sure how to
write a test to exercise this path.
I also noticed another bug in this code. There is no way the array
texture case could possibly work. This will generate code for the
TEXEL_FETCH macro like:
#define TEXEL_FETCH(coord) texelFetch(texSampler, ivec3(coord), sample_map[int(2 * fract(coord.x))]);
Since the coord parameter of this macro is a vec2 at all invocations, no
expansion of this macro will even compile.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Cc: Topi Pohjolainen <topi.pohjolainen at intel.com>
Cc: Jordan Justen <jordan.l.justen at intel.com>
commit 767c33e88138afa64443417860b264a494eba33d
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Sep 2 16:06:58 2015 -0700
meta: Always bind the texture
We may have been called from glGenerateTextureMipmap with CurrentUnit
still set to 0, so we don't know when we can skip binding the texture.
Assume that _mesa_BindTexture will be fast if we're rebinding the same
texture.
v2: Remove currentTexUnitSave because it is now unused. Suggested by
both Neil and Anuj.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91847
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Neil Roberts <neil at linux.intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 86c0a2d57413f04fabd40fd09d87b0ff9d1cb092
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Sep 2 15:44:04 2015 -0700
i915, i965: Silence unused parameter warnings in intel_batchbuffer_advance
These only occurred in release builds, but they occurred in every file
that included intel_batchbuffer.h. Lots of spam. :(
intel_batchbuffer.h: In function 'intel_batchbuffer_advance':
intel_batchbuffer.h:153:47: warning: unused parameter 'brw' [-Wunused-parameter]
intel_batchbuffer_advance(struct brw_context *brw)
^
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 307d5e58496a73bace8c89dbdbba91be171b7c95
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Sep 2 15:11:34 2015 -0700
i915: Silence unused parameter warning in intel_miptree_create_layout
The for_bo parameter of intel_miptree_create_layout appears to be unused
since 27eedca when Eric removed some Gen5 code (after the i915 and i965
drivers parted ways).
intel_mipmap_tree.c: In function 'old_intel_miptree_create_layout':
intel_mipmap_tree.c:77:35: warning: unused parameter 'for_bo' [-Wunused-parameter]
bool for_bo)
^
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 5c8aa21309cb8cabd61b73b6706b295d6237d53d
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Sep 2 15:04:59 2015 -0700
i915, i965: Silence unused parameter warnings in intel_miptree_unmap_gtt
intel_mipmap_tree.c: In function 'intel_miptree_unmap_gtt':
intel_mipmap_tree.c:777:34: warning: unused parameter 'map' [-Wunused-parameter]
struct intel_miptree_map *map,
^
intel_mipmap_tree.c:778:17: warning: unused parameter 'level' [-Wunused-parameter]
unsigned int level,
^
intel_mipmap_tree.c:779:17: warning: unused parameter 'slice' [-Wunused-parameter]
unsigned int slice)
^
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 04122312662b60d8a2d472ff6492960b4d923587
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Sep 2 15:01:18 2015 -0700
i915: Silence unused parameter warnings
intel_mipmap_tree.c: In function 'old_intel_miptree_unmap_raw':
intel_mipmap_tree.c:726:51: warning: unused parameter 'intel' [-Wunused-parameter]
intel_miptree_unmap_raw(struct intel_context *intel,
^
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 20915dd2e0539ec5eba958230bbda2215cb19c2c
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Sep 2 14:56:18 2015 -0700
i915: Remove prototype for nonexistent brw_miptree_layout
Hasn't existed in the i915 source since the i915 and i965 drivers parted
ways.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 31f0967fb50101437d2568e9ab9640ffbcbf7ef9
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Sep 2 14:43:18 2015 -0700
i965: Make intel_miptree_map_raw static
This hasn't been used outside intel_mipmap_tree.c since d5d4ba9 started
using meta instead of the blitter for PBO TexSubImage. While we're
here, remove the unused brw parameter from the function formerly known
as intel_miptree_unmap_raw.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 68b44dd5b23c0fca8c09357ffb5d6826f8b4b344
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Sep 2 14:33:59 2015 -0700
i915, i965: Silence unused parameter warnings in intel_mipmap_tree.h
These only occurred in release builds, but they occurred in every file
that included intel_mipmap_tree.h. Lots of spam. :(
intel_mipmap_tree.h: In function 'intel_miptree_check_level_layer':
intel_mipmap_tree.h:595:59: warning: unused parameter 'mt' [-Wunused-parameter]
intel_miptree_check_level_layer(struct intel_mipmap_tree *mt,
^
intel_mipmap_tree.h:596:42: warning: unused parameter 'level' [-Wunused-parameter]
uint32_t level,
^
intel_mipmap_tree.h:597:42: warning: unused parameter 'layer' [-Wunused-parameter]
uint32_t layer)
^
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 094877f9d23169b1d209fb0c97f9b6d4679842d9
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Sep 2 14:02:18 2015 -0700
i965: Silence unused parameter warnings in intel_mipmap_tree.c
The target parameter of compute_msaa_layout appears to be unused since
83b83fb when support for CMS textures was added for Gen7.
The brw parameter of intel_get_non_msrt_mcs_alignment appears to be
unused since e92fbdc when the GEN check (along with the "can we fast
clear" decision) was moved to a different function.
intel_mipmap_tree.c: In function 'compute_msaa_layout':
intel_mipmap_tree.c:62:73: warning: unused parameter 'target' [-Wunused-parameter]
compute_msaa_layout(struct brw_context *brw, mesa_format format, GLenum target,
^
intel_mipmap_tree.c: In function 'intel_get_non_msrt_mcs_alignment':
intel_mipmap_tree.c:143:54: warning: unused parameter 'brw' [-Wunused-parameter]
intel_get_non_msrt_mcs_alignment(struct brw_context *brw,
^
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Cc: Ben Widawsky <benjamin.widawsky at intel.com>
commit 38e412d548273382c1e56192d6d0a0fd8d08b3c0
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Sep 9 10:33:52 2015 -0700
i965: Silence unused parameter warnings in intel_fbo.c
intel_fbo.c: In function 'intel_alloc_window_storage':
intel_fbo.c:415:48: warning: unused parameter 'ctx' [-Wunused-parameter]
intel_alloc_window_storage(struct gl_context * ctx, struct gl_renderbuffer *rb,
^
intel_fbo.c: In function 'intel_nop_alloc_storage':
intel_fbo.c:428:74: warning: unused parameter 'rb' [-Wunused-parameter]
intel_nop_alloc_storage(struct gl_context * ctx, struct gl_renderbuffer *rb,
^
intel_fbo.c:429:32: warning: unused parameter 'internalFormat' [-Wunused-parameter]
GLenum internalFormat, GLuint width, GLuint height)
^
intel_fbo.c:429:55: warning: unused parameter 'width' [-Wunused-parameter]
GLenum internalFormat, GLuint width, GLuint height)
^
intel_fbo.c:429:69: warning: unused parameter 'height' [-Wunused-parameter]
GLenum internalFormat, GLuint width, GLuint height)
^
intel_fbo.c: In function 'intel_blit_framebuffer_with_blitter':
intel_fbo.c:790:61: warning: unused parameter 'filter' [-Wunused-parameter]
GLbitfield mask, GLenum filter)
^
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit b46cbc36072ae050f648f9baa974c4180d9bb8a3
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Sep 4 01:24:39 2015 +0100
st/mesa: set the vbuffer to NULL if we are skipping it
If we skip a vbuffer we need to make sure we NULL out
the contents, otherwise when it gets passed to the driver
it will get confused.
This was hit by:
GL41-CTS.gpu_shader_fp64.varyings
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 34cff76fc2da1ce9abad6e2b1856fec6a950d19c
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Wed Nov 5 00:47:41 2014 -0800
i965/cs: Enable barrier in MEDIA_INTERFACE_DESCRIPTOR
Enable barrier in MEDIA_INTERFACE_DESCRIPTOR if the program uses the
barrier() GLSL function.
On Ivy Bridge and Haswell, this allows the piglit test
tests/spec/arb_compute_shader/execution/simple-barrier-atomics.shader_test
to pass. On gen8, this enables a similar test with a local group size
of 896 to pass.
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit b01d0473917ba15de3aa146006bfef5836d10e93
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Wed Mar 11 22:54:20 2015 -0700
i965/cs: Emit texture surfaces to enable CS sampling
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 1180b794871e53a94811f7279f42504bca4d9434
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Fri Oct 3 19:07:45 2014 -0700
i965: Set up sampler state for compute shaders
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit af48612b88cb51cd3b957e70490462c0c404f92c
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Fri Oct 3 19:05:32 2014 -0700
i965/fs: Set first_non_payload_grf in assign_curb_setup
first_non_payload_grf may be updated in assign_urb_setup for FS or
assign_vs_urb_setup for VS.
We need to set this in assign_curb_setup for compute shaders since cs
does not have an assign_cs_urb_setup like assign_urb_setup (fs) or
assign_vs_urb_setup (vs).
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 75d04e561b58d1f00e387c3402e2c299eb3dee87
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Fri Oct 3 19:01:24 2014 -0700
i965: Support compute shaders in is_scalar_shader_stage()
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 2b9c35945a74c6e2b559bb52eb612231465e86a1
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Fri Oct 3 18:58:39 2014 -0700
i965: Support CS in update_stage_texture_surfaces
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit bfc5ace5bda6510d4dd3893a3b8c677a1c85e23e
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Tue Aug 11 20:38:48 2015 -0400
i965: enable ARB_shader_texture_image_samples
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 55ebaa6d003b69c0a159a00d82a1e96f685062d6
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Aug 27 23:34:47 2015 -0400
i965: add handling for imageSamples
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 56238305e5474d749881006622c5ee65dee4fb40
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Aug 27 23:27:50 2015 -0400
nir: convert glsl imageSamples into a new intrinsic
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 37c5c862810ddf8f3973ec738aa0a2a33af3bcb2
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Aug 27 23:22:18 2015 -0400
glsl: add support for the imageSamples function
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 0b91bcea98c0fe201bba89abe1ca3aee4d04c56c
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Tue Aug 11 20:37:32 2015 -0400
i965: add support for textureSamples function
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
[v2: kayden-supplied code in fs_nir replacing need for logical opcode]
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 0c7fbcb84403ec318c77a51c98addd653529ae48
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Aug 27 23:06:57 2015 -0400
glsl: add support for the textureSamples function
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit fb18ee9ba6950e61f6d4ac28a0b5aea85c457d79
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Aug 27 23:06:29 2015 -0400
glsl: add ARB_shader_texture_image_samples infrastructure
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 1807a08e4f35b014f2a80d1e88dd74a9f096d7a5
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Aug 27 23:05:03 2015 -0400
nir: add nir_texop_texture_samples and convert from glsl
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit f9052914e979228d28502a7f7953f98ff4731f99
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Aug 27 23:03:46 2015 -0400
glsl: add ir_texture_samples texture opcode
Will be used for textureSamples()
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 6efae687b7ef46eb1f738f1bc2acbde1805e364b
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Aug 27 23:01:29 2015 -0400
mesa: add infra for ARB_shader_texture_image_samples
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 284dcad20a9a55278c1d3dd98f53e45650b22896
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Aug 19 16:36:35 2015 -0700
i965: Fix typos in license
grep -lr 'sub license' | while read f; do \
sed --in-place -e 's/sub license/sublicense/' $f ;\
done
grep -lr 'NON-INFRINGEMENT' | while read f; do \
sed --in-place -e 's/NON-INFRINGEMENT/NONINFRINGEMENT/' $f ;\
done
As noted by Matt, both of these changes match the MIT license text found
at http://opensource.org/licenses/MIT.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit aa1a5c0c9e0de71ecd15e7190c121d6dd98471a6
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Aug 19 19:24:45 2015 -0700
i965: Remove horizontal bars from file header comments
Why was that ever a thing?
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit a9b143a648ff77ac76ff6f4580559f1a061e37f9
Author: Brian Paul <brianp at vmware.com>
Date: Thu Sep 10 08:55:01 2015 -0600
svga: clean up the compile_vs/gs/fs() functions
Sipmlify structure and remove gotos.
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
commit 289804515f7de20cb41a5e1b4c20864f0dab8d51
Author: Brian Paul <brianp at vmware.com>
Date: Thu Sep 10 08:47:16 2015 -0600
svga: fix shader variant memory leak
Fixes a small leak in a seldom-hit corner case for VS/FS compilation.
Found with coverity.
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
commit ece33f96879775401361d14cb2faeb1a2f1ea806
Author: Brian Paul <brianp at vmware.com>
Date: Tue Sep 8 09:40:29 2015 -0600
svga: remove useless MAX2() call
The sum of two unsigned ints is always >= 0. Found with Coverity.
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
commit bc75fe214d428f857155ae6737194c73ddfed55f
Author: Brian Paul <brianp at vmware.com>
Date: Tue Sep 8 09:39:40 2015 -0600
winsys/svga: remove useless assertion
An unsigned int is always >= 0. Found with Coverity.
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
commit 9de62819c9d4764b77b092e3007b489e3e2f1448
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Sep 10 19:12:38 2015 +0100
docs: add news item and link release notes for 10.6.7
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit ded289e3480a8e9421754d920d7ee5f174d9c5a5
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Sep 10 19:02:21 2015 +0100
docs: add sha256 checksums for 10.6.7
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit 8789dd627ce3411a8d9271abead240f3265bd4d2)
commit e3c5aeee71e4c00555185e30fd766acb5b8ffd35
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Sep 10 18:45:17 2015 +0100
docs: add release notes for 10.6.7
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit 32efdc87cbf89cfe08ad9571cd756e27c803caa8)
commit 423a1dca2fefc41e2ceac8da90b86225488ab647
Author: Krzesimir Nowak <krzesimir at kinvolk.io>
Date: Thu Sep 10 14:16:00 2015 +0200
docs: Update wrt. textureQueryLod on softpipe
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 60905f2b19e13b03b5ae981e36ac434c6a4529ae
Author: Krzesimir Nowak <krzesimir at kinvolk.io>
Date: Thu Sep 10 14:15:59 2015 +0200
softpipe: Implement and enable textureQueryLod
Passes the shader piglit tests and introduces no regressions.
This commit finally makes use of the refactoring in previous
commits.
v2:
- adapted the code to changes in previous commits (renames,
need_cube_convert stuff)
- splitted too long lines
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 263d4a74062b16529a4819e870fa12b926e339ec
Author: Krzesimir Nowak <krzesimir at kinvolk.io>
Date: Thu Sep 10 14:15:58 2015 +0200
tgsi: Add code for handling lodq opcode
This introduces new vfunc in tgsi_sampler just for this opcode. I
decided against extending get_samples vfunc to return the mipmap level
and LOD - the function's prototype is already too scary and doing the
sampling for textureQueryLod would be a waste of time.
v2:
- splitted too long lines
Reviewed-by: Brian Paul <brianp at vmware.com>
commit d71a3be86008c275b5902de7759385643546a210
Author: Krzesimir Nowak <krzesimir at kinvolk.io>
Date: Thu Sep 10 14:15:57 2015 +0200
softpipe: Add functions for computing relative mipmap level
These functions will be used by textureQueryLod.
v2:
- renamed mip_level_* funcs to mip_rel_level_* to indicate that
these functions return mip level relative to base level and
documented them
- renamed a level member in sp_filter_funcs struct to relative_level
- changed mip_rel_level_none and mip_rel_level_nearest to return mip
level relative to base level, mip_rel_level_linear already did
that
- documented clamp_lod function
Reviewed-by: Brian Paul <brianp at vmware.com>
commit ac3637dda04fe1315f19099bd142e4f8f6754b1d
Author: Krzesimir Nowak <krzesimir at kinvolk.io>
Date: Thu Sep 10 14:15:56 2015 +0200
softpipe: Split 3D to 2D coords conversion into separate function
This is to avoid tying the conversion to the sampling -
textureQueryLod will need to do the conversion too, but it does not do
any sampling.
So instead of a "get_samples" vfunc, there is just a bool saying
whether the conversion is needed or not. This solution keeps a nice
property of not adding any overhead for the common case (2D textures).
v2:
- replaced the "convert_coords" vfunc with a "need_cube_convert"
boolean to avoid overhead of copying arrays in common case
- removed an unused typedef
- splitted too long lines in convert_cube
- const fixes in convert_cube
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 380a3c08049e5a3b0b1a891e3288b001c535d62f
Author: Krzesimir Nowak <krzesimir at kinvolk.io>
Date: Thu Sep 10 14:15:55 2015 +0200
softpipe: Split code getting a filter into separate function
This function will be later used by textureQueryLod. The
img_filter_func are optional, because textureQueryLod will not need
them.
v2:
- adapted to changes in previous commit (renames)
- simplified conditions a bit
- updated docs
- splitted too long lines
Reviewed-by: Brian Paul <brianp at vmware.com>
commit b9bc6c42c96773a5784897c55da5387045c0e9b3
Author: Krzesimir Nowak <krzesimir at kinvolk.io>
Date: Thu Sep 10 14:15:54 2015 +0200
softpipe: Put mip_filter_func inside a struct
Putting this function pointer into a struct enables grouping of
several related functions in a single place. For now it is just a
single function, but the struct will be later extended with a
mip_level_func for returning relative mip level.
v2:
- renamed sp_mip struct to sp_filter_funcs
- renamed sp_filter_funcs instances from mip_foo to funcs_foo
- splitted too long lines
- sp_sampler now holds a pointer to sp_filter_funcs instead of an
instance of it
- some const fixes
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 16084cd2cf055849933e19047e604d384da81f8e
Author: Krzesimir Nowak <krzesimir at kinvolk.io>
Date: Thu Sep 10 14:15:53 2015 +0200
softpipe: Split compute_lambda_lod into two functions
textureQueryLod returns a vec2 with a mipmap information and a
LOD. The latter needs to be not clamped.
v2:
- changed the "not_clamped" part to "unclamped"
- corrected "clamp into" to "clamp to"
- splitted too long lines
Reviewed-by: Brian Paul <brianp at vmware.com>
commit bdc69552ca0268fa489daa215dff7db96fdbeb1d
Author: Krzesimir Nowak <krzesimir at kinvolk.io>
Date: Thu Sep 10 14:15:52 2015 +0200
softpipe: Fix textureLod with nonzero GL_TEXTURE_LOD_BIAS value
The level-of-detail bias wasn't simply added in the explicit LOD case.
This case seems to be tested only in piglit's
fs-texturequerylod-nearest-biased test, which is currently skipped, as
softpipe does not support textureQueryLod at the moment.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 85500fe2e154c1664dc3a89f1e58e9a9c0dff012
Author: Krzesimir Nowak <krzesimir at kinvolk.io>
Date: Thu Sep 10 14:15:51 2015 +0200
tgsi: Remove trailing backslash in comment
It clearly is here by accident.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit b409524fef1b02c717b4cc1fef70d5710781f824
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Sep 6 15:41:35 2015 +0200
gallium/radeon: handle PIPE_TRANSFER_FLUSH_EXPLICIT
Basically, do the same thing as for buffer_unmap, but use the explicit range
instead. It's for apps which want to map a whole buffer and mark touched
ranges explicitly.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 60ec8fb448f292b8aac08f74c26da8171b2b6a8f
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Sep 3 19:34:58 2015 +0200
radeonsi: don't update polygon offset state if it has no effect
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit afa752d3f03ac6697581ff5d324e8ac0512ef513
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Sep 6 15:59:33 2015 +0200
radeonsi: decrease the size of si_pm4_state
Acked-by: Michel Dänzer <michel.daenzer at amd.com>
commit 6a684ff67e650d2da5ccbd7ba72ade0d0abb7ea7
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Sep 6 15:49:55 2015 +0200
radeonsi/compute: add buffers to the CS directly
Packets are emitted immediately anyway.
Acked-by: Michel Dänzer <michel.daenzer at amd.com>
commit 2176b3b09f49c1fca9ab2dbcd6b821d5637230d0
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Jul 3 20:17:36 2014 +0200
radeonsi: only use new versions of LLVM image and sample intrinsics
Just a cleanup I had made a long time ago and forgot about.
v2: use tgsi_is_shadow_target
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
commit e6d3846dd0873a2ded19c6416648ad61f66fbd60
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Sep 6 16:26:21 2015 +0200
gallium/radeon: drop support for LLVM 3.4
This allows using the new tex instrinsics unconditionally.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 5fbfd8dd231a70b921ff69677ce35ecc1305932c
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Sep 6 16:19:33 2015 +0200
r600/llvm: remove dead code for LLVM 3.3
LLVM 3.3 has been unsupported for quite a while.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 5c6c5b524649997805d0128d4df9dda5e8567cbb
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Sep 6 16:40:21 2015 +0200
r600g: use pipe_resource::width0 instead pb_buffer::size
pb_buffer::size was aligned by 29aaab2b5f55cc6d9a84f58ce2bb8607e76a9dde,
which broke the CMASK code I think.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91881
Cc: 11.0 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 7956eae1c76e298ca1ded46679c1a9bf875ec4ee
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Sep 2 19:05:09 2015 +0200
radeonsi: enable VGPR spilling on VI
This fixes corruption in Unigine Heaven on VI
Cc: 11.0 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
commit c6502e880bba00f8a68f004fe6be7a4bc275494a
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Sep 2 19:04:25 2015 +0200
winsys/amdgpu: calculate the maximum number of compute units
Required for register spilling.
Cc: 11.0 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
commit adeba943e1d89cba824c054bac6a1b64e415921e
Author: Jon TURNEY <jon.turney at dronecode.org.uk>
Date: Fri Sep 4 14:00:19 2015 +0100
Use IMP_LIB_EXT when checking for LLVM shared libraries
When checking for LLVM shared libraries, use IMP_LIB_EXT for the extension for
shared libraries appropriate to the target, rather than hardcoding '.so'
Also add some comments to explain why we have this circus of pain.
Signed-off-by: Jon TURNEY <jon.turney at dronecode.org.uk>
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 2c3007652d5177fe6d018de67be8209a1c3f1b83
Author: Rhys Kidd <rhyskidd at gmail.com>
Date: Tue Sep 8 23:52:50 2015 +0800
i965: Resolve GCC sign-compare warning.
mesa/src/mesa/drivers/dri/i965/brw_eu_compact.c: In function 'set_3src_control_index':
mesa/src/mesa/drivers/dri/i965/brw_eu_compact.c:805:22: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (int i = 0; i < ARRAY_SIZE(gen8_3src_control_index_table); i++) {
^
mesa/src/mesa/drivers/dri/i965/brw_eu_compact.c: In function 'set_3src_source_index':
mesa/src/mesa/drivers/dri/i965/brw_eu_compact.c:839:22: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (int i = 0; i < ARRAY_SIZE(gen8_3src_source_index_table); i++) {
^
mesa/src/mesa/drivers/dri/i965/brw_state_dump.c: In function 'dump_sampler_state':
mesa/src/mesa/drivers/dri/i965/brw_state_dump.c:382:18: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (i = 0; i < size / 16; i++) {
^
mesa/src/mesa/drivers/dri/i965/brw_state_upload.c: In function 'brw_pipeline_state_finished':
mesa/src/mesa/drivers/dri/i965/brw_state_upload.c:801:13: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
if (i != pipeline) {
^
mesa/src/mesa/drivers/dri/i965/intel_mipmap_tree.c: In function 'intel_gen7_hiz_buf_create':
mesa/src/mesa/drivers/dri/i965/intel_mipmap_tree.c:1544:47: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (int level = mt->first_level; level <= mt->last_level; ++level) {
^
mesa/src/mesa/drivers/dri/i965/intel_mipmap_tree.c: In function 'intel_gen8_hiz_buf_create':
mesa/src/mesa/drivers/dri/i965/intel_mipmap_tree.c:1638:44: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (int level = mt->first_level; level <= mt->last_level; ++level) {
^
mesa/src/mesa/drivers/dri/i965/intel_mipmap_tree.c: In function 'intel_miptree_alloc_hiz':
mesa/src/mesa/drivers/dri/i965/intel_mipmap_tree.c:1771:44: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (int level = mt->first_level; level <= mt->last_level; ++level) {
^
mesa/src/mesa/drivers/dri/i965/intel_mipmap_tree.c:1775:33: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (int layer = 0; layer < mt->level[level].depth; ++layer) {
^
Signed-off-by: Rhys Kidd <rhyskidd at gmail.com>
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 1c194840fda7b1a6344aa40def9879b418fa977d
Author: Rhys Kidd <rhyskidd at gmail.com>
Date: Tue Sep 8 23:52:49 2015 +0800
mesa: Resolve GCC sign-compare warning.
mesa/src/mesa/program/prog_to_nir.c: In function 'setup_registers_and_variables':
/mesa/src/mesa/program/prog_to_nir.c:1059:22: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (int i = 0; i < c->prog->NumTemporaries; i++) {
^
Signed-off-by: Rhys Kidd <rhyskidd at gmail.com>
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
Reviewed-by: Jan Vesely <jan.vesely at rutgers.edu>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 32cdb49fe2f0211040bfb16e668169097199bfcc
Author: Rhys Kidd <rhyskidd at gmail.com>
Date: Tue Sep 8 23:52:48 2015 +0800
glsl: Resolve GCC sign-compare warning.
mesa/src/glsl/nir/nir_lower_tex_projector.c: In function 'nir_lower_tex_projector_block':
mesa/src/glsl/nir/nir_lower_tex_projector.c:63:25: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (int i = 0; i < tex->num_srcs; i++) {
^
mesa/src/glsl/nir/nir_lower_tex_projector.c: In function 'nir_lower_tex_projector_block':
mesa/src/glsl/nir/nir_lower_tex_projector.c:114:38: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (int i = proj_index + 1; i < tex->num_srcs; i++) {
^
mesa/src/glsl/nir/nir_lower_tex_projector.c: In function 'nir_lower_tex_projector_block':
mesa/src/glsl/nir/nir_lower_tex_projector.c:53:39: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (proj_index = 0; proj_index < tex->num_srcs; proj_index++) {
^
mesa/src/glsl/nir/nir_lower_tex_projector.c:57:22: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
if (proj_index == tex->num_srcs)
^
mesa/src/glsl/nir/nir_search.c: In function 'match_value':
mesa/src/glsl/nir/nir_search.c:84:22: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (int i = 0; i < num_components; ++i)
^
mesa/src/glsl/nir/nir_search.c: In function 'match_value':
mesa/src/glsl/nir/nir_search.c:110:28: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (int i = 0; i < num_components; ++i) {
^
mesa/src/glsl/nir/nir_search.c: In function 'match_value':
mesa/src/glsl/nir/nir_search.c:139:19: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
if (i < num_components)
^
mesa/src/glsl/nir/nir_opt_peephole_ffma.c: In function 'get_mul_for_src':
mesa/src/glsl/nir/nir_opt_peephole_ffma.c:130:27: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (unsigned i = 0; i < num_components; i++)
^
Signed-off-by: Rhys Kidd <rhyskidd at gmail.com>
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
Reviewed-by: Jan Vesely <jan.vesely at rutgers.edu>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 548bf70fd22ca862692abc83700ff5010f92b9b6
Author: Rhys Kidd <rhyskidd at gmail.com>
Date: Tue Sep 8 23:15:27 2015 +0800
mesa: Resolve GCC missing field initializer warning.
Resolve a series of missing field initializer warnings within get_hash_params.py
Of the form:
In file included from mesa/src/mesa/main/get.c:495:0:
mesa/src/mesa/main/get_hash.h:180:5: warning: missing initializer for field
'extra' of 'const struct value_desc' [-Wmissing-field-initializers]
{ GL_POINT_SIZE_ARRAY_BUFFER_BINDING_OES, LOC_CUSTOM, TYPE_INT, 0 },
^
mesa/src/mesa/main/get.c:165:15: note: 'extra' declared here
const int *extra;
^
This patch addresses some likely code rot around the *extra field, where the
initialization is via C code generated indirectly from a Python script.
It resolves a number of warnings reported by GCC when configured to be pedantic.
$ gcc --version
gcc (Ubuntu 4.9.2-10ubuntu13) 4.9.2
No piglit regressions on Ironlake.
v2:
- Squash series into a single patch.
Signed-off-by: Rhys Kidd <rhyskidd at gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
Reviewed-by: Jan Vesely <jan.vesely at rutgers.edu>
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 1691ead1b8ae4018a805af58977a43ef90af4203
Author: Albert Freeman <albertwdfreeman at gmail.com>
Date: Tue Sep 8 13:06:40 2015 +0000
clover: Avoid using typename to allow compilation of clover by clang
When parsing an variable declaration qualified with the typename
keyword, clang attempted to declare a variable with the type of non
type member "enum type type" of module::argument (within the header
file clover/core/module.hpp) instead of the typed member of
module::argument "enum type".
Replaced "typename" with "enum" to force clang to declare the variable
marg_type with type "enum type" of module::argument.
CC: "11.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Signed-off-by: Albert Freeman <albertwdfreeman at gmail.com>
commit bf58a2c362d5afdba512f40b3eb300154201c7f0
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Sep 8 15:41:11 2015 -0700
i965: Advertise 65536 for GL_MAX_UNIFORM_BLOCK_SIZE.
Our old value of 16384 is the minimum value. DirectX apparently
requires 65536 at a minimum; that's also what nVidia and the Intel
Windows driver advertise. AMD advertises MAX_INT.
Ilia Mirkin noticed that "Shadow Warrior" uses UBOs larger than 16k
on Nouveau, which advertises 65536 bytes for this limit. Traces
captured on Nouveau don't work on i965 because our lower limit causes
the GLSL linker to reject the captured shaders. While this isn't
important in and of itself, it does suggest that raising the limit
would be beneficial.
We can read linear buffers up to 2^27 bytes in size, so raising this
should be safe; we could probably even go larger. For now, matching
nVidia and Intel/Windows seems like a good plan.
We have to reinitialize MaxCombinedUniformComponents as core Mesa will
have set it based on a stale value for MaxUniformBlockSize.
According to Tapani, there's an unreleased game that asserts on this.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
commit 74b86b971f3bf9b0482341b07c1cbc2e520fb1d0
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Sep 10 05:02:26 2015 -0400
nv50/ir: don't fold immediate into mad if registers are too high
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91551
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
commit ce28ca713364dbe83cb3c371ca034bc2c2947616
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Sep 10 03:55:06 2015 -0400
nv50/ir: fix emission of 8-byte wide interp instruction
This can come up if the target register number is > 63, which is fairly
rare.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91551
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
commit 641eda0c792e10c2792730b1833353564479a557
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Sep 10 03:49:36 2015 -0400
nv50/ir: r63 is only 0 if we are using less than 63 registers
It is advantageous to use r63 instead of r127 since r63 can fit into the
shorter encoding. However if we've RA'd over 63 registers, we must use
r127 as the replacement instead.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
commit a072ef8748a65d286e9b542bb9ea6e020fdcc7f8
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Sep 10 01:54:30 2015 -0400
nv50/ir: make edge splitting fix up phi node sources
Unfortunately nv50_ir phi nodes aren't directly connected to the CFG, so
the mapping between source and the actual BB is by inbound edge order.
So when manipulating edges one has to be extremely careful. We were
insufficiently careful when splitting critical edges which resulted in
the phi nodes being confused as to where their sources were coming from.
This primarily manifests itself with the TXL-lowering logic on nv50,
when it is inside of a conditional. I've been unable to trigger the
issue anywhere else so far. This resolves rendering failures
in a number of games like Two Worlds 2, Trine: Enchanted Edition, Trine 2,
XCOM:Enemy Unknown, Stacking. It also improves the situation in
Hearthstone, Sonic Generations, and The Raven: Legacy of a Master Thief.
However more work needs to be done there (splitting a lot more edges
solves it, so it's some other sort of RA-related issue).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90887
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
commit 13a974f9aea03a538c2a67417b5bee8bc732cca2
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Aug 26 13:45:52 2015 +0100
glsl: Remove ADD_VARYING macro
The purpose of the macro was to create the name_as_gs_input from name.
The previous commit removed the name_as_gs_input from add_varying, so
the macro is unnecessary.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit bd0245b8b2fba3852178d635f4e9602845ea6dd3
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Aug 26 13:38:49 2015 +0100
glsl: Silence unused parameter warnings
builtin_variables.cpp:1062:53: warning: unused parameter 'name_as_gs_input' [-Wunused-parameter]
const char *name_as_gs_input)
^
builtin_functions.cpp:4774:47: warning: unused parameter 'intrinsic_name' [-Wunused-parameter]
const char *intrinsic_name,
^
builtin_functions.cpp:4907:66: warning: unused parameter 'state' [-Wunused-parameter]
_mesa_glsl_find_builtin_function_by_name(_mesa_glsl_parse_state *state,
^
builtin_functions.cpp:4915:49: warning: unused parameter 'num_arguments' [-Wunused-parameter]
unsigned num_arguments,
^
builtin_functions.cpp:4916:49: warning: unused parameter 'flags' [-Wunused-parameter]
unsigned flags)
^
ir_print_visitor.cpp:589:37: warning: unused parameter 'ir' [-Wunused-parameter]
ir_print_visitor::visit(ir_barrier *ir)
^
linker.cpp:3212:48: warning: unused parameter 'ctx' [-Wunused-parameter]
build_program_resource_list(struct gl_context *ctx,
^
standalone_scaffolding.cpp:65:57: warning: unused parameter ‘id’ [-Wunused-parameter]
_mesa_shader_debug(struct gl_context *, GLenum, GLuint *id,
^
v2: Rebase on top of GL_ARB_shader_image_size work (especially
58a86897). Silence more warnings added by that work.
v3: Remove mention of the removed parameter from comments. Suggested by
Iago.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu> [v1]
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
Cc: "Martin Peres <martin.peres at linux.intel.com>"
commit 342e68dc60eebb20ac1be9f47800ee9e604354f0
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Sep 9 21:50:03 2015 -0400
nvc0: remove BGRA4 format support
Something is wrong with the support somewhere. I couldn't get the blob
driver to use it either, although it happily used RGB5_A1.
teximage-colors works, but WoW seems to fail in the menus for drawing
text.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91526
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
commit 9ce2e3072696428277988040908c9ae7a0abf9ad
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Sep 9 17:27:17 2015 -0400
gallium/ttn: fix cursor handling vs builder
After inserting instructions the cursor.option becomes _after_instr
(even if it started life as an _after_block). So we cannot simply stash
the current cursor on the if/loop_stack. Otherwise we end up inserting
instructions after the endif/endloop in the block preceeding the if/
loop.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit e50c01d5af305e07110cb4a38d5a655437058f04
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Sep 9 03:17:38 2015 -0400
nvc0: keep track of cb bindings per buffer, use for upload settings
CB updates to bound buffers need to go through the CB_DATA endpoints,
otherwise the shader may not notice that the updates happened.
Furthermore, these updates have to go in to the same address as the
bound buffer, otherwise, again, the shader may not notice updates.
So we keep track of all the places where a constbuf is bound, and
iterate over all of them when updating data. If a binding is found that
encompasses the region to be updated, then we use the settings of that
binding for the upload. Otherwise we upload as a regular data update.
This fixes piglit 'arb_uniform_buffer_object-rendering offset' as well
as blurriness in Witcher2.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91890
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
commit b828f7a27b2b8d6b90e646c08dfa25e1d737a9bb
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Sep 8 14:31:11 2015 -0700
nir/glsl: Use lower_outputs_to_temporaries instead of relying on GLSL IR
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 1dbe4af9c9e318525fc082b542b93fb7f1e5efba
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Aug 28 17:09:02 2015 -0700
nir: Add a pass to lower outputs to temporary variables
This pass can be used as a helper for NIR producers so they don't have to
worry about creating the temporaries themselves.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit f5e08ab6b1351c41000fd2f1a16c1273d2f74d40
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Aug 28 17:17:39 2015 -0700
nir/cursor: Add a constructor for the end of a block but before the jump
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 3e9df0e3af7a8a84147ae48f588e9c435bf65b98
Author: Hans de Goede <hdegoede at redhat.com>
Date: Wed Sep 9 15:52:09 2015 +0200
nv30: Disable msaa unless requested from the env by NV30_MAX_MSAA
Some modern apps try to use msaa without keeping in mind the
restrictions on videomem of older cards. Resulting in dmesg saying:
[ 1197.850642] nouveau E[soffice.bin[3785]] fail ttm_validate
[ 1197.850648] nouveau E[soffice.bin[3785]] validating bo list
[ 1197.850654] nouveau E[soffice.bin[3785]] validate: -12
Because we are running out of video memory, after which the program
using the msaa visual freezes, and eventually the entire system freezes.
To work around this we do not allow msaa visauls by default and allow
the user to override this via NV30_MAX_MSAA.
Signed-off-by: Hans de Goede <hdegoede at redhat.com>
[imirkin: move env var lookup to screen so that it's only done once]
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
commit ac066bf65cb585a4f6b4a2fb1d055b033f2b94ae
Author: Hans de Goede <hdegoede at redhat.com>
Date: Wed Sep 9 15:52:08 2015 +0200
nv30: Fix color resolving for nv3x cards
We do not have a generic blitter on nv3x cards, so we must use the
sifm object for color resolving.
This commit divides the sources and dest surfaces in to tiles which
match the constraints of the sifm object, so that color resolving
will work properly on nv3x cards.
Signed-off-by: Hans de Goede <hdegoede at redhat.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
commit 30a915bd174a4a4dd950870eca19dde45bbd524b
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Sep 3 14:53:03 2015 -0400
gallium/docs: clairify dmabuf fd ownership
Since debugging issues w/ fd's close()d at the wrong time can be quite
fun, this should probably be made more explicit in the docs.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit c12ffb30b4a53eda55ef8f541b760c309c488e66
Author: Mauro Rossi <issor.oruam at gmail.com>
Date: Sun Sep 6 14:15:38 2015 +0200
android: radeonsi: add support for sid_tables.h generated sources
This patch is necessary to avoid building error on android,
due to missing sid_tables.h generated sources
v2:[Emil Velikov] Correctly split the lists.
Fixes: fbbebeae10f(radeonsi: inline si_cmd_context_control)
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 8056b3ffeb0cdca890cf9cde05dcd5afff4c50fc
Author: Mauro Rossi <issor.oruam at gmail.com>
Date: Fri Aug 21 23:46:29 2015 +0200
android: Always define __STDC_LIMIT_MACROS.
Analogous to commit 02a4fe22b13 (configure.ac: Always define
__STDC_LIMIT_MACROS.)
v2: [Emil Velikov] keep the LLVM specific __STDC_FORMAT_MACROS
Cc: 11.0 <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 5235bfe7b709d5cf0fcd38dff43a97909cfbc38c
Author: Mauro Rossi <issor.oruam at gmail.com>
Date: Fri Aug 21 23:46:28 2015 +0200
android: rename LLVM_VERSION_PATCH to MESA_LLVM_VERSION_PATCH
Fixes: 797f4eacea8(configure.ac: rename LLVM_VERSION_PATCH to avoid
conflict with llvm-config.h)
Cc: 11.0 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit e838d91b94c3d1d20db62a61bfd9163f675d3139
Author: Mauro Rossi <issor.oruam at gmail.com>
Date: Fri Aug 21 23:46:27 2015 +0200
nouveau: android: add space before PRIx64 macro
Otherwise the android build fails with
error : unable to find string literal operator ‘operator"" PRIx64’
There are several resources referring to the problem, which is related
to c++11, in our case used when building mesa for lollipop.
http://comments.gmane.org/gmane.comp.graphics.opensg.user/5883
I've not investigated all the semantics, some people even suggested a
bug in the gcc compiler,
I just saw the building error was solved with one little space for
lollipop and no side effect when c+11 not used.
v2: [Emil Velikov] add an alternative commit message from Mauro.
Cc: 11.0 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit d9df8c2fa274629de689c7e364c3c1a65f0b7d0c
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Sep 9 13:22:23 2015 +0100
svga: pick all the files into the tarball
Signed-off-by: Emil Velikov <emil.velikov at collabora.co.uk>
commit 0d39279448bbda6e824bcfd4997b4583bc0481af
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Jul 17 10:52:35 2015 +0100
auxiliary: rework the python generated sources rules
There are a few bits this commit aims to resolve:
One can generalise the mkdir rule to a simple MKDIR_P $(@D) which will
expand appropriately for even if we change the subdir name, and/or add
new rules. We can also drop the explicit $(srcdir) prefix for the
dependency rules, they they are not strictly required, nor used
elsewhere in mesa.
Finally replace $< with explicit filename to be consistent through the
file, and honour PYTHON_FLAGS.
v2: Add comprehensive commit summary/message (Ian, Matt)
Cc: 11.0 <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit c373eaedfc09ff2af7002b64ba0ae8ba71df86a1
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Sep 9 12:40:03 2015 +0100
glsl: build: remove bogus dependency
v2: rebase on top of the previous commit - don't touch the LOCAL_PATH
prefix for nir_constant_expressions.h
Cc: 11.0 <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit a3b05e04921a4fcc05cfc994e415e3ceb39fd184
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Jul 17 13:30:51 2015 +0100
glsl: build: use makefile.sources variables when possible
Rather than folding one variable within the other only to unwrap them,
just use the ones we need.
v2: bring back LOCAL_PATH prefix for nir_constant_expressions,h
Cc: 11.0 <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com> (v1)
commit da5e4559ee3b239d2483645ed54b35aa6628fbaf
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Jul 17 13:28:00 2015 +0100
glsl: automake: reuse $(NIR_GENERATED_FILES) where possible
Cc: 11.0 <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 9e0594418d8fa47e19bfe57450198d3fa7d087a0
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Sep 9 12:28:37 2015 +0100
glsl: automake: rework the sources generation rules
The glsl equivalent of "mesa: automake: rework the source generation
rules". Plus let's make things consistent and always explicitly provide
the header name.
v2: Rebase on top of reverted "remove custom AM_V_LEX/YACC" (Matt)
Cc: 11.0 <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit fd913f47b7fcc724d8d191f2752f328d037abb20
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Jul 17 10:44:30 2015 +0100
mesa: automake: rework the source generation rules
Same logic as previous commit applies.
Additionally remove the odd (set -e/mv/INDENT) from the rules.
The last one is the only one we remotely care about, if reading the
generated sources.
Upcoming work from DylanB which will replace the existing python
scripts with ones that produce more readable output anyway.
Cc: 11.0 <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 96509aa80429db1884a78fae95c169aa40641e84
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Jul 17 10:27:29 2015 +0100
mapi: automake: rework the source generation rules
Same logic as previous commit applies. Also fix bogus MESA_MAPI_DIR -
the sources are located in the source dir (duh).
Cc: 11.0 <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 449ce5d64f3d0e5840287040755df23e86ce6bb2
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Sep 9 12:14:00 2015 +0100
mapi: automake: rework the *api/glapi_mapi_tmp.h rules
Same logic as previous commit applies.
v2: Merge with "inline glapi_gen_mapi define" (Matt)
Cc: 11.0 <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit d65bd7a7be48d7805f68cd45218794f3e4590408
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Jul 17 10:21:06 2015 +0100
util: automake: rework the format_srgb.c rule
A handful of changes/cleanups paving the way to bmake support:
- Remove optional $(srcdir)/ prefix for files in the prereq list.
- Drop the space after the AM_V_GEN variable.
- Using $< in a non-suffix rule is a GNU make idiom.
- Use $(@D) over $(dir $@). The latter is a POSIX standard.
v2: Cosmetic tweaks in the commit summary.
Cc: 11.0 <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com> (v1)
commit c8984a7a4686c2045666d32fbe5733ff5a5c3bd8
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Jul 15 10:28:05 2015 +0100
xmlpool: 'promote' LOCALEDIR variable
This is the only place in mesa that uses this constuct which seems
to be GNUmake-ism. Attempting to build with POSIX make implementations
(bmake) would fail as below.
--- options.h ---
LOCALEDIR := .
sh: line 2: LOCALEDIR: command not found
*** [options.h] Error code 127
So let's keep things consistent and compatible by making the variable
non target specific.
v2:
- Bring back LOCALEDIR.
- Reword the commit message
- Change mesa-stable tag 10.6 > 11.0
Cc: 11.0 <mesa-stable at lists.freedesktop.org>
Cc: Jonathan Gray <jsg at jsg.id.au>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 63c4b7ee1e76efece745fc581ac4990d197824cc
Author: Boyan Ding <boyan.j.ding at gmail.com>
Date: Tue Jul 21 23:43:58 2015 +0800
egl_dri2: Add support for EGL_KHR_create_contest when using swrast
This requires swrast version >= 3. Also EGL_EXT_create_context_robostness
is supported if __DRI2_ROBUSTNESS extension is found.
Reference: https://bugs.freedesktop.org/show_bug.cgi?id=80821
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Signed-off-by: Boyan Ding <boyan.j.ding at gmail.com>
commit 6345d2da60eb6eace23bc9b5a6e606726c3caea2
Author: Boyan Ding <boyan.j.ding at gmail.com>
Date: Tue Jul 21 23:43:57 2015 +0800
egl_dri2: Use createContextAttribs if swrast version >= 3
v2: Change return type of the new function from int to bool
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Signed-off-by: Boyan Ding <boyan.j.ding at gmail.com>
commit b9ea608c1a0f3356f5c4e13bdd7307b726dc42ba
Author: Boyan Ding <boyan.j.ding at gmail.com>
Date: Tue Jul 21 23:43:56 2015 +0800
egl_dri2: Move filling context_attrib array in a separate function
v2: Change return type of the new function from int to bool
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Boyan Ding <boyan.j.ding at gmail.com>
commit b8d6de87f6e2d5fc621db573b9ce579b1a27ee56
Author: Marta Lofstedt <marta.lofstedt at intel.com>
Date: Mon Aug 31 15:04:18 2015 +0200
mesa: Allow query of GL_VERTEX_BINDING_BUFFER
According to OpenGL ES 3.1 specification table : 20.2 and
OpenGL specification 4.4 table 23.4. The glGetIntegeri_v
functions should report the name of the buffer bound
when called with GL_VERTEX_BINDING_BUFFER.
Signed-off-by: Marta Lofstedt <marta.lofstedt at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit ea69ae04dba501016e9faf5f71095908f011d29d
Author: Marta Lofstedt <marta.lofstedt at intel.com>
Date: Mon Aug 10 13:24:00 2015 +0200
mesa/es3.1: Enable GL_MAX_VERTEX_ATTRIB enums for GLES 3.1
Signed-off-by: Marta Lofstedt <marta.lofstedt at linux.intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 0cc331dddd1a99c7af3619c92c48b5c32e17f6b3
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Aug 3 16:10:21 2015 -0700
i965/nir: Use nir_system_value_from_intrinsic to reduce duplication.
This code is all pretty much identical. We just needed the translation
from one enum value to the other.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit d5d74d0b86207cff2820561cc3c8b40546a11bc9
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Aug 3 16:02:16 2015 -0700
nir: Add a nir_system_value_from_intrinsic() function.
This converts NIR intrinsics that load system values into Mesa's
SYSTEM_VALUE_* enumerations.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 8fbc4ae330b9ef51bce9023c2f58d1888fb6b796
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Jul 24 21:03:31 2015 -0700
i965: Mark topologies with adjacency information as G45+.
These didn't exist on the original 965.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit aa18fa30c5e692a0b77aea40a966d4bf99ebe02e
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Jul 24 21:01:43 2015 -0700
i965: Fix value of _3DPRIM_TRIFAN_NOSTIPPLE.
TRIFAN_NOSTIPPLE has always been 0x16 - 0x15 is marked "Reserved" on all
platforms. See the 965 PRM, Volume 2, Table 3-1, "3D Primitive Topology
Type Encoding" for a list.
We don't currently use this, and I don't expect we will, but we may as
well not leave the bogus value around.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit 70650094ef89ec0261071862ca1589f0550fb792
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Sun Dec 7 15:32:11 2014 +1300
i965: Add 64-bit dirty flag handling to brw_upload_pull_constants
Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit a9df772e0e76254ab232876016ec09b1fadbd700
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Fri Nov 7 00:04:01 2014 +1300
i965: Add defines for all new Gen7/8 URB opcodes
Tessellation needs to emit URB reads and atomics;
Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit e8a219ab463a0071f4d9c5d88feeeaa87b2a01f2
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Wed Aug 26 10:52:58 2015 -0700
i965/gen8+: Skip depth stalls on state change
Docs suggest this is no longer required starting with Gen8.
Perf (no regressions in n=20)
OglMultithread 0.67%
OglTerrainPanInst 0.12%
trex 0.45%
warsow 0.64%
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
commit 6d2ceb10cd63b89892131a27d238620f00922dfb
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Sep 8 08:36:32 2015 +1000
r600: don't use shader key without verifying shader type (v2)
Since 7a32652231f96eac14c4bfce02afe77b4132fb77
r600: Turn 'r600_shader_key' struct into union
we were accessing key fields that might be aliased in the union
with other fields, so we should check what shader type we are
compiling for before using key values from it.
v1.1: make it compile
v2: have caffeine, make it work - we don't set type
until later, so don't reference it until we've set it.
Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit f5509874aa747167255c2fb739ed44be2445a4c6
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Tue Sep 8 10:19:22 2015 -0700
i965/skl: Use more compact hiz dimensions
I meant to do this here, but it was in the wrong place:
commit c1151b18f2dce7c6f238f057e9c4fa8d912ce6b5
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Wed Jun 24 20:07:54 2015 -0700
i965/skl: Use more compact hiz dimensions
NOTE: Jordan did go back and look at the original mailing list post. I mailed
the right thing, and pushed the wrong one.
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Neil Roberts <neil at linux.intel.com>
commit 458e55d7c5793b02af8b08ebec90906a829d3f65
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Tue Sep 8 16:58:43 2015 -0400
st/mesa: increase viewport bounds limits for GL4 hw
According to the ARB_viewport_array spec, GL4 limit is higher than the
GL3 limit. Also take this opportunity to fix the GL3 limit.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 39df725f731f75f488c75a4910169beb352213fb
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Sep 6 04:51:29 2015 -0400
nvc0: always emit a full shader colormask
Indications are that if the colormask indicates a single bit set on
fermi, that value will always be read from $r0 instead of a potentially
higher register (if e.g. green is set). Not to upset the counting logic,
always set the header up with a full color mask for each RT. Such a
situation can basically only ever happen with generated blit shaders.
Fixes the following piglit on Fermi (Kepler is unaffected):
fbo-stencil blit GL_DEPTH32F_STENCIL8
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
commit a3b0b3fda5bd4fcedc84ef21bad5ddbe591a1cfb
Author: Brian Paul <brianp at vmware.com>
Date: Tue Sep 8 08:47:01 2015 -0600
docs: fix date formatting in index.html
commit 205ff843ffa12f461c5307903c200baa1d3c87c0
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Tue Sep 1 11:32:29 2015 +0200
nir: UBO loads no longer use const_index[1]
Commit 2126c68e5cba killed the array elements parameter on load/store
intrinsics that was stored in const_index[1]. It looks like that
patch missed to remove this assignment in the UBO path.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 87073c69f3e253044bc235f34917aaa89041a63c
Author: Hans de Goede <hdegoede at redhat.com>
Date: Mon Sep 7 21:50:48 2015 +0200
nv30: Fix max width / height checks in nv30 sifm code
The sifm object has a limit of 1024x1024 for its input size and 2048x2048
for its output. The code checking this was trying to be clever resulting
in it seeing a surface of e.g 1024x256 being outside of the input size
limit.
This commit fixes this.
Signed-off-by: Hans de Goede <hdegoede at redhat.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
commit be519c2d50f4aaa48fdb8b27707114cc5bfd348f
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Sat Sep 5 19:19:33 2015 +0100
i965: Disallow fast blit paths for CopyTexImage with PixelTransfer ops
glCopyTexImage behaves similarly to glReadPixels with respect to the
pixel transfer operations. Therefore if any are set we cannot use the
simple blit-only fast paths.
(Though if would be possible to relax the blorp path to handle
pixel zoom, or we can just enhance meta.)
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Jason Ekstrand <jason.ekstrand at intel.com>
Cc: Kenneth Graunke <kenneth at whitecape.org>
Reviwewed-by: Iago Toral <itoral at igalia.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Cc: mesa-stable at lists.freedesktop.org
commit a1575b55c2384faa461e7802371c5ddd37e5befe
Author: Jon TURNEY <jon.turney at dronecode.org.uk>
Date: Fri Sep 4 12:43:06 2015 +0100
mesa/tests: Remove unneeded X11_CFLAGS
X11_CFLAGS is never defined. Path to X11 headers is not needed here, so
just remove.
Future work: Using AM_CFLAGS here looks wrong, as this Makefile only builds
C++ files
Signed-off-by: Jon TURNEY <jon.turney at dronecode.org.uk>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 5f9c72ad23e3f646c2007b70f482561c98b94ea7
Author: Jon TURNEY <jon.turney at dronecode.org.uk>
Date: Fri Sep 4 12:43:05 2015 +0100
glxl/tests: Use X11_INCLUDES instead of X11_CFLAGS
X11_CFLAGS is undefined, so these tests will fail to build if x11proto is
installed in a non-standard location.
(See also commits 35189d76, bc93c3798, 54b028ba, d901d7e08, etc.)
Signed-off-by: Jon TURNEY <jon.turney at dronecode.org.uk>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit f1ef89eaab765789d777a5bd1bdfcb7811e3a22d
Author: Thomas Hellstrom <thellstrom at vmware.com>
Date: Fri Sep 4 03:26:05 2015 -0700
svga: Fix surface view error handling
Make sure errors are correcly propagated.
Also don't flush during state emission if emission fails.
Signed-off-by: Thomas Hellstrom <thellstrom at vmware.com>
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 1432a182414352e853bfdad997591598e621fd73
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Sep 2 23:13:33 2015 -0700
xa: add xa_surface_from_handle2 v2
Like xa_surface_from_handle(), but takes a handle type, rather than
hard-coding 'shared' handle. This is needed to fix bugs seen with
xf86-video-freedreno with xrandr rotation, for example. The root issue
is that doing a GEM_OPEN ioctl on a bo that already has a GEM handle
associated with the drm_file will result in two unique handles for the
same bo. Which causes all sorts of follow-on fail.
v2:
- Add support for for fd handles.
- Avoid duplicating code.
- Bump xa version minor.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Signed-off-by: Thomas Hellstrom <thellstrom at vmware.com>
commit 00c568f679413ee627421d5724beb85be3da55c1
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Sat Sep 5 15:26:59 2015 +0200
i965/nir/vec4: removed unneeded tex src swizzle set
At that point the swizzle should be correct.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit ae535cb0bf86e3ae376d42f4fd064bb73c22427e
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Sep 7 00:06:51 2015 -0400
util: make mesa-sha1.c completely empty when there are no SHA1 impls
My earlier attempt to fix this missed the fact that there was a #else
clause that assumes that you have openssh. This moves the whole thing
under #ifdef HAVE_SHA1 which should avoid this issue.
Fixes: 13bfa5201 (util: always include sha1 into the build)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91898
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Dave Airlie <airlied at gmail.com>
commit 13bfa5201162185005fa9a45f7bc76e5909ab193
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Sep 4 16:43:22 2015 -0400
util: always include sha1 into the build
SHA1 is now used in all builds when HAVE_SHA1 is defined. Adjust src to
do the same thing, rather than predicating on shader cache.
Fixes: 04e201d0c02 ("mesa: change 'SHADER_SUBST' facility to work with env variables")
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Dave Airlie <airlied at gmail.com>
commit e40f32d5626c87d9e77bbc261df3648cd54bd066
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Sep 6 11:29:00 2015 -0400
st/mesa: don't fall back to 16F when 32F is requested
Nothing in the spec allows for the reduced precision, and this also
fixes st_QuerySamplesForFormat for nv50, which does not allow MS8 on
RGBA32F. Now this will be respected instead of reporting MS8 as
supported with an assumption that the format used will be RGBA16F.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit bfd3d5244b26aca7696715066f5e5331e0b5fe2a
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Sep 5 13:11:27 2015 -0400
st/mesa: properly handle u_upload_alloc failure
vbuf is never null. We want to make sure that a resource was allocated
for the vbuf, which is *vbuf.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit a778831735ea45f789c247c40677cd26adc78e3e
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Jul 2 18:44:18 2015 -0400
nouveau: don't mark full range as used on unmap with explicit flush
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org
commit c830d193db5c90cf0af57ff73606e2aa12aed9a8
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Aug 24 11:49:05 2015 -0400
nv50: avoid using inline vertex data submit when gl_VertexID is used
The hardware only generates vertexid when vertices come from a VBO. This
fixes:
vertexid-drawelements
vertexid-drawarrays
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
commit 4a025c6bc835387a31007fdf30a130e612e54e19
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Jul 3 20:32:53 2015 -0400
nv50: don't flush vertex arrays when index buffer changes
The index buffer is fed in inline over a pushbuf. It's not related to
vertices or any caching that might be done on them.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org
commit 1f62d36ae21043c472fc182fd4b738ec1d54a2d2
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Jul 3 20:16:48 2015 -0400
nv50: rebind bo to bufctx when invalidating idxbuf storage
There is nothing to be done on a dirty idxbuf, but the bo may have
changed, so we have to rebind it to the bufctx.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org
commit 114cc18b98b6e016ab1986577aa3df12acc22cca
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Jul 3 19:21:21 2015 -0400
nv50: clear buffer status on all vertex bufs, not just the first one
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org
commit 75e34d1df8b0ab56e5e658b8ef90ff6057ec954e
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Jan 1 06:09:59 2015 -0500
nv50: fix drawing from tfb, direct-to-pushbuf submits
The stride was being set to 0, which is illegal (and also non-sensical).
Also we must wait for the buffer to become available for reading as
otherwise a wrong value may be prefetched. Since we must wait for the
buffer anyways, and it's mapped and in GART, we may as well avoid the
annoyance of the indirect pushbuf submit.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org
commit 5165e464f225cd1b0f61e0da0758052b9b9ff518
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Fri Sep 4 10:42:33 2015 -0700
i965: Remove base miplevel from sampler state.
Gen9 changes the meaning of this to coarse LOD quality mode. Although that's a
desirable thing to be setting, it doesn't match the gen8 behavior and this was
unintentional. More importantly, we don't ever use this field. So instead of
getting it "wrong" drop it entirely.
This is a respin of a patch which only [incorrectly] tried to address gen9.
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 509ba61d5a28d95ce73f3d4e8d973eee56aad5c1
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Sep 4 23:11:40 2015 +0100
docs: add news item and link release notes for 10.6.6
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit f39bc1c828e14b8e8d71ea02e4c21ea7397a1ab4
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Sep 4 23:05:47 2015 +0100
docs: add sha256 checksums for 10.6.6
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit e3e2a3e0e581da39dcd9268951edb52f68916940)
commit 5685ed72b8209a8aa4415822e136a3b989173a61
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Sep 4 22:16:07 2015 +0100
docs: add release notes for 10.6.6
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit 4b05739e9d718a48415270b95c0a73b56666c364)
commit 4f2290d1612569686284609059d29a85c9de67cf
Author: Oded Gabbay <oded.gabbay at gmail.com>
Date: Thu Sep 3 19:00:26 2015 +0300
llvmpipe: convert double to long long instead of unsigned long long
round(val*dscale) produces a double result, as val and dscale are double.
However, LLVMConstInt receives unsigned long long, so there is an
implicit conversion from double to unsigned long long.
This is an undefined behavior. Therefore, we need to first explicitly
convert the round result to long long, and then let the compiler handle
conversion from that to unsigned long long.
This bug manifests itself in POWER, where all IMM values of -1 are being
converted to 0 implicitly, causing a wrong LLVM IR output.
Signed-off-by: Oded Gabbay <oded.gabbay at gmail.com>
CC: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit 3c6c4d4f298ec81fe57992790a68aaab2e573519
Author: Hans de Goede <hdegoede at redhat.com>
Date: Thu Sep 3 12:38:01 2015 +0200
nv30: Implement color resolve for msaa
Note this is not ideal. Since the sifm can only do source sizes upto
1024x1024 we end up using the blitter on nv4x, which is not that fast.
And on nv3x we end up using the cpu which is really slow.
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Hans de Goede <hdegoede at redhat.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 3329703eb116a7ad73bc694356b43e014532240b
Author: Hans de Goede <hdegoede at redhat.com>
Date: Wed Aug 12 13:39:42 2015 +0200
nv30: Fix creation of scanout buffers
Scanout buffers on nv30 must always be non-swizzled and have special
width alignment constraints.
These constrains have been taken from the xf86-video-nouveau
src/nv_accel_common.c: nouveau_allocate_surface() function.
nouveau_allocate_surface() applies these width constraints only when a
tiled attribute is set, which it sets for all surfaces allocated via
dri, and this "tiling" is not the same as swizzling, scanout surfaces
must be linear / have a uniform_pitch or only complete garbage is shown.
This commit fixes dri3 on nv30 showing a garbled display, with dri3 the
scanout buffers are allocated by mesa, rather then by the ddx, and the
wrong stride of these buffers was causing the garbled display.
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Hans de Goede <hdegoede at redhat.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 48de40ce9c45de154965490843f9e50407970c26
Author: Boyan Ding <boyan.j.ding at gmail.com>
Date: Wed Aug 26 19:52:50 2015 +0800
vc4: Initialize pack field of qreg to 0 in qir_get_temp
This avoids generation of undefined packing in qir and qpu instructions,
fixing a lot of rendering errors.
Fixes 8b36d107fdd (vc4: Pack the unorm-packing bits into a src MUL
instruction when possible.)
Cc: mesa-stable at lists.freedesktop.org
Signed-off-by: Boyan Ding <boyan.j.ding at gmail.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 099f5b3a62be1919add02a4cb887841c9f0f2fe4
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Fri Sep 4 19:02:28 2015 +0100
i965: Disallow PixelTransfer operations for tiled-memcpy TexImage/ReadPixels
The tiled memcpy fast paths perform a simple blit (with only a couple of
trivial pixel conversion routines) and do not accommodate PixelTransfer
operations. Therefore if any are set, fallback to the regular routines.
Note that PixelTransfer only applies to TexImage and ReadPixels, not to
GetTexImage.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Jason Ekstrand <jason.ekstrand at intel.com>
Cc: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Cc: mesa-stable at lists.freedesktop.org
commit 96ea1663082c4a17eaf59873190f1e9677623d91
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Fri Sep 4 13:23:20 2015 +0200
i965/vec4: Don't unspill the same register in consecutive instructions
If we have spilled/unspilled a register in the current instruction, avoid
emitting unspills for the same register in the same instruction or consecutive
instructions following the current one as long as they keep reading the spilled
register. This should allow us to avoid emitting costy unspills that come with
little benefit to register allocation.
v2:
- Apply the same logic when evaluating spilling costs (Curro).
v3:
- Abstract the logic that decides if a register can be reused in a function.
that can be used from both spill_reg and evaluate_spill_costs (Curro).
v4:
- Do not disallow reusing scratch_reg in predicated reads (Curro).
- Track if previous sources in the same instruction read scratch_reg (Curro).
- Return prev_inst_read_scratch_reg at the end (Curro).
- No need to explicitily skip scratch read/write opcodes in spill_reg (Curro).
- Fix the comments explaining what happens when we hit an instruction that
does not read or write scratch_reg (Curro)
- Return true early when the current or previous instructions read
scratch_reg with a compatible mask.
v5:
- Do not return true early, the loop should not be expensive anyway
and this adds more complexity (Curro).
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit bd6e516fc24128d604f677a16f692d88d65a49f1
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Thu Jul 23 11:11:53 2015 +0200
i965: Add a debug option for spilling everything in vec4 code
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 6cf4142db88796ff66a73a36530467101533fdb6
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Sep 3 15:20:04 2015 +0300
dri/common: Tokenize driParseDebugString() argument before matching debug flags.
Fixes debug string parsing when one of the supported flags is a
substring of another.
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 3d4f75506c9233ca4039021024c4b918cc974f86
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Sep 3 14:50:12 2015 +0300
dri/common: Fix codestyle of driParseDebugString().
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 08e9049e3d204265d803aac5ff6bf0b4e5d82d00
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Thu Sep 3 14:26:48 2015 +0300
glsl: error out on ES 3.1 if VS or FS present but not both
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 69678953d1740a5d27da4f9dd522f68d5a95d223
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Thu Sep 3 14:20:46 2015 +0300
glsl: error on linking if no shaders are attached to program
This applies to OpenGL Core >= 4.5 and OpenGL ES >= 3.1.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 4323e78d3f6d935cb75fc20375e6730613d41119
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Aug 13 14:52:55 2015 -0700
i965: Improve disassembly of data port read messages.
We now print out the name of the message instead of its numerical
value, and label the message control and surface numbers.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit 0e23c246c0eb84bd46dfdfe6babe3762e49c58d2
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri May 15 10:08:19 2015 -0700
i965: Optimize VUE map comparisons.
The entire VUE map is computed based on the slots_valid bitfield;
calling brw_compute_vue_map on the same bitfield will return the
same result. So we can simply compare those.
struct brw_vue_map is 136 bytes; doing a single 8-byte comparison is
much cheaper and should work just as well.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit 6e03377daf90c6f6ac953a08e3a8f8f5caf9abf6
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Aug 28 23:47:25 2015 -0700
i965/gs: Don't reserve space for clip plane uniforms.
These were only for legacy userclipping, which we no longer support
in geometry shaders.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit fba4823a916b63f279955dbe6d98b6efc666f53e
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Aug 28 01:43:23 2015 -0700
i965: Don't do legacy userclipping in non-compatibility contexts.
According to the GLSL 1.50 specification, page 76:
"The shader must also set all values in gl_ClipDistance that have been
enabled via the OpenGL API, or results are undefined."
With this patch, we only enable clip distance writes when the shader
actually writes them. We no longer force a value to be written when
clip planes are enabled in the API. This could mean the first varying
slot would be used as clip distances - I believe it should be the safe
kind of undefined behavior.
Empirically, it doesn't seem to cause a problem.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit 4f4b7c4711d98606270133dfd456acabfa8267a6
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Aug 27 18:24:39 2015 -0700
i965: Remove the brw_vue_prog_key base class.
The legacy userclip fields are only used for the vertex shader, and at
that point there's only program_string_id and the tex struct, which are
common to all keys. So there's no need for a "VUE" key base class.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit 323962182547aeafcdb3bac28434ef81f70eb785
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Aug 28 00:29:05 2015 -0700
i965: Virtualize vec4_visitor::emit_urb_slot().
This avoids a downcast of key, which won't exist in the base class soon.
I'm not a huge fan of this patch, but given that we're currently using
inheritance, this seems like the "right" way to do it. The alternative
is to make key a void pointer in the parent class and continue
downcasting.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit 27e83b62bb52de7a681ed82679a707555023f43d
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Aug 27 23:55:28 2015 -0700
i965: Store a key_tex pointer in vec4_visitor.
I'm about to remove the base class for VS/GS/HS/DS program keys, at
which point we won't be able to use key->tex anymore. Instead, we'll
need to store a direct pointer (like we do in the FS backend).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit 014b90221ad5cf833bfdd55b0336771d209f0f1d
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Aug 27 23:49:03 2015 -0700
i965: Move legacy clip plane handling to vec4_vs_visitor.
This is now only used for the vertex shader, so it makes sense to get it
out of any paths run by the geometry shader.
Instead of passing the gl_clip_plane array into the run() method (which
is shared among all subclasses), we add it as a vec4_vs_visitor
constructor parameter. This eliminates the bogus NULL parameter in the
GS case.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit 082b7f1876095f32578720f30fdc35771b2b3e0a
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Aug 27 17:02:27 2015 -0700
i965: Delete the brw_vue_program_key::userclip_active flag.
There are two uses of this flag.
The primary use is checking whether we need to emit code to convert
legacy gl_ClipVertex/gl_Position clipping to clip distances. In this
case, we also have to upload the clip planes as uniforms, which means
setting nr_userclip_plane_consts to a positive value. Checking if it's
> 0 works for detecting this case.
Gen4-5 also wants to know whether we're doing clipping at all, so it can
emit user clip flags. Checking if output_reg[VARYING_SLOT_CLIP_DIST0]
is set to a real register suffices for this.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit 294282aaa6a517b455d3e31d12e2d85516ac04e6
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Aug 27 14:04:40 2015 -0700
i965: Remove legacy clip plane handling from geometry shaders.
We only support geometry shaders in core profiles, where gl_ClipVertex
doesn't exist. Presumably the even older behavior of clipping to
gl_Position isn't supported either. In fact, GLSL 1.50 page 76 claims:
"The shader must also set all values in gl_ClipDistance that have been
enabled via the OpenGL API, or results are undefined."
So we don't need to handle legacy clipping in geometry shaders. I think
Paul added this back when we were considering supporting the old
GL_ARB_geometry_shader4 extension.
This removes a non-orthagonal state dependency on GS compilation.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit a2151560b8d65be31129c00872ea8d70c564b110
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Aug 27 18:27:20 2015 -0700
i965: Move brw_setup_tex_for_precompile to brw_program.[ch].
This living in brw_fs.{h,cpp} is a historical artifact of us supporting
texturing for fragment shaders before any other stages. It's kind of
awkward given that we use it for all stages.
This avoids having to include brw_fs.h in geometry shader code in order
to access this function.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit 04e201d0c02cd30ace5c6fe80e9f021ebb733682
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Mon Aug 31 09:54:23 2015 +0300
mesa: change 'SHADER_SUBST' facility to work with env variables
Patch modifies existing shader source and replace functionality to work
with environment variables rather than enable dumping on compile time.
Also instead of _mesa_str_checksum, _mesa_sha1_compute is used to avoid
collisions.
Functionality is controlled via two environment variables:
MESA_SHADER_DUMP_PATH - path where shader sources are dumped
MESA_SHADER_READ_PATH - path where replacement shaders are read
v2: cleanups, add strerror if fopen fails, put all functionality
inside HAVE_SHA1 since sha1 is required
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Suggested-by: Eero Tamminen <eero.t.tamminen at intel.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 0db323a62481a57269a46287a64fa743756e80f3
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Thu Sep 3 08:34:42 2015 +0300
build: add HAVE_SHA1 define when using --with-sha1 option
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Acked-by: Brian Paul <brianp at vmware.com>
commit 2ace64fd598816fd1be9877962734242fc27b87b
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Sep 2 16:39:27 2015 -0700
i965: Fix copy propagation type changes.
commit 472ef9a02f2e5c5d0caa2809cb736a0f4f0d4693 introduced code to
change the types of SEL and MOV instructions for moves that simply
"copy bits around". It didn't account for type conversion moves,
however. So it would happily turn this:
mov(8) vgrf6:D, -vgrf5:D
mov(8) vgrf7:F, vgrf6:UD
into this:
mov(8) vgrf6:D, -vgrf5:D
mov(8) vgrf7:D, -vgrf5:D
which erroneously drops the conversion to float.
Cc: "11.0 10.6" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 5fa5a012b163bad80d01a65e2947510f15e1be6b
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Sep 4 08:02:14 2015 +1000
r600: fix loop overrun in cayman_mul_double_instr
Coverity warned about this. Ilia pointed it out.
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit b05619c627122a0e35a18f92e457d3aefa55f2f7
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Wed Aug 26 16:35:40 2015 -0700
i965/gen9: Annotate input coverage mask change
As far as I can tell, the behavior is preserved from the previous generations.
Before we set a single bit to tell the FS whether or not we'll be using an input
coverage mask. Now we have some options which are implementing various
extensions. These bits are used for the various conservative rasterization
mechanisms (for collision detection, binning, and whatever else).
I believe that the behavior is preserved because the problem which conservative
rasterization is attempting to fix would go away with the "NORMAL" mode (at the
cost of performance, I believe).
This patch serves as documentation of the change by creating the enums, as well
as giving some of the history with the links here so that the next person who
comes along and looks at it doesn't spend as long as I had to in order to
determine if there is an issue or not.
Previously, this algorithm had been done in software, and this can still be used
as long as we don't export an extension stating otherwise.
References: https://www.opengl.org/registry/specs/NV/conservative_raster.txt
References: https://http.developer.nvidia.com/GPUGems2/gpugems2_chapter42.html
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 70dbdca15fa173302481111cdfb86881dd13dc38
Author: Brian Paul <brianp at vmware.com>
Date: Thu Sep 3 11:23:36 2015 -0600
svga: update call to u_upload_alloc()
u_upload_alloc() no longer returns a return value.
Trivial.
commit efea7c3a3f91219db6e2fa3588388b6be4ecfa40
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Sep 1 04:14:43 2015 +0200
winsys/radeon: remove exported buffers from the cache
Cc: 11.0 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
commit 54964c77510b060806615c842692c0f393e807e6
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Sep 1 04:14:33 2015 +0200
winsys/amdgpu: remove exported buffers from the cache
Cc: 11.0 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
commit 35d0f12797237cdd38e7fd2c39d3c19e875875ca
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Sep 1 04:07:54 2015 +0200
gallium/pb_bufmgr_cache: add a way to remove buffers from the cache explicitly
This must be done before exporting a buffer as dmabuf fds, because
we lose track of who is using it and can't trust the reference counter.
Cc: 11.0 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
commit 44dbaa1746833f2874786fc2067f8837f149261f
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Sep 2 15:11:40 2015 +0200
u_upload_mgr: remove the return value from u_upload_data
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 0c5df863ba27d31993f3fdc85b26407f398514fa
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Sep 2 15:11:40 2015 +0200
u_upload_mgr: remove the return value from u_upload_buffer
Reviewed-by: Brian Paul <brianp at vmware.com>
commit b4f7639955b6c74436db6dea9174a8c7ce37ec62
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Sep 2 15:11:40 2015 +0200
u_upload_mgr: remove the return value from u_upload_alloc_buffer
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 8c6ff05517137ab9d96015783fcf1bf9d8d1fa12
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Sep 2 15:08:23 2015 +0200
u_upload_mgr: remove the return value from u_upload_alloc
The return buffer or the returned pointer can be used instead.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 6c1e368cf38e02174a8c88218ae711ab0b27954f
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Sep 2 14:57:55 2015 +0200
u_upload_mgr: optimize u_upload_alloc
This is probably the most called util function. It does almost nothing,
yet it can consume 10% of the CPU on the profile. This drops it down to 5%.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 722ce747436f5b9c79d1fa4a8c59eed2f9cb611b
Author: Grazvydas Ignotas <notasas at gmail.com>
Date: Thu Sep 3 01:54:32 2015 +0300
gallium/radeon: remove 'dirty' member from r600_atom
It's no longer used by both r600 and radeonsi now.
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit ccbc7952a4c125741f412ebc0278e17b65cf6fd7
Author: Grazvydas Ignotas <notasas at gmail.com>
Date: Thu Sep 3 01:54:31 2015 +0300
r600g: simplify dirty atom tracking
Now that R600_NUM_ATOMS is below 64, dirty atom tracking can be
simplified.
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit 6ef4572937015c1e076afc12f19e8453d08babec
Author: Grazvydas Ignotas <notasas at gmail.com>
Date: Thu Sep 3 01:54:30 2015 +0300
r600g: start numbering atoms from 1
There doesn't seem any reason to start from 4.
Start from 1 instead (0 is left reserved to catch uninitialized atoms).
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit 4d9af438bc41ed20da1963a438249fee43213121
Author: Grazvydas Ignotas <notasas at gmail.com>
Date: Thu Sep 3 01:54:29 2015 +0300
r600g: make all viewport states use single atom
Similarly to scissor states, we can use single atom to track all viewport
states. This will allow to simplify dirty atom handling later.
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit fbb423b43380d0e43d14056e96846da412693148
Author: Grazvydas Ignotas <notasas at gmail.com>
Date: Thu Sep 3 01:54:28 2015 +0300
r600g: apply disable workaround on all scissors
During review of the "r600g: make all scissor states use single atom" patch
Marek Olšák noticed that scissor disable workaround should be applied on
all scissor states and not just first one, so let's do so.
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit 7d475bad66b99e171542bc9ea62abac56abfa6f2
Author: Grazvydas Ignotas <notasas at gmail.com>
Date: Thu Sep 3 01:54:27 2015 +0300
r600g: make all scissor states use single atom
As suggested by Marek Olšák, we can use single atom to track all scissor
states. This will allow to simplify dirty atom handling later.
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit ce181aea6cb5353181add7b5aca3c0b196a9b513
Author: Neil Roberts <neil at linux.intel.com>
Date: Wed Sep 2 11:29:16 2015 +0100
mesa/pbo: Handle zero width, height or depth when validating access
It's legal to call glTexSubImage with zero values for the width,
height or depth. Previously this was breaking the PBO access
validation because it tries to work out the last pixel accessed by
getting the pixel at height-1 and depth-1 which would end up with
bogus values.
This was causing GL errors to be generated during the Piglit
texsubimage test, although the test was passing anyway.
v2: Also check for width == 0. Don't validate the start pointer if any
of the dimensions are zero.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 30e84530a097278c7cf01c0491dba5866510c4c5
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Sep 3 00:55:40 2015 -0700
glsl: Remove unused total_attribs_size variable.
Accidentally left behind by my previous patch.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
commit c3294ca5a13cf3f0eb3d9907a46ff8ce4bc2963b
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Sep 2 10:42:57 2015 -0700
glsl: Handle attribute aliasing in attribute storage limit check.
In various versions of OpenGL and GLSL, it's possible to declare
multiple VS input variables with aliasing attribute locations.
So, when computing the storage requirements for vertex attributes,
we can't simply add up the sizes. Instead, we need to look at the
enabled slots.
This patch begins tracking which attributes are double types that
are larger than 128-bits (i.e. take up two vec4 slots). We then
count normal attributes once, and count the double-size attributes
a second time.
Fixes deQP functional.attribute_location.bind_aliasing.max_cond_* tests
on i965, which regressed with commit ad208d975a6d3aebe14f7c2c16039ee20.
No Piglit changes on llvmpipe (which actually supports dvecs).
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
Tested-by: Mark Janes <mark.a.janes at intel.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Dave Airlie <airlied at redhat.com>
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
commit 6e3730452152ca74ad3b51bf1dd4b69b20dbc019
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Sep 1 17:42:31 2015 -0700
i965/meta: Fix typo in comment
Trivial.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
commit 7237c937af3b495191bee2f7240901e3a9daf1fb
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Aug 31 18:44:42 2015 -0700
mesa: Don't allow wrong type setters for matrix uniforms
Previously we would allow glUniformMatrix4fv on a dmat4 and
glUniformMatrix4dv on a mat4. Both are illegal. That later also
overwrites the storage for the mat4 and causes bad things to happen.
Should fix the (new) arb_gpu_shader_fp64-wrong-type-setter piglit test.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
Cc: Dave Airlie <airlied at redhat.com>
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
commit a6976f09727014730f45ec27c714c6a8140e074a
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Aug 31 18:30:48 2015 -0700
mesa: Pass the type to _mesa_uniform_matrix as a glsl_base_type
This matches _mesa_uniform, and it enables the bug fix in the next
patch.
v2: s/type/basicType/ in the assert in _mesa_uniform_matrix.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au> [v1]
Cc: Dave Airlie <airlied at redhat.com>
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
commit 882aab00abb226c103b8c6fe514247334b4d2d04
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Aug 26 13:50:04 2015 +0100
mesa: Silence unused parameter warnings in bufferobj.c
main/bufferobj.c: In function 'count_buffer_size':
main/bufferobj.c:520:26: warning: unused parameter 'key' [-Wunused-parameter]
count_buffer_size(GLuint key, void *data, void *userData)
^
main/bufferobj.c: In function 'flush_mapped_buffer_range_fallback':
main/bufferobj.c:740:56: warning: unused parameter 'index' [-Wunused-parameter]
gl_map_buffer_index index)
^
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 8ba3b7661b4985194a01f565d2ae27db153bb12c
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Aug 26 13:55:54 2015 +0100
mesa: Remove target parameter from _mesa_handle_bind_buffer_gen
main/bufferobj.c: In function '_mesa_handle_bind_buffer_gen':
main/bufferobj.c:915:37: warning: unused parameter 'target' [-Wunused-parameter]
GLenum target,
^
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 1e4d3d25fff65b2508ae12b4b4d6b64057dabe95
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Aug 19 14:25:48 2015 -0700
i965: Make gen7_enable_hw_binding_tables static
All of the other state upload functions are static because the only use
is in the brw_tracked_state structure.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
commit 97ce8bd437a138c102fcf466d03101c0437fa6ea
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Aug 19 13:54:21 2015 -0700
i965: Make gen8_upload_state_base_address static
All of the other state upload functions are static because the only use
is in the brw_tracked_state structure.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 4ff9e599cb05d2e33e3c642ba2ded9afbe76d552
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Aug 19 13:36:22 2015 -0700
linker: Silence GCC unused parameter warnings
linker.cpp:320:55: warning: unused parameter 'ir' [-Wunused-parameter]
virtual ir_visitor_status visit_leave(ir_function *ir)
^
linker.cpp:327:53: warning: unused parameter 'ir' [-Wunused-parameter]
virtual ir_visitor_status visit_leave(ir_return *ir)
^
linker.cpp:333:49: warning: unused parameter 'ir' [-Wunused-parameter]
virtual ir_visitor_status visit_enter(ir_if *ir)
^
linker.cpp:339:49: warning: unused parameter 'ir' [-Wunused-parameter]
virtual ir_visitor_status visit_leave(ir_if *ir)
^
linker.cpp:345:51: warning: unused parameter 'ir' [-Wunused-parameter]
virtual ir_visitor_status visit_enter(ir_loop *ir)
^
linker.cpp:351:51: warning: unused parameter 'ir' [-Wunused-parameter]
virtual ir_visitor_status visit_leave(ir_loop *ir)
^
linker.cpp:2824:53: warning: unused parameter 'ctx' [-Wunused-parameter]
link_calculate_subroutine_compat(struct gl_context *ctx, struct gl_shader_program *prog)
^
linker.cpp:2854:47: warning: unused parameter 'ctx' [-Wunused-parameter]
check_subroutine_resources(struct gl_context *ctx, struct gl_shader_program *prog)
^
linker.cpp:3368:49: warning: unused parameter 'ctx' [-Wunused-parameter]
link_assign_subroutine_types(struct gl_context *ctx,
^
Also make link_assign_subroutine_types static since it is only called
from this file.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 8fafb0a67faa548cb16e122e214912a17835e369
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Aug 18 17:41:30 2015 -0700
mesa: Fix warning about static being in the wrong place
Because the compiler already has enough things to complain about.
grep -rl 'const static' src/ | while read f
do
sed --in-place -e 's/const static/static const/g' $f
done
brw_eu_emit.c: In function 'brw_reg_type_to_hw_type':
brw_eu_emit.c:98:7: warning: 'static' is not at beginning of declaration [-Wold-style-declaration]
const static int imm_hw_types[] = {
^
brw_eu_emit.c:120:7: warning: 'static' is not at beginning of declaration [-Wold-style-declaration]
const static int hw_types[] = {
^
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 06ada493fbc22e99867e14f26f1a511b343e3759
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Tue Sep 23 16:46:39 2014 -0700
i965/cs: Setup push constant data for uniforms
brw_upload_cs_push_constants was based on gen6_upload_push_constants.
v2:
* Add FINISHME comments about more efficient ways to push uniforms
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit 4bdd5e09c3a1f97840dbbfb9e9a3c74bb0143968
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Mon May 25 12:23:05 2015 -0700
meta: Save/restore compute shaders
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 4a9480b64aed6986095c391ebba6b91212fb9277
Author: Charmaine Lee <charmainel at vmware.com>
Date: Fri Aug 21 11:41:26 2015 -0700
svga: fix referencing a NULL framebuffer cbuf
Check for a valid framebuffer cbuf pointer before accessing its
associated surface.
Fix piglit test fbo-drawbuffers-none.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 5a5e5e39592292a8ffa861e6f9b21934af428b9b
Author: Charmaine Lee <charmainel at vmware.com>
Date: Fri Aug 21 10:36:24 2015 -0700
svga: increment texture age when surface is to be marked as dirty
Commit b9ba8492 removes an unneeded pipe_surface_release() from
st_render_texture(). This implies a surface can now be reused for a
render buffer. Currently, when we render to a texture, we mark the
surface as dirty. But in svga_mark_surface_dirty(), if the surface
is already marked as dirty, it does not increment the texture age.
Any view to this texture might not be updated properly then.
With this patch, the texture age is incremented regardless of whether
the surface is already marked as dirty or not.
Fix bug 1499181.
Reviewed-by: Sinclair Yeh <syeh at vmware.com>
commit b2fd41ce465e16a178d51000b843b5228640b670
Author: Charmaine Lee <charmainel at vmware.com>
Date: Thu Aug 13 15:08:22 2015 -0700
svga: fix backed surface view regression
Commit b9ba8492 removes an unneeded pipe_surface_release() from
st_render_texture() and exposes a bug in the backed surface view
creation. Currently a backed surface view for a conflicted surface view
is created at framebuffer emit time. But if shader sampler views are changed
but framebuffer surface views remain unchanged, emit_framebuffer() will not
be called and conflicted surface views will not be detected.
To fix this, also check for conflicted surface views when setting sampler
views. If there is any conflicted surface views, enable the
framebuffer dirty bit so that the framebuffer emit code has a chance to
create a backed surface view for the conflicted surface view.
Fix cinebench-r11-test regression.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 9390cb84593bda516e8c1521c87a08475574d1be
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Sep 1 22:00:24 2015 -0700
i965/fs: Handle MRF destinations in lower_integer_multiplication().
The lowered code reads from the destination, which isn't possible from
message registers.
Fixes the following dEQP tests on SNB:
dEQP-GLES3.functional.shaders.precision.int.highp_mul_fragment
dEQP-GLES3.functional.shaders.precision.int.mediump_mul_fragment
dEQP-GLES3.functional.shaders.precision.int.lowp_mul_fragment
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
Tested-by: Mark Janes <mark.a.janes at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 4fd314852cb4cfc528123145c0e4b5383fad95d4
Author: Brian Paul <brianp at vmware.com>
Date: Thu Aug 13 13:50:13 2015 -0700
docs: document VMware OpenGL 3.3 support
Signed-off-by: Brian Paul <brianp at vmware.com>
commit e054251ed11e25a080f64b92db9334c9b07c8c76
Author: Brian Paul <brianp at vmware.com>
Date: Thu Aug 13 11:00:58 2015 -0700
svga: update driver for version 10 GPU interface
This is a squash commit of roughly two years of development work.
Authors include:
Brian Paul
Charmaine Lee
Thomas Hellstrom
Jakob Bornecrantz
Sinclair Yeh
Mingcheng Chen
Kai Ninomiya
MengLin Wu
The driver supports OpenGL 3.3.
Signed-off-by: Brian Paul <brianp at vmware.com>
commit 656dac120d27e060986d97e790334f67a34a6e23
Author: Brian Paul <brianp at vmware.com>
Date: Fri Aug 7 15:41:17 2015 -0600
svga: add new version 10 device command prototypes
Signed-off-by: Brian Paul <brianp at vmware.com>
commit e8c20d97eb711babcb4f54cc1ac174eaacc0b8a0
Author: Brian Paul <brianp at vmware.com>
Date: Fri Aug 7 15:23:51 2015 -0600
svga: add new svga_streamout.h file
Signed-off-by: Brian Paul <brianp at vmware.com>
commit 8ddf98d671f39df9c97e66f7bbe9d00aefc8707a
Author: Brian Paul <brianp at vmware.com>
Date: Fri Aug 7 16:04:03 2015 -0600
svga: add new svga_state_tgsi_transform.c file
Signed-off-by: Brian Paul <brianp at vmware.com>
commit 26d8bae88908b490a37b6ba39b88f44945bb5613
Author: Brian Paul <brianp at vmware.com>
Date: Fri Aug 7 15:22:18 2015 -0600
svga: add new svga_state_sampler.c file
Signed-off-by: Brian Paul <brianp at vmware.com>
commit a633948e7ea2445ff88c469edf47c44cfec8d962
Author: Brian Paul <brianp at vmware.com>
Date: Fri Aug 7 15:22:01 2015 -0600
svga: add new svga_state_gs.c file
Signed-off-by: Brian Paul <brianp at vmware.com>
commit ff85bcdba21ccf88f1a359f2055847e2c820e85f
Author: Brian Paul <brianp at vmware.com>
Date: Fri Aug 7 15:21:46 2015 -0600
svga: add new svga_pipe_streamout.c file
Signed-off-by: Brian Paul <brianp at vmware.com>
commit 7ce20cf59a1171c4fa2e17a6c0c2f7e24b1150d2
Author: Brian Paul <brianp at vmware.com>
Date: Fri Aug 7 15:21:29 2015 -0600
svga: add new svga_pipe_gs.c file
Signed-off-by: Brian Paul <brianp at vmware.com>
commit 9cb2d9ddfacfcf7fe3f91942d0ad147ccafd29cf
Author: Brian Paul <brianp at vmware.com>
Date: Fri Aug 7 15:21:10 2015 -0600
svga: add new svga_link.[ch] files
Signed-off-by: Brian Paul <brianp at vmware.com>
commit 53d07910c3a3be496f5c789b708a82d2022ecd5b
Author: Brian Paul <brianp at vmware.com>
Date: Fri Aug 7 14:57:22 2015 -0600
svga: add new svga_cmd_vgpu10.c file
Signed-off-by: Brian Paul <brianp at vmware.com>
commit 35bb29d4994efadd1719a147731afa34e78a0be1
Author: Brian Paul <brianp at vmware.com>
Date: Fri Aug 7 14:56:51 2015 -0600
svga: add new svga_tgsi_vgpu10.c file
Signed-off-by: Brian Paul <brianp at vmware.com>
commit 1c5468e9c0b2f6c832051de0070c8ef49a0c9fd2
Author: Brian Paul <brianp at vmware.com>
Date: Fri Aug 7 16:11:14 2015 -0600
svga: remove unused SVGA3D_* command functions
Signed-off-by: Brian Paul <brianp at vmware.com>
commit 133a47107cc03a69b4b88c1fef331d507f521fa7
Author: Brian Paul <brianp at vmware.com>
Date: Fri Aug 7 14:54:24 2015 -0600
gallium/st: add pipe_context::get_timestamp()
The VMware svga driver doesn't directly support pipe_screen::get_timestamp()
but we can do a work-around. However, we need a gallium context to do so.
This patch adds a new pipe_context::get_timestamp() function that will only
be called if the pipe_screen::get_timestamp() function is NULL.
Signed-off-by: Brian Paul <brianp at vmware.com>
commit e2a1d21cb665b7e7bc2c9684cf533003cdc817b3
Author: Brian Paul <brianp at vmware.com>
Date: Thu Aug 6 16:44:35 2015 -0600
svga/winsys: Add support for VGPU10
This involves a few driver modifications to keep things building.
The driver may not actually run properly at this point.
Signed-off-by: Brian Paul <brianp at vmware.com>
commit c191b507cbbc4572c9a58cf019db08def651b265
Author: Brian Paul <brianp at vmware.com>
Date: Thu Aug 6 16:28:19 2015 -0600
svga: update the svga3d device header files
Remove some obsolete svga_dump.c code for items which no longer exist.
Signed-off-by: Brian Paul <brianp at vmware.com>
commit 3a9252670450b80e333fadeb7c85367ab15a273e
Author: Brian Paul <brianp at vmware.com>
Date: Fri Aug 7 14:56:03 2015 -0600
svga: add new version 10 device header files
Signed-off-by: Brian Paul <brianp at vmware.com>
commit 75f92e28b40ced21fb92df6e00277733bbca7f07
Author: Brian Paul <brianp at vmware.com>
Date: Wed Jul 29 11:23:29 2015 -0600
winsys/svga: add new vmw_query.c[h] files
Functions for creating, destroying, getting queries, etc.
Signed-off-by: Brian Paul <brianp at vmware.com>
commit f30cf3258e495a583e011e07d5b4a19031c5518f
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Tue Sep 1 09:31:15 2015 +0100
meta: Compute correct buffer size with SkipRows/SkipPixels
If the user is specifying a subregion of a buffer using SKIP_ROWS and
SKIP_PIXELS, we must compute the buffer size carefully as the end of the
last row may be much shorter than stride*image_height*depth. The current
code tries to memcpy from beyond the end of the user data, for example
causing:
==28136== Invalid read of size 8
==28136== at 0x4C2D94E: memcpy@@GLIBC_2.14 (vg_replace_strmem.c:915)
==28136== by 0xB4ADFE3: brw_bo_write (brw_batch.c:1856)
==28136== by 0xB5B3531: brw_buffer_data (intel_buffer_objects.c:208)
==28136== by 0xB0F6275: _mesa_buffer_data (bufferobj.c:1600)
==28136== by 0xB0F6346: _mesa_BufferData (bufferobj.c:1631)
==28136== by 0xB37A1EE: create_texture_for_pbo (meta_tex_subimage.c:103)
==28136== by 0xB37A467: _mesa_meta_pbo_TexSubImage (meta_tex_subimage.c:176)
==28136== by 0xB5C8D61: intelTexSubImage (intel_tex_subimage.c:195)
==28136== by 0xB254AB4: _mesa_texture_sub_image (teximage.c:3654)
==28136== by 0xB254C9F: texsubimage (teximage.c:3712)
==28136== by 0xB2550E9: _mesa_TexSubImage2D (teximage.c:3853)
==28136== by 0x401CA0: UploadTexSubImage2D (teximage.c:171)
==28136== Address 0xd8bfbe0 is 0 bytes after a block of size 1,024 alloc'd
==28136== at 0x4C28C20: malloc (vg_replace_malloc.c:296)
==28136== by 0x402014: PerfDraw (teximage.c:270)
==28136== by 0x402648: Draw (glmain.c:182)
==28136== by 0x8385E63: ??? (in /usr/lib/x86_64-linux-gnu/libglut.so.3.9.0)
==28136== by 0x83896C8: fgEnumWindows (in /usr/lib/x86_64-linux-gnu/libglut.so.3.9.0)
==28136== by 0x838641C: glutMainLoopEvent (in /usr/lib/x86_64-linux-gnu/libglut.so.3.9.0)
==28136== by 0x8386C1C: glutMainLoop (in /usr/lib/x86_64-linux-gnu/libglut.so.3.9.0)
==28136== by 0x4019C1: main (glmain.c:262)
==28136==
==28136== Invalid read of size 8
==28136== at 0x4C2D940: memcpy@@GLIBC_2.14 (vg_replace_strmem.c:915)
==28136== by 0xB4ADFE3: brw_bo_write (brw_batch.c:1856)
==28136== by 0xB5B3531: brw_buffer_data (intel_buffer_objects.c:208)
==28136== by 0xB0F6275: _mesa_buffer_data (bufferobj.c:1600)
==28136== by 0xB0F6346: _mesa_BufferData (bufferobj.c:1631)
==28136== by 0xB37A1EE: create_texture_for_pbo (meta_tex_subimage.c:103)
==28136== by 0xB37A467: _mesa_meta_pbo_TexSubImage (meta_tex_subimage.c:176)
==28136== by 0xB5C8D61: intelTexSubImage (intel_tex_subimage.c:195)
==28136== by 0xB254AB4: _mesa_texture_sub_image (teximage.c:3654)
==28136== by 0xB254C9F: texsubimage (teximage.c:3712)
==28136== by 0xB2550E9: _mesa_TexSubImage2D (teximage.c:3853)
==28136== by 0x401CA0: UploadTexSubImage2D (teximage.c:171)
==28136== Address 0xd8bfbe8 is 8 bytes after a block of size 1,024 alloc'd
==28136== at 0x4C28C20: malloc (vg_replace_malloc.c:296)
==28136== by 0x402014: PerfDraw (teximage.c:270)
==28136== by 0x402648: Draw (glmain.c:182)
==28136== by 0x8385E63: ??? (in /usr/lib/x86_64-linux-gnu/libglut.so.3.9.0)
==28136== by 0x83896C8: fgEnumWindows (in /usr/lib/x86_64-linux-gnu/libglut.so.3.9.0)
==28136== by 0x838641C: glutMainLoopEvent (in /usr/lib/x86_64-linux-gnu/libglut.so.3.9.0)
==28136== by 0x8386C1C: glutMainLoop (in /usr/lib/x86_64-linux-gnu/libglut.so.3.9.0)
==28136== by 0x4019C1: main (glmain.c:262)
==28136==
Fixes regression from commit 7f396189f073d626c5f7a2c232dac92b65f5a23f
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Jan 5 18:17:04 2015 -0800
meta: Add a BlitFramebuffers-based implementation of TexSubImage
v2: However, the teximage we create does need to be width x full_height x 1
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Jason Ekstrand <jason.ekstrand at intel.com>
Cc: Neil Roberts <neil at linux.intel.com>
Reviewed-by Neil Roberts <neil at linux.intel.com>
commit 4de86e1371b0d59a5b9a787b726be3d373024647
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Tue Sep 1 17:02:20 2015 +0200
i965/vec4: fill src_reg type using the constructor type parameter
The src_reg constructor that received the glsl_type was using it
only to build the swizzle, but not to fill this->type as dst_reg
is doing.
This caused some type mismatch between movs and alu operations
on the NIR path, so copy propagation optimization was not applied
to remove unneeded movs if negate modifier was involved. This was
first detected on minus (negate+add) operations.
Shader DB results (taking into account only vec4):
total instructions in shared programs: 20019 -> 19934 (-0.42%)
instructions in affected programs: 2918 -> 2833 (-2.91%)
helped: 79
HURT: 0
GAINED: 0
LOST: 0
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit d2cab815b451d2ddc29cb332f96e79cdec25443d
Author: Glenn Kennard <glenn.kennard at gmail.com>
Date: Wed Aug 12 10:27:39 2015 +1000
r600g: Add doubles support for CYPRESS
This doesn't enable the support, just adds some of
the code, so we don't have to keep rebasing.
Signed-off-by: Glenn Kennard <glenn.kennard at gmail.com>
Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 3be5ee1574e0a3494c0550f4b7ae09117855d749
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Feb 20 10:47:15 2015 +1000
r600g: add doubles support for CAYMAN
Only a subset of AMD GPUs supported by r600g support doubles,
CAYMAN and CYPRESS are probably all we'll try and support, however
I don't have a CYPRESS so ignore that for now.
This disables SB support for doubles, as we think we need to
make the scheduler smarter to introduce delay slots.
[airlied: pushing this to avoid pain of rebasing, it mostly
works on cayman only so far, Glenn has some ideas about
delay slot issues we need to look into. turned off by
default for now]
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit ee67fd70c22c6389fd90886ef3ddf5bf6601b3a0
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Feb 20 10:40:46 2015 +1000
tgsi/scan: add uses_doubles to tgsi scanner
This allows drivers to work out if a shader contains any
double opcodes easily.
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 3bfa345c1eb3b0ec008d29fc0c62fe941412e4c6
Author: Glenn Kennard <glenn.kennard at gmail.com>
Date: Thu Jul 9 16:37:28 2015 +1000
r600g: add multiple stream support for geom shaders
This patch is taken from work by Glenn and myself,
and I've spent some time making it all work here.
This adds support for the multiple streams part of
ARB_gpu_shader5 to r600g.
It doesn't enable ARB_gpu_shader5 yet.
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 3d497e0d915df8b71cd845c2cfbc6703db313628
Author: Dave Airlie <airlied at redhat.com>
Date: Thu Jul 9 16:36:16 2015 +1000
r600g/sb: add support for multiple streams to SB backend
This adds a peephole and removes an assert that isn't
actually valid with some of the stream emit instructions.
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit d503bbbf3082b5b301019721466d6fd2b41da03a
Author: Dave Airlie <airlied at redhat.com>
Date: Thu Jul 9 16:30:26 2015 +1000
r600g: add support for streams to the assembler.
This just adds support to the assembler dumper and allows
stream instructions to be generated. Also fix up the stream
debugging to add stream info.
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 90ac5fb6bb8b663f722b5bc3fed1c10e27b8c050
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Aug 25 11:18:48 2015 +1000
r600g/sb: dump sampler/resource index modes for textures.
This just aids debugging.
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 32769ac016dee4ce5767a922f91de47df4ce984d
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Sep 1 15:57:02 2015 +1000
mesa/readpixels: check strides are equal before skipping conversion
The CTS packed_pixels test checks that readpixels doesn't write
into the space between rows, however we fail that here unless
we check the format and stride match.
This fixes all the core mesa problems with CTS packed_pixels
tests.
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit b4a70401f52e5d7e08c94715b250ea1de8f63d15
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Sep 1 15:44:46 2015 +1000
texcompress_s3tc/fxt1: fix stride checks (v1.1)
The fastpath currently checks the RowLength != width, but
if you have a RowLength of 7, and Alignment of 4, then
that shouldn't match.
align the rowlength to the pack alignment before comparing.
This fixes compressed cases in CTS packed_pixels_pixelstore
test when SKIP_PIXELS is enabled, which causes row length
to get set.
v1.1: add fxt1 fix (Iago)
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 6a3e1fb958778e00e8fe2d860b6327fc4409c148
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Sep 1 15:13:45 2015 +1000
st/readpixels: fix accel path for skipimages.
We don't need to use the 3d image address here as that will
include SKIP_IMAGES, and we are only blitting a single
2D anyways, so just use the 2D path.
This fixes some memory overruns under CTS
packed_pixels.packed_pixels_pixelstore when PACK_SKIP_IMAGES
is used.
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit c3c242070e868225a81e1afe5fb424c33eb94c2f
Author: Dave Airlie <airlied at redhat.com>
Date: Thu Jul 30 02:48:37 2015 +0100
mesa/formats: 8-bit channel integer formats addition
Add enough 8-bit channel formats to handle all the
different things CTS throws at us.
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp at vmware.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 8185a02316cfb7dc3d64b8772af82ad2bb49754e
Author: Dave Airlie <airlied at redhat.com>
Date: Thu Jul 30 02:48:36 2015 +0100
mesa/formats: add some formats from GL3.3
GL3.3 added GL_ARB_texture_rgb10_a2ui, which specifies
a lot more things than just rgb10/a2ui.
While playing with ogl conform one of the tests must
attempted all valid formats for GL3.3 and hits the
unreachable here.
This adds the first chunk of formats that hit the
assert.
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp at vmware.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 5b6c7da460b8f6c908df7060ec0709a9848ce160
Author: Dave Airlie <airlied at gmail.com>
Date: Tue Aug 25 21:13:13 2015 +1000
mesa: handle SwapBytes in compressed texture get code.
This case just wasn't handled, so add support for it.
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp at vmware.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 0ad3a475ef81dad3baf607d749b91dfa1700ca23
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Aug 25 14:36:01 2015 +1000
mesa: fix SwapBytes handling in numerous places
In a number of places the SwapBytes handling didn't handle cases with
GL_(UN)PACK_ALIGNMENT set and 7 byte width cases aligned to 8 bytes.
This adds a common routine to swap bytes a 2D image and uses this
code in:
texture storage
texture get
readpixels
swrast drawpixels.
[airlied: updated with Brian's nitpicks].
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp at vmware.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 60aea3011525de8bf6506e08c913cbe24cc17767
Author: José Fonseca <jfonseca at vmware.com>
Date: Tue Sep 1 16:29:17 2015 -0600
auxiliary/os: Don't implement os_get_option() on embedded builds.
Let it be defined externally instead, allowing setting mechanisms other
than environment variables.
Reviewed-by: Zack Rusin <zackr at vmware.com>
Reviewed-by: Matthew McClure <mcclurem at vmware.com>
commit 84e71ef2ee4ab4a781aa86a7239036257e5992ce
Author: Brian Paul <brianp at vmware.com>
Date: Tue Sep 1 16:29:17 2015 -0600
util: add a couple primitive restart helper functions
The first function translates prim restart indexes to be 0xffff or
0xffffffff.
The second splits indexed primitives with restart indexes into sub-
primitives without restart indexes.
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit 14f35194d89901a04cb2180a788f90e1bedf5399
Author: Charmaine Lee <charmainel at vmware.com>
Date: Tue Sep 1 16:29:17 2015 -0600
tgsi: add tgsi utility to transform a fragment shader to support aa point
This adds a tgsi utility tgsi_add_aa_point to transform a fragment shader
to support anti-aliased wide point by computing the fragment distance from
the point center. This utility assumes the geometry shader is emitting
an extra generic output with point coord data. The semantic index of
this generic output is passed to the tgsi_add_aa_point utility.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit bca238d4f55dd0a9325132c73b1acade51017ba3
Author: Charmaine Lee <charmainel at vmware.com>
Date: Tue Sep 1 16:29:17 2015 -0600
tgsi: adds tgsi utility to transform a shader to support point sprite
This adds a tgsi utility tgsi_add_point_sprite to transform a geometry
shader to emulate wide points by drawing quads. This utility adds an
extra output for the original point position if the point position is
to be written to a stream output buffer. It also assumes the driver will
add a constant for inverse viewport scale after the user defined constants.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit a65bdf5f47689b52ec97181ec870b089872b508e
Author: Brian Paul <brianp at vmware.com>
Date: Tue Sep 1 16:29:17 2015 -0600
tgsi: add new tgsi_two_side.c utility code
This could be used by any driver where the device doesn't directly
support two-sided lighting. This code modifies a fragment shader
to accecpt back-face colors and choose between the front/back colors
depending on the triangle's front-face sign.
commit da33c2434b1dc4ca24a131a9625166278333b7d3
Author: Brian Paul <brianp at vmware.com>
Date: Tue Sep 1 16:29:17 2015 -0600
util: add util_strcasecmp() wrapper
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 0c4b6215909f140305dfa65ca6b58e8119e229b8
Author: Charmaine Lee <charmainel at vmware.com>
Date: Tue Sep 1 16:29:17 2015 -0600
gallium/util: add a utility to create geometry passthrough shader
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 17542086174ed1c2ea47f3b9b5917ce478442819
Author: Roland Scheidegger <sroland at vmware.com>
Date: Tue Sep 1 16:29:17 2015 -0600
gallium/util: fix returning empty box for rectangle intersection
These functions deal with inclusive coordinates, hence a 0/0/0/0 rect
returned when there's no intersection doesn't actually represent an empty
rectangle. Hence return 0/-1/0/-1 instead.
This fixes some problems in llvmpipe with empty scissor rects (which up
to now didn't really matter because while the intersect test returned the
wrong result all pixels were scissored away later anyway).
commit fec4f5de67b22a7048266fb7e57f49fe6fc3744a
Author: Roland Scheidegger <sroland at vmware.com>
Date: Tue Sep 1 16:29:17 2015 -0600
gallium/util: return FALSE for intersection if there's empty rectangles
It isn't really obvious if intersection test should take into account empty
rectangles or if the caller should do it. But it looks like most callers
actually verified one of the rects but not the other, but since correctly
returning an empty rect that other rect could actually be empty leading to
more bugs. Hence just verify both rects for emptyness in the intersection
test itself which makes the code easier in the caller (though it will be
slower if the caller knows the rectangles are non-empty).
Reviewed-by: Zack Rusin <zackr at vmware.com>
commit 17756876378137003443f9eebb51002564b2ac2a
Author: Charmaine Lee <charmainel at vmware.com>
Date: Tue Sep 1 16:29:17 2015 -0600
tgsi: add some more helper functions
This patch adds some more helper functions such as
. tgsi_transform_temps_decl
. tgsi_transform_output_decl
. tgsi_transform_dst_reg
. tgsi_transform_src_reg
Reviewed-by: Brian Paul <brianp at vmware.com>
commit f8da1e14599d96ced92a548d56e9110a8a54e772
Author: Brian Paul <brianp at vmware.com>
Date: Tue Sep 1 16:29:17 2015 -0600
tgsi: added tgsi_is_shadow_target() helper
commit bd883c90708207c6848b7f7b263ce1ef4e6a475b
Author: Brian Paul <brianp at vmware.com>
Date: Tue Sep 1 16:29:17 2015 -0600
tgsi: add negate parameter to tgsi_transform_kill_inst()
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
commit 56852e925e262c9a10454ed59a42ce12fb9c801c
Author: Brian Paul <brianp at vmware.com>
Date: Tue Sep 1 16:29:17 2015 -0600
util: added ffsll() function
v2: fix errant _GNU_SOURCE test, per Matt Turner.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 84dad65088147fa8c177c3e6aea20c8ae0868fde
Author: Brian Paul <brianp at vmware.com>
Date: Tue Sep 1 16:29:17 2015 -0600
util: added util_set_index_buffer()
Like util_set_vertex_buffers_count(), this basically just copies a
pipe_index_buffer object, taking care of refcounting.
commit 47b4efc710defee5a2bf81ad7c7626eee4e9aba5
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Aug 31 14:55:49 2015 -0700
mesa: Move gl_vert_attrib from mtypes.h to shader_enums.h
It is a shader enum after all...
Acked-by: Brian Paul <brianp at vmware.com>
commit e34834f059c68fc8cc6fc941bbde6d7a460595a7
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu Sep 25 17:28:20 2014 -0700
glapi: Inline x86_64_current_tls().
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit d351bab9c52e96026b2d49cdfd0dc68fdd9a499e
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date: Tue Sep 1 18:38:34 2015 +1000
r600g: Simplify out a couple of unnecessary branches
Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
commit 2d8f7d3c153bf73fa7137b89e194d4e0e79d943d
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Aug 30 18:46:06 2015 +0200
radeonsi: use an indirect buffer for init_config
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
commit df12ddb55dc5c3d1887e7742bb9e2d4d4011f3fd
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Aug 30 18:39:19 2015 +0200
radeonsi: add IB2 indirect buffer support for pm4 states
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
commit 8a9ab86ca6d510763bfe8532071c5fcfd977e3c4
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Aug 30 17:41:23 2015 +0200
winsys/radeon: add a flag telling how gfx IBs should be padded
This is always false on amdgpu (set by calloc).
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
commit ba79ff7fa8c202ea9c55c0764118be481beb8a83
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Aug 30 17:39:03 2015 +0200
winsys/amdgpu: remove IB padding for SI
SI is unsupported by amdgpu
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
commit 0f4688fbe7237c4bc5b9849e90452a9731cd3748
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Aug 30 14:43:59 2015 +0200
radeonsi: remove unused macro si_pm4_set_state
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
commit b89fa63d45cc5c8b3eec0d38ba30c57a5ecf5565
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Aug 30 14:39:54 2015 +0200
radeonsi: remove si_pm4_cleanup
All remaining pm4 state are created and destroyed by state trackers.
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
commit a9971e85d9a4038645bdc7496d73906fc324b805
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Aug 30 14:13:10 2015 +0200
radeonsi: rework uploading border colors
The border colors are uploaded only once when the state is created.
This brings truly immutable sampler descriptors, because they don't have
to be updated every time a sampler state is re-bound.
It also moves the TA_BC_BASE_ADDR registers to init_config, removing one
more state. The catch is there is now a limit: only 4096 border colors can
be used by one context. I don't think that will be a problem.
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
commit 5e2619ef3078fe4f9c3e0780ee520fbfb727ee54
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Aug 30 13:17:15 2015 +0200
radeonsi: use all built-in border colors
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
commit fbbebeae10f85e6fe9b81cf4187b8eb8ecba6da5
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Aug 30 12:39:45 2015 +0200
radeonsi: inline si_cmd_context_control
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
commit 77f80a20be9bbd8a51885e2e946106b45abf198a
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Aug 30 12:35:02 2015 +0200
radeonsi: remove unused si_pm4_state code
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
commit 228e80123ad7e9006c56f688ea065a0ec525bf33
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Aug 30 12:25:03 2015 +0200
radeonsi: reorder si_context variables
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
commit 28b34b474e330be881d15a34859811e9f5e36eb5
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Aug 30 03:56:13 2015 +0200
radeonsi: don't send IB dword usage to si_need_cs_space
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
commit aad43f0768edc0711d5f54ea79b052fb4f1d3321
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Aug 30 03:53:39 2015 +0200
radeonsi: don't set number of IB dwords for states
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
commit ec9d5e181e3ae30e00abed64762945beda6d3c0e
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Aug 30 03:49:15 2015 +0200
radeonsi: don't count IB space for states, just use an upper bound
Since we don't put any resource descriptors in IBs, the space used by draw
calls is quite small.
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
commit fc95058add3d7a90220548e0bb5679d97264f3d2
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Aug 30 03:17:30 2015 +0200
radeonsi: convert SPI state to an atom
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
commit 7ff2991e344130c8eb6e4be0b146320b3f02c1e6
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Aug 30 02:04:37 2015 +0200
gallium/radeon: rename r600_context_bo_reloc -> radeon_add_to_buffer_list
this name should be easy to understand without other knowledge
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
commit d2e63ac042ce4b0ff7d4645fc9bc8d2d73967b7e
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Aug 30 01:54:00 2015 +0200
gallium/radeon: rename write_*_reg functions
e.g. radeon_set_context_reg is nicer and looks consistent next to
radeon_emit().
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
commit 0da159ecacbc2dc89e7866679912fdc3e73e20a1
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Aug 30 01:35:03 2015 +0200
radeonsi: rename and precalculate polygon offset states
one less calloc and state construction while drawing
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
commit 45e549fcbc8c2454e242155f0cf4c21360f0b958
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Aug 30 00:50:42 2015 +0200
radeonsi: convert CB_TARGET_MASK setup to an atom
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
commit 8a67e78bb8f66a5a142222fdb4d193da1a03ed22
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Aug 30 00:16:01 2015 +0200
radeonsi: don't set VGT_VTX_CNT_EN twice in init_config
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
commit e21418f221f645397847c867b5f368ad0753e6fe
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Aug 29 17:00:11 2015 +0200
radeonsi: convert stencil ref state into an atom
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
commit c44de3097925e0d7b4f310432448a62a681189d5
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Aug 29 15:05:53 2015 +0200
radeonsi: convert blend color state into an atom
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
commit 74aa64876b54bc2d0088bc9ed2d390eaa2b73349
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Aug 29 15:05:53 2015 +0200
radeonsi: convert sample mask state into an atom
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
commit 12b205341acd2d95887099e14a217902fe21a476
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Aug 29 14:54:58 2015 +0200
radeonsi: convert clip state into an atom
Reducing calloc overhead.
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
commit 0c2eed0edec877584c9362bd9cb9004ff10a8b91
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Aug 29 02:32:13 2015 +0200
radeonsi: avoid redundant CB and DB register updates
The main idea is to avoid setting CB_COLORi_INFO = 0 for i>0 repeatedly
when those colorbuffers aren't used. This is mainly for glamor.
Same for DB. Z_INFO and STENCIL_INFO need to be cleared only once.
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
commit c2a42d1f9ff104c562822d7ab2cbaa361666266b
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Aug 29 02:02:29 2015 +0200
radeonsi: don't rebind GSVS ring buffers every draw call using GS
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
commit c9a3196b14500bcd4330f9e7ba945474440a07f2
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Aug 29 01:56:27 2015 +0200
radeonsi: don't clear the tessellation factor ring buffer
Leftover from the bring-up.
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
commit a2c6ae07b443396b43493155c2418de9a5ee9591
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Aug 29 01:45:28 2015 +0200
radeonsi: remove the tf_ring state, add the registers to init_config
One less state to worry about.
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
commit 0d46c3bc9d09b376d74f7399e1a2d1b0a923640b
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Aug 29 01:45:28 2015 +0200
radeonsi: remove the gs_rings state, add the registers to init_config
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
commit 87c1e9e19c6baa8c6fb03b0894c72744a07cde63
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Aug 29 00:49:40 2015 +0200
radeonsi: use a bitmask for tracking dirty atoms
This mainly removes the cache misses when checking the dirty flags.
Not much else though.
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
commit 2fe040ee61d3c08e8d38c3552ad4e7b5060074a1
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Aug 29 00:03:02 2015 +0200
radeonsi: initialize atom IDs for external atoms
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
commit 5bb0ad7ccc74e3aa69a1d55d2f7935587288312c
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Aug 28 23:52:47 2015 +0200
radeonsi: call si_init_atom for remaining radeonsi atoms
I need to initialize more atom IDs.
This adds 4 more si_init_atom calls, which simplifies the code.
(si_init_atom needs a different context type of the emit functions though)
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
commit e191c58324ebd5c37223a5a2c16701d236bd9cb4
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Aug 28 23:26:50 2015 +0200
radeonsi: initialize atom IDs
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
commit ba7a6cf6264dbb747f5b897d09bf1b98b232c1d0
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Aug 28 21:59:22 2015 +0200
radeonsi: define the state atom array separately
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
commit 8a97528b3a97a430a887e9044b938b349585f4ab
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Aug 28 21:48:37 2015 +0200
radeonsi: optimize viewport states
same as scissors
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
commit f6a10f60b75821c20ce7cf338b519b92ed0330fc
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Aug 28 21:08:49 2015 +0200
radeonsi: optimize scissor states
- convert 16 states to 1 atom
- only emit 1 scissor if VIEWPORT_INDEX isn't written
- use only one packet when emitting consecutive scissors
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
commit 02c8e06497c14bed37dc1780585348bb2675cab6
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Aug 28 22:33:02 2015 +0200
radeonsi: add SI_MAX_ATTRIBS
PIPE_MAX_ATTRIBS is 32, but we currently only support 16.
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
commit 05af645a951fd985d0dbe3c22614e1dee8dfb3f0
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Aug 30 03:44:03 2015 +0200
radeonsi: fix memory usage checking for big IBs
Cc: 11.0 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
commit 08775a219628611989ab87c621255ac3c841dcda
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Aug 30 00:12:03 2015 +0200
radeonsi: set all 16 viewport Z bounds for GL 4.1
Cc: 11.0 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
commit 9b510a9652297a63677f1d55b2bf444694fd94e1
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Aug 29 22:59:23 2015 +0200
radeonsi: fix a Unigine Heaven hang when drirc is missing
Cc: 10.6 11.0 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
commit b1e54512117e0269095273514e5ab70b697a41f4
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Aug 30 11:59:23 2015 +0200
winsys/amdgpu: use small IBs for better performance on VI
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
commit fc292b5821ca2d21cf5ebc83994138b87085d878
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Aug 28 20:53:08 2015 +0200
gallium/util: add u_bit_scan_consecutive_range
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
commit d38a5601068ae1d923efece8f28757777f4474e4
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Sat Jun 6 09:33:33 2015 +0100
i965: Prevent coordinate overflow in intel_emit_linear_blit
Fixes regression from
commit 8c17d53823c77ac1c56b0548e4e54f69a33285f1
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Apr 15 03:04:33 2015 -0700
i965: Make intel_emit_linear_blit handle Gen8+ alignment restrictions.
which adjusted the coordinates to be relative to the nearest cacheline.
However, this then offsets the coordinates by up to 63 and this may then
cause them to overflow the BLT limits. For the well aligned large
transfer case, we can use 32bpp pixels and so reduce the coordinates by
4 (versus the current 8bpp pixels). We also have to be more careful
doing the last line just in case it may exceed the coordinate limit.
Reported-and-tested-by: kaillasse91 at hotmail.fr
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90734
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth at whitecape.org>
Cc: Ian Romanick <ian.d.romanick at intel.com>
Cc: Anuj Phogat <anuj.phogat at gmail.com>
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 1484d8c9aa2e7e78462ffb5c207394bef77af89b
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Fri May 1 02:51:12 2015 -0400
i965/nir: enable the dead control flow optimization
total instructions in shared programs: 7541551 -> 7541381 (-0.00%)
instructions in affected programs: 3054 -> 2884 (-5.57%)
helped: 29
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit aec6744501be06e37dbcb620eba0deef54fcad31
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Fri May 8 14:42:14 2015 -0400
nir/dead_cf: add support for removing useless loops
v2: fix detecting if the loop has any phi nodes after it.
v2: use nir_foreach_ssa_def() instead of nir_foreach_dest() when
checking for values live after the loop to catch const_load
instructions.
v2: fix handling return instructions
v2: add some documentation to loop_is_dead()
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 019eea1c4fadaa86ce88ab81ac2f14613381738b
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Fri May 8 14:40:58 2015 -0400
nir: add a helper for iterating over blocks in a cf node
We were already doing this internally for iterating over a function
implementation, so just expose it directly.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 89dc0626bd71343312049bdca291704cb2f7fffe
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Fri May 8 13:17:10 2015 -0400
nir: add nir_block_get_following_loop() helper
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit f649afc9ddabfc70a5f9861e6daa2cb996461f45
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Fri May 8 01:44:24 2015 -0400
nir/dead_cf: delete code that's unreachable due to jumps
v2: use nir_cf_node_remove_after().
v2: use foreach_list_typed() instead of hardcoding a list walk.
v3: update to new control flow modification helpers.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 1e6ad4b0270fa524e7a6374e1b15540e02668019
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Fri May 1 02:38:17 2015 -0400
nir: add an optimization for removing dead control flow
v2: use nir_cf_node_remove_after() instead of our own broken thing.
v3: use the new control flow modification helpers.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 0de53ccc8cbee0f63ba25c9e72664b3cbd31be54
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Sep 1 12:29:58 2015 +1000
r600g: fix calculation for gpr allocation
I've been chasing a geom shader hang on rv635 since I wrote
r600 geom code, and finally I hacked some values from fglrx
in and I could run texelfetch without failures.
This is totally my fault as well, maths fail 101.
This makes geom shaders on r600 not fail heavily.
Cc: "10.6" "11.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit f8a938814e8cdbf65153c277f257df8e22fae9c5
Author: Marta Lofstedt <marta.lofstedt at intel.com>
Date: Mon Aug 24 13:01:53 2015 +0200
mesa: Limit Framebuffer Parameter OpenGL ES 3.1 usage
According to OpenGL ES 3.1 specification, section 9.2.1 for
glFramebufferParameter and section 9.2.3 for glGetFramebufferParameteriv:
"An INVALID_ENUM error is generated if pname is not FRAMEBUFFER_DEFAULT_WIDTH,
FRAMEBUFFER_DEFAULT_HEIGHT, FRAMEBUFFER_DEFAULT_SAMPLES, or
FRAMEBUFFER_DEFAULT_FIXED_SAMPLE_LOCATIONS."
Therefore exclude OpenGL ES 3.1 from using the GL_FRAMEBUFFER_DEFAULT_LAYERS
parameter.
Signed-off-by: Marta Lofstedt <marta.lofstedt at intel.com>
Reviewed-by: Kevin Rogovin <kevin.rogovin at intel.com>
commit d770e2746c0b63e47dfd4ab1733ab304dd7222da
Author: Marta Lofstedt <marta.lofstedt at intel.com>
Date: Tue Sep 1 08:19:11 2015 +0300
mesa: Expose GL_ARB_framebuffer_no_attachments to GLES 3.1
V2: Conform to new standard for exposing enums for OpenGL ES 3.1.
Signed-off-by: Marta Lofstedt <marta.lofstedt at intel.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit e16531fbe3a79bc27cf00701616a260b452597ef
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Aug 31 16:54:02 2015 -0700
nir/builder: Use nir_after_instr to advance the cursor
This *should* ensure that the cursor gets properly advanced in all cases.
We had a problem before where, if the cursor was created using
nir_after_cf_node on a non-block cf_node, that would call nir_before_block
on the block following the cf node. Instructions would then get inserted
in backwards order at the top of the block which is not at all what you
would expect from nir_after_cf_node. By just resetting to after_instr, we
avoid all these problems.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit f3a483069a6f0d38c10cec88417ae2b5b5aa3392
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Tue May 19 12:28:20 2015 -0700
i965: advertise ASTC support for Skylake
v2: remove OES ASTC extension reference.
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
commit be7f640257e832a5161645f3dfcbd9acace6931e
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Mon Aug 31 16:38:09 2015 -0700
mesa/glformats: recognize ASTC formats as color formats
ASTC formats contain RGBA components.
Reviewed-by: Chad Versace <chad.versace at intel.com>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
commit 76f17266ec68c644b2609d355018329636ae8e75
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Wed Aug 12 14:41:50 2015 -0700
mesa/texformat: use format conversion function in _mesa_choose_tex_format
This function's cases for non-generic compressed formats duplicate
the GL to MESA translation in _mesa_glenum_to_compressed_format().
This patch replaces the switch cases with a call to the translation
function. This change teaches this function about ASTC, thus enabling
ASTC for glTex*Storage*() calls.
Reviewed-by: Chad Versace <chad.versace at intel.com>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
commit 01024ded1e791b33353ffa09d4e3dfb5b638179d
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Wed Aug 26 12:01:38 2015 -0700
mesa/texcompress: correct mapping of S3TC formats in conversion function
MESA_FORMAT_RGBA_DXT5 should actually be reserved for GL_RGBA[4]_DXT5_S3TC.
Also, Gallium and other dri drivers (radeon and nouveau) follow this mapping
scheme.
Reviewed-by: Chad Versace <chad.versace at intel.com>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
commit 3063913f77cd2db1a263cb824a5c8c3dcc1a51a0
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Aug 31 14:22:23 2015 +1000
r600/sb: update last_cf for finalize if.
As Glenn did for finalize_loop we need to update_cf when we
add a POP at the end of a shader.
I think this fixes one of the earlier shader going off end
of memory problems we've stopped.
Reviewed-by: Glenn Kennard <glenn.kennard at gmail.com>
Cc: "10.6" "11.0" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit a4ba41638d41865ef34bf36a525efcf8102c01ee
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Aug 28 17:10:00 2015 -0700
i965/fs: Use greater-equal cmod to implement maximum.
The docs specifically call out SEL with .l and .ge as the
implementations of MIN and MAX respectively. Among other things,
SEL with these conditional mods are commutative.
See commit 3b7f683f.
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit d2e3638ef9e2ddf7e02b9fbe3fa8d40c63ebe5da
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Wed Jul 8 17:04:10 2015 -0700
i965/chv|skl: Apply sampler bypass w/a
Certain compressed formats require this setting. The docs don't go into much
detail as to why it's needed exactly.
This patch introduces no piglit regressions on gen9 (bsw is untested). Note that
the SKL "regressions" are fixed tests, and the egl_khr_gl_colorspace tests are
WTF. The patch also fixes nothing I can find.
http://otc-mesa-ci.jf.intel.com/job/Leeroy/127820/
v2:
Reworded commit message (Matt); Added piglit results link.
Restructured condition (Matt)
Moved check out to function (Nanley). I left the setting of the bit in the
surface state open coded because it seems to go better with the existing code.
v3:
Use and inline function only in gen8_emit_texture_surface_state() (Matt).
Cc: Matt Turner <mattst88 at gmail.com>
Cc: Nanley Chery <nanleychery at gmail.com>
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 78027c965a50719959df821b7f545db191574724
Author: Dave Airlie <airlied at redhat.com>
Date: Thu Aug 27 02:13:14 2015 +0100
st/mesa: move to renumbering registers in a group
This can be done with a single pass for the instruction base,
and takes renumber_registers out of its spot on the profile.
Acked-by: Marek Olšák <marek.olsak at amd.com
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit aee73f2942eff2ffb4a0497ac81f01a3b00294b8
Author: Dave Airlie <airlied at redhat.com>
Date: Thu Aug 27 01:46:33 2015 +0100
st/mesa: reduce time spent in calculating temp read/writes
The glsl->tgsi convertor does some temporary register reduction
however in profiling shader-db this shows up quite highly,
so optimise things to reduce the number of loops through
all the instructions we do. This drops merge_registers
from 4-5% on the profile to 1%. I think this can be reduced
further by possibly optimising the renumber pass.
Acked-by: Marek Olšák <marek.olsak at amd.com
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 46968c114003b30be335adccbc30445aca9b5dea
Author: Dave Airlie <airlied at redhat.com>
Date: Thu Aug 27 01:01:00 2015 +0100
st/mesa: cache tgsi opcode info in the instruction
Instead of looking this up lots, lets just cache it in the instruction
translation up front. I just noticed this function what high in a profile
of shader-db on radeonsi.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 03b7ec877843cd622717b01c1047e08baf34facf
Author: Dave Airlie <airlied at redhat.com>
Date: Sun Aug 30 20:40:31 2015 +1000
r600: move prim convert from geom shader to function.
This should avoid C++ fail including this header.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit c8bc8d723598ec87bbce9a2439075dfe1612a359
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Sun Aug 9 16:25:50 2015 +1000
glsl: remove specical case subroutine type counting
Unlike samplers we can get the correct value for subroutines from
component_slots()
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit 0d19dc302f21d00b88ccb7b70e5a110d17ea4fdf
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date: Sat Aug 29 18:31:09 2015 +1000
r600g: Use TGSI parse results instead of manually exfiltrating
This makes better use of the work that the TGSI API has done for
us.
Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit 3eed81a97b2fa1f98a2ae577b8b6e04cb144f31a
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date: Sat Aug 29 18:31:08 2015 +1000
r600g: Set geometry properties in r600_create_shader_state()
The selector is shared by all shader variants, so the
individual shaders shouldn't change it. Use tgsi_shader_scan()
results to set geometry properties within a
r600_create_shader_state() call and treat said propertices in
the selector as read-only within r600_shader_from_tgsi().
Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit b4dee1b6360a91117c7a754ed70f359f6000a0de
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date: Sat Aug 29 18:31:07 2015 +1000
r600g: Move geometry properties state from shader to selector
Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit 7b6369eb69e688e5bf739dbe60452950a794f55d
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date: Sat Aug 29 18:31:06 2015 +1000
r600g: Remove dead assigment to 'gs_input_prim' in shader state
Note that 'geometry shader properties' should be carried in the
selector state over the shader state in any case.
Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit 7dc8a3497fdf0fbd8ff4381712a54c2cd94bfbfc
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Aug 25 19:21:38 2015 +0200
radeonsi: don't use the emit qt keyword in si_init_atom
It confuses my editor.
commit 379e3382e8631fdd15c28c6643512205483e7b99
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Aug 23 13:05:53 2015 +0200
radeonsi: remove no-op 32-bit masking
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
commit 437cb1e3f482570447501526927df4d80c845bf5
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Aug 23 12:57:09 2015 +0200
gallium/radeon: fix the ADDRESS_HI mask for EVENT_WRITE CIK packets
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
commit e321596e9f66207cc679b4ddbee13d4c8cdb896f
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Aug 22 18:05:37 2015 +0200
winsys/radeon: handle non-zero finite timeout when waiting for buffers
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
commit a5a96118ed728969c5a41e643cf6ffd0c42461f0
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Aug 26 00:11:23 2015 -0400
freedreno/a3xx: implement half-z clipping
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 58e24b4761ec8c348bf6825c2355a6e047599306
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Aug 24 23:31:00 2015 -0400
freedreno/a3xx: add basic clip plane support
The hardware is capable of dealing with GL1-style user clip planes.
No clip vertex, no clip distances. Fixes a number of ucp tests, as well
as neverball.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
commit c8a61ea4fbcb09215a95dc569dba335b766e5d4d
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Sat Aug 29 10:58:49 2015 +0200
nvc0: change prefix of MP performance counters to HW_SM
According to NVIDIA, local performance counters (MP) are prefixed
with SM, while global performance counters (PCOUNTER) are called PM.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
commit 21bdb4d8f381e4f33b7028a049162c71c2daff73
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Fri Aug 28 19:09:33 2015 +0200
nvc0: sort performance counter queries by name
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
commit ebca85423cf18e987ffebadcde79e95fc2609291
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Fri Aug 28 18:41:16 2015 +0200
nvc0: make names of performance counter queries consistent
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
commit 981f46aa95b27ff1d139a6d5e059f9fd32cf83f0
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Fri Aug 28 18:30:13 2015 +0200
nvc0: use enumerations for driver queries
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
commit 0eac5990016dbc435ef3260cf602783bebf03e59
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Fri Aug 28 18:15:13 2015 +0200
nvc0: remove commented out code related to PCOUNTER queries
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
commit 6941883175612ae602a8745945153ba064f53a7a
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Aug 28 10:46:10 2015 +1000
r600: port si_conv_prim_to_gs_out from radeonsi
This code was broken by the tess merge, and I totally missed it
until now. I'm not sure this fixes anything but it stops the assert.
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Glenn Kennard <glenn.kennard at gmail.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit c149d84d458101e188386a92bbff1e071284d375
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Aug 28 09:58:15 2015 +1000
r600g: use PRIi64 for some compute debug printfs
Otherwise this will crash on 32-bit, and it gets rid of
warnings building on 32-bit.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 8d6d0cc17d945317f44328a7761801e6781dc3fc
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Aug 28 09:57:04 2015 +1000
gallium/util: fix debug_get_flags_option on 32-bit
On 32-bit we need to use PRIu64 flags for printfs,
otherwise this segfaults in R600_DEBUG=help otherwise.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 275c5810ca7e38560b2a77281e7a0498c50126f8
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Aug 20 21:55:52 2015 -0400
glsl: provide the option of using BFE for unpack builting lowering
This greatly improves generated code, especially for the snorm variants,
since it is able to get rid of the lshift/rshift for sext, as well as
replacing each shift + mask with a single op.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 889a946a455c54a5a9bca144b2ea2fe66be39274
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Aug 20 20:52:32 2015 -0400
glsl: use bitfield_insert instead of and + shift + or for packing
It is fairly tricky to detect the proper conditions for using bitfield
insert, but easy to just use it up front. This removes a lot of
instructions on nvc0 when invoking the packing builtins.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit c676c432f30158190c260e7f3731ee6667ad4103
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Aug 17 14:38:31 2015 -0700
i965/fs: Remove fs_visitor::try_replace_with_sel().
No shader-db changes on g4x, snb, hsw, or bdw.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 64e312d7fab1b8a4bc0edb9cd9458a511e66d037
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu Aug 27 18:30:34 2015 -0700
i965/fs: Replace awful variable names.
start_to -> dst_start
end_to -> dst_end
start_from -> src_start
end_from -> src_end
var_to -> dst_var
var_from -> src_var
reg_to -> dst_reg
reg_to_offset -> dst_reg_offset
reg_from -> src_reg
Not sure how these made sense to me before.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit a2ff1e95a43d0ebcaeee4c239bd8d32963f5224c
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Aug 18 17:47:00 2015 -0700
i965/fs: Skip blocks in register coalescing interference check.
No need to walk through instructions in blocks we know don't contain our
registers' live ranges.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit f2f8c43af92ad446a5c56bd0f88af36e1a3e0506
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Aug 17 16:03:27 2015 -0700
i965/fs: Improve register coalescing interference check.
I always thought that the is_control_flow() -> return false check was a
bad hack, and some previous attempts to remove it have failed and have
been reverted.
The previous two patches fix some problems that caused register
coalescing to not notice some interference between registers, which the
is_control_flow() check apparently works around.
With that fixed, we can calculate interference more accurately.
total instructions in shared programs: 6261319 -> 6257917 (-0.05%)
instructions in affected programs: 346282 -> 342880 (-0.98%)
helped: 1552
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit f3d0a894af61d9ccc3f00086fbac3809bfed1160
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Aug 18 17:10:44 2015 -0700
i965/fs: Use overwrites_reg() instead of dst.equals().
equals() returns false for registers with different types, using it
isn't appropriate to determine whether an is overwriting a register.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 8765f1d7ddfb00dc5b202e4e679ebe640a547d50
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Aug 18 14:28:03 2015 -0700
i965: Only consider fixed_hw_reg in equals() if file is HW_REG/IMM.
Noticed when debugging things that lead to the next patch.
On G45 (and presumably ILK) this helps register coalescing:
total instructions in shared programs: 4077373 -> 4077340 (-0.00%)
instructions in affected programs: 43751 -> 43718 (-0.08%)
helped: 52
HURT: 2
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 2581fe931a48478123d8054ce7a291cffa851de9
Author: Marta Lofstedt <marta.lofstedt at intel.com>
Date: Fri Aug 28 10:22:41 2015 +0200
i965/fs: Do not set the size for zero-size uniforms
Zero sized uniforms can exist in the list, but they don't get get any space
allocated in prog_data->params or in the param_size array, so the size
should not be set for them. This was previously fixed in:
commit: 781dc7c0e1f41502f18e07c0940af949a78d2792.
However,
commit: 259f7291de2387aa3ac5f856b39b7b934a1d8e7d
removed the fix.
Signed-off-by: Marta Lofstedt <marta.lofstedt at intel.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 05161596137994ab4b31e054d5afbff877c0a074
Author: Daniel Scharrer <daniel at constexpr.org>
Date: Fri Aug 28 11:45:36 2015 +0200
mesa: return old name for deleted samplers for SAMPLER_BINDING queries
If the sampler object has been deleted in the same context the binding
will have been cleared. If it has been deleted in another context, the
spec does not say what should returned. None of the other binding point
queries check for deletion in another context.
Also, as names of deleted objects are free for reuse, the current code
didn't even work reliably.
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
commit 5aaaaebf22c920745d577c49e463d23b90ba5ea8
Author: Daniel Scharrer <daniel at constexpr.org>
Date: Fri Aug 28 11:45:35 2015 +0200
mesa: add missing queries for ARB_direct_state_access
This adds index queries (glGet*i_v) for GL_TEXTURE_BINDING_* and
GL_SAMPLER_BINDING, as well as textue queries
(glGetTex{,ture}Parameter*) for GL_TEXTURE_TARGET.
CC: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
commit 2dbc6a0ad9f5432e5a9a1e66b1c27c574f0def80
Author: Neil Roberts <neil at linux.intel.com>
Date: Fri Aug 28 14:29:22 2015 +0100
docs: Fix a typo in GL3.txt concerning GL_KHR_context_flush_control
commit b319fd7c14707ff345b7ce1461e5fee81b75a4cf
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Aug 28 02:50:25 2015 -0400
mesa: fix dispatch sanity with GL_OES_texture_storage_multisample_2d_array
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91785
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit 2ef5a4f8304ed368e56806e1e2be6e7d2bd290f7
Author: Vinson Lee <vlee at freedesktop.org>
Date: Tue Jul 21 14:02:01 2015 -0700
ABI-check: Use more portable bash invocation.
Fixes 'make check' on FreeBSD.
Signed-off-by: Vinson Lee <vlee at freedesktop.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 86c57ebe0ed1acc98545746058862db7429412da
Author: Boyan Ding <boyan.j.ding at gmail.com>
Date: Fri Aug 21 21:42:45 2015 +0800
i965/nir: Make use of nir_opt_undef
Shader-db result on Ivy Bridge:
total instructions in shared programs: 145484 -> 145445 (-0.03%)
instructions in affected programs: 225 -> 186 (-17.33%)
helped: 5
HURT: 0
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
Signed-off-by: Boyan Ding <boyan.j.ding at gmail.com>
commit 559b8842fa2d315f009a039e7bbc503c524de894
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu Sep 25 11:49:48 2014 -0700
glapi: Remove _x86_64_get_get_dispatch symbol from x86-64 assembly.
Never used.
Reviewed-by: Mark Janes <mark.a.janes at intel.com>
commit 4a6a47ed056f37544083048287fec96c88e0e386
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Aug 12 11:55:53 2015 -0400
glsl: clean up textureSize prototype
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
commit 608c7b4a63d5818f7ae0b3d48496b02cf8458d9b
Author: Glenn Kennard <glenn.kennard at gmail.com>
Date: Thu Aug 27 19:04:17 2015 +0200
r600g/sb: Don't crash on empty if jump target
Signed-off-by: Glenn Kennard <glenn.kennard at gmail.com>
Cc: <mesa-stable at lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit a830225adbb77073272961df409885cca6b861ee
Author: Glenn Kennard <glenn.kennard at gmail.com>
Date: Thu Aug 27 19:04:16 2015 +0200
r600g/sb: Don't read junk after EOP
Shaders that contain instruction data after an instruction with EOP could end
up parsing that as an instruction, leading to various crashes and asserts in
SB as it gets very confused if it sees for instance a loop start instruction
jumping off to some random point.
Add a couple of asserts, and print EOP bit if set in old asm printer.
Signed-off-by: Glenn Kennard <glenn.kennard at gmail.com>
Cc: <mesa-stable at lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 36f1999a87258603b6720d55e6020d5d24c215c9
Author: Glenn Kennard <glenn.kennard at gmail.com>
Date: Thu Aug 27 19:04:15 2015 +0200
r600g/sb: Handle undef in read port tracker
e8e443 missed adding check for undef values also in
unreserve function, leading to an assert triggering.
Signed-off-by: Glenn Kennard <glenn.kennard at gmail.com>
Cc: <mesa-stable at lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 52f748792393c681f35025be7d843e6426fa327d
Author: Brian Paul <brianp at vmware.com>
Date: Thu Aug 27 14:33:40 2015 -0600
mesa: rename rowStride to imageStride in texturesubimage()
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 2259b111003f2e8c55cae42677ec45345fb1b6e3
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Aug 27 15:28:24 2015 -0400
mesa: only copy the requested teximage faces
Cube maps are special in that they have separate teximages for each
face. We handled that by copying the data to them separately, but in
case zoffset != 0 or depth != 6 we would read off the end of the client
array or modify the wrong images.
zoffset/depth have already been verified by the time the code gets to
this stage, so no need to double-check.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Brian Paul <brianp at vmware.com>
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
commit 0a913a9d85f2eb772be6a133965c5b8a4aa3c800
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Aug 6 07:16:07 2015 -0700
nir: Convert the builder to use the new NIR cursor API.
The NIR cursor API is exactly what we want for the builder's insertion
point. This simplifies the API, the implementation, and is actually
more flexible as well.
This required a bit of reworking of TGSI->NIR's if/loop stack handling;
we now store cursors instead of cf_node_lists, for better or worse.
v2: Actually move the cursor in the after_instr case.
v3: Take advantage of nir_instr_insert (suggested by Connor).
v4: vc4 build fixes (thanks to Eric).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Eric Anholt <eric at anholt.net> [v1]
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com> [v4]
Acked-by: Connor Abbott <cwabbott0 at gmail.com> [v4]
commit 3e3cb77901c9c9efbf4cf550da80509fe6dbbd9f
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sun Aug 9 18:30:33 2015 -0700
nir: Convert the NIR instruction insertion API to use cursors.
This patch implements a general nir_instr_insert() function that takes a
nir_cursor for the insertion point. It then reworks the existing API to
simply be a wrapper around that for compatibility.
This largely involves moving the existing code into a new function.
Suggested by Connor Abbott.
v2: Make the legacy functions static inline in nir.h (requested by
Connor Abbott).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Acked-by: Connor Abbott <cwabbott0 at gmail.com>
commit f90c6b1ce0d96c7dbdd32ab913d5c88913700ba2
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Aug 25 10:01:31 2015 -0700
nir: Move nir_cursor to nir.h.
We want to use this for normal instruction insertion too, not just
control flow. Generally these functions are going to be extremely
useful when working with NIR, so I want them to be widely available
without having to include a separate file.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Acked-by: Connor Abbott <cwabbott0 at gmail.com>
commit c44d50775209266b5c8bad0ab7a7c4ccd7db14a4
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Aug 24 17:30:08 2015 -0700
nir: Strengthen "no jumps" assertions in instruction insertion API.
Jumps must be the last instruction in a block, so inserting another
instruction after a jump is illegal.
Previously, we only checked this when the new instruction being inserted
was a jump. This is a red herring - inserting *any* kind of instruction
after a jump is illegal.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Acked-by: Connor Abbott <cwabbott0 at gmail.com>
commit bcae4640c89bc2775d1a85b2b27d2787cac8f843
Author: Brian Paul <brianp at vmware.com>
Date: Wed Aug 26 13:58:23 2015 -0600
st/mesa: use PROGRAM_ARRAY for storing structs containing arrays
Previously, we used PROGRAM_ARRAY only for variables which were
arrays or matrices. But if the variable is a structure containing
an array or matrix, we need to use PROGRAM_ARRAY for that too.
Before, we failed an assertion:
state_tracker/st_glsl_to_tgsi.cpp:4900:
Assertion `src_reg->file != PROGRAM_TEMPORARY' failed.
when running the piglit test
glsl-1.20/execution/fs-const-array-of-struct-of-array.shader_test
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 42c7be5877665dfcbeb317c7eb163a03d56fe661
Author: Brian Paul <brianp at vmware.com>
Date: Wed Aug 26 13:23:47 2015 -0600
glsl: fix comment typo: s/filed/field/
commit 3c256f572b0377e5cff23e022aef49c356055514
Author: Brian Paul <brianp at vmware.com>
Date: Tue Aug 25 13:25:31 2015 -0600
gallium/util: fix code formatting in u_blitter.h
Trivial.
commit fee0c5af11dd0995de96e7053377d425a66d03a0
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Aug 19 14:29:53 2015 -0700
i965/fs: Split VGRFs after lowering pull constants
The split_virtual_grfs code doesn't properly rewrite reladdr so we need to
make sure that any uniform indirects are lowered away first.
This fixes the glsl-fs-uniform-indexed-by-swizzled-vec4.shader_test in piglit
Cc: "10.6" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit f2e667172a6382f81d1f3e709f02c7ee6cfda4c7
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Aug 18 17:40:02 2015 -0700
i964/fs: Refactor assign_constant_locations
Now that all constant locations are assigned in a single function, we can
refactor it a bit to unify things. In particular, we now handle
pull_constant_loc and push_constant_loc more similarly and we only modify
stage_prog_data->params[] in one place at the end of the function.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 885a9b058cd8f2d49ae675513003eb1164888ad3
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Aug 25 16:17:14 2015 -0700
i965: Rename INTEL_DEBUG=vec4vs to INTEL_DEBUG=vec4.
driParseDebugString() doesn't have actual code to parse comma separated
lists (or any other supported options?); instead it dumbly uses strstr().
This means that INTEL_DEBUG="vec4vs" will trigger both DEBUG_VEC4VS and
DEBUG_VS, as "vs" is also a substring.
We should probably improve the driconf parsing, but for now, just rename
the option so it's usable in the meantime.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Acked-by: Jason Ekstrand <jason.ekstrand at intel.com>
Acked-by: Kristian Høgsberg <krh at bitplanet.net>
commit 16ad1d2a8d9d1d2d816f8b8d70f1134a7d4ba8dc
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Mon Aug 24 10:09:52 2015 +0300
mesa: enable enums for OES_texture_storage_multisample_2d_array
v2: use _mesa_is_gles31(ctx) for verifying we are on ES 3.1,
remove _es31 usage from get_hash_params.py
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Marta Lofstedt <marta.lofstedt at intel.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit c2c64fd26999cedf4b63c754145f7258517f5bce
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Fri Aug 21 09:42:10 2015 +0300
glsl: add support for OES_texture_storage_multisample_2d_array
v2: use ARB_texture_multisample enable bit
Patch adds extension enable bit and enables required keywords
and builtin functions for the extension.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Marta Lofstedt <marta.lofstedt at intel.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit b9101b14439836c337abeffafc4b058a8d80d3ef
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Fri Aug 21 09:40:11 2015 +0300
mesa: Add extension enable for OES_texture_storage_multisample_2d_array
v2: use ARB_texture_multisample bit to enable extension
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Marta Lofstedt <marta.lofstedt at intel.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit f4280b740d835d5c62b330e2fd563eeb119005b1
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Fri Aug 21 09:43:27 2015 +0300
glapi: add GL_OES_texture_storage_multisample_2d_array extension
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Marta Lofstedt <marta.lofstedt at intel.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 9a759a6ee002203a045e9df1f91823204609fd4a
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Sun May 31 13:29:41 2015 -0700
swrast: add a new macro, FETCH_COMPRESSED
This patch creates a new macro, FETCH_COMPRESSED - similar in nature
to the other FETCH_* macros. This reduces repetition in the code that
deals with compressed textures.
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
commit 42ee16176dca797c395592b0245f370ea58ca3a8
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Wed Jun 17 17:14:40 2015 -0700
mesa: return bool instead of GLboolean in compressedteximage_only_format()
In agreement with the coding style, functions that aren't directly visible
to the GL API should prefer the use of bool over GLboolean.
Suggested-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
commit 43d5b4db969930f9d85f605c75ef9ffe67e58ad3
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Thu May 28 16:02:34 2015 -0700
i965: refactor miptree alignment calculation code
Remove redundant checks and comments by grouping our calculations for
align_w and align_h wherever possible.
v2: reintroduce brw.
don't include functional changes.
don't adjust function parameters or create a new function.
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
commit a6877341358e1534e74dd9e5fc72934a20b78228
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Thu May 21 14:27:55 2015 -0700
i965: change the meaning of cpp for compressed textures
An ASTC block takes up 16 bytes for all block width and height configurations.
This size is not integrally divisible by all ASTC block widths. Therefore cpp
is changed to mean bytes per block if the texture is compressed.
Because the original definition was bytes per block divided by block width, all
references to the mipmap width must be divided the block width. This keeps the
address calculation formulas consistent. For example, the units for miptree_level
x_offset and miptree total_width has changed from pixels to blocks.
v2: reuse preexisting ALIGN_NPOT macro located in an i965 driver file.
v3: move ALIGN_NPOT into seperate commit.
simplify cpp assignment in copy_image_with_blitter().
update miptree width and offset variables in: intel_miptree_copy_slice(),
intel_miptree_map_gtt(), and brw_miptree_layout_texture_3d().
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
commit 1a9ceed4ba764cf73a643f8f2135b5b84cfe4581
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Thu Jun 18 11:02:17 2015 -0700
i965: correct mt->align_h for 2D textures on Skylake
In agreement with commit 4ab8d59a23, vertical alignment values are equal to
four times the block height on Gen9+.
v2: add newlines to separate declarations, statments, and comments.
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Neil Roberts <neil at linux.intel.com>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
commit 10ff64fd3d19bc9da793fa43eb746c29608bfddd
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Thu May 21 14:27:55 2015 -0700
i965: use ALIGN_NPOT for setting ASTC mipmap layouts
ALIGN is changed to ALIGN_NPOT because alignment values are sometimes not
powers of two when working with ASTC.
v2: handle texture arrays and LDR-only systems.
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
commit 54d2aa4258f0bfcc669b2bc4e82332f7ff4876dd
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Tue Jun 2 11:03:22 2015 -0700
mesa/macros: move ALIGN_NPOT to macros.h
Aligning with a non-power-of-two number is a general task that can be used in
various places. This commit is required for the next one.
v2: add greater than 0 assertion (Anuj).
convert the macro to a static inline function.
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
commit 97f4efd573aed7ffc0ea9395f4e69ccdeb5041f6
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Wed May 27 13:25:30 2015 -0700
mesa/macros: add power-of-two assertions for alignment macros
ALIGN and ROUND_DOWN_TO both require that the alignment value passed
into the macro be a power of two in the comments. Using software assertions
verifies this to be the case.
v2: use static inline functions instead of gcc-specific statement expressions (Brian).
v3: fix indendation (Brian).
v4: add greater than zero requirement (Anuj).
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
commit 8b1f008e9acf94645a28c27fa261f6450a3edb84
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Wed Apr 15 14:15:10 2015 -0700
i965/surface_formats: add support for 2D ASTC surface formats
Define two-thirds of the 2D Intel ASTC surface formats (LDR-only). This allows
a 1-to-1 mapping from the mesa format to the Intel format.
ASTC textures will default to being processed in LDR mode. If there is
hardware support for HDR/Full mode and the texture is not sRGB, add the
format bit necessary to process it in HDR/Full mode.
v2: remove extra newlines.
v3: follow existing coding style in translate_tex_format().
v4: expound on the GEN9_SURFACE_ASTC_HDR_FORMAT_BIT comment.
update SF table - ASTC is actually supported in Gen8.
v5: conform the ASTC MESA_FORMAT enums to the existing naming convention.
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
commit cd49b97a8a2c0dd8dc1d7f32b86f519e936571fd
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Tue Apr 28 15:10:11 2015 -0700
mesa/teximage: return the base internal format of the ASTC formats
This is necesary to initialize the gl_texture_image struct.
From the KHR_texture_compression_astc_ldr spec:
"Added to Section 3.8.6, Compressed Texture Images
Add the tokens specified above to Table 3.16, Compressed Internal Formats.
In all cases, the base internal format will be RGBA. The encoding allows
images to be encoded with fewer channels, but this is always presented as
RGBA to the sampler."
v2. use _mesa_is_astc_format().
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
commit 12b519b4571d27a45abd3266f35b126d00dcb926
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Mon Jul 27 16:09:09 2015 -0700
mesa/teximage: accept ASTC formats for 3D texture specification
The ASTC spec was revised as follows:
Revision 2, April 28, 2015 - added CompressedTex{Sub,}Image3D to
commands accepting ASTC format tokens in the New Tokens section [...].
Support only exists in the HDR submode:
Add a second new column "3D Tex." which is empty for all non-ASTC
formats. If only the LDR profile is supported by the implementation,
this column is also empty for all ASTC formats. If both the LDR and HDR
profiles are supported only, this column is checked for all ASTC
formats.
LDR-only systems should generate an INVALID_OPERATION error when
attempting to call CompressedTexImage3D with the TEXTURE_3D target.
v2. return the proper error for LDR-only systems.
v3. update is_astc_format().
v4. use _mesa_is_astc_format().
v5. place logic in _mesa_target_can_be_compressed.
v6. fix issues handling ASTC formats.
Reviewed-by: Chad Versace <chad.versace at intel.com>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
commit 23c9cd5a9613ad07bdbe55708a56562ee23f25d5
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Tue Apr 28 15:08:32 2015 -0700
mesa/texcompress: enable translation between MESA and GL ASTC formats
v3. conform the ASTC MESA_FORMAT enums to the existing naming convention.
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
commit 692578ed134bacff1a315489ad47514450b3387f
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Tue May 19 15:41:56 2015 -0700
mesa/glformats: recognize ASTC formats as compressed
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
commit 4143511b15e8f1d63176257ae8a83b4906e3204c
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Tue May 19 15:41:28 2015 -0700
mesa: add ASTC extensions to the extensions table
v2: alphabetize the extensions.
remove OES ASTC extension.
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
commit 582ce1ea976a16aa8f32ff72cb2fecb00186e253
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Mon May 18 16:30:30 2015 -0700
mesa: don't enable online compression for ASTC formats
In agreement with the ASTC spec, this makes calls to TexImage*D unsuccessful.
Implied by the spec, Generate[Texture]Mipmap and [Copy]Tex[Sub]Image*D calls
must be unsuccessful as well.
v2. actually force attempts to compress online to fail.
v3. indentation (Matt).
v4. update copytexture_error_check to account for CopyTexImage*D (Chad).
Reviewed-by: Chad Versace <chad.versace at intel.com>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
commit e9fd8e154fdb0394cbaed5e14ac52e689a020ebe
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Tue Apr 28 14:41:49 2015 -0700
glapi: add support for KHR_texture_compression_astc_ldr
v2: correct the spelling of the sRGB variants.
remove spaces around "=" when setting the enum value.
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
commit 8ae37365f30594498184fe5428f961a9c310fd8c
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Tue May 19 10:35:39 2015 -0700
mesa/formats: define the 2D ASTC formats
Define the mesa formats and make changes necessary for compilation
without errors. Also add support for _mesa_get_srgb_format_linear().
v2. conform the ASTC MESA_FORMAT enums to the existing naming convention.
v3. remove ASTC cases for _mesa_get_uncompressed_format(). This function is
only used for generating mipmaps - something ASTC formats do not support
due to lack of online compression.
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
commit c4cbaca327174135e28353c3438241b08bf96755
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Aug 26 14:04:03 2015 -0400
nouveau: avoid build failures since 0fc21ecf
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 6924ecac77d1d041420c571de9d31cff1d30aecc
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Aug 22 14:17:10 2015 +0200
gallium/radeon: read_registers should return bool meaning success or failure
Acked-by: Christian König <christian.koenig at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
commit 16e5d8ad388445c2e577406953a403608f1addc5
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Aug 19 18:45:11 2015 +0200
radeonsi: add IB parser support for CP DMA packets
If the packet encoding is defined in the same format as register definitions,
the python script can process them automatically and the parser support
becomes trivial.
Acked-by: Christian König <christian.koenig at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
commit 2c14a6d3b1c53d5814414ce9e91fd8d24c90b787
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Aug 19 11:53:25 2015 +0200
radeonsi: add IB tracing support for debug contexts
This adds trace points to all IBs and the parser prints them and also
prints which trace points were reached (executed) by the CP.
This can help pinpoint a problematic packet, draw call, etc.
Acked-by: Christian König <christian.koenig at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
commit 189953ee13ad7d6b5d9d04ac21a230e8137a700d
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Aug 17 19:17:16 2015 +0200
radeonsi: remove old CS tracing code
Some of it is left there and it will be re-used in the next commit.
Acked-by: Christian König <christian.koenig at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
commit df6a5666b6398613e552f66cd092369b12cce9ed
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Aug 16 00:54:34 2015 +0200
radeonsi: parse and dump status registers on GPU hang
GPU hang detection must be enabled by setting: GALLIUM_DDEBUG=[timeout in ms]
This may print too much information that we might not understand yet,
but some of the bits are very useful.
Acked-by: Christian König <christian.koenig at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
commit 61df4f0cd3f34ed11dd64932aeb7731d354f2bde
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Aug 15 23:57:22 2015 +0200
radeonsi: add an IB parser
Acked-by: Christian König <christian.koenig at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
commit be6dc8777662645958d4be6639ee2bb47c5054d8
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Aug 15 12:46:17 2015 +0200
radeonsi: save the contents of indirect buffers for debug contexts
This will be used by the IB parser.
Acked-by: Christian König <christian.koenig at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
commit a6a6c68955bb8526aac3c04af96fdfdee71bc8bc
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Aug 15 23:44:04 2015 +0200
radeonsi: generate register and packet tables for an IB parser from sid.h
This makes writing a good IB parser a lot easier.
It generates 2 tables:
- packet3 table
- register table with all registers, fields, and named values
Acked-by: Christian König <christian.koenig at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
commit d15b71b4bd4666619f5bee0e7fcb21d4608edf70
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Aug 15 18:48:06 2015 +0200
radeonsi: remove duplicated register definitions and instruction definitions
Instruction encoding isn't needed in Mesa.
The border color address registers were duplicated.
Acked-by: Christian König <christian.koenig at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
commit c59ad265df655a19285d813144f6b76d7f49d7fd
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Aug 15 18:43:27 2015 +0200
r600g,radeonsi: remove unused ill-formed register field definitions
Acked-by: Christian König <christian.koenig at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
commit 110873ed11342426584a75bf27e85b74035c3b4c
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Aug 15 23:56:22 2015 +0200
radeonsi: add an initial dump_debug_state implementation dumping shaders
This is usually called after a draw call.
Acked-by: Christian König <christian.koenig at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
commit 93d97db3492cc1af8fb401ed5eb6766e608f744e
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jul 11 13:13:07 2015 +0200
radeonsi: allow si_dump_key to write to a file
Acked-by: Christian König <christian.koenig at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
commit 525921ed51176255474c73adacfc6801a7bf2783
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jul 4 14:10:21 2015 +0200
gallium/ddebug: new pipe for hang detection and driver state dumping (v2)
v2: lots of improvements
This is like identity or trace, but simpler. It doesn't wrap most states.
Run with:
GALLIUM_DDEBUG=1000 [executable]
where "executable" is the app and "1000" is in miliseconds, meaning that
the context will be considered hung if a fence fails to signal in 1000 ms.
If that happens, all shaders, context states, bound resources, draw
parameters, and driver debug information (if any) will be dumped into:
/home/$username/dd_dumps/$processname_$pid_$index.
Note that the context is flushed after every draw/clear/copy/blit operation
and then waited for to find the exact call that hangs.
You can also do:
GALLIUM_DDEBUG=always
to do the dumping after every draw/clear/copy/blit operation without
flushing and waiting.
Examples of driver states that can be dumped are:
- Hardware status registers saying which hw block is busy (hung).
- Disassembled shaders in a human-readable form.
- The last submitted command buffer in a human-readable form.
v2: drop pipe-loader changes, drop SConscript
rename dd.h -> dd_pipe.h
Acked-by: Christian König <christian.koenig at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
commit 0fc21ecfc0891d239f20bf7724e51bc75503570c
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jul 25 18:40:59 2015 +0200
gallium: add flags parameter to pipe_screen::context_create
This allows creating compute-only and debug contexts.
Reviewed-by: Brian Paul <brianp at vmware.com>
Acked-by: Christian König <christian.koenig at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
commit 7b5c92391f15533ec02327d617c4e8639a2f8bb4
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jul 11 12:34:46 2015 +0200
gallium: add an interface for dumping debug driver state
Reviewed-by: Brian Paul <brianp at vmware.com>
Acked-by: Christian König <christian.koenig at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
commit a3b617a25859ebbfe74b294b7e6bee7af1d24b8c
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Aug 24 11:34:42 2015 -0400
mesa: remove pointless es31 checks, fix indirect to only be in es31
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 332fb341dd100f167055d68871a240fd8d416a85
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Aug 24 09:35:04 2015 -0400
mesa: uncomment checks in es31 computation, add texture_ms
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
commit f432ae899fb81468778dbeb17ac7615da3ed5c0d
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Aug 24 00:22:37 2015 +0200
mesa: create multisample fallback textures like normal textures
This works if drivers upsample on upload (like all radeon ones do).
The alternative is an unexpected GL error from anything calling
_mesa_update_state and possibly other issues.
Cc: 10.6 11.0 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit f8b01ae47cc4760d5687e50f3315b5a89e19cd26
Author: Grazvydas Ignotas <notasas at gmail.com>
Date: Tue Aug 18 03:23:29 2015 +0300
radeonsi: mark unreachable paths to avoid warnings
Otherwise we get:
warning: 'num_user_sgprs' may be used uninitialized in this function
...
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit e0c2ea03377b52058324f735f7e1f55bb9d29750
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Tue Jul 28 11:25:35 2015 +0300
mesa: GetTexLevelParameter{if}v changes for OpenGL ES 3.1
Patch refactors existing parameters check to first check common enums
between desktop GL and GLES 3.1 and modifies get_tex_level_parameter_image
to be compatible with enums specified in 3.1.
v2: remove extra is_gles31() checks (suggested by Ilia)
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com> (v1)
Reviewed-by: Marta Lofstedt <marta.lofstedt at intel.com> (v1)
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit ae8d0e7abef27b25637ee25b857c44f13aef0d11
Author: Marta Lofstedt <marta.lofstedt at intel.com>
Date: Wed Aug 19 15:30:33 2015 +0200
mesa/es3.1: Allow GL_COMPUTE_WORK_GROUP_SIZE for OpenGL ES 3.1
According to OpenGL ES specification section 7.12,
GL_COMPUTE_WORK_GROUP_SIZE, is supported by the
glGetProgramiv function.
Signed-off-by: Marta Lofstedt <marta.lofstedt at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit c2a766880d6a92a0b7b3411062f61090d77f65c0
Author: Marta Lofstedt <marta.lofstedt at intel.com>
Date: Wed Aug 19 15:33:21 2015 +0200
mesa/es3.1: Enable getting MAX_COMPUTE_WORK_GROUP_ values for OpenGL ES 3.1
According to the OpenGL ES 3.1 specification chapter 17, the
MAX_COMPUTE_WORK_GROUP_COUNT and MAX_COMPUTE_WORK_GROUP_SIZE
is available for glGetIntegeri_v.
Signed-off-by: Marta Lofstedt <marta.lofstedt at linux.intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 73e5adc4b2bf082addd1ae76fb23c2773887162b
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Aug 26 10:37:09 2015 +1000
mesa/formats: pass correct parameter to _mesa_is_format_compressed
commit 26c549e69d12e44e2e36c09764ce2cceab262a1b
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Fri Jul 31 10:26:36 2015 -0700
mesa/formats: remove compressed formats from matching function
caused a regression in my CTS testing, this looks like a clear
thinko.
Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>
sSigned-off-by: Dave Airlie <airlied at redhat.com>
commit 48e6404c04da6c9655d7a8b625830d0d40f393ae
Author: Roland Scheidegger <sroland at vmware.com>
Date: Sun Aug 9 02:50:10 2015 +0200
gallium/auxiliary: optimize rgb9e5 helper some more
I used this as some testing ground for investigating some compiler
bits initially (e.g. lrint calls etc.), figured I could do much better
in the end just for fun...
This is mathematically equivalent, but uses some tricks to avoid
doubles and also replaces some float math with ints. Good for another
performance doubling or so. As a side note, some quick tests show that
llvm's loop vectorizer would be able to properly vectorize this version
(which it failed to do earlier due to doubles, producing a mess), giving
another 3 times performance increase with sse2 (more with sse4.1), but this
may not apply to mesa.
No piglit change.
Acked-by: Marek Olšák <marek.olsak at amd.com>
commit 941346a80323c9419b70e3987b900a69ebb08fb4
Author: Roland Scheidegger <sroland at vmware.com>
Date: Sun Aug 9 02:03:33 2015 +0200
gallium/auxiliary: optimize rgb9e5 helper a bit
This code (lifted straight from the extension) was doing things the most
inefficient way you could think of.
This drops some of the more expensive float operations, in particular
- int-cast floors (pointless, values always positive)
- 2 raised to (signed) integers (replace with simple exponent manipulation),
getting rid of a misguided comment in the process (implement with table...)
- float division (replace with mul of reverse of those exponents)
This is like 3 times faster (measured for float3_to_rgb9e5), though it depends
(e.g. llvm is clever enough to replace exp2 with ldexp whereas gcc is not,
division is not too bad on cpus with early-exit divs).
Note that keeping the double math for now (float x + 0.5), as the results may
otherwise differ.
Acked-by: Marek Olšák <marek.olsak at amd.com>
commit c1452983b44cc8ee238b8c7e2cfca1105c707487
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Aug 24 09:52:12 2015 +1000
mesa/texgetimage: fix missing stencil check
GetTexImage can read to stencil8 but only from
a stencil or depthstencil textures.
This fixes a bunch of failures in CTS
GL33-CTS.gtf32.GL3Tests.packed_pixels
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 1d2a844e7d55645ea3d24fb589bec03695b3d2b1
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Fri Aug 21 13:09:08 2015 -0700
mesa/teximage: Add GL error parameter to _mesa_target_can_be_compressed
Enables _mesa_target_can_be_compressed to return the appropriate GL error
depending on it's inputs. Use the parameter to return the appropriate GL error
for ETC2 formats on GLES3.
Suggested-by: Chad Versace <chad.versace at intel.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
commit 26c549e69d12e44e2e36c09764ce2cceab262a1b
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Fri Jul 31 10:26:36 2015 -0700
mesa/formats: remove compressed formats from matching function
All compressed formats return GL_FALSE and there isn't any evidence to
support that this behaviour would change. Remove all switch cases for
compressed formats.
v2. Since the exhaustive switch is removed, add a gtest to ensure
all formats are handled.
v3. Ensure that GL_NO_ERROR is set before returning.
v4. Fix an arg to _mesa_uncompressed_format_to_type_and_comps();
fix formatting and misc improvements (Chad).
Reviewed-by: Chad Versace <chad.versace at intel.com>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
commit 8e581747d2342950ff44488064eef53768b3ae82
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Tue Aug 18 12:42:57 2015 -0700
mesa/formats: make format testing a gtest
We currently check that our format info table is sane during context
initialization in debug builds. Perform this check during
`make check` instead. This enables format testing in release builds
and removes the requirement of an exhuastive switch for
_mesa_uncompressed_format_to_type_and_comps().
v2. indentation and conditional inclusion fixes (Chad).
allow tests to continue running if any format fails
and display the failing format name.
Reviewed-by: Chad Versace <chad.versace at intel.com>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
commit 1bec29d04d970b4d60a8c60252313f25bebfe024
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Aug 6 07:44:35 2015 -0700
gallium/ttn: Use nir_builder_insert() rather than poking at cf_list.
I intend to remove nir_builder::cf_node_list, so I can't have this code
poking at it directly. The proper way is to set the insertion point and
then simply insert things there.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 78856194c191bf5dc9e28c13b6d4c4d89b3206c1
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Aug 6 07:39:34 2015 -0700
prog_to_nir: Use nir_builder_insert() rather than poking at cf_list.
I intend to remove nir_builder::cf_node_list, so I can't have this code
poking at it directly. The proper way is to set the insertion point and
then simply insert things there.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 5f14c417c86ced1847746c64d4db54c7e5ddc187
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Aug 18 01:53:29 2015 -0700
nir: Use nir_shader::stage rather than passing it around.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit d4d5b430a52aab148c8697deaedd8864e1749f3c
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Aug 18 01:48:34 2015 -0700
nir: Store gl_shader_stage in nir_shader.
This makes it easy for NIR passes to inspect what kind of shader they're
operating on.
Thanks to Michel Dänzer for helping me figure out where TGSI stores the
shader stage information.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit dfacae3a56463e2df3a67e245f868e9f2be64dcd
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Aug 18 17:04:53 2015 -0700
i965/fs: Combine assign_constant_locations and move_uniform_array_access_to_pull_constants
The comment above move_uniform_array_access_to_pull_constants was
completely bogus because it has nothing to do with lowering instructions.
Instead, it's assiging locations of pull constants.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit c999a58f50578a826a66e2d95334245b6c4c9559
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Aug 18 14:45:35 2015 -0700
nir/lower_io: Remove assign_var_locations_direct_first
This is no longer used so we might as well get rid of it.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 259f7291de2387aa3ac5f856b39b7b934a1d8e7d
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Aug 18 12:00:15 2015 -0700
i965/fs: Rework uniform handling
Previously, we treated the entire UNIFORM file as if it had two elements:
One for direct things and one for indirect. This is substantially
different from how the old visitor code handled it where each element was
effectively its own uniform. This commit makes the NIR path more like the
old ir_visitor path where each uniform is separate. This should allow us
to more easily make decisions about what to push.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit cfa056c6a5eadf87f92a71346c0dddd2a080e302
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Aug 18 11:42:02 2015 -0700
i965/vec4_nir: Get rid of the uniform_driver_location tracking
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit ce5e9139aa1eee78e9154ded84b724b0cecbece7
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Aug 18 11:20:40 2015 -0700
nir/lower_io: Separate driver_location and base offset for uniforms
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 0db8e87b4a16b123f7c0b44d54f23b535a136ee6
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Aug 18 11:18:55 2015 -0700
nir/intrinsics: Add a second const index to load_uniform
In the i965 backend, we want to be able to "pull apart" the uniforms and
push some of them into the shader through a different path. In order to do
this effectively, we need to know which variable is actually being referred
to by a given uniform load. Previously, it was completely flattened by
nir_lower_io which made things difficult. This adds more information to
the intrinsic to make this easier for us.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 6c33d6bbf9b54784e4498a81c73b712dca5dd737
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Aug 12 14:29:25 2015 -0700
nir: Pass a type_size() function pointer into nir_lower_io().
Previously, there were four type_size() functions in play - the i965
compiler backend defined scalar and vec4 type_size() functions, and
nir_lower_io contained its own similar functions.
In fact, the i965 driver used nir_lower_io() and then looped over the
components using its own type_size - meaning both were in play. The
two are /basically/ the same, but not exactly in obscure cases like
subroutines and images.
This patch removes nir_lower_io's functions, and instead makes the
driver supply a function pointer. This gives the driver ultimate
flexibility in deciding how it wants to count things, reduces code
duplication, and improves consistency.
v2 (Jason Ekstrand):
- One side-effect of passing in a function pointer is that nir_lower_io is
now aware of and properly allocates space for image uniforms, allowing
us to drop hacks in the backend
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
v2 Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit a23f82053d18c2f7d78e28551368437ded4c1a03
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Aug 24 16:39:24 2015 -0700
prog_to_nir: Don't allocate nir_variable with type vec4[0] for uniforms.
If there are no parameters, we don't need to create a nir_variable to
hold them...and allocating an array of length 0 is pretty bogus.
Should avoid i965 backend assertions in future patches Jason and I are
working on.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 640c472fd075814972b1276c5b0ed3a769aacda5
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Aug 12 14:19:17 2015 -0700
i965: Move type_size() methods out of visitor classes.
I want to use C function pointers to these, and they don't use anything
in the visitor classes anyway.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit c56899f41a904762225267cb9c543a0abd901ad5
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Aug 19 10:32:32 2015 -0700
i965: Make setup_vec4_uniform_value and _image_uniform_values take an offset
This way they don't implicitly increment the uniforms variable and don't
have to be called in-sequence during uniform setup.
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 8d8b8f58540abbdb8a006a38830a08346a0edf34
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Aug 19 09:56:57 2015 -0700
i965: Rename setup_vector_uniform_values to setup_vec4_uniform_value
The new name more accurately represents what it does: Set up a single vec4
uniform value.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 0ab29751b62680cd77195bb33cf18068bd73f2f3
Author: Rob Clark <robclark at freedesktop.org>
Date: Tue Aug 25 08:17:30 2015 -0400
freedreno/ir3: fix compile break after splitting out nir_control_flow.h
The commit:
commit b49371b8ede380f10ea3ab333246a3b01ac6aca5
Author: Connor Abbott <cwabbott0 at gmail.com>
AuthorDate: Tue Jul 21 19:54:18 2015 -0700
nir: move control flow modification to its own file
split out some control flow related APIs into a separate header, but did
not update drivers.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 8b2d0bb844e4c9b6141f68431b6e6dc135eb3503
Author: Rob Clark <robclark at freedesktop.org>
Date: Tue Aug 25 08:13:04 2015 -0400
freedreno/ir3: fix compile break after fxn->start_block removal
The commit:
commit 8e0d4ef3410ea07d9621df3e083bc3e7c1ad2ab0
Author: Kenneth Graunke <kenneth at whitecape.org>
AuthorDate: Thu Aug 6 18:18:40 2015 -0700
nir: Delete the nir_function_impl::start_block field.
removed the start_block field without fixing up drivers..
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 529acab22a3e21e0ed0c5243675aec6c0ee27e8f
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Jul 29 18:09:44 2015 +1000
mesa: enable texture stencil8 for multisample
This fixes GL45-CTS.gtf44.GL31Tests.texture_stencil8.texture_stencil8_gl44
from the ogl conform suite.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: 10.6 11.0 <mesa-stable at lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit e089ca26e1efc095fd38715def5f410cf7476ad5
Author: Brian Paul <brianp at vmware.com>
Date: Mon Aug 24 07:50:51 2015 -0600
mesa: make _mesa_bind_texture_unit() static
It's only called from the file it's defined in.
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
commit 8f378d1083179ea9e760688582faf95aea880b94
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Tue May 19 09:58:17 2015 -0700
mesa/formats: store whether or not a format is sRGB in gl_format_info
v2: remove extra newline.
v3: use bool instead of GLboolean.
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
commit 4f2cdd849738019ce9552ee1d5f8dafce8af3f10
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Aug 24 12:18:51 2015 -0700
nir: Use !block_ends_in_jump() in a few places rather than open-coding.
Connor introduced this helper recently; we should use it here too.
I had to move the function earlier in the file for it to be available.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit d7971b41ce3bd5ffce9580b3796b40d3591d6e5e
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Tue Jul 21 19:54:35 2015 -0700
nir/cf: reimplement nir_cf_node_remove() using the new API
This gives us some testing of it. Also, the old nir_cf_node_remove()
wasn't handling phi nodes correctly and was calling cleanup_cf_node()
too late.
Signed-off-by: Connor Abbott <connor.w.abbott at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit fc7f2d2364a98d4ec8fb8627b03c6f84b353998c
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Tue Jul 21 19:54:34 2015 -0700
nir/cf: add new control modification API's
These will help us do a number of things, including:
- Early return elimination.
- Dead control flow elimination.
- Various optimizations, such as replacing:
if (foo) {
...
}
if (!foo) {
...
}
with:
if (foo) {
...
} else {
...
}
Signed-off-by: Connor Abbott <connor.w.abbott at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 476eb5e4a16efdbc54c4418e44b1f38989026add
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Tue Jul 21 19:54:33 2015 -0700
nir/cf: use a cursor for inserting control flow
Signed-off-by: Connor Abbott <connor.w.abbott at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit d356f84d4ceb9fb63e4b254ab8b26ce891c2f2b9
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Tue Jul 21 19:54:32 2015 -0700
nir/cf: add split_block_cursor()
This is a helper that will be shared between the new control flow
insertion and modification code.
Signed-off-by: Connor Abbott <connor.w.abbott at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 58a360c6b8aead1fec34aea298654ab544e7c8e8
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Tue Jul 21 19:54:31 2015 -0700
nir/cf: add split_block_before_instr()
Signed-off-by: Connor Abbott <connor.w.abbott at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 6e47a34b29459dcf977a8c1223805cb0a275a8c8
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Tue Jul 21 19:54:30 2015 -0700
nir/cf: add a cursor structure
For now, it allows us to refactor the control flow insertion API's so
that there's a single entrypoint (with some wrappers). More importantly,
it will allow us to reduce the combinatorial explosion in the extract
function. There, we need to specify two points to extract, which may be
at the beginning of a block, the end of a block, or in the middle of a
block. And then there are various wrappers based off of that (before a
control flow node, before a control flow list, etc.). Rather than having
9 different functions, we can have one function and push the actual
logic of determining which variant to use down to the split function,
which will be shared with nir_cf_node_insert().
In the future, we may want to make the instruction insertion API's as
well as the builder use this, but that's a future cleanup.
Signed-off-by: Connor Abbott <connor.w.abbott at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 6f5c81f86f9b1b08b57435562be657fb2d220408
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Tue Jul 21 19:54:29 2015 -0700
nir/cf: fix link_blocks() when there are no successors
When we insert a single basic block A into another basic block B, we
will split B into C and D, insert A in the middle, and then splice
together C, A, and D. When we splice together C and A, we need to move
the successors of A into C -- except A has no successors, since it
hasn't been inserted yet. So in move_successors(), we need to handle the
case where the block whose successors are to be moved doesn't have any
successors. Fixing link_blocks() here prevents a segfault and makes it
work correctly.
Signed-off-by: Connor Abbott <connor.w.abbott at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 6d028749ac593b6c724ab86a42bf969da47cc569
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Tue Jul 21 19:54:28 2015 -0700
nir/cf: clean up jumps when cleaning up CF nodes
We may delete a control flow node which contains structured jumps to
other parts of the program. We need to remove the jump as a predecessor,
as well as remove any phi node sources which reference it. Right now,
the same problem exists for blocks that don't end in a jump instruction,
but with the new API it shouldn't be an issue, since blocks that don't
end in a jump must either point to another block in the same extracted
CF list or not point to anything at all.
Signed-off-by: Connor Abbott <connor.w.abbott at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 211c79515d2d4cde12cc6a19bb064692b2de3f26
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Tue Jul 21 19:54:27 2015 -0700
nir/cf: remove uses of SSA definitions that are being deleted
Unlike calling nir_instr_remove(), calling nir_cf_node_remove() (and
later in the series, the nir_cf_list_delete()) implies that you're
removing instructions that may still have uses, except those
instructions are never executed so any uses will be undefined. When
cleaning up a CF node for deletion, we must clean up any uses of the
deleted instructions by making them point to undef instructions instead.
Signed-off-by: Connor Abbott <connor.w.abbott at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 633cbbc0682b1cec3107398a21a057697e8572aa
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Tue Jul 21 19:54:26 2015 -0700
nir/cf: handle jumps better in stitch_blocks()
In particular, handle the case where the earlier block ends in a jump
and the later block is empty. In that case, we want to preserve the jump
and remove any traces of the later block. Before, we would only hit this
case when removing a control flow node after a jump, which wasn't a
common occurance, but we'll need it to handle inserting a control flow
list which ends in a jump, which should be more common/useful.
Signed-off-by: Connor Abbott <connor.w.abbott at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 940873bf22c90db79d065f14ff44dab12415feb0
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Tue Jul 21 19:54:25 2015 -0700
nir/cf: handle jumps in split_block_end()
Before, we would only split a block with a jump at the end if we were
inserting something after a block with a jump, which never happened in
practice. But now, we want to use this to extract control flow lists
which may end in a jump, in which case we really need to do the correct
patching up. As a side effect, when removing jumps we now correctly
insert undef phi sources in some corner cases, which can't hurt.
Signed-off-by: Connor Abbott <connor.w.abbott at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit f596e4021c4c1b2ce95ff32606e2f217955504bd
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Tue Jul 21 19:54:24 2015 -0700
nir/cf: add block_ends_in_jump()
Signed-off-by: Connor Abbott <connor.w.abbott at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 788d45cb478d6285fe6811c87b4f1db1daded6d9
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Tue Jul 21 19:54:23 2015 -0700
nir/cf: handle phi nodes better in split_block_beginning()
Signed-off-by: Connor Abbott <connor.w.abbott at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 747ddc3cdd51cc3786894e2ba56d86334a7051a5
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Tue Jul 21 19:54:22 2015 -0700
nir/cf: split up and improve nir_handle_remove_jumps()
Before, the process of removing a jump and wiring up the remaining block
correctly was atomic, but with the new control flow modification it's
split into two parts: first, we extract the jump, which creates a new
block with re-wired successors as well as a free-floating jump, and then
we delete the control flow containing the jump, which removes the entry
in the predecessors and any phi node sources. Split up
nir_handle_remove_jumps() to accomodate this, and add the missing
support for removing phi node sources.
Signed-off-by: Connor Abbott <connor.w.abbott at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 13482111d0dd9649d4b14ed05df344d5a2cea3de
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Tue Jul 21 19:54:21 2015 -0700
nir/cf: add remove_phi_src() helper
Signed-off-by: Connor Abbott <connor.w.abbott at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit f41e108d8bdd360caedd1497dc676c928c7f18a3
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Tue Jul 21 19:54:20 2015 -0700
nir: add nir_foreach_phi_src_safe()
Signed-off-by: Connor Abbott <connor.w.abbott at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 762ae436ea578651c9f8a50620196b5d744b8eee
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Tue Jul 21 19:54:19 2015 -0700
nir/cf: add insert_phi_undef() helper
Signed-off-by: Connor Abbott <connor.w.abbott at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit b49371b8ede380f10ea3ab333246a3b01ac6aca5
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Tue Jul 21 19:54:18 2015 -0700
nir: move control flow modification to its own file
We want to start reworking and expanding this code, but it'll be a lot
easier to do once we disentangle it from the rest of the stuff in nir.c.
Unfortunately, there are a few unavoidable dependencies in nir.c on
methods we'd rather not expose publicly, since if not used in very
specific situations they can cause Bad Things (tm) to happen. Namely, we
need to do some magical control flow munging when adding/removing jumps.
In the future, we may disallow adding/removing jumps in
nir_instr_insert_*() and nir_instr_remove(), and use separate functions
that are part of the control flow modification code, but for now we
expose them and put them in a separate, private header.
Signed-off-by: Connor Abbott <connor.w.abbott at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 1c53f89696124de2c7e93665ef8b07bc17b2cb86
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Tue Jul 21 19:54:17 2015 -0700
nir: make cleanup_cf_node() not use remove_defs_uses()
cleanup_cf_node() is part of the control flow modification code, which
we're going to split into its own file, but remove_defs_uses() is an
internal function used by nir_instr_remove(). Break the dependency by
making cleanup_cf_node() use nir_instr_remove() instead, which simply
calls remove_defs_uses() and then removes the instruction from the list.
nir_instr_remove() does do extra things for jumps, though, so we avoid
calling it on jumps which matches the previous behavior (this will be
fixed later in the series).
Signed-off-by: Connor Abbott <connor.w.abbott at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 9d5944053ca7bed58b299211fe8028274d480b5b
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Tue Jul 21 19:54:16 2015 -0700
nir: inline block_add_pred() a few places
It was being used to initialize function impls and loops, even though
it's really a control flow modification helper. It's pretty trivial, so
just inline it to avoid the dependency.
Signed-off-by: Connor Abbott <connor.w.abbott at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit c7df141c71c3fa0bdbcf6d0bbd4b8158a35c7f5a
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Tue Jul 21 19:54:15 2015 -0700
nir/validate: check successors/predecessors more carefully
We should be checking almost everything now.
Signed-off-by: Connor Abbott <connor.w.abbott at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 8e0d4ef3410ea07d9621df3e083bc3e7c1ad2ab0
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Aug 6 18:18:40 2015 -0700
nir: Delete the nir_function_impl::start_block field.
It's simply the first nir_cf_node in the nir_function_impl::body list,
which is easy enough to access - we don't to store a pointer to it
explicitly. Removing it means we don't need to maintain the pointer
when, say, splitting the start block when modifying control flow.
Thanks to Connor Abbott for suggesting this.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 9f00af672b59766008994a190730d48ae03773dd
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Fri Jul 31 09:25:56 2015 -0700
mesa/formats: only do type and component lookup for uncompressed formats
Only uncompressed formats have a non-void type and actual
components per pixel. Rename _mesa_format_to_type_and_comps
to _mesa_uncompressed_format_to_type_and_comps and require
callers to check if the format is not compressed.
v2. include compressed format cases to avoid gcc warnings (Chad).
Reviewed-by: Chad Versace <chad.versace at intel.com>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
commit 000e225360c020e8b3de142c4c898baad321d242
Author: Rob Clark <robclark at freedesktop.org>
Date: Sat Aug 15 11:57:22 2015 -0400
freedreno/a4xx: formats update
Fixes glamor, which wants to use R8 integer textures.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit afb6c24a207fe7b9917644b940e4c5d1870c5c92
Author: Rob Clark <robclark at freedesktop.org>
Date: Mon Aug 24 12:58:08 2015 -0400
freedreno: update generated headers
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 4e5752e2b78243a71766538f62ca0a80488047a7
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Sun Aug 23 09:24:57 2015 +0100
i965: Always re-emit the pipeline select during invariant state emission
On the older platforms where we don't have logical contexts preserving
state across batches, we emit the invariant state setup on every batch
using the brw_invariant_state atom. This includes the pipeline selection
which is cached with the introduction of
commit 0e0e23ef537c9add672ff322f34e129a07edc55e
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Wed Apr 22 11:43:50 2015 -0700
i965/state: Emit pipeline select when changing pipelines
However, we do not reset the cache between batches on context-less
platforms resulting in us not setting the pipeline selection and can
cause GPU hangs if a media pipelined was loaded in the meantime (e.g.
mixing mplayer/gstreamer using libva and gnome-shell). A simple solution
is to just forcibly re-emit the pipeline select along with the invariant
state and reset the cache at that point.
Reported-and-tested-by: Tomasz C. <tomaszc at o2.pl>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91254
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Jordan Justen <jordan.l.justen at intel.com>
Cc: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
commit a83c36b5c0c64c717ced76db89bab900006648aa
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Aug 23 18:57:44 2015 +0200
Revert "radeon/winsys: increase the IB size for VM"
This reverts commit 567394112d904096abff1d994ab952f475dfb444.
It regressed performance. It looks like smaller IBs are better, because
the GPU goes idle quicker and there is less waiting for buffers and fences.
Cc: 11.0 <mesa-stable at lists.freedesktop.org>
commit e18c29b03105567cf20bc235ce23cf08986cc537
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Aug 23 03:11:09 2015 -0400
nv50: fix 2d engine blits for 64- and 128-bit formats
This fixes bin/ext_framebuffer_multisample-formats all_samples
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
commit a6ad49cbbd599aec054d0a3163fff5ad724f2b18
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Aug 23 02:56:45 2015 -0400
nv50: account for the int RT0 rule for alpha-to-one/cov
Same as commit 1af0641db but for nvc0. If an integer texture is
bound to RT0, don't do alpha-to-one or alpha-to-coverage.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
commit 45971fd0df1cbfc400f89f2e8df206625b40d65f
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Jul 27 13:13:49 2015 +1000
mesa/arb_gpu_shader_fp64: add support for glGetUniformdv
This was missed when I did fp64, I've sent a piglit test to cover
the case as well.
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit abbf05cfc2bea0787bcf710ef984d73ee8ba8f9e
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Aug 22 23:59:50 2015 -0400
nv50,nvc0: disable depth bounds test on blit
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
commit 3a1ab2348050fd32f41553b9febfd9972b5761aa
Author: Neil Roberts <neil at linux.intel.com>
Date: Wed Aug 19 18:55:44 2015 -0700
i965/bdw: Fix 3DSTATE_VF_INSTANCING when the edge flag is used
When the edge flag element is enabled then the elements are slightly
reordered so that the edge flag is always the last one. This was
confusing the code to upload the 3DSTATE_VF_INSTANCING state because
that is uploaded with a separate loop which has an instruction for
each element. The indices used in these instructions weren't taking
into account the reordering so the state would be incorrect.
v2: Use nr_elements instead of brw->vb.nr_enabled so that it will cope
when gl_VertexID is used.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91292
Cc: <mesa-stable at lists.freedesktop.org>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Tested-by: Mark Janes <mark.a.janes at intel.com>
commit fb02b4ec482762ccf2a9fedf24fe6f50787932a9
Author: Neil Roberts <neil at linux.intel.com>
Date: Mon Jul 13 18:01:14 2015 +0100
i965: Swap the order of the vertex ID and edge flag attributes
The edge flag data on Gen6+ is passed through the fixed function hardware as
an extra attribute. According to the PRM it must be the last valid
VERTEX_ELEMENT structure. However if the vertex ID is also used then another
extra element is added to source the VID. This made it so the vertex ID is in
the wrong register in the vertex shader and the edge attribute is no longer in
the last element.
v2: Also implement for BDW+
v3 [by Ben]: Remove 10.5 tag. Too late.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84677
Cc: <mesa-stable at lists.freedesktop.org>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Tested-by: Ben Widawsky <ben at bwidawsk.net>
Tested-by: Mark Janes <mark.a.janes at intel.com>
commit 50932268aad0cc21511f370793e77c76e038bd06
Author: Glenn Kennard <glenn.kennard at gmail.com>
Date: Sun Aug 23 01:01:31 2015 +0200
r600g: Fix assert in tgsi_cmp
Fixes https://bugs.freedesktop.org/show_bug.cgi?id=91726
Signed-off-by: Glenn Kennard <glenn.kennard at gmail.com>
Cc: "11.0" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied at gmail.com>
commit 5abbd1caccf4653ac1a8760de68d8ed101c814d8
Author: Alexander von Gluck IV <kallisti5 at unixzen.com>
Date: Tue Aug 18 20:47:59 2015 -0500
egl: scons: fix the haiku build, do not build the dri2 backend
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit a8c5c62359454ec4e543a50e3048d726df2d0dd7
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Aug 22 13:28:16 2015 +0100
docs: add 11.1.0-devel release notes template, bump version
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit d7bafcafd329d23ab0c76e3a6ae06277506f50f3
Author: Boyan Ding <boyan.j.ding at gmail.com>
Date: Fri Aug 21 21:44:36 2015 +0800
egl/wayland: define set_cloexec_or_close only when mkostemp is not present
Fixes a compiler warning of defined but not used function when
HAVE_MKOSTEMP is defined.
Fixes: eb3e2562a4b(configure.ac: check for mkostemp())
Signed-off-by: Boyan Ding <boyan.j.ding at gmail.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
commit ec256eceedd0a00b41c2c94d5a32609f0e1870b2
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Aug 22 12:58:03 2015 +0100
mapi: ship ARB_tessellation_shader.xml
Fixes: e2b59a39cbb(mapi: add ARB_tessellation_shader)
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 79da1b262de0df61c1bf74a55c9b18cd6eeb2fc5
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Aug 22 12:15:27 2015 +0100
nouveau: add codegen/unordered_set.h to the tarball
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit a8f451cd0e06278699fb7139213bbc6c98a9cc52
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Aug 21 02:01:42 2015 +0100
winsys/sw/kms-dri: don't attempt to bundle the sconscript
The build/file was removed with an earlier commit while the EXTRA_DIST
was forgotten.
Fixes: 66d77cd71c6 (scons: don't build the kms-dri winsys)
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 4a21da709be3b2aa8d4b22830d56a5cc7661ccad
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Aug 20 22:55:49 2015 +0100
winsys/amdgpu: automake: remove missing headers
The files are not referenced in any other place in whole of
mesa. They are likely remnants of the early development stage.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit cfbcabe673f0657a96752c5db18671989b745a95
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Aug 20 22:52:49 2015 +0100
automake: build all drivers but vc4 during distcheck
vc4 conflicts with ilo, when build on x86 as it's build for emulation
purposes. In that mode a i965-like symbol is exported by vc4, which
conflicts with the ilo one in the gallium-dri megadriver.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 4b5936335b0a253e61473ed026d0f6309b169859
Author: Mauro Rossi <issor.oruam at gmail.com>
Date: Tue Aug 18 11:53:32 2015 +0200
android: enable amdgpu winsys in radeonsi driver
Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 6aaa814995d922d6f9cc68bc26276fd752866ceb
Author: Mauro Rossi <issor.oruam at gmail.com>
Date: Tue Aug 18 11:53:31 2015 +0200
android: fix cflags and includes for amdgpu winsys
Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 807b1e5b05dacd46b5f563f5c6e561e660a2872e
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Aug 22 11:04:11 2015 +0100
docs: add news item and link release notes for 10.6.5
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 32cd1252b8c816c1662ac4b95f74e86d797bc894
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Aug 22 11:00:47 2015 +0100
docs: add sha256 checksums for 10.6.5
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit fa34225167396008e75e93f23696666caba8a7bf)
commit fa52cf0ccf3f109b3119ca0980bb1dcba45e8911
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Aug 22 10:20:54 2015 +0100
docs: add release notes for 10.6.5
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit a43b3dd99bd4c114d0f3e90f4fd4792164fe7539)
commit 6817e0f1ce71d2a6d347d4c182f2cf4742dd5deb
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Fri Aug 21 15:28:22 2015 +0100
i965: Move control flush into pipelined conditional render
The nv_conditional_render piglits were sporadically failing. Moving
the control flush from the write and placing it just before the read
was sufficient to make the piglits pass a 1000/1000 times. The bspec
says that the flush enable bit "waits until all previous writes of
immediate data from post sync circles are complete before executing the
next command" - the operative word being previous!
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90691
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Neil Roberts <neil at linux.intel.com>
Cc: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit eb2776504ae32feaf41a5bad9f09f154045e96a3
Author: Eric Anholt <eric at anholt.net>
Date: Fri Aug 21 10:57:24 2015 -0700
vc4: Actually allow math results to allocate into r4.
I switched us to tracking whether the results *could* go to r4, but then
didn't make a separate register class for the class bits that included r4.
Switch the "any" class to actually be "any", and name the "any but r4"
class more appropriately.
total instructions in shared programs: 96798 -> 94680 (-2.19%)
instructions in affected programs: 62736 -> 60618 (-3.38%)
commit 89b1b33f44bc6ce71109ac8668529c30b6d6d910
Author: Eric Anholt <eric at anholt.net>
Date: Fri Aug 21 00:08:13 2015 -0700
vc4: Fold the 16-bit integer pack into the instructions generating it.
total instructions in shared programs: 97580 -> 96798 (-0.80%)
instructions in affected programs: 52826 -> 52044 (-1.48%)
commit 7e0b868cf31003ada12063398fb91485ed8043dd
Author: Eric Anholt <eric at anholt.net>
Date: Fri Aug 21 00:04:36 2015 -0700
vc4: Reuse QPU dumping for packing bits in QIR.
commit 4ae137534a8718db4611782dbfec773504b6e3be
Author: Eric Anholt <eric at anholt.net>
Date: Tue Aug 18 20:26:05 2015 -0700
vc4: Make _dest variants of qir ALU helpers to provide an explicit dest.
commit 2002438c91981b22991ae70fefc5d492dda72835
Author: Eric Anholt <eric at anholt.net>
Date: Fri Aug 21 09:22:32 2015 -0700
vc4: Use the SSA defs list for figuring out eligible MOVs for copy prop.
I thought I'd converted this over previously. It was copy propagating
MOVs badly with the new destination packing flags.
commit 20746c2e7d8d065445bbb30f0d1383c30459a784
Author: Krzysztof Sobiecki <sobkas at gmail.com>
Date: Thu Aug 20 23:19:30 2015 +0200
st/nine: Always use user constant buffers
We had several reports of users hitting bugs
with the other path to upload constants,
and switching to the user constant buffer
path solves the bugs.
User constant buffers are expected to be slower
for Nvidia cards, so ideally this patch should be
reverted when the path is fixed.
Reviewed-by: Axel Davy <axel.davy at ens.fr>
Signed-off-by: Krzysztof Sobiecki <sobkas at gmail.com>
commit f57e9c77e388e1c5373265f4bc15434e63477757
Author: Axel Davy <axel.davy at ens.fr>
Date: Sun Aug 16 13:11:50 2015 +0200
st/nine: Silent warning in nine_ff
release build was complaining
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 3cc205bbeb19d417b17be0f6200cb5cda9adca8a
Author: Axel Davy <axel.davy at ens.fr>
Date: Sun Aug 16 13:11:27 2015 +0200
st/nine: Silent warning in sm1_declusage_to_tgsi
release build was complaining
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit d48cab9fa6b75db054e3a53819b465611923e9bc
Author: Axel Davy <axel.davy at ens.fr>
Date: Sun Aug 16 12:58:41 2015 +0200
st/nine: Silent warning in NineCubeTexture9_ctor
The compiler was complaining the value may be uninitialised
when it is used (which is wrong). Initialize to NULL to silent
the warning.
commit 2f02d5e814904d7a5c041d6869751731712e8195
Author: Axel Davy <axel.davy at ens.fr>
Date: Sun Aug 16 12:57:40 2015 +0200
st/nine: Silent warning in update_vertex_buffer
There was an unused variable
commit 719f124620d3c9b4d6ce14db3dbfc7af05626e5b
Author: Axel Davy <axel.davy at ens.fr>
Date: Sun Aug 9 19:06:01 2015 +0200
st/nine: Catch setting the same shader
This is quite rare that an app does set again
the same shaders, but it isn't an expensive check
either.
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit eba3c390a3c6221781ca4d9c344c6f448e177b6c
Author: Axel Davy <axel.davy at ens.fr>
Date: Sun Aug 9 19:02:02 2015 +0200
st/nine: Avoid Constant upload when there is no change
It is very common for d3d9 apps to set again the constants
they need before every draw call, even if nothing changed.
Since we are mostly gpu bound, it is better to check
for change, and upload constants again (and thus use
gpu bandwith) only if the constants changed.
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 1a747094ed0ab32541936dd18931f382901affe6
Author: Axel Davy <axel.davy at ens.fr>
Date: Sat Jul 25 17:54:26 2015 +0200
st/nine: Fix the number of texture stages
The number of texture stages is 8.
'tex_stage' array was too big, and thus
the checks with 'Elements(state->ff.tex_stage)' were passing,
causing some invalid API calls to pass, and crash because of
out of bounds write since bumpmap_vars was just the correct size.
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit f15ff98e2c53f6ce62443b24e3a9cf79c60ddff7
Author: Axel Davy <axel.davy at ens.fr>
Date: Thu May 14 19:24:57 2015 +0200
st/nine: Use CSO cache for sampler views
The CSO cache unbinds views that are not needed anymore,
which we don't do.
It checks for change before committing the views.
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 98f786b270b3e55a1e8a7bdc8182e436702748a2
Author: Axel Davy <axel.davy at ens.fr>
Date: Thu May 14 19:10:41 2015 +0200
st/nine: Calculate dummy sampler state only once
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit f5effeb8eaf16e39a2f561b4b277f3810a69fc88
Author: Axel Davy <axel.davy at ens.fr>
Date: Thu May 14 15:42:50 2015 +0200
st/nine: Better check shader constant limits
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit bae2c7c15444b02a4820e3182c345545bd348561
Author: Axel Davy <axel.davy at ens.fr>
Date: Thu Aug 13 19:24:02 2015 +0200
st/nine: Remove NINED3DRS_ZBIASSCALE
It wasn't giving the expected result.
This fixes some object being transparents
in games like FEAR.
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 6379a28aa75a38676120891b355c434bec4125e1
Author: Axel Davy <axel.davy at ens.fr>
Date: Sun May 17 00:22:33 2015 +0200
st/nine: Implement special DOTPRODUCT3 behaviour
Taken from wine tests
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 791b794a849f4576e59bda29680bdd49ed0429a9
Author: Axel Davy <axel.davy at ens.fr>
Date: Sat May 16 12:14:54 2015 +0200
st/nine: Implement ff vertex data passthrough
Fixes Wine tests
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit fb6c76f1bac039cddc66cb823e85437981ce8bef
Author: Axel Davy <axel.davy at ens.fr>
Date: Sat May 16 01:24:29 2015 +0200
st/nine: Change nine_state_update order
nine_update_state called every draw call.
This patch attemps to change the order
of the checks to have better control flow
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 4a00e4cdc970582df338ebf880168a4ef4ec05d9
Author: Axel Davy <axel.davy at ens.fr>
Date: Thu May 14 01:27:33 2015 +0200
st/nine: Programmable ps D3DTTSS_PROJECTED support
The implementation used Wine tests for conformance
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit b7261528ea964f6cba3173f72608c1afc0750d6b
Author: Axel Davy <axel.davy at ens.fr>
Date: Tue May 12 23:49:54 2015 +0200
st/nine: Complete ff texture transform implementation
Wine tests were used to get it right.
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit dcb6f764cfb13c21b5bc56e973daf05db5c1bc1c
Author: Axel Davy <axel.davy at ens.fr>
Date: Sat Aug 15 22:52:19 2015 +0200
st/nine: Change a few advertised caps
There were flags all sm3 cards do advertise,
and we weren't.
Some games can trigger buggy rendering path
if the caps are not what they expect.
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit c2480bbab1a15960d8b30dda8351a6869a424679
Author: Axel Davy <axel.davy at ens.fr>
Date: Fri May 8 19:50:15 2015 +0200
st/nine: Advertise Fog flags
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit fcca7ff38a6ba923abd910f50a8e2bcf6560e6ae
Author: Axel Davy <axel.davy at ens.fr>
Date: Sun Aug 16 14:59:52 2015 +0200
st/nine: Revert to userbuf path when needed
Automatically switch to userbuf path when
we would need to upload fog or bumpmat
constants
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 8f39ffc11e8b6fdf7c940f9c1853a362a886977a
Author: Axel Davy <axel.davy at ens.fr>
Date: Tue May 12 21:56:04 2015 +0200
st/nine: Finish Fog implementation
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 69de5d626f2e67e74e4de94ce13f7ac50fa52161
Author: Axel Davy <axel.davy at ens.fr>
Date: Mon May 11 21:32:57 2015 +0200
st/nine: Rework shader states
Separate state setting and commit
Changes how the shader key is computed
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 854778ea0fea474eea0c984f1c0fc32aed91f10e
Author: Axel Davy <axel.davy at ens.fr>
Date: Sun May 10 11:42:25 2015 +0200
st/nine: Remove some useless variables
Signed-off-by: Axel Davy <axel.davy at ens.fr>
Reviewed-by: David Heidelberg <david at ixit.cz>
commit cb0816c0f6e2ccf81cbb433206b616f4662a803a
Author: Axel Davy <axel.davy at ens.fr>
Date: Sun May 10 12:01:10 2015 +0200
st/nine: Fix nine_ff_ps_key padding
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit dd4802c8deedc0b2bad7d361c487761be31f2b56
Author: Axel Davy <axel.davy at ens.fr>
Date: Fri May 8 19:48:45 2015 +0200
st/nine: Begin programmable shader fog support
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 2dd59a2d286cca8ccbc7a25622cd7036cdbf437d
Author: Axel Davy <axel.davy at ens.fr>
Date: Fri May 8 19:26:20 2015 +0200
st/nine: Fix fixed function fog support
Previous code had only a subcase of fog working right.
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 87ec6b56b28c25d4184422c40f576c24ebe7cd75
Author: Axel Davy <axel.davy at ens.fr>
Date: Tue Mar 24 11:06:22 2015 +0100
st/nine: Rework ff constant buffers
Always use a user constant buffer for ff.
It means we have to:
. commit the user constant buffer for ff when we use it
. commit back the non-ff constant buffer when we stop using it
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 993e68fa6a431a7c7c451c738e07d02a84ea40e4
Author: Axel Davy <axel.davy at ens.fr>
Date: Tue Mar 24 10:47:35 2015 +0100
st/nine: Rework constant buffer state handling
We have two paths:
. One that uses a fixed constant buffer, and updates it when needed
. One that uses a user constant buffer, and uploads it when needed.
This patch separates the preparation of the constant buffer
and the commit.
It also removes NineDevice9_RestoreNonCSOState, which was
used to restore all states. Instead the commit of the constant
buffer is moved to nine_state, and the other field settings
moved to other functions where more appropriate.
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit a3f0d21da9a33e58a4be41f65f77eebe1dd85841
Author: Axel Davy <axel.davy at ens.fr>
Date: Tue Mar 24 10:10:25 2015 +0100
st/nine: Rework blend states
Separate state preparation and state commit
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit b06f3ee6f4ebf6ad403e7ee917c54bef85899c19
Author: Axel Davy <axel.davy at ens.fr>
Date: Sat Jan 3 11:36:09 2015 +0100
st/nine: Improve fallback when driver doesn't support user buffers.
For now the path updated is only used by Amd drivers, but a later
patch will make it used by all drivers. Some drivers like llvmpipe
doesn't support the uploading of constants from user buffers, so improve
the path to work for all drivers
Inspired from the gl state tracker.
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit a7ce3cd0d3a9f3580d02afe5a4fc6588d20aba6b
Author: Axel Davy <axel.davy at ens.fr>
Date: Sun Feb 15 16:22:43 2015 +0100
st/nine: Avoid useless updates in SetSamplerState
Check for redundant settings
Signed-off-by: Axel Davy <axel.davy at ens.fr>
Reviewed-by: David Heidelberg <david at ixit.cz>
commit 5a2302b5ece2edf944b474eeb19ad7fc17906e7d
Author: Axel Davy <axel.davy at ens.fr>
Date: Tue Mar 24 10:16:59 2015 +0100
st/nine: Rework rasterizer states
Separate state preparation and state commit
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 71616d0c501077a04deb4f2a3cc115b50634763d
Author: Axel Davy <axel.davy at ens.fr>
Date: Fri May 15 23:52:09 2015 +0200
st/nine: Reorder DSA state settings
Separate state preparation and state commit
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 06285530566ea3387b6eb3f8e1a0443132c3659b
Author: Axel Davy <axel.davy at ens.fr>
Date: Tue Mar 24 09:35:18 2015 +0100
st/nine: Reorder nine_state.
Instead of mixing state preparation (filling pipe_****)
and state commit (pipe->set_*****),
begin doing so in two separate functions.
This will allow to implement efficient Stateblocks,
and eventually lead to optimisation where the complete
pipe_*** structure is only partially updated.
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 99537f68db829bd4708eb8e1b1ef0948f3dd3c66
Author: Axel Davy <axel.davy at ens.fr>
Date: Sun Feb 15 09:19:16 2015 +0100
st/nine: Remove group_mask argument from nine_update_state
It was only used to discriminate update framebuffer vs update
everything. Instead use two functions.
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 360ba5b74858b3854784e3d4678c242140088395
Author: Tiziano Bacocco <tizbac2 at gmail.com>
Date: Fri Jan 30 20:10:38 2015 +0100
st/nine: Implement TEXBEM,TEXBEML and BEM
Signed-off-by: Tiziano Bacocco <tizbac2 at gmail.com>
commit 620f3e9bfe4bc56c65638a49b1c4f1d5cbef057d
Author: Patrick Rudolph <siro at das-labor.org>
Date: Sun May 17 12:46:42 2015 +0200
st/nine: Fix use of uninitialized values
Set all values to 0 after allocation. Found using valgrind.
Reviewed-by: Axel Davy <axel.davy at ens.fr>
Signed-off-by: Patrick Rudolph <siro at das-labor.org>
commit 248833ff4072da4f3362dc9f0eab84eb015f3964
Author: Patrick Rudolph <siro at das-labor.org>
Date: Sat May 16 19:47:00 2015 +0200
st/nine: Prevent possible crash
In case NineBaseTexture9_ctor returns an error
This->surfaces[l] might be NULL.
Reviewed-by: Axel Davy <axel.davy at ens.fr>
Signed-off-by: Patrick Rudolph <siro at das-labor.org>
commit bc6c80e54714e939e4bc116374f410680e7a3632
Author: Patrick Rudolph <siro at das-labor.org>
Date: Tue May 19 20:18:29 2015 +0200
st/nine: Return correct error codes in NineDevice9_Reset
Allow more than two errors, and return D3DERR_INVALIDCALL
for failed display resolution changes.
Reviewed-by: Axel Davy <axel.davy at ens.fr>
Signed-off-by: Patrick Rudolph <siro at das-labor.org>
commit d0a4374e1a04ba16f36ea91fdb390633fe941978
Author: Patrick Rudolph <siro at das-labor.org>
Date: Wed May 13 19:51:30 2015 +0200
st/nine: Fail on D3DUSAGE_DYNAMIC for D3DPOOL_SCRATCH textures
Texture with pool D3DPOOL_SCRATCH and D3DPOOL_MANAGED
cannot be used with flag D3DUSAGE_DYNAMIC.
Signed-off-by: Patrick Rudolph <siro at das-labor.org>
commit f396cd43ab148ff77b8df3344610ee6f2224d21d
Author: Axel Davy <axel.davy at ens.fr>
Date: Thu May 14 17:22:26 2015 +0200
st/nine: Fix Lock Checks for Compressed textures
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit d0daec1797a22b51f7a3f5aa585ad6826af06cd3
Author: Axel Davy <axel.davy at ens.fr>
Date: Thu May 14 17:01:40 2015 +0200
st/nine: Impose restrictions on DXTN texture sizes
This is the expected behaviour.
Fixes wine tests.
Signed-off-by: Axel Davy <axel.davy at ens.fr>
Reviewed-by: David Heidelberg <david at ixit.cz>
commit 48d895aa4b2475ef0af234b832d92d0ac4a47761
Author: Patrick Rudolph <siro at das-labor.org>
Date: Wed May 13 19:43:04 2015 +0200
st/nine: Return NULL pointer in lock error cases
Tests showed, that in case of errors, the pBits pointer is set to NULL.
The pBits field isn't set to NULL in case of an already locked object.
Reviewed-by: Axel Davy <axel.davy at ens.fr>
Signed-off-by: Patrick Rudolph <siro at das-labor.org>
commit 74a77a4c1a5dafccbad0ff8c7fb55156c6643685
Author: Patrick Rudolph <siro at das-labor.org>
Date: Wed May 13 07:19:11 2015 +0200
st/nine: Fix resource SetPriority/GetPriority
Return 0 for non MANAGED textures and surfaces.
Fixes failing wine d3d9 tests device.c test_resource_priority.
Reviewed-by: Axel Davy <axel.davy at ens.fr>
Signed-off-by: Patrick Rudolph <siro at das-labor.org>
commit 40a8943f53ff42f2a3b782e42d8a79711d814ab8
Author: Patrick Rudolph <siro at das-labor.org>
Date: Tue May 12 20:28:17 2015 +0200
st/nine: Clean GetPrivateData
Move the assert to return error codes in the correct order.
Always set the pSizeOfData to the required buffer size.
Fixes failing wine test device.c test_private_data()
Reviewed-by: Axel Davy <axel.davy at ens.fr>
Signed-off-by: Patrick Rudolph <siro at das-labor.org>
commit 9ba3f83592730e98cb5be0fbc88f1e40ff5471a8
Author: Patrick Rudolph <siro at das-labor.org>
Date: Mon Apr 20 19:26:55 2015 +0200
st/nine: Allow lock coordinates outside range
This fixes wine test device.c test_lockrect_invalid()
Mimic WindowsXp behaviour and allow negative values in the rectangle passed.
Add comment to point out behaviour used.
Reviewed-by: Axel Davy <axel.davy at ens.fr>
Signed-off-by: Patrick Rudolph <siro at das-labor.org>
commit bb1c2c2aa3b15ee1fdf8b8085cc1ca9f8ef04ed9
Author: Patrick Rudolph <siro at das-labor.org>
Date: Tue May 12 20:07:09 2015 +0200
st/nine: Fix GenerateMipSubLevels potential crash
For the case of D3DPOOL_MANAGED textures, This->base.resource can be NULL
at the start of the function. In This case, UploadSelf will take care
of the defining. Assign resource after the UploadSelf call
to prevent NULL pointer exception.
Reviewed-by: Axel Davy <axel.davy at ens.fr>
Signed-off-by: Patrick Rudolph <siro at das-labor.org>
commit 3bcab9ba75b24bd6cabcd9d31165ad4c1fe9d75c
Author: Axel Davy <axel.davy at ens.fr>
Date: Sat May 16 18:40:02 2015 +0200
st/nine: Fix FillColor Flag check
IT is better check if the surface was created with RT flag,
instead of checking capability (llvmpipe was complaining)
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit ef8ade6f09410b734fb84861a8bce23dc9e49afc
Author: Axel Davy <axel.davy at ens.fr>
Date: Fri May 8 01:29:35 2015 +0200
st/nine: Fix StretchRect checks
Fixes Wine tests
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit c57f777b095fbbb6273fccfe7ea2d1ced5fbc0a4
Author: Axel Davy <axel.davy at ens.fr>
Date: Fri May 8 16:54:53 2015 +0200
st/nine: Implement EvictManagedResources
EvictManagedResources is used by apps to free
the gpu memory of MANAGED textures (which have
a cpu memory backing)
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 4c126f0b5837227d93e481fb04e43c96b3316413
Author: Axel Davy <axel.davy at ens.fr>
Date: Thu May 7 00:03:21 2015 +0200
st/nine: Track managed textures
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 41f54040e20d40e5e2ecbf73c09dcb4a154c4577
Author: Axel Davy <axel.davy at ens.fr>
Date: Tue May 5 20:40:12 2015 +0200
st/nine: Only update dirty rect for UpdateTexture
UpdateTexture is supposed to optimise by uploading only for the
dirty region of the source (d3d9 doc, wine tests).
This patch adds the behaviour for surfaces, but not entirely for
volumes.
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 43d5c5a11b35dc09f369b08ff7066ccc8ab34e82
Author: Axel Davy <axel.davy at ens.fr>
Date: Mon May 4 00:17:09 2015 +0200
st/nine: Textures start dirty
According to the spec all textures start
dirty.
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit e139e0debd2e0dfa1f233adafab4a0c322598a7e
Author: Axel Davy <axel.davy at ens.fr>
Date: Sun May 3 23:53:48 2015 +0200
st/nine: Track dirty region for SYSTEMMEM too
Dirty regions should be tracked for both MANAGED
and SYSTEMMEM.
Until now we didn't bother to track for SYSTEMMEM,
because we hadn't implemented using the dirty region
to avoid some copies
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 8a61894cdb0f97df48775f5a16ba60d33519e36a
Author: Axel Davy <axel.davy at ens.fr>
Date: Sun May 3 23:46:14 2015 +0200
st/nine: Add missing BASETEX_REGISTER_UPDATE calls
If the texture is bound and dirty_mip is true,
BASETEX_REGISTER_UPDATE adds the texture to the list
of things to update before the next draw call.
Some calls to it were missing.
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit e4f69bc394e1b92e3d1dabf320258425c2876091
Author: Axel Davy <axel.davy at ens.fr>
Date: Sun May 3 23:28:25 2015 +0200
st/nine: SetAutoGenFilterType should regenerate the sublevels
It should regenerate the sublevels according to the spec
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit b75f830166eaf294e43746f1bf5630f7f2dcf30f
Author: Axel Davy <axel.davy at ens.fr>
Date: Sun May 3 22:57:13 2015 +0200
st/nine: Simplify NineVolume9_CopyVolume
We had only one usage for this function.
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit bc42c29013209f80182a634e32c702edb2327b22
Author: Axel Davy <axel.davy at ens.fr>
Date: Sun May 3 22:40:38 2015 +0200
st/nine: Split NineSurface9_CopySurface
NineSurface9_CopySurface was supporting more cases than what
we needed, and doing checks that were innapropriate for
some NineSurface9_CopySurface use cases.
This patch splits it into two for the two use cases, and moves
the checks to the caller.
This patch also adds a few checks to NineDevice9_UpdateSurface
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 3f36ad732c7fbe8fd38aa852c3699101fdd5041d
Author: Axel Davy <axel.davy at ens.fr>
Date: Tue May 5 23:51:24 2015 +0200
st/nine: Simplify Volume9 dirty region tracking
Similar to what was done for Surface9, track the dirty region
only in VolumeTexture9.
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit ab0643225e2718884eea874b67b55eb4aa936e53
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Nov 8 13:02:47 2014 +0100
util/u_blitter: implement alpha blending for pipe->blit
commit 23da32a9234065e0a16e91ef2f54f1e1d9bf52e5
Author: Christoph Bumiller <e0425955 at student.tuwien.ac.at>
Date: Sat May 31 23:13:24 2014 +0200
gallium: Add blending to pipe blit
This type of blending is used for gallium nine software cursor
Signed-off-by: David Heidelberg <david at ixit.cz>
commit a30684712ee9a3ef6738de8c357134a01a24924c
Author: Axel Davy <axel.davy at ens.fr>
Date: Sat Mar 21 22:28:59 2015 +0100
st/nine: Revert to sw cursor in case of failure to set hw cursor
Signed-off-by: Axel Davy <axel.davy at ens.fr>
Reviewed-by: David Heidelberg <david at ixit.cz>
commit df6f1f77cc63db3e6a7c105f3e7bab246b576eb9
Author: Axel Davy <axel.davy at ens.fr>
Date: Sat Mar 21 22:23:56 2015 +0100
st/nine: Do not call ID3DPresent_GetCursorPos for sw cursor
For sw cursor we do not tell wine the cursor position (the app
tells us directly). We shouldn't use ID3DPresent_GetCursorPos.
device->cursor.pos already contains the coordinates the app
gave us.
Signed-off-by: Axel Davy <axel.davy at ens.fr>
Reviewed-by: David Heidelberg <david at ixit.cz>
commit 78b304e2f9f9ad9b97ac8665a44af09567159800
Author: Axel Davy <axel.davy at ens.fr>
Date: Sun Mar 22 18:48:07 2015 +0100
st/nine: Force hw cursor for Windowed mode
According to the spec, Windowed mode must
have hw cursor
Signed-off-by: Axel Davy <axel.davy at ens.fr>
Reviewed-by: David Heidelberg <david at ixit.cz>
commit 1b20eaff67fba9ac6310511c79d6de8851c39145
Author: Axel Davy <axel.davy at ens.fr>
Date: Sat Mar 21 22:21:14 2015 +0100
st/nine: Hide hardware cursor when we don't use it
We have either hardware cursor or software cursor.
When we use software cursor, we should hide the hardware
cursor.
Signed-off-by: Axel Davy <axel.davy at ens.fr>
Reviewed-by: David Heidelberg <david at ixit.cz>
commit 34708783833bb99e9e42cd40a745fed1354317f2
Author: Axel Davy <axel.davy at ens.fr>
Date: Sun Feb 15 21:30:44 2015 +0100
st/nine: fix D3DRS_DITHERENABLE wrong state group
D3DRS_DITHERENABLE was assigned to the rasterizer state
group, but it was used for the blend group.
Assign it to the blend group.
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 1b645df2f309833cca5dbeaa2deceeda36a7426c
Author: Patrick Rudolph <siro at das-labor.org>
Date: Sun Apr 19 10:14:30 2015 +0200
st/nine: Account POINTSIZE_MIN and POINTSIZE_MAX for point size
When using D3DRS_POINTSIZE make sure the value is at least
D3DRS_POINTSIZE_MIN but not greater than D3DRS_POINTSIZE_MAX.
Fixes some Wine tests.
Reviewed-by: Axel Davy <axel.davy at ens.fr>
Signed-off-by: Patrick Rudolph <siro at das-labor.org>
commit 886227d363b7e889e2a9162c27059e2a9fe79cb7
Author: Patrick Rudolph <siro at das-labor.org>
Date: Tue May 12 07:27:37 2015 +0200
st/nine: Align texture memory
Align texture memory on 32 byte boundry to allow
SSE/AVX memcpy to work on locked rects.
This fixes some crashes with games using SSE.
Reviewed-by: David Heidelberg <david at ixit.cz>
Reviewed-by: Axel Davy <axel.davy at ens.fr>
Signed-off-by: Patrick Rudolph <siro at das-labor.org>
commit 3c4864fa5539d6b34863c28f3650289fd2a4ce93
Author: Axel Davy <axel.davy at ens.fr>
Date: Sat May 16 18:41:51 2015 +0200
st/nine: Always set point_quad_rasterization to 1
Both Points and Point Sprites are rasterized like quads,
according to d3d9 doc and gallium rasterizer doc.
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 74de849bd44ee4a99d36d4d0c43d2a82a6ec07c2
Author: Axel Davy <axel.davy at ens.fr>
Date: Sat May 16 22:41:26 2015 +0200
st/nine: Fix Swizzle for ATI2 format
We had red and green in the wrong channels
for the ATI2 format (RGTC2).
Found thanks to wine tests.
Signed-off-by: Axel Davy <axel.davy at ens.fr>
Reviewed-by: David Heidelberg <david at ixit.cz>
commit cb2d680232d64d614db93e2d011bb446e863e384
Author: Patrick Rudolph <siro at das-labor.org>
Date: Mon May 25 10:36:21 2015 +0200
target/d3dadapter9: Return Windows like card names
Add support for multiple cards and fill in Win
like card name, driver name and version info.
Use fallback for unknown vendors and unknown card names.
Reviewed-by: Axel Davy <axel.davy at ens.fr>
Signed-off-by: Patrick Rudolph <siro at das-labor.org>
commit 56717c0b069a20b0c4438ac1dc9280cd9026b36f
Author: David Heidelberg <david at ixit.cz>
Date: Sat Apr 11 00:13:53 2015 +0200
st/nine: Require gcc >= 4.6
Nine code uses some C11 features, and this
leads to compile error on gcc <= 4.5
Another way would have been to use the
-fms-extensions CFLAG
Signed-off-by: David Heidelberg <david at ixit.cz>
Cc: "10.4 10.5 10.6" <mesa-stable at lists.freedesktop.org>
commit 365d631eb220e7d546a726d6f38f76e2e3746d65
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Aug 21 15:08:15 2015 -0400
glsl: fix error message when validating tcs output decls
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 3b4d03d44044f683d9b194c069cd3c1e6acb105f
Author: Rob Clark <robclark at freedesktop.org>
Date: Mon Aug 10 17:27:19 2015 -0400
relnote updates
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 3525aa1dc9c27fb2394a37788a29c272b3a81d1b
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Aug 20 20:06:50 2015 -0400
st/mesa: pass through 4th opcode argument in bitmap/pixel visitors
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.6" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 681efdf7a18b73ce06989cb2d3299e3feabdb5f5
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Aug 20 19:59:04 2015 -0400
st/mesa: fix assignments with 4-operand arguments (i.e. BFI)
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.6" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit f142e64b2938ab3ebc42fd40436a1de74e3ed2e2
Author: Martin Peres <martin.peres at linux.intel.com>
Date: Fri Aug 21 16:25:14 2015 +0300
i965: allow image_size on float images
This got missed because the piglit test only tested int images to avoid a
combinatiorial explosion of format, targets, stages and sizes which
takes more than 5 minutes to test on nvidia's driver.
This patch also drops the IMAGE_FUNCTION_AVAIL_ATOMIC which is not applicable
to the image_size codepath but was not hurting in any way.
Signed-off-by: Martin Peres <martin.peres at linux.intel.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit df5cdec1329507d5ac52a6d3db49c2608b9226bc
Author: Zoltan Gilian <zoltan.gilian at gmail.com>
Date: Wed Aug 19 11:56:08 2015 +0200
clover: fix llvm 3.5 build error
There is no MDOperand in llvm 3.5.
v2: Check if kernel metadata is present to avoid crash (EdB).
v3: Second attempt to avoid crash: switch off metadata query for llvm < 3.6.
Reviewed-by: Serge Martin (EdB) <edb+mesa at sigluy.net>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 7eda897bf05dc572dbe83f3a1075b773b0c65708
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Thu Aug 20 10:25:59 2015 +0300
mesa: update fbo state in glTexStorage
We have to re-validate FBOs rendering to the texture like is done
with TexImage and CopyTexImage.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91673
Cc: "10.6" <mesa-stable at lists.freedesktop.org>
commit 8cae9f2fda37b9868ea973a665e1acc115172b45
Author: Eric Anholt <eric at anholt.net>
Date: Tue Aug 18 22:19:12 2015 -0700
vc4: Add algebraic opt for rcp(1.0).
We're generating rcps as part of backend lowering of the packed coordinate
in the CS, and we don't want to lower them in NIR because of the extra
newton-raphson steps in the common case. However, GLB2.7 is moving a
vertex attribute with a 1.0 W component to the position, and that makes us
produce some silly RCPs.
total instructions in shared programs: 97590 -> 97580 (-0.01%)
instructions in affected programs: 74 -> 64 (-13.51%)
commit c800fef2e2c65f7d81215cb316de6f73b15ba6c5
Author: Eric Anholt <eric at anholt.net>
Date: Tue Aug 18 22:07:47 2015 -0700
vc4: Allow unpack_8[abcd]_f's src to stay in r4.
I had QPU emit code to do it, but forgot to flag the register class.
total instructions in shared programs: 97974 -> 97590 (-0.39%)
instructions in affected programs: 25291 -> 24907 (-1.52%)
commit 8b36d107fdd6f6b91556fcdc3498df16803d4181
Author: Eric Anholt <eric at anholt.net>
Date: Tue Aug 18 21:26:05 2015 -0700
vc4: Pack the unorm-packing bits into a src MUL instruction when possible.
Now that we do non-SSA QIR instructions, we can take a NIR SSA src that's
only used by the unorm packing and just stuff the pack bits into it.
total instructions in shared programs: 98136 -> 97974 (-0.17%)
instructions in affected programs: 4149 -> 3987 (-3.90%)
commit 572a48366d9dfac6a7f9ee8f4d29832c496125e2
Author: Eric Anholt <eric at anholt.net>
Date: Tue Aug 18 21:43:42 2015 -0700
vc4: Add a QIR helper for whether the op is a MUL type.
commit fd74da11c48dcd9098d4f64508aae65775c68b75
Author: Eric Anholt <eric at anholt.net>
Date: Tue Aug 18 20:18:51 2015 -0700
vc4: Drop an unused algebraic op.
NIR now handles this optimization for us.
commit 98728ce0718e49864b872beb76fc3afbf341b38a
Author: Eric Anholt <eric at anholt.net>
Date: Wed Aug 5 20:54:02 2015 -0700
vc4: Switch QPU_PACK_SCALED to be two non-SSA instructions.
total instructions in shared programs: 98159 -> 98136 (-0.02%)
instructions in affected programs: 12279 -> 12256 (-0.19%)
commit 69ef08d303cdf153fe2432a7e40faccae5d62aab
Author: Eric Anholt <eric at anholt.net>
Date: Wed Aug 5 20:31:21 2015 -0700
vc4: Make the pack-to-unorm instructions be non-SSA.
This helps ensure that the register allocator doesn't force the later pack
operations to insert extra MOVs.
total instructions in shared programs: 98170 -> 98159 (-0.01%)
instructions in affected programs: 2134 -> 2123 (-0.52%)
commit 0bba4fa070583f5fd8a0f7208fbfa181dc25e71b
Author: Eric Anholt <eric at anholt.net>
Date: Mon Aug 3 19:25:47 2015 -0700
vc4: Allow QIR registers to be non-SSA.
Now that we have NIR, most of the optimization we still need to do is
peepholes on instruction selection rather than general dataflow
operations. This means we want to be able to have QIR be a lot closer to
the actual QPU instructions, just with virtual registers. Allowing
multiple instructions writing the same register opens up a lot of
possibilities.
commit ceb1a318424bf219eace29955ae473c1ccf9f8b8
Author: Eric Anholt <eric at anholt.net>
Date: Wed Aug 5 20:11:07 2015 -0700
vc4: We can now move TEX_RESULT accesses across other r4 ops.
No difference on shader-db.
commit ad89748541159968787dce02bb9c19d9367fddc6
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Wed May 27 20:12:42 2015 +1000
glsl: fix binding validation for interface blocks
V2: rebase on SSBO changes
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit dd6a6dbaf707c120f6db38036985fcc258ebe294
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Sun Aug 16 14:26:23 2015 +1000
glsl: interleave constant propagation and folding
The constant folding pass can take a long time to complete
so rather than running through the entire pass each time
a new constant is propagated (and vice versa) interleave them.
This change helps ES31-CTS.arrays_of_arrays.InteractionFunctionCalls1
go from around 2 min -> 23 sec.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 8483577f6b393c26dc21f6693e44760404ba6fcb
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Aug 20 22:13:48 2015 -0400
nv50/ir: pre-compute BFE arg when both bits and offset are imm
Due to a quirk in how the nv50 opt passes run, the algebraic
optimization that looks for these BFE's happens before the constant
folding pass. Rearranging these passes isn't a great idea, but this is
easy enough to fix. Allows a following cvt to eliminate the bfe in
certain situations.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit ecebd3dbfcb769b44e99733279c8fb0745818708
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Aug 19 18:43:47 2015 -0400
glsl: expose textureQueryLod in GLSL 4.00+ fragment shaders
See issue from the ARB_texture_query_lod spec for LOD vs Lod confusion:
(3) The core specification uses the "Lod" spelling, not "LOD". Should
this extension be modified to use "Lod"?
RESOLVED: The "Lod" spelling is the correct spelling for the core
specification and the preferred spelling for use. However, use of
"LOD" also exists, as the extension predated the core specification,
so this extension won't remove use of "LOD".
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
commit 29e953b07b8c1e4d27f53c4a1430154a3d67f896
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Thu Aug 20 18:00:20 2015 -0700
Revert "mesa/formats: refactor by collapsing cases in switch statement by type"
This reverts commit ffe6c6ad5f719dedd1b6b95e8590e3f20b23d340.
_mesa_format_num_components() does not include the padding bits in mesa formats
containing 'X' channels. This could cause mipmap generation for certain
uncompressed formats to underestimate the number of channels in the source
image by 1.
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
commit 4237dfb97815a50de7be464a0d62bd19e62d17b7
Author: Glenn Kennard <glenn.kennard at gmail.com>
Date: Thu Aug 13 20:30:07 2015 +0200
r600g: Fix handling of TGSI_OPCODE_ARR with SB
FLT_TO_INT goes in the vector pipes on evergreen/NI,
not the trans unit as on earlier chips.
Signed-off-by: Glenn Kennard <glenn.kennard at gmail.com>
Reviewed-by: Dave Airlie <airlied at redhat.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 7a32652231f96eac14c4bfce02afe77b4132fb77
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date: Wed Aug 19 18:58:47 2015 +1000
r600: Turn 'r600_shader_key' struct into union
This struct was getting a bit crowded, following the lead of
radeonsi, mirror the idea of having sub-structures for each
shader type. Turning 'r600_shader_key' into an union saves
some trivial memory and CPU cycles for the shader keys.
[airlied: drop as_ls, and reorder so larger fields at start.]
Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit e2145de74d6333f099613c595c5c46f79f54e59f
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date: Wed Aug 19 18:58:46 2015 +1000
r600: Rewrite r600_shader_selector_key() to use a switch stmt
Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit bbf8291bf869e219bd0e71063bf26a060682a000
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Aug 3 08:17:42 2015 -0700
i965: Use NIR by default for vertex shaders
Shader-db results for vec4 on i965:
total instructions in shared programs: 1499894 -> 1502261 (0.16%)
instructions in affected programs: 1414224 -> 1416591 (0.17%)
helped: 2434
HURT: 10543
GAINED: 1
LOST: 0
Shader-db results for vec4 on g4x:
total instructions in shared programs: 1437411 -> 1439779 (0.16%)
instructions in affected programs: 1362402 -> 1364770 (0.17%)
helped: 2434
HURT: 10544
GAINED: 0
LOST: 0
Shader-db results for vec4 on Iron Lake:
total instructions in shared programs: 1437214 -> 1439593 (0.17%)
instructions in affected programs: 1362205 -> 1364584 (0.17%)
helped: 2433
HURT: 10544
GAINED: 1
LOST: 0
Shader-db results for vec4 on Sandy Bridge:
total instructions in shared programs: 2022092 -> 1941570 (-3.98%)
instructions in affected programs: 1886838 -> 1806316 (-4.27%)
helped: 7510
HURT: 10737
GAINED: 0
LOST: 0
Shader-db results for vec4 on Ivy Bridge:
total instructions in shared programs: 1853749 -> 1804960 (-2.63%)
instructions in affected programs: 1686736 -> 1637947 (-2.89%)
helped: 6735
HURT: 11101
GAINED: 0
LOST: 0
Shader-db results for vec4 on Haswell:
total instructions in shared programs: 1853749 -> 1804960 (-2.63%)
instructions in affected programs: 1686736 -> 1637947 (-2.89%)
helped: 6735
HURT: 11101
GAINED: 0
LOST: 0
Signed-off-by: Jason Ekstrand <jason.ekstrand at intel.com>
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit 6921f170b62d9f9c0e5bd2cb6666c15395addba8
Author: Kai Wasserbäch <kai at dev.carbon-project.org>
Date: Fri Aug 14 14:49:43 2015 +0200
glsl: check if return_deref in lower_subroutine_visitor::visit_leave isn't NULL
Fixes a crash in Piglit's
spec at arb_shader_subroutine@linker at no-mutual-recursion.vert for me.
Signed-off-by: Kai Wasserbäch <kai at dev.carbon-project.org>
Reviewed-by: Dave Airlie <airlied at redhat.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 3e6adbd761f72b612aba57fd86bb5203aae07133
Author: Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de>
Date: Sun Jan 11 22:40:22 2015 +0100
nv50/ir: Handle OP_CVT when folding constant expressions
[imirkin: handle more type combinations, use macro]
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit f5b926183ded75661ab3f786ac1739b1f912c6c5
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Tue Aug 18 23:16:32 2015 -0400
nvc0/ir: undo more shifts still by allowing a pre-SHL to occur
This happens with unpackSnorm lowering. There's yet another
bitfield-extract behind it, but there's too much variation to be worth
cutting through.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 9ebe7dc09479d9a8df2733ef96525a2b5e758f6d
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Tue Aug 18 22:53:11 2015 -0400
nvc0/ir: don't require AND when the high byte is being addressed
unpackUnorm* lowering doesn't AND the high byte/word as it's
unnecessary. Detect that situation as well.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 63cb85e567ad1025ee990b38f43c2f1ef811821b
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Tue Aug 18 21:09:12 2015 -0400
nvc0/ir: detect i2f/i2i which operate on specific bytes/words
Some Unigine shaders have been observed to unpack bytes out of 32-bit
integers and convert them to floats. I2F/I2I can handle this sort of
thing directly. Detect the handleable situations.
This misses 16-bit word capabilities in nv50, but I haven't seen shaders
that would actually make use of that.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 51499bb5ff5626b893383545c494c7f808763404
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Tue Aug 18 21:07:33 2015 -0400
nvc0/ir: detect AND/SHR pairs and convert into EXTBF
Some shaders appear to extract bits using shift/and combos. Detect
(some) of those and convert to EXTBF instead.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 2a4af36517333ef61d5f7ca2264fec3f49ee3662
Author: Chih-Wei Huang <cwhuang at android-x86.org>
Date: Sat Jun 20 02:00:15 2015 +0800
nv50/ir: support different unordered_set implementations
If build with C++11 standard, use std::unordered_set.
Otherwise if build on old Android version with stlport,
use std::tr1::unordered_set with a wrapper class.
Otherwise use std::tr1::unordered_set.
Signed-off-by: Chih-Wei Huang <cwhuang at linux.org.tw>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 56ebd3314bfc5895fab47586fc8cda024aac4fd8
Author: Martin Peres <martin.peres at linux.intel.com>
Date: Thu Aug 20 15:15:56 2015 +0300
i965: Fix "handle nir_intrinsic_image_size"
I pushed a half-baked version of "i965: handle nir_intrinsic_image_size" by
accident. Not having the Reviewed-by: tags on the last two commits should
have been a red flag but I somehow missed it after the QA check.
This patch should fix image-size for non-int images. I will add support to
the piglit test for all the other image types.
Sorry for the noise.
Signed-off-by: Martin Peres <martin.peres at linux.intel.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit e5851cff45169f4e635299da4ed5b41aeb0d2f83
Author: Martin Peres <martin.peres at linux.intel.com>
Date: Wed Apr 29 12:42:16 2015 +0300
i965: enable GL_ARB_shader_image_size
Signed-off-by: Martin Peres <martin.peres at linux.intel.com>
commit 50db9c1db645c1a4d5777d2cacfd7ac74ebbe544
Author: Martin Peres <martin.peres at linux.intel.com>
Date: Wed Apr 29 12:39:16 2015 +0300
i965: handle nir_intrinsic_image_size
v2, Review from Francisco Jerez:
- avoid the camelCase for the booleans
- init the booleans using the sampler type
- force the initialization of all the components of the output register
v3:
- Rename a variable from CubeMapArray to CubeArray to re-use GLSL's name (Ilia)
- Fix some indentation and drop parenthesis (Topi)
- Fix a signed/unsigned comparaison warning
Signed-off-by: Martin Peres <martin.peres at linux.intel.com>
commit 80b1707e26734ac9c957cfc876ab5893f1749c74
Author: Martin Peres <martin.peres at linux.intel.com>
Date: Tue Aug 11 17:42:12 2015 +0300
nir: convert the glsl intrinsic image_size to nir_intrinsic_image_size
v2, review from Francisco Jerez:
- make the destination variable as large as what the nir instrinsic
defines (4) instead of the size of the return variable of glsl. This
is still safe for the already existing code because all the intrinsics
affected returned the same amount of components as expected by glsl IR.
In the case of image_size, it is not possible to do so because the
returned number of component depends on the image type and this case
is not well handled by nir.
v3:
- Style fix
Signed-off-by: Martin Peres <martin.peres at linux.intel.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 58a8689717a5965919934d1b4b44b4eef0a6bf64
Author: Martin Peres <martin.peres at linux.intel.com>
Date: Mon Apr 27 19:25:34 2015 +0300
glsl: add support for the imageSize builtin
The code is heavily inspired from Francisco Jerez's code supporting the
image_load_store extension.
Backends willing to support this builtin should handle
__intrinsic_image_size.
v2: Based on the review of Ilia Mirkin
- Enable the extension for GLES 3.1
- Fix indentation
- Fix the return type (float to int, number of components for CubeImages)
- Add a warning related to GLES 3.1
v3: Based on the review of Francisco Jerez
- Refactor the code to share both add_image_function and _image with the other
image-related functions
v4: Based on Topi Pohjolainen's comments
- Do not add parenthesis for the return value
v5: based on Francisco Jerez's comments:
- Fix a few indent issues
- Reduce the size of a condition by testing the dimension and array properties
instead of enumerating all the formats.
Signed-off-by: Martin Peres <martin.peres at linux.intel.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 3d93f65ef2dbecbf615ee8041d92354ae660d71b
Author: Martin Peres <martin.peres at linux.intel.com>
Date: Mon Apr 27 20:05:14 2015 +0300
main: add extension GL_ARB_shader_image_size
Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
Signed-off-by: Martin Peres <martin.peres at linux.intel.com>
commit f6c622f58432b0c3cb80bc2ed41e314abf876e03
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Aug 20 13:46:53 2015 +0300
docs: Mark GLES 3.1 image load/store as done on i965.
commit f5070c801c4885521df17a65c297f24ae628d414
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Aug 19 14:42:50 2015 +0300
mesa: Add ES31 API tag for the extension table.
I'll mark the OES_shader_image_atomic extension entry with this tag to
make sure that we don't expose it on earlier GLES API versions
accidentally, because according to the extension:
"OpenGL ES 3.1 and GLSL ES 3.10 are required."
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 6379f5cb2ab7c5ae3f3769204f95088e35c53217
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Aug 17 01:47:50 2015 +0300
glsl: Parse the allowed image format qualifiers in GLSL ES 3.1.
This includes the minimum required desktop/ES GLSL version in the
format qualifier table in anticipation of new GLSL versions extending
the set of supported image formats. According to section 4.4.7 of the
GLSL ES 3.1 spec:
"The format layout qualifier identifiers for image variable
declarations are:
[...]
rgba32f
rgba16f
r32f
rgba8
rgba8_snorm
[...]
rgba32i
rgba16i
rgba8i
r32i
[...]
rgba32ui
rgba16ui
rgba8ui
r32ui"
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit e3fb2e1f0e160573c3d164818f556c7f6725835e
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Aug 17 19:12:00 2015 +0300
glsl: Recognise image memory qualifiers in GLSL ES 3.1.
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 307c382c1b514629c342587d2f320f5491de9b65
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Aug 17 17:42:30 2015 +0300
glsl: Define image-related built-in constants required by GLSL ES 3.1.
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit a976b7255b2c84e6cccefb447029add02ddf86ae
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Aug 17 01:39:38 2015 +0300
glsl: Remove duplicate definition of gl_MaxTess*ImageUniforms built-in constants.
These seem to have been re-added at some point during the
ARB_tessellation_shader implementation work. AFAICT the second
(correct) definition of each constant would have had no effect because
the symbols were already defined.
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 9d0bb6be097080e2568b7b6cc18f2bf800fed1b1
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Aug 17 01:38:00 2015 +0300
glsl: Accept atomic_uint type in GLSL ES 3.1.
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit d589df94013bd04b23ef88cdac6debe04e3075a1
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Aug 17 01:37:12 2015 +0300
glsl: Accept supported image types in GLSL ES 3.1.
These are a subset of the image types supported by desktop GL,
excluding 1D, 1D array, rectangle, buffer, cube array, 2D MS and 2D
MS array texture targets.
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 6da187f80560b44b59551757c1322e921d8ca025
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Aug 17 01:34:41 2015 +0300
glsl: Expose image load and store built-ins in GLSL ES 3.1.
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 76a09c87c14f65d8ad8bd805ef03101f4455a24f
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Aug 17 01:34:13 2015 +0300
glsl: Use a separate availability class for image atomic built-ins.
These are not part of unextended GLSL ES 3.1.
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 26b1141a78cfec0e2eface4b399009ee5eb421df
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Aug 17 01:28:57 2015 +0300
glsl: Allow precision qualifiers on general opaque types.
From the GLSL ES 3.1 spec, section 4.7.3:
"Any floating point, integer, opaque type declaration can have the
type preceded by one of these precision qualifiers: [...] highp
[...], mediump [...], lowp [...]."
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit ee7bf349d865b18ca2827508fb947b7e549c7fc6
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Aug 17 01:27:43 2015 +0300
glsl: Implement GLSL ES restriction on images being either readonly or writeonly.
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 527ae5d4286e76fc2ec3d70f4b6cea3798539372
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Aug 17 01:26:40 2015 +0300
glsl: Require that all image uniforms have a format qualifier in GLSL ES.
Note that this is slightly more permissive than the spec language
requires: "Any image variable must specify a format layout qualifier."
The GLSL ES spec seems really sketchy regarding format layout
qualifiers on function formal parameters -- On the one hand they are
required, but on the other hand it doesn't provide any syntax to
specify them (see section 6.1.1), they don't participate in parameter
type matching for overload resolution, and are in fact explictly
forbidden ("Layout qualifiers cannot be used on formal function
parameters"). Of course none of the image built-in functions defined
by the spec specify format layout qualifiers (and they probably
couldn't sensibly), to contradict its own requirement.
This probably qualifies for a spec bug, but in the meantime do the
sensible thing and require layout qualifiers on uniforms *only*.
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
commit 241774aa03d6dda5fe4cd86c1988f1678d4c0e5f
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Aug 17 01:25:11 2015 +0300
glsl: Add support for image binding qualifiers.
Support for binding an image to an image unit explicitly in the shader
source is required by both GLSL 4.2 and GLSL ES 3.1, but not by the
original ARB_shader_image_load_store extension.
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
commit ebf1196d82eeed2f7863984ec33d26538a97b531
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Aug 17 01:21:01 2015 +0300
glsl: Forbid non-constant image array indexing in GLSL ES 3.1.
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
commit 6c161405dc191f3d4083a48dfc033d4401b8055a
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Aug 17 02:05:43 2015 +0300
mesa: Refuse to bind image uniforms using glUniform in GLES.
The GLES 3.1 spec removed support for updating the image unit bound to
an image uniform using glUniform1i() calls.
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 86a64dfccfd3e98befa1e58f1a252cf993e5b680
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Aug 17 02:02:17 2015 +0300
mesa: Refuse to bind a mutable texture object to an image unit in GLES.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
commit d70edfcfd53b50da0c4bb7aad909302dca6d4722
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Aug 17 02:01:40 2015 +0300
mesa: Initialize image unit state to different defaults in GLES.
There is no GL_R8 image format in GLES, according to the state table
20.32 of the GLES 3.1 spec the default value should be GL_R32UI. The
ES31-CTS.shader_image_load_store.basic-api-bind Khronos conformance
test checks that this is the case.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 3b70f7900ba14e83081d8ebcd1b827ba605a8e8b
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Aug 17 02:00:48 2015 +0300
mesa: Reset image unit state to the default values when a bound image is deleted.
The ES31-CTS.shader_image_load_store.basic-api-bind conformance test
expects the whole image unit state to be reset when the bound texture
object is deleted. The ARB_shader_image_load_store extension is
rather vague regarding what should happen with image unit state other
than the texture object in that case, but the GL 4.2 and GLES 3.1
specifications (section "Automatic Unbinding of Deleted Objects")
explicitly require it to be reset to the default values.
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 10b7cf1a01cf0467f5c8d1cea08d8f93e401a454
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Aug 17 01:58:53 2015 +0300
mesa: Reject image formats not supported by GLES.
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit b97d8c95a91773dc002e3ba42bd02e84a00eada3
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Aug 17 01:53:48 2015 +0300
mesa: Don't lose track of the shader image layer originally specified by the user.
The spec requires that all layers of the image starting from the 0-th
are bound to the image unit regardless of the Layer parameter when
Layered is true, so I was setting gl_image_unit::Layer to zero in that
case for the convenience of the driver back-end. However the
ES31-CTS.shader_image_load_store.basic-api-bind conformance test
checks that the layer value returned by glGetInteger is the same that
was originally specified, regardless of the value of layered. Rename
Layer to _Layer as is usual for other derived state and keep track of
the original layer value as gl_image_unit::Layer.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 47e0d5b9b28b0753adda70cbfb3ad111ba6169a8
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Aug 17 19:10:46 2015 +0300
mesa: Rename MaxCombinedImageUnitsAndFragmentOutputs to MaxCombinedShaderOutputResources.
The name of both the GLSL built-in variable and the glGetInteger param
with the same value changed in GLSL ES 3.1 and GL 4.5. Its semantics
also changed slightly, since the limit now also takes into account the
number of SSBs in use. Switch our internal data structures to the
up-to-date name.
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 3547d9855c2103ecc5001a082965d3dda5d69d34
Author: Dave Airlie <airlied at gmail.com>
Date: Sun Aug 16 07:37:37 2015 +1000
GL: update glext to svn 31811
This brings in the new ARB extensions.
Acked-by: Chris Forbes <chrisf at ijw.co.nz>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit ab83be590d4b45f50461a004b672f7640a4d8f53
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Aug 12 11:26:34 2015 -0700
nir: Use nir_builder in nir_lower_io's get_io_offset().
Much more readable.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit ed2afec3fc2210ee737216981a41df8a396b11f6
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Aug 12 10:57:31 2015 -0700
nir: Pull nir_lower_io's load_op selection into a helper function.
Makes the function a bit smaller.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit ffe6c6ad5f719dedd1b6b95e8590e3f20b23d340
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Tue Aug 11 11:56:35 2015 -0700
mesa/formats: refactor by collapsing cases in switch statement by type
Combine the adjacent cases which have the same GL type in the switch statemnt.
Reviewed-by: Chad Versace <chad.versace at intel.com>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
commit 0872b042b13388bc870a3acf167a6ce692b734dd
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Fri Aug 7 14:36:23 2015 -0700
mesa/formats: add more MESA_FORMAT_LAYOUTs
Add the classes of compressed formats as layouts. This allows the detection
of compressed formats belonging to a certain category of compressed formats.
v2. simplify layout name construction (Ilia).
Reviewed-by: Chad Versace <chad.versace at intel.com>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
commit 2438e2fe326d7cb9f9d003f6edf77821e41ef22c
Author: Marta Lofstedt <marta.lofstedt at intel.com>
Date: Mon Aug 10 13:04:42 2015 +0200
glsl: Fix up GL_ARB_compute_shader for GLSL ES 3.1
GL_ARB_compute_shader is limited for GLSL version 430.
This enables for GLSL ES version 310.
V2: Updated error string to also include GLSL 3.10
Signed-off-by: Marta Lofstedt <marta.lofstedt at linux.intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 3df7856b4625f21ebf5465bad2556583b808c8bf
Author: Marta Lofstedt <marta.lofstedt at intel.com>
Date: Wed Aug 12 11:57:39 2015 +0200
mesa/main: Add GL_IMAGE_FORMAT_COMPATIBILITY_TYPE to glGetTexParameterfv
According to Open GL ES 3.1 specification, section 8.10.2
GL_IMAGE_FORMAT_COMPATIBILITY_TYPE should be supported by
glGetTexParameterfv.
Signed-off-by: Marta Lofstedt <marta.lofstedt at linux.intel.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 3b1e283d884b0c5c93c32d3e4a0325fbf2e96234
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Aug 19 00:56:33 2015 +0200
radeonsi: fix a typo as_es -> as_ls in a string
Trivial.
commit 5fb0180592b124857e2e0369e2cdee74bd552bb9
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Aug 17 19:55:57 2015 +0200
winsys/amdgpu: fix the type of memory usage counters
If the 32-bit types overflowed, the driver could submit an IB that uses much
more memory than is available.
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 421b809db10b939d9baf7b904560c37b68261aaf
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Aug 15 11:51:48 2015 +0200
radeonsi: fix indirect indexing of MSAA textures
FMASK wasn't handled correctly.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit f33a7ab150ea01f3550904fe3c56fcad32ce85e0
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Jul 20 15:19:53 2015 -0400
st/mesa: add fake ARB_copy_image support in Gallium
This support should be removed in favor of something that actually works
in all the weird cases. However this is simple and is enough to allow
Bioshock Infinite to render properly on nvc0.
Since the functionality is not implemented correctly, the extension will
not appear in the extension string and mesa will still return
INVALID_OPERATION for any glCopyImageSubData calls. In order to make use
of this functionality, run with
MESA_EXTENSION_OVERRIDE=GL_ARB_copy_image
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 89759381dbfe3784bc780a3ab6e0fe13e77e06ef
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Mon Aug 17 12:11:03 2015 +0300
glsl: enable textureSize and texelFetch on GLSL ES 3.10 with MS samplers
Patch separates array samplers from the texture_multisample check so that we
can enable only [iu]sampler2DMS, [iu]sampler2DMSArray are not supported.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
commit 6a8e08cb890b47394e667ec86d9a678060c19e61
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Mon Aug 17 10:14:35 2015 +0300
mesa: validate size parameters for glTexStorage*Multisample
v2: code cleanup
v3: check only dimensions, samples is checked separately later
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
commit a342becc490b38436396e98ee653a6b81c037663
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Mon Aug 10 10:50:06 2015 +0300
mesa: expose dimension check for glTex*Storage functions
This is done so that following patch can use it to verify dimensions
for multisample variants of glTex*Storage.
v2: move function to header, use bool instead GLboolean
v3: small changes, cleanup
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
commit 2b40a144b7a589ebd5e80c9a8a8241c53201035e
Author: Roland Scheidegger <sroland at vmware.com>
Date: Wed Aug 19 04:17:49 2015 +0200
util/ra: (trivial) fix c99 loop variable initialization
Fails with old msvc otherwise.
commit 3f797ef0c038afecb8702cc90a452903694975a2
Author: Roland Scheidegger <sroland at vmware.com>
Date: Wed Aug 19 04:17:36 2015 +0200
util: (trivial) include c99_math.h in rounding.h
Needed for rint/rintf.
commit c03247bae010dfd81a08572a32067e9ea8637f63
Author: Neil Roberts <neil at linux.intel.com>
Date: Mon Jul 13 18:01:13 2015 +0100
i965/bdw: Fix setting the instancing state for the SGVS element
When gl_VertexID or gl_InstanceID is used a 3DSTATE_VF_SGVS
instruction is sent to create a sort of element to store the generated
values. The last instruction in this chunk of code looks like it was
trying to set the instancing state for the element using the
3DSTATE_VF_INSTANCING instruction. However it was sending
brw->vb.nr_buffers instead of the element index. This instruction is
supposed to take an element index and that is how it is used further
down in the function so the previous code looks wrong. Perhaps
previously the number of buffers coincidentally matched the number of
enabled elements so the value was generally correct anyway. In a
subsequent patch I want to change a bit how it chooses the SGVS
element index so this needs to be fixed.
v2 [by Ben]
Remove stable 10.5 stable tag (it's too late now)
Commit update as follows:
The number of vertex buffers emitted is always <= the number of vertex elements.
To maximize reuse (actually, to minimize relocations - according to the code
comments), a vertex buffer is only emitted once, even when we setup multiple
components (3DSTATE_VERTEX_ELEMENT) from that buffer. This meant that the
previous code would use the wrong indexed element for these reuse cases. This
patch by itself prevents hangs on BSW in the linked bug. It doesn't make the
test pass, the remaining patches are needed for that.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91610
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
Tested-by: Mark Janes <mark.a.janes at intel.com>
Cc: <mesa-stable at lists.freedesktop.org>
commit f01bdb0484dd5224b183526d020ee3f2888cac45
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Sat Aug 15 09:58:32 2015 -0700
util/ra: Make allocating conflict lists optional
Since i965 is now using make_reg_conflicts_transitive and doesn't need
q-value computations, they are disabled on i965. They are enabled
everywhere else so that they get the old behavior. This reduces the time
spent in eglInitialize() on BDW by around 10-15%.
Reviewed-by: Eric Anholt <eric at anholt.net>
commit c3b21f2d56d77c8c11115bf110a5e25e9dd7e3d5
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Sat Aug 15 09:50:11 2015 -0700
i965/reg_allocate: Use make_reg_conflicts_transitive
Instead of adding transitive conflicts as we go, we now add regular
conflicts and them make them all transitive at the end. This reduces
screen creation time substantially on BDW. The time spent in eglInitialize
is reduced from 27.78 ms/call to 9.92 ms/call in debug mode and from 13.15
ms/call to 4.54 ms/call in release mode (about 65% in either case).
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 9b49284c223b284295675775d4344f066b4455db
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Sat Aug 15 09:43:05 2015 -0700
util/ra: Add a function for making all conflicts on a register transitive
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 7c8e53f1bee370c1a8a0c640313c12df220f4114
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Sat Aug 15 09:30:40 2015 -0700
util/bitset: Add a BITSET_FOREACH_SET macro
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 6ff3341fc77c8e22a62505eb374938db3c95144f
Author: Eric Anholt <eric at anholt.net>
Date: Tue Aug 4 10:43:58 2015 -0700
mesa: Move varying slots and FS output names to shader_enums.h
They're used by glsl_to_nir.cpp, and I want to use them in TGSI-to-NIR as
well (our use of the var->index slot to store slot properties no longer
works since it got truncated).
The *_MAX defines are left in mtypes.h, because they depend on config.h.
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
commit fdacadc87c708b519a8a4e35b1d551773ca95f4c
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Thu Aug 13 23:26:01 2015 +1000
mesa: undo split out of create shader code
This code was split out into a separate function to be used also
by GL_EXT_separate_shader_objects which has since been removed from
Mesa, so move it back.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 4a0bea38635e29b20701855131fa2b5dd6d3978f
Author: Rob Clark <robclark at freedesktop.org>
Date: Tue Aug 18 15:07:02 2015 -0400
freedreno: use fd_pipe_wait_timeout()
To properly support the case of waiting on a fence with a 0 timeout, we
still need to call down to the kernel. Which requires the use of the
new fd_pipe_wait_timeout() API.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit fd7a14f8ddeae5fc868a8d452445d708505cc930
Author: Rob Clark <robclark at freedesktop.org>
Date: Sun Aug 16 19:18:22 2015 -0400
freedreno: fence fix
Don't take current timestamp/fence from current ring, as we might have
already rolled over to new rb.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 885762e18291eb4dc0b449297c3a78f7c036bcde
Author: Neil Roberts <neil at linux.intel.com>
Date: Mon Aug 10 17:31:02 2015 +0100
Add mesa.icd to the .gitignore
Since 4d7e0fa8c731776 this file is generated by the configure script.
Reviewed-by: Tapani Palli <tapani.palli at intel.com>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit ec6af4f54cbfe1a779af7245f1bd65c9e5a00dce
Author: Richard Yao <ryao at gentoo.org>
Date: Wed Aug 12 12:48:22 2015 -0400
drirc: Add "Unigine Oil Rush" quirk (allow_glsl_extension_directive_midshader).
Appears to fix shader compilation. Tested by starting the client and observing
that the screen was correct after the trailers ran when previously, it was
blank. Play tested on amd64.
This was suggested by "Kuuchan" on the Steam forums:
https://steamcommunity.com/app/200390/discussions/0/540731690861139279/?insideModal=1#c594820656479479870
Acked-by: Matt Turner <mattst88 at gmail.com>
Signed-off-by: Richard Yao <ryao at gentoo.org>
commit 49d0a36bd6593ce09486678a7bf3d500af5e265c
Author: Thomas Helland <thomashelland90 at gmail.com>
Date: Thu Aug 6 13:36:05 2015 +0200
nir: Simplify feq(fneg(a), a)) -> feq(a, 0.0)
The positive and negative value of a float can only
be equal to each other if it is -0.0f and 0.0f.
This is safe for Nan and Inf, as -Nan != Nan, and -Inf != Inf
This gives no changes in my shader-db
Signed-off-by: Thomas Helland <thomashelland90 at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit a39167d5949c76dfb48994caead4b59ab5f80318
Author: Thomas Helland <thomashelland90 at gmail.com>
Date: Thu Aug 6 13:36:04 2015 +0200
nir: Simplify fne(fneg(a), a) -> fne(a, 0.0)
-NaN != NaN, and -Inf != Inf, so this should be safe.
Found while working on my VRP pass.
Shader-db results on my IVB:
total instructions in shared programs: 1698267 -> 1698067 (-0.01%)
instructions in affected programs: 15785 -> 15585 (-1.27%)
helped: 36
HURT: 0
GAINED: 0
LOST: 0
Some shaders was found to have the following pattern in NIR:
vec1 ssa_26 = fneg ssa_21
vec1 ssa_27 = fne ssa_21, ssa_26
Make that:
vec1 ssa_27 = fne ssa_21, 0.0f
This is found in Dota2 and Brutal Legend.
One shader is cut by 8%, from 323 -> 296 instructons in SIMD8
Signed-off-by: Thomas Helland <thomashelland90 at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 29264d0d0cd5ca24314630d9dc22b3f971344a34
Author: Rhys Kidd <rhyskidd at gmail.com>
Date: Thu Aug 6 16:34:17 2015 +1000
i965/gen7: Resolve GCC sign-compare warning.
mesa/src/mesa/drivers/dri/i965/gen7_sol_state.c: In function 'gen7_upload_3dstate_so_decl_list':
mesa/src/mesa/drivers/dri/i965/gen7_sol_state.c:119:22: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (int i = 0; i < linked_xfb_info->NumOutputs; i++) {
^
Signed-off-by: Rhys Kidd <rhyskidd at gmail.com>
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
commit 94bdb50c0b02160d0b391eafc68259ab78310d37
Author: Rhys Kidd <rhyskidd at gmail.com>
Date: Thu Aug 6 16:34:16 2015 +1000
i965/gen6: Resolve GCC sign-compare warning.
mesa/src/mesa/drivers/dri/i965/gen6_vs_state.c: In function 'gen6_upload_push_constants':
mesa/src/mesa/drivers/dri/i965/gen6_vs_state.c:85:21: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (i = 0; i < prog_data->nr_params; i++) {
^
mesa/src/mesa/drivers/dri/i965/gen6_vs_state.c:92:17: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (i = 0; i < prog_data->nr_params; i++) {
^
Signed-off-by: Rhys Kidd <rhyskidd at gmail.com>
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
commit 1d1056c4e3b7125a5092730837fff2a9585e99ab
Author: Rhys Kidd <rhyskidd at gmail.com>
Date: Thu Aug 6 16:34:15 2015 +1000
i965: Resolve GCC sign-compare warning.
mesa/src/mesa/drivers/dri/i965/brw_vs_surface_state.c: In function 'brw_upload_pull_constants':
mesa/src/mesa/drivers/dri/i965/brw_vs_surface_state.c:84:18: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (i = 0; i < prog_data->nr_pull_params; i++) {
^
mesa/src/mesa/drivers/dri/i965/brw_vs_surface_state.c:89:21: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (i = 0; i < ALIGN(prog_data->nr_pull_params, 4) / 4; i++) {
^
Signed-off-by: Rhys Kidd <rhyskidd at gmail.com>
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
commit 30694b3f42d0da4fb106561fc898279babb498ad
Author: Rhys Kidd <rhyskidd at gmail.com>
Date: Thu Aug 6 16:34:14 2015 +1000
i965: Resolve GCC sign-compare warning.
mesa/src/mesa/drivers/dri/i965/brw_wm_surface_state.c: In function 'brw_upload_abo_surfaces':
mesa/src/mesa/drivers/dri/i965/brw_wm_surface_state.c:961:22: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (int i = 0; i < prog->NumAtomicBuffers; i++) {
^
Signed-off-by: Rhys Kidd <rhyskidd at gmail.com>
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
commit 5fb58012be6f783d735ded79582aa46a2c71e0fd
Author: Rhys Kidd <rhyskidd at gmail.com>
Date: Thu Aug 6 16:34:13 2015 +1000
i965: Resolve GCC sign-compare warning.
mesa/src/mesa/drivers/dri/i965/brw_wm_surface_state.c: In function 'brw_upload_ubo_surfaces':
mesa/src/mesa/drivers/dri/i965/brw_wm_surface_state.c:901:22: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (int i = 0; i < shader->NumUniformBlocks; i++) {
^
Signed-off-by: Rhys Kidd <rhyskidd at gmail.com>
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
commit 6625ca2370bc9b3927cf5c50be9220513320ca26
Author: Rhys Kidd <rhyskidd at gmail.com>
Date: Thu Aug 6 16:34:12 2015 +1000
i965: Resolve GCC sign-compare warning.
mesa/src/mesa/drivers/dri/i965/brw_tex_layout.c: In function 'brw_miptree_layout_texture_array':
mesa/src/mesa/drivers/dri/i965/brw_tex_layout.c:560:25: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (int q = 0; q < mt->level[level].depth; q++) {
^
Signed-off-by: Rhys Kidd <rhyskidd at gmail.com>
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
commit 1512b086d385ac9ee575e2f90cda6bec467505c7
Author: Rhys Kidd <rhyskidd at gmail.com>
Date: Thu Aug 6 16:34:11 2015 +1000
i965: Resolve GCC sign-compare warning.
mesa/src/mesa/drivers/dri/i965/brw_state_cache.c: In function 'brw_try_upload_using_copy':
mesa/src/mesa/drivers/dri/i965/brw_state_cache.c:216:18: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (i = 0; i < cache->size; i++) {
^
Signed-off-by: Rhys Kidd <rhyskidd at gmail.com>
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
commit 9febec0811a842644b6f4ea7cf20e845d9d55120
Author: Rhys Kidd <rhyskidd at gmail.com>
Date: Thu Aug 6 16:34:10 2015 +1000
i965: Resolve GCC sign-compare warning.
mesa/src/mesa/drivers/dri/i965/brw_primitive_restart.c: In function 'can_cut_index_handle_prims':
mesa/src/mesa/drivers/dri/i965/brw_primitive_restart.c:94:22: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (int i = 0; i < nr_prims; i++) {
^
Signed-off-by: Rhys Kidd <rhyskidd at gmail.com>
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
commit 5be455281eca77955aff52f01c6adb9281f4d747
Author: Rhys Kidd <rhyskidd at gmail.com>
Date: Thu Aug 6 16:34:09 2015 +1000
i965: Resolve GCC sign-compare warning.
mesa/src/mesa/drivers/dri/i965/brw_draw_upload.c: In function 'brw_prepare_vertices':
mesa/src/mesa/drivers/dri/i965/brw_draw_upload.c:434:22: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (i = j = 0; i < brw->vb.nr_enabled; i++) {
^
mesa/src/mesa/drivers/dri/i965/brw_draw_upload.c:557:17: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (i = 0; i < nr_uploads; i++) {
^
mesa/src/mesa/drivers/dri/i965/brw_draw_upload.c:569:18: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (i = 0; i < nr_uploads; i++) {
^
Signed-off-by: Rhys Kidd <rhyskidd at gmail.com>
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
commit 82bc45bb0863f895a6ac7c734bf127a7d0290eeb
Author: Rhys Kidd <rhyskidd at gmail.com>
Date: Thu Aug 6 16:34:08 2015 +1000
i965: Resolve GCC sign-compare warning.
mesa/src/mesa/drivers/dri/i965/brw_draw.c: In function 'brw_draw_destroy':
mesa/src/mesa/drivers/dri/i965/brw_draw.c:630:18: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (i = 0; i < brw->vb.nr_buffers; i++) {
^
mesa/src/mesa/drivers/dri/i965/brw_draw.c:636:18: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (i = 0; i < brw->vb.nr_enabled; i++) {
^
Signed-off-by: Rhys Kidd <rhyskidd at gmail.com>
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
commit 4864977e51872bf4c810358f03cf56722f9efb9b
Author: Rhys Kidd <rhyskidd at gmail.com>
Date: Thu Aug 6 16:34:07 2015 +1000
mesa/egl: Resolve GCC sign-compare warning.
mesa/src/egl/drivers/dri2/platform_drm.c: In function 'release_buffer':
mesa/src/egl/drivers/dri2/platform_drm.c:73:18: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (i = 0; i < ARRAY_SIZE(dri2_surf->color_buffers); i++) {
^
mesa/src/egl/drivers/dri2/platform_drm.c: In function 'has_free_buffers':
mesa/src/egl/drivers/dri2/platform_drm.c:87:18: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (i = 0; i < ARRAY_SIZE(dri2_surf->color_buffers); i++)
^
mesa/src/egl/drivers/dri2/platform_drm.c: In function 'dri2_drm_destroy_surface':
mesa/src/egl/drivers/dri2/platform_drm.c:199:18: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (i = 0; i < ARRAY_SIZE(dri2_surf->color_buffers); i++) {
^
mesa/src/egl/drivers/dri2/platform_drm.c: In function 'get_back_bo':
mesa/src/egl/drivers/dri2/platform_drm.c:224:21: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (i = 0; i < ARRAY_SIZE(dri2_surf->color_buffers); i++) {
^
mesa/src/egl/drivers/dri2/platform_drm.c: In function 'dri2_drm_swap_buffers':
mesa/src/egl/drivers/dri2/platform_drm.c:425:24: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (i = 0; i < ARRAY_SIZE(dri2_surf->color_buffers); i++)
^
Signed-off-by: Rhys Kidd <rhyskidd at gmail.com>
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
commit 1d8c6949285dc59e53c6145d5b93b6549981711a
Author: Rhys Kidd <rhyskidd at gmail.com>
Date: Thu Aug 6 16:34:06 2015 +1000
mesa/gbm: Resolve GCC sign-compare warning.
mesa/src/gbm/main/backend.c: In function 'find_backend':
mesa/src/gbm/main/backend.c:70:18: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (i = 0; i < ARRAY_SIZE(backends); ++i) {
^
mesa/src/gbm/main/backend.c: In function '_gbm_create_device':
mesa/src/gbm/main/backend.c:95:18: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (i = 0; i < ARRAY_SIZE(backends) && dev == NULL; ++i) {
^
Signed-off-by: Rhys Kidd <rhyskidd at gmail.com>
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
commit f5bb5b957a1ca33015400dd2274c7b73cb0e40f4
Author: Rhys Kidd <rhyskidd at gmail.com>
Date: Thu Aug 6 16:34:05 2015 +1000
mesa/glx: Resolve GCC sign-compare warning.
mesa/src/glx/dri_common_query_renderer.c: In function 'dri2_convert_glx_query_renderer_attribs':
mesa/src/glx/dri_common_query_renderer.c:61:18: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (i = 0; i < ARRAY_SIZE(query_renderer_map); i++)
^
Signed-off-by: Rhys Kidd <rhyskidd at gmail.com>
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
commit dc7a1effc41b1fea7a7138fae942ae57ccd63d1d
Author: Rhys Kidd <rhyskidd at gmail.com>
Date: Thu Aug 6 16:34:04 2015 +1000
mesa/glx: Resolve GCC sign-compare warning.
mesa/src/glx/dri_common.c: In function 'scalarEqual':
mesa/src/glx/dri_common.c:259:18: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (i = 0; i < ARRAY_SIZE(attribMap); i++)
^
Signed-off-by: Rhys Kidd <rhyskidd at gmail.com>
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
commit f4ef8d084ce68784037d7f0b2f68d263359e0e00
Author: Rhys Kidd <rhyskidd at gmail.com>
Date: Thu Aug 6 16:34:03 2015 +1000
i965: Resolve GCC sign-compare warning.
mesa/src/mesa/drivers/dri/i965/intel_screen.c: In function 'intel_screen_make_configs':
mesa/src/mesa/drivers/dri/i965/intel_screen.c:1222:22: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (int i = 0; i < ARRAY_SIZE(formats); i++) {
^
mesa/src/mesa/drivers/dri/i965/intel_screen.c:1259:22: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (int i = 0; i < ARRAY_SIZE(formats); i++) {
^
mesa/src/mesa/drivers/dri/i965/intel_screen.c:1291:22: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (int i = 0; i < ARRAY_SIZE(formats); i++) {
^
Signed-off-by: Rhys Kidd <rhyskidd at gmail.com>
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
commit dc2b0b2067c686b802137ad34719e35545a67e6e
Author: Rhys Kidd <rhyskidd at gmail.com>
Date: Thu Aug 6 16:34:02 2015 +1000
i965: Resolve GCC sign-compare warning.
mesa/src/mesa/drivers/dri/i965/intel_fbo.c: In function 'intel_validate_framebuffer':
mesa/src/mesa/drivers/dri/i965/intel_fbo.c:734:18: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (i = 0; i < ARRAY_SIZE(fb->Attachment); i++) {
^
Signed-off-by: Rhys Kidd <rhyskidd at gmail.com>
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
commit 3637e1e7f69f9b344a98274e21f75220ca8674e6
Author: Rhys Kidd <rhyskidd at gmail.com>
Date: Thu Aug 6 16:34:01 2015 +1000
mesa: Resolve GCC sign-compare warning.
mesa/src/mesa/drivers/dri/common/utils.c: In function 'driGetConfigAttrib':
mesa/src/mesa/drivers/dri/common/utils.c:457:19: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (i = 0; i < ARRAY_SIZE(attribMap); i++)
^
Signed-off-by: Rhys Kidd <rhyskidd at gmail.com>
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
commit 65fe7c6ff112a979aa8c37bafcf54001e26e150f
Author: Rhys Kidd <rhyskidd at gmail.com>
Date: Thu Aug 6 16:34:00 2015 +1000
i965: Resolve GCC sign-compare warning.
mesa/src/mesa/drivers/dri/i965/intel_screen.c: In function 'aub_dump_bmp':
mesa/src/mesa/drivers/dri/i965/intel_screen.c:125:22: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (int i = 0; i < fb->_NumColorDrawBuffers; i++) {
^
Signed-off-by: Rhys Kidd <rhyskidd at gmail.com>
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
commit 2722284b94c5007d738a082c8c29c29972308e88
Author: Rhys Kidd <rhyskidd at gmail.com>
Date: Thu Aug 6 16:33:59 2015 +1000
i965: Resolve GCC sign-compare warning.
mesa/src/mesa/drivers/dri/i965/intel_fbo.c: In function 'intel_blit_framebuffer_with_blitter':
mesa/src/mesa/drivers/dri/i965/intel_fbo.c:836:21: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (i = 0; i < drawFb->_NumColorDrawBuffers; i++) {
^
V2 (Thomas Helland):
-Use unsigned instead of GLuint (trivial)
Signed-off-by: Rhys Kidd <rhyskidd at gmail.com>
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
commit 89b285ba0e3503de05e97cbb915485302e2fd37d
Author: Rhys Kidd <rhyskidd at gmail.com>
Date: Thu Aug 6 16:33:58 2015 +1000
i965: Resolve GCC sign-compare warning.
mesa/src/mesa/drivers/dri/i965/brw_wm_state.c: In function 'brw_color_buffer_write_enabled':
mesa/src/mesa/drivers/dri/i965/brw_wm_state.c:53:18: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
^
Signed-off-by: Rhys Kidd <rhyskidd at gmail.com>
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
commit 3696e620f562aad5b14f01d70c68957b7fbe8a48
Author: Rhys Kidd <rhyskidd at gmail.com>
Date: Thu Aug 6 16:33:57 2015 +1000
i965: Resolve GCC sign-compare warning.
mesa/src/mesa/drivers/dri/i965/brw_draw.c: In function 'brw_postdraw_set_buffers_need_resolve':
mesa/src/mesa/drivers/dri/i965/brw_draw.c:390:22: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (int i = 0; i < fb->_NumColorDrawBuffers; i++) {
^
Signed-off-by: Rhys Kidd <rhyskidd at gmail.com>
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
commit 8f7ebcb6fad53ea6d2f80fc5b7a046db07690032
Author: Adam Jackson <ajax at redhat.com>
Date: Fri Jul 31 11:32:58 2015 -0400
glx: Fix __glXWireToEvent for BufferSwapComplete
In the DRI2 path this event is magically synthesized from the
corresponding DRI2 event, but with Present, the server sends us the
event itself. The DRI2 path fills in the serial number, send_event, and
display fields of the XEvent struct that the app sees, but the Present
path did not.
This is likely related to a class of crashes seen in gtk/clutter apps:
https://bugzilla.redhat.com/attachment.cgi?id=1032631
Note that the crashing instruction is looking up the lock_fns slot in
the Display *, and %rdi (holding the Display *) is 0x1.
Cc: mesa-stable at lists.freedesktop.org
Signed-off-by: Adam Jackson <ajax at redhat.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 97f5d00648046a711b7806c3a47b28543c084f0e
Author: Grazvydas Ignotas <notasas at gmail.com>
Date: Tue Aug 18 02:51:58 2015 +0300
radeon/uvd: remove unused variables
Recent commits introduced new unused variable warnings, fix them.
Reviewed-by: Christian König <christian.koenig at amd.com>
commit df97126731a745c1797c783414a44652be039d84
Author: Marcos Paulo de Souza <marcos.souza.org at gmail.com>
Date: Sun Aug 16 13:31:58 2015 -0300
nouveau: recognize tess stages in nouveau_compiler
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 723a5a2e6881e55b50b23c470d7591360f061dba
Author: Marcos Paulo de Souza <marcos.souza.org at gmail.com>
Date: Sun Aug 16 13:31:57 2015 -0300
tgsi: fix parsing of tessellation shader inputs/outputs
Tessellation control shaders write to outputs as OUT[ADDR[0].x][0], make
sure to parse the indirect dimension on outputs.
Also tess control inputs/outputs and tess eval input declarations need
to receive the same treatment as geometry shader inputs.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit a37fa7653bead4985668c359391bdf01dec8b084
Author: Marcos Paulo de Souza <marcos.souza.org at gmail.com>
Date: Sun Aug 16 13:31:56 2015 -0300
tgsi: set implicit array size for tess stages
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 46684d3ae3a4084b00355df3feeeb25159656a8e
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Thu Aug 13 18:44:51 2015 +1000
mesa: move non-generic samples validation
The previous patch replaces the other use case.
V2: remove the validation from it old location.
Cc: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit d3ace603a97bdd031bdff7517728eff4d0fd6458
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Mon Aug 17 21:33:49 2015 +1000
mesa: check samples > 0 for glTex*Multisample
The GL 4.5 spec says its an GL_INVALID_VALUE error if samples equals 0 for
glTexImage*Multisample and an GL_INVALID_VALUE error if samples < 1 for
glTexStorage*Multisample.
The spec says its undefined what happens if glTexImage*Multisample is passed
a samples value < 0 but we currently already produced a GL_INVALID_VALUE error
in this case, this is also consistent with the Nvidia binary.
Cc: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 2450cbfcbc3671056afad9e858acadbb6edea068
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Aug 12 11:35:17 2015 -0700
i965/vec4/nir: Emit single MOV to generate a scalar constant.
If an immediate is written to multiple channels, we can load it in a
single writemasked MOV.
total instructions in shared programs: 6285144 -> 6261991 (-0.37%)
instructions in affected programs: 718991 -> 695838 (-3.22%)
helped: 5762
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 5af71fb5ac4dafed3ecc4b849922208cab76070f
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Dec 3 03:29:38 2014 -0500
freedreno/a3xx: add s3tc texture format support
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 581cbfdec1eda9128a9ed7ff9b0ea13ec4d3e493
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Aug 16 13:15:55 2015 -0400
freedreno/a3xx: fix up logic for handling block formats
This only appears in cubemaps which have have packed layers, so are very
sensitive to any layout disagreement between sw and hw.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 12e1bf0b68b3c0e8dccb74384554f56d22eda961
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Aug 16 15:26:38 2015 -0400
freedreno/a3xx: double the polygon offset value
A few other drivers do this, fixes the gl-1.4-polygon-offset piglit test
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 1af0641db345209c076e9b1ba4dca7524541671a
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Aug 17 04:08:01 2015 -0400
nvc0: implement the color buffer 0 is integer rule for alpha-to-one/cov
The hardware checks for multisampling being enabled, but does not have
the rule about cbuf0 being an integer format. Only enable
alpha-to-one/alpha-to-coverage if cbuf0 is not an integer format.
Fixes piglits
ext_framebuffer_multisample-int-draw-buffers-alpha-to-one
ext_framebuffer_multisample-int-draw-buffers-alpha-to-coverage
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 19a5a91ea49bd411f4d438d416000d49ecc2de7e
Author: Marta Lofstedt <marta.lofstedt at intel.com>
Date: Thu Aug 13 14:38:14 2015 +0200
mesa: Raise INVALID_VALUE from glCreateShaderProgramv if count < 0
According to OpenGL version 4.5 and OpenGL ES 3.1 standards, section 7.3:
GL_INVALID_VALUE should be generated, if count is less than 0.
V2: Changed title, eased Open GL ES 3.1 restriction and added comments.
Signed-off-by: Marta Lofstedt <marta.lofstedt at intel.com>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
commit dd9d2963d66d24394b20823fcffb809cc8d5389d
Author: Marta Lofstedt <marta.lofstedt at intel.com>
Date: Thu Aug 13 12:59:40 2015 +0200
mesa: AtomicBufferBindings should be initialized to zero.
According to OpenGL specification version 4.5 table 23.46
and OpenGL ES specification version 3.1 table 20.31:
ATOMIC_COUNTER_BUFFER_START and ATOMIC_COUNTER_BUFFER_SIZE
should have the initial value of zero.
Signed-off-by: Marta Lofstedt <marta.lofstedt at intel.com>
Reviewed-by: Erik Faye-Lund <kusmabite at gmail.com>
commit a7e6f8cc9f72fcf4eaef814eb50d53ccffd58730
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Thu Aug 13 17:03:44 2015 +0300
mesa: fix target error checking in glGetTexLevelParameter
With non-dsa functions we need to do target error checking before
_mesa_get_current_tex_object which would just call _mesa_problem without
raising GL_INVALID_ENUM error. In other places of Mesa, target gets checked
before this call.
Fixes failures in:
ES31-CTS.texture_storage_multisample.APIGLGetTexLevelParameterifv.*
v2: do the target check also for dsa functions (Timothy)
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
commit 2f5ee9bf27b912726dea969a5e5159e1d6665f6c
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Aug 17 02:11:55 2015 -0400
gk110/ir: fix sched calculator to consider all registers in the ISA
GK110/GK208 have 256 registers, not 64. Find out the number of registers
from the target to avoid unnecessary iteration for pre-GK110.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit e32325fc85f0d1485dec63b363c18d76f4e89714
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Sat Aug 15 13:29:19 2015 +1000
mesa: rename texture function now that its static
Reviewed-by: Brian Paul <brianp at vmware.com>
commit a0cea8f642688f9a51ee5cb96a3963372d14f14e
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Fri Aug 14 13:36:40 2015 +0300
glsl: add missing MS sampler builtin types for GLSL ES 3.10
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit f67dde0b0546779e422133f8b896a9b3669320c7
Author: Marta Lofstedt <marta.lofstedt at intel.com>
Date: Fri Aug 14 13:30:45 2015 +0200
mesa: Implement glMemoryBarrierByRegion
The function glMemoryBarrierByRegion is part of OpenGL ES 3.1
and OpenGL 4.5 core and compatibility profiles.
Signed-off-by: Marta Lofstedt <marta.lofstedt at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit ae5cf4f3f7525c49d1cd012697e8e30db86a8890
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Aug 17 00:53:04 2015 -0400
nvc0: program smooth line width when multisampling is enabled
There are separate line widths for smooth and aliased lines. The smooth
one is selected when multisampling is enabled even if line smoothing
isn't explicitly turned on.
Fixes the ext_framebuffer_multisample-line-smooth piglits
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 884b4df3b6f3980bb75f20fd256f9e2cca4d9403
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Jul 26 00:56:34 2015 -0400
nvc0: bind a fake tess control program when there isn't one available
Apparently this is necessary in order for tess factors to work in a tess
eval program without a tess control program bound. Probably because it
uses the fake program's shader header to work out the number of patch
constants.
Fixes vs-tes-tessinner-tessouter-inputs
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit f13073b7755e78306975a24f3286ff5a9c910a47
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Jul 24 01:25:13 2015 -0400
gm107/ir: avoid letting the lowering pass get out of sync
There's a lot of functionality duplicated in the gm107 lowering pass
from the nvc0 pass. As that one gets updated, the gm107 one falls
behind. Avoid this by sharing the code.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 2514c78fba507ca8ab94d2e6de553b8b20d653d2
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Aug 15 22:05:15 2015 -0400
nv50,nvc0: take level into account when doing eng2d multi-layer blits
This fixes arb_get_texture_sub_image-get, and any situation where the 2d
engine was being used for multi-layer blits to a non-0 level.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.6" <mesa-stable at lists.freedesktop.org>
commit bb9881fccf4c3606e66ec607dfb0387c9e068e3d
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Aug 15 21:42:02 2015 -0400
st/mesa: also move yoffset to zoffset for 1d array textures
Do the same as in st_TexSubImage. This fixes
arb_get_texture_sub_image-get on llvmpipe when it is set to prefer
blits, and nouveau when it uses the 3d engine for blits.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit afccbd725655e6e607029a8b359886f62e4aa807
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue May 12 01:12:46 2015 -0700
nir: Add a glsl_uint_type() wrapper.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
commit ca628085b6753c1dc5c9bd59460b5fa8fe0b34f2
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Aug 7 23:11:45 2015 -0400
freedreno/a3xx: add per-texture seamless cubemap control
The default is to enable seamless cubemap filtering, but there's a bit
to turn it off.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit b4ace13eeae7ec58262d8a3ec38adca63b6add76
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Aug 3 02:13:33 2015 -0400
freedreno/a4xx: add cube map array support
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 868b66fce7a156efda840c00088f89f4ba6163c9
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Aug 13 13:53:43 2015 -0400
freedreno/a4xx: fix srgb render targets
Also fixes mipmap level generation for srgb textures.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit dd412c8fcb1c44846419523bb0e3956f38f578b5
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Aug 13 20:38:01 2015 -0400
freedreno: update generated headers
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit ee113bbbc51f7c19da5c873410fadabfdd4d4a6d
Author: Vinson Lee <vlee at freedesktop.org>
Date: Fri Aug 14 15:19:49 2015 -0700
scons: Always define __STDC_LIMIT_MACROS.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91591
Signed-off-by: Vinson Lee <vlee at freedesktop.org>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit d19a98e2e63293e1dfd6947c18356e5bbefd2410
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Aug 14 10:49:46 2015 -0400
freedreno: expose OES exts for float linear filtering
a4xx can do both float and half-float, while a3xx can only do half-float
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit d3e23f1ff915c01541f8df375b50b93b3da565a8
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Aug 14 15:58:28 2015 -0400
nvc0: disable tessellation on maxwell
The address calculations are all different (e.g. see GP), there appear
to be sync's in programs, and probably a bunch of other differences.
Just disable it for now.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit a6e75e3cd74fd60200cc8dddc672a2d88495eb06
Author: Eric Anholt <eric at anholt.net>
Date: Fri Feb 6 16:24:36 2015 -0800
nir: Add support for CSE on textures.
NIR instruction count results on i965:
total instructions in shared programs: 1261954 -> 1261937 (-0.00%)
instructions in affected programs: 455 -> 438 (-3.74%)
One in yofrankie, two in tropics. Apparently i965 had also optimized all
of these out anyway.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit fb2425a641dd7f891964e6f51b10cce63dff7d2c
Author: Eric Anholt <eric at anholt.net>
Date: Tue Aug 11 17:10:35 2015 -0700
nir: Zero out texture instructions when creating them.
There are so many flags in textures, that the CSE pass would have a hard
time referencing the correct set when figuring out if two texture ops are
the same. By zeroing, we can avoid that fragility.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit bf3c50fba221f216e38d3f60f89161ced4c684c0
Author: Eric Anholt <eric at anholt.net>
Date: Mon Apr 13 21:36:24 2015 -0700
vc4: Move all of our fixed function fragment color handling to NIR.
This massively reduces our dependency on VC4-specific optimization passes.
shader-db:
total uniforms in shared programs: 32077 -> 32067 (-0.03%)
uniforms in affected programs: 149 -> 139 (-6.71%)
total instructions in shared programs: 98208 -> 98182 (-0.03%)
instructions in affected programs: 2154 -> 2128 (-1.21%)
commit 38c6c0f5b499e2bcff2cc9607f67c0f1836f305b
Author: Eric Anholt <eric at anholt.net>
Date: Fri Jul 31 09:02:01 2015 -0700
vc4: Add a helper for making driver-specific NIR load_uniform for GL state
In order to move more of our lowering into NIR, we need the ability to
reference various pipeline state (like texture rectangle scaling factors
or blend colors), so we just set those up as a load_uniform with a big
offset to indicate that it's not within the shader's uniform storage and
is one of our state values.
commit d50c182671a6aa315c83b5e203655e902996c0e7
Author: Eric Anholt <eric at anholt.net>
Date: Fri Jul 31 15:35:22 2015 -0700
nir: Don't try to scalarize unpack ops.
Avoids regressions in vc4 when trying to do our blending in NIR.
v2: Add the other unpack ops I meant to when writing the original commit
message.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 9e6dc5b64d5e931c7ebc272096eccab102b75d76
Author: Eric Anholt <eric at anholt.net>
Date: Tue Aug 4 16:25:24 2015 -0700
nir: Add a nir_opt_undef() to handle csels with undef.
We may find a cause to do more undef optimization in the future, but for
now this fixes up things after if flattening. vc4 was handling this
internally most of the time, but a GLB2.7 shader that did a conditional
discard and assign gl_FragColor in the else was still emitting some extra
code.
total instructions in shared programs: 100809 -> 100795 (-0.01%)
instructions in affected programs: 37 -> 23 (-37.84%)
v2: Use nir_instr_rewrite_src() to update def/use on src[0] (by Thomas
Helland).
v3: Make sure to flag metadata dirties, and copy the swizzle and abs/neg
over to src[0], too (by anholt).
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com> (v2)
Tested-by: Thomas Helland <thomashelland90 at gmail.com> (v2)
commit b346a84e270a50f0a8f1a6e474a51da04dd72f0e
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Aug 14 14:10:36 2015 -0400
gm107/ir: indirect handle goes first on maxwell also
Fixes fs-simple-texture-size.shader_test
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.6" <mesa-stable at lists.freedesktop.org>
commit 7ff7d5d799a54f2b08a3019df7fd531501174182
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Tue Aug 11 12:19:54 2015 -0400
nv30: add depth bounds test support for hw that has it
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit a6bf20d153f06639e1ae7d52d37ace9df440354d
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Tue Aug 11 11:59:56 2015 -0400
nv50: add depth bounds test support
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit d4087265f656c1998e20cbe2c9b6beaff6762b76
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Tue Aug 11 11:46:22 2015 -0400
nvc0: add depth bounds test support
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit a90aa54fde37cbdf162bf909a9e895b764eb41ea
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Aug 13 23:46:13 2015 +0200
docs/relnotes: document amdgpu, GL 4.1 and other new features
commit 7bfb9ee5ee0551ef2c2056e7fe2e63e35c629e3c
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Apr 16 22:59:41 2015 +0200
radeonsi: add all new VI PCI IDs including Fiji
commit f47c59322e614d6304091207fc81cfa5beba6ea9
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Aug 10 16:23:53 2015 +0200
radeonsi: revert a wrong DB bug workaround for VI
The bug was misunderstood. Besides that, the bug affects a DB feature we
don't use yet.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 839bf82606ae9c7b1c7d8d5055ab5e3cadae9bf9
Author: Boyuan Zhang <boyuan.zhang at amd.com>
Date: Wed Jul 8 16:54:48 2015 -0400
radeon/uvd: implement HEVC support
add context buffer to fix H265 uvd decode issue.
fix H265 corruption issue caused by incorrect assigned ref_pic_list.
v2: disable interlace for HEVC
add CZ sps flag workaround
fix coding style
Signed-off-by: Christian König <christian.koenig at amd.com>
Signed-off-by: Boyuan Zhang <boyuan.zhang at amd.com>
Reviewed-by: Leo Liu <leo.liu at amd.com>
commit 0654a9ca17c17fe140f70d126c878a0ce4736b76
Author: Leo Liu <leo.liu at amd.com>
Date: Mon Jul 13 13:36:27 2015 -0400
radeon/vce: disable VCE dual instance for harvest part
Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
commit 09def7e1e06827ab1eae091f0e765d91c6715cf9
Author: Leo Liu <leo.liu at amd.com>
Date: Thu Jun 25 10:14:14 2015 -0400
radeon/vce: implement VCE dual instance support
VCE dual instances are encoding in parallel, it needs two frames for
encoding with their own parameters in one IB. Master instance will check
the task info to find another frame, assign it to the slave instance
Signed-off-by: Leo Liu <leo.liu at amd.com>
Signed-off-by: Christian König <christian.koenig at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
commit 4dfcf6e3a91be97fcf9d3f44e76a7a389f8f40b2
Author: Leo Liu <leo.liu at amd.com>
Date: Thu Jun 25 12:12:12 2015 -0400
radeon/video: config encode stacked frame number based on HW
since VCE 3.0 with dual instances, we need stack frames for them.
Signed-off-by: Leo Liu <leo.liu at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
commit 42bc4e6be434b398d9edaff0ed10dfb5bf89b6a6
Author: Christian König <christian.koenig at amd.com>
Date: Mon Jun 15 20:19:48 2015 +0200
radeon/vce: make reloc offset signed
We need a negative offset for FW 50.
Signed-off-by: Christian König <christian.koenig at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
commit 57fabe9f3a21a2a370284575833637d37e987cb5
Author: Leo Liu <leo.liu at amd.com>
Date: Mon Jun 1 13:48:24 2015 -0400
radeon/vce: add config task and put task info into encoder v2
The config task has own task ID, extract the configuration functions
into config task.
v2 (chk): calculate offset automatically
Signed-off-by: Leo Liu <leo.liu at amd.com>
Signed-off-by: Christian König <christian.koenig at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
commit e91a67abfa5112acd481ee4a3f07c03f6ff2708c
Author: Leo Liu <leo.liu at amd.com>
Date: Mon Jun 15 15:20:20 2015 -0400
radeon/vce: fix VCE fail after rebase
Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
commit fa80c1fe20f1fc33864f04fd9cf49f8bddfa4448
Author: Leo Liu <leo.liu at amd.com>
Date: Mon Jun 15 14:11:57 2015 -0400
radeon/vce: add dual pipe support for VI
Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
commit 468fcdcb4fafeba466bb1006ece1f16cc38805c7
Author: Leo Liu <leo.liu at amd.com>
Date: Fri May 29 13:43:00 2015 -0400
radeon/vce: add new firmware support for VI and CI
Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
commit 1550790b3fab901c697e9d8e5b01ea67d8843e99
Author: Leo Liu <leo.liu at amd.com>
Date: Wed Apr 15 12:36:32 2015 -0400
radeon/vce: implement VCE two pipe support
v2: rebase by Marek
Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
commit 22f71dbf7976d1803940bc2a0429c3d302dae9fa
Author: Leo Liu <leo.liu at amd.com>
Date: Thu Mar 12 16:24:57 2015 -0400
radeon/uvd: make 30M as minimum for MPEG4 dpb buffer size
Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
commit baecc518c9adcd073e725268421a049dd610d22f
Author: Leo Liu <leo.liu at amd.com>
Date: Thu Mar 12 16:13:44 2015 -0400
radeon/uvd: recalculate dbp buffer size
Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
commit c29f0d4722832a9d284aba899875955e60a41c03
Author: Leo Liu <leo.liu at amd.com>
Date: Mon Mar 9 16:24:48 2015 -0400
radeon/video: add 4K support for decode/encode parameters
Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
commit 261ed775475db8d328a772fc4ff151d63969c84a
Author: Leo Liu <leo.liu at amd.com>
Date: Mon Dec 15 12:51:50 2014 -0500
gallium/radeon: add h264 performance HW decoder support
v2: -make tonga use new h264 performance HW decoder;
-integrate it scaling buffer to msg_fb buffer
Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
commit 67586c4b40881940535658c3c89b5b1a42f94027
Author: Christian König <christian.koenig at amd.com>
Date: Thu Apr 10 17:18:32 2014 +0200
gallium/radeon: use VM for VCE
v2: (leo) add checking for driver backend
v3: (leo) change variable name from use_amdgpu to use_vm
v4: rebase by Marek
Signed-off-by: Christian König <christian.koenig at amd.com>
Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
commit 0248c13a8b1e10e2c8c8d614473c701239627a71
Author: Christian König <christian.koenig at amd.com>
Date: Wed Apr 9 19:41:06 2014 +0200
gallium/radeon: use VM for UVD
v2: (leo) add checking for driver backend
v3: (leo) change variable name from use_amdgpu to use_vm
v4: rebase by Marek
Signed-off-by: Christian König <christian.koenig at amd.com>
Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
commit 767ad50a10d01274b1d1a877add12b5552ba6984
Author: Alex Deucher <alexander.deucher at amd.com>
Date: Wed Jul 29 15:40:46 2015 -0400
radeonsi: add support for FIJI (v4)
v2: incorporate comments from Marek
v3: add missing fiji case in winsys init
use tonga raster config (double check this)
v4: rebase on harvest patch
Reviewed-by: Marek Olšák <marek.olsak at amd.com> (v3)
Reviewed-by: Christian König <christian.koenig at amd.com> (v3)
Reviewed-by: David Zhang <david1.zhang at amd.com> (v3)
Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
commit 528a6ff5992e6710921d6e4157a8a51884bc277f
Author: Alex Deucher <alexander.deucher at amd.com>
Date: Tue Jul 7 22:18:13 2015 -0400
winsys/amdgpu: add addrlib support for Fiji (v2)
v2: fix tonga chip check
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
Reviewed-by: David Zhang <david1.zhang at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
commit d69686f1d375c3a65a4398f69da843e833987b0e
Author: Alex Deucher <alexander.deucher at amd.com>
Date: Wed Jul 8 22:19:55 2015 -0400
radeonsi: add harvest support for CI/VI parts (v3)
Properly calculate the PA_SC_RASTER_CONFIG[_1] settings
for harvest chips.
v2: - fix default raster config settings for CZ and KV
- Suggestions from Michel
v3: - handle multiple packers properly for CI+
- GRBM_GFX_INDEX is privileged on VI+
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com> (v2)
Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
commit 933d24b1768d769f1847a023ea3c70b6c9723e33
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jun 27 13:57:25 2015 +0200
gallium/radeon: enable the GPU load query for amdgpu
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
commit f0e24a7beae57f24501fa9d3b6b947fc20ca23bb
Author: Alex Deucher <alexander.deucher at amd.com>
Date: Wed Jun 10 11:43:24 2015 -0400
radeonsi: properly handler raster_config setup on CZ
Need to take into account the number of RBs.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
commit 649975e7162cc4ee0586ee76d24321cd7250581f
Author: Alex Deucher <alexander.deucher at amd.com>
Date: Wed Jun 10 11:39:30 2015 -0400
radeonsi: properly set the raster_config for KV
This enables the second RB on asics that support it which
should boost performance.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
Cc: mesa-stable at lists.freedesktop.org
commit bf2c3422d7c12bdead944c3de8b37b809f4cbcbb
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Apr 30 17:02:38 2015 +0200
radeonsi: add amdgpu support for querying the GPU reset state
Reviewed-by: Christian König <christian.koenig at amd.com>
commit 2d1952e2a5abd273983374b420371d263388bb20
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Apr 16 20:44:54 2015 +0200
radeonsi: add VI hardware support
commit 943a4b5e963a3bbeb3a0a39d0123e359fdf3ec07
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jul 11 13:22:22 2015 +0200
radeonsi: add definitions for VI status registers
Useful for debugging hangs with the read-register interface.
I checked that this adds the same register fields as the kernel driver.
Acked-by: Michel Dänzer <michel.daenzer at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
commit 8f49f6ed19ba4ee6a26c77786dcbc151c6615d48
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Apr 16 20:12:24 2015 +0200
radeonsi: add VI register definitions
commit 8ba70e0a7405005c079eb72f94999245c992aa91
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Apr 16 20:35:27 2015 +0200
radeonsi: fix DRM version checks for amdgpu DRM 3.0.0
commit e7fc664b91a5d886c2709d05a498f6a1dfbaf136
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Apr 16 19:41:33 2015 +0200
winsys/amdgpu: add addrlib - texture addressing and alignment calculator
This is an internal project that Catalyst uses and now open source will do
too.
v2: squashed these commits in:
- winsys/amdgpu: fix warnings in addrlib
- winsys/amdgpu: set PIPE_CONFIG and NUM_BANKS in tiling_flags
commit 2eb067db0febcd71b4182153155e3e43f215624c
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Apr 16 22:43:23 2015 +0200
winsys/amdgpu: add a new winsys for the new kernel driver
v2: - lots of changes according to Emil Velikov's comments
- implemented radeon_winsys::read_registers
v3: - a lot of new work, many of them adapt to libdrm interface changes
Squashed patches:
winsys/amdgpu: implement radeon_winsys context support
winsys/amdgpu: add reference counting for contexts
winsys/amdgpu: add userptr support
winsys/amdgpu: allocate IBs like normal buffers
winsys/amdgpu: add IBs to the buffer list, adapt to interface changes
winsys/amdgpu: don't use KMS handles as reloc hash keys
winsys/amdgpu: sync buffer accesses to different rings
winsys/amdgpu: use dependencies instead of waiting for last fence v2
gallium/radeon: unify buffer_wait and buffer_is_busy in the winsys interface (amdgpu part)
winsys/amdgpu: track fences per ring and be thread-safe
winsys/amdgpu: simplify waiting on a variable in amdgpu_fence_wait
gallium/radeon: allow the winsys to choose the IB size (amdgpu part)
winsys/amdgpu: switch to new amdgpu_cs_query_fence_status interface
winsys/amdgpu: handle fence and dependencies merge
winsys/amdgpu follow libdrm change to move user fence into UMD
winsys/amdgpu: use amdgpu_bo_va_op for va map/unmap v2
winsys/amdgpu: use the new tiling flags
winsys/amdgpu: switch to new GTT_USWC definition
winsys/amdgpu: expose amdgpu_cs_query_reset_state to drivers
winsys/amdgpu: fix valgrind warnings
winsys/amdgpu: don't use VRAM with APUs that don't have much of it
winsys/amdgpu: require LLVM 3.6.1 for VI because of bug fixes there
winsys/amdgpu: remove amdgpu_winsys::num_cpus
winsys/amdgpu: align BO size to page size
winsys/amdgpu: reduce BO cache timeout
winsys/amdgpu: remove useless flushing and waiting in amdgpu_bo_set_tiling
winsys/amdgpu: use amdgpu_device_handle as a unique device ID instead of fd
winsys/amdgpu: use safer access to amdgpu_fence_wait::signalled
winsys/amdgpu: allow maximum IB size of 4 MB
winsys/amdgpu: add ip_instance into amdgpu_fence
gallium/radeon: add RING_COMPUTE instead of RADEON_FLUSH_COMPUTE
winsys/amdgpu: set the ring type at CS initilization
winsys/amdgpu: query the GART page size from the kernel
winsys/amdgpu: correctly wait for shared buffers to become idle
winsys/amdgpu: set the amdgpu_cs_fence structure only once at fence creation
winsys/amdgpu: add a specific error message for cs_submit -> -ENOMEM
winsys/amdgpu: check num_active_ioctls before calling amdgpu_bo_wait_for_idle
winsys/amdgpu: clear user fence BO after allocating it
winsys/amdgpu: fix user fences
winsys/amdgpu: make amdgpu_winsys_create public
winsys/amdgpu: remove thread offloading
winsys/amdgpu: flatten the amdgpu_cs_context structure and simplify more
v4: require libdrm 2.4.63
commit 5609a6986f3eb3c452d66d373b6081df5c6fb34c
Author: Christian König <christian.koenig at amd.com>
Date: Wed Apr 29 15:35:02 2015 +0200
st/vdpau: add HEVC support v2
v2: fix return code
Signed-off-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Leo Liu <leo.liu at amd.com>
commit 5581f9f28aeaef63bc1495febb402435ddfde556
Author: Leo Liu <leo.liu at amd.com>
Date: Thu Jun 25 13:19:56 2015 -0400
st/omx/enc: stack frame tasks for the gathering
Put tasks to the FIFO queue for results
Signed-off-by: Leo Liu <leo.liu at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
commit 0729c251bbff8375ab5d24b80cfc2f8becd6afff
Author: Leo Liu <leo.liu at amd.com>
Date: Fri May 29 14:50:44 2015 -0400
st/omx/enc: flush after eos handling v2
v2 (chk): reorder the flush
Signed-off-by: Leo Liu <leo.liu at amd.com>
Signed-off-by: Christian König <christian.koenig at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
commit facba49d839b01da139261e587a05c744cc9a1fa
Author: Christian König <christian.koenig at amd.com>
Date: Tue Apr 28 15:31:37 2015 +0200
vl: add HEVC profiles and defines
Signed-off-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Leo Liu <leo.liu at amd.com>
commit 716a67da12be0656a6dae2a448175946aaf57377
Author: Leo Liu <leo.liu at amd.com>
Date: Thu Jun 25 12:09:11 2015 -0400
vl: add cap for stacking frames
Signed-off-by: Leo Liu <leo.liu at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
commit 973988ab8dd4d04b925a5859d1da0801e858a6fe
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Aug 13 01:51:37 2015 +0200
swrast: fix EXT_depth_bounds_test
zMin and zMax can't use _DepthMaxF, because the test is done in Z32_UNORM.
Probably a useless patch given how popular swrast is nowadays, but it helped
create and validate the piglit test.
v2: add an explicit cast to GLuint
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 97f58fb59a45f04c9d03709063a081f572509f51
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Aug 10 02:23:21 2015 +0200
radeonsi: add support for EXT_depth_bounds_test
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 36a6f848bb03828aa9c4dc28774acf09055f2831
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Aug 10 02:18:43 2015 +0200
st/mesa: add EXT_depth_bounds_test
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 3b7800e75089d4dc8ed9b2a0ce994760c167b93a
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Aug 10 02:11:48 2015 +0200
gallium: add an interface for EXT_depth_bounds_test
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 2ebb8efa08b4ea290b8a2bb9aa2e3784b8272d87
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Aug 10 19:53:22 2015 +0200
st/mesa: small cleanup in st_extensions.c
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
commit 44dc1d307d7eacef0d6f1618ba0fb7f62e08f896
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Aug 10 19:37:01 2015 +0200
gallium: add support for GLES texture float extensions (v3)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74329
v2: add a CAP for half floats
drivers should not expose the CAPs if they don't support the formats
v3: update relnotes
Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit 78493c33183bf2a4b8be0e58963162ef2e3aa54a
Author: Zoltan Gilian <zoltan.gilian at gmail.com>
Date: Tue Jul 7 23:38:27 2015 +0200
r600,compute: setup compute sampler states and views
v2: Add compute mode flag to sampler state setup (Marek).
Drop branches which avoid reference counting (Marek).
Simplify unset branch condition (Marek).
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 7f4ad692a10bf0f247dedd4968b7ffe9b07d2af2
Author: Michel Dänzer <michel.daenzer at amd.com>
Date: Fri Aug 14 15:16:12 2015 +0900
st/clover: Fix build against LLVM 3.8 SVN r244928
raw_svector_ostream::flush() is now unnecessary and forbidden:
CXX llvm/libclllvm_la-invocation.lo
../../../../../src/gallium/state_trackers/clover/llvm/invocation.cpp: In function 'clover::module {anonymous}::build_module_llvm(llvm::Module*, unsigned int (&)[7])':
../../../../../src/gallium/state_trackers/clover/llvm/invocation.cpp:574:29: error: use of deleted function 'void llvm::raw_svector_ostream::flush()'
bitcode_ostream.flush();
^
In file included from /home/daenzer/src/llvm-git/llvm/include/clang/Basic/VirtualFileSystem.h:22:0,
from /home/daenzer/src/llvm-git/llvm/include/clang/Basic/FileManager.h:20,
from /home/daenzer/src/llvm-git/llvm/include/clang/Basic/SourceManager.h:38,
from /home/daenzer/src/llvm-git/llvm/include/clang/Frontend/CompilerInstance.h:16,
from ../../../../../src/gallium/state_trackers/clover/llvm/invocation.cpp:25:
/home/daenzer/src/llvm-git/llvm/include/llvm/Support/raw_ostream.h:512:8: note: declared here
void flush() = delete;
^
Makefile:862: recipe for target 'llvm/libclllvm_la-invocation.lo' failed
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 7a144aaf64e5cfff5aa53d7fd340c91762e51aa5
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Thu Aug 13 09:30:35 2015 +0300
mesa: set correct error for non-renderable multisample textures
v2: same common error on gles31 and desktop OpenGL
(spotted by Erik Faye-Lund)
Signed-off-by: Marta Lofstedt <marta.lofstedt at linux.intel.com>
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
commit 28ed1e08e8ba98ebd4ff0b56326372f0df9c73ad
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Fri Aug 7 13:58:37 2015 -0700
i965/skl: Remove early platform support
We do not want bug reports from this early stepping of SKL. Few if any were ever
shipped outside of Intel to early enabling partners, and none will be sold.
There is a functional change here. If you're using new mesa on an old
kernel/libdrm, the revid will be -1, and we'll use new SKL values instead of
early ones (a hopefully irrelevant improvement IMO).
v2: Remove hunk which warned before dying. Instead, default to normal SKL
support (Ken)
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Neil Roberts <neil at linux.intel.com>
commit d9603be038b6d30f17ca7c05e60cc78100a625ac
Author: Frank Binns <frank.binns at imgtec.com>
Date: Wed Aug 12 16:36:00 2015 +0100
egl: improve attribute checking for eglCreateContext
The EGL 1.4 spec states for eglCreateContext:
"attribute EGL_CONTEXT_CLIENT_VERSION is only valid when the current
rendering API is EGL_OPENGL_ES_API"
Additionally, if the EGL_KHR_create_context EGL extension is supported
(this is mandatory in EGL 1.5) then the EGL_CONTEXT_MAJOR_VERSION_KHR,
which is an alias for EGL_CONTEXT_CLIENT_VERSION, and
EGL_CONTEXT_MINOR_VERSION_KHR attributes are also accepted by
eglCreateContext with the extension spec stating:
"The values for attributes EGL_CONTEXT_MAJOR_VERSION_KHR and
EGL_CONTEXT_MINOR_VERSION_KHR specify the requested client API
version. They are only meaningful for OpenGL and OpenGL ES
contexts, and specifying them for other types of contexts will
generate an error."
Add the necessary checks against the extension and rendering APIs when
validating these attributes as part of eglCreateContext.
Signed-off-by: Frank Binns <frank.binns at imgtec.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
[Emil Velikov: Add newline before the spec quote (Matt)]
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 21b2c6fd5ea5ec2a810945c3c61b14d93a53991d
Author: Frank Binns <frank.binns at imgtec.com>
Date: Wed Aug 12 16:35:59 2015 +0100
egl: don't allow eglGetConfigs to set num_configs param to a negative value
When a buffer is provided to eglGetConfigs it's supposed to set the value
of the num_config parameter to the total number of configs that have been
copied into this buffer. For some reason the EGL spec doesn't consider it
to be an error to pass this function a buffer while specifying its size to
be less than 0. Given this, one would expect this combination to result in
the num_config parameter being set to 0 but this wasn't the case. This was
due to the buffer size being copied straight into num_configs without being
clamped to 0.
This was causing the following dEQP EGL test to fail:
dEQP-EGL.functional.query_config.get_configs.get_configs_bounds
Signed-off-by: Frank Binns <frank.binns at imgtec.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 9a4eae61c24858d69d731d63b141d2acaed40d69
Author: Frank Binns <frank.binns at imgtec.com>
Date: Tue Aug 4 14:32:45 2015 +0100
egl/x11: don't abort when creating a DRI2 drawable fails
When calling either eglCreateWindowSurface or eglCreatePixmapSurface it
was possible for an application to be aborted as a result of it failing
to create a DRI2 drawable on the server. This could happen due to an
application passing in an invalid native drawable handle, for example.
v2: Handle the case where an error has been set on the connection
Cc: <mesa-stable at lists.freedesktop.org>
Signed-off-by: Frank Binns <frank.binns at imgtec.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 3b491cbc42f6cfad2e750957f720b15b95278acf
Author: Frank Binns <frank.binns at imgtec.com>
Date: Tue Aug 4 14:32:44 2015 +0100
egl/x11: set EGL_BAD_NATIVE_(PIXMAP|WINDOW) for invalid pixmaps/windows
Both eglCreatePixmapSurface and eglCreateWindowSurface were incorrectly
setting the EGL error to be EGL_BAD_ALLOC when an invalid native drawable
handle was being passed in. The EGL spec states the following for
eglCreatePixmapSurface:
"If pixmap is not a valid native pixmap handle, then an EGL_BAD_-
NATIVE_PIXMAP error should be generated."
(eglCreateWindowSurface has similar text)
Correctly set the EGL error value based on xcb_get_geometry_reply returning
an error structure containing something other than BadAlloc.
v2: Check for BadAlloc error and update commit message to reflect this
Signed-off-by: Frank Binns <frank.binns at imgtec.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 2900e8ca9077d20c5b29bb5a4171ac59ea9d1767
Author: Frank Binns <frank.binns at imgtec.com>
Date: Tue Aug 4 14:32:43 2015 +0100
egl/x11: fix use of EGL_BAD_NATIVE_WINDOW
Commit 4ed23fd590 introduced some calls to _eglError inappropriately
passing it EGL_BAD_NATIVE_WINDOW. This was actually harmless in two of the
cases as _eglError gets called later on with a more appropriate error code
but (just to be safe) switch these to _eglLog calls instead.
The final case is a little trickier as it actually needs to set an error
of which the following are available (according to the EGL spec):
EGL_BAD_MATCH, EGL_BAD_CONFIG, EGL_BAD_NATIVE_(PIXMAP|WINDOW) and
EGL_BAD_ALLOC.
Of these, EGL_BAD_ALLOC seems to be the most appropriate given that
failure can occur either as a result of xcb_get_setup failing due to an
earlier error on the connection (where the most commonly occurring error
code is XCB_CONN_CLOSED_MEM_INSUFFICIENT) or as a result of the
xcb_screen_iterator_t 'rem' field being 0.
In addition to this, commit af2aea40d2 unconditionally set the error to
EGL_BAD_NATIVE_WINDOW when creating a window or pixmap surface with a NULL
native handle. Change this to correctly set the error based on surface
type.
v2: Updated patch description (Emil Velikov)
Return EGL_BAD_NATIVE_PIXMAP when eglCreatePixmapSurface is called
with a NULL native pixmap handle
Signed-off-by: Frank Binns <frank.binns at imgtec.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 8dffa89e013b611cdafbb2cc5216450fa248cb7c
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Thu Aug 13 18:42:54 2015 +1000
mesa: remove extern from texture function
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit b8f63b3c1002eea9cc6d54191bd41ea43c467e96
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Wed Aug 12 17:01:52 2015 +1000
glsl: make linker error message more informative
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 1bba29ed403e735ba0bf04ed8aa2e571884fcaaf
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Thu Jun 25 14:00:41 2015 +0300
i965: Stop aux data compare preventing program binary re-use
Items in the program cache consist of three things: key, the data
representing the instructions and auxiliary data representing
uniform storage. The data consisting of instructions is stored into
a drm buffer object while the key and the auxiliary data reside in
malloced section. Now the cache uploading is equipped with a check
that iterates over existing items and seeks to find a another item
using identical instruction data than the one being just uploaded.
If such is found there is no need to add another section into the
drm buffer object holding identical copy of the existing one. The
item just being uploaded should instead simply point to the same
offset in the underlying drm buffer object.
Unfortunately the check for the matching instruction data is
coupled with a check for matching auxiliary data also. This
effectively prevents the cache from ever containing two items
that could share a section in the drm buffer object.
The constraint for the instruction data and auxiliary data to
match is, fortunately, unnecessary strong. When items are stored
into the cache they will anyway contain their own copy of the
auxiliary data (even if they matched - which they in real world
never will). The only thing the items would be sharing is the
instruction data and hence we should only check for that to match
and nothing else.
No piglit regression in jenkins.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 12a66d91f6b0beff123fb6fd8a4f3c3796379532
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Thu Jun 25 14:35:26 2015 +0300
i965: Only write program to cache when it doesn't exist yet
Current logic re-writes the same data when existing data is found.
Not that this actually matters at the moment in practice, the
contraint for finding matching data is too severe to ever allow
data to be shared between two items in the cache.
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit b4897eb70a994c4630b0fde4a66dd6ace833c33a
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Thu Jun 25 14:31:03 2015 +0300
i965: Rename brw_upload_item_data to brw_alloc_item_data
and simplify the interface to take directly the size and to return
the offset. The routine does nothing more than allocate, it doesn't
upload anything.
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 853853b2ac527698215b4290629ec242333e264a
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Wed Aug 12 11:13:40 2015 +0300
mesa: update MaxShaderStorageBlockSize to 2^27
Extension spec originally required 2^24 but 2^27 is the minimum value
required by OpenGL 4.5 and OpenGL ES 3.1 specifications.
Fixes:
ES31-CTS.shader_storage_buffer_object.basic-max
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 24695f4b2738d930a2bc71b4ebc9e5d993980cae
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Mon Aug 3 10:46:33 2015 +0300
mesa: fix name returned for XFB varyings
_mesa_get_program_resource_name has logic to append '[0]' in name
if variable is an array, this should be skipped for XFB varyings
that have array index already appended.
v2: fix comment, change also GL_NAME_LENGTH query to match
the behaviour
Fixes:
ES31-CTS.program_interface_query.transform-feedback-types
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
commit 86a72ee48eb371566765566fc778d790bc9ce201
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date: Wed Jul 29 21:49:45 2015 +1000
mesa: Fix printf format specifier warn of the ptrdiff_t
See §7.19.6.1, paragraph 7 of the ISO C specification.
Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit 8c0b943e87b48e7359230825cc06fbdd059a9e58
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Aug 11 21:37:59 2015 +0200
r600g: allow setting geometry shader sampler states
We were ignoring them. This is both hilarious and sad.
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
commit d335aad11b208bcdcc75a99d4b6c5fc8b69ce368
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Aug 11 22:36:51 2015 +0200
r600g: fix polygon offset scale
The value was copied from r300g, which uses 1/12 subpixels, but this hw
uses 1/16 subpixels.
Should fix piglit: gl-1.4-polygon-offset (formerly a glean test)
(untested, ported from radeonsi)
Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Cc: mesa-stable at lists.freedesktop.org
commit bfac8ba9d32be351277c7ea814ac9848bdcb1f16
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Aug 11 22:36:51 2015 +0200
radeonsi: fix polygon offset scale
The value was copied from r300g, which uses 1/12 subpixels, but this hw
uses 1/16 subpixels.
Fixes piglit: gl-1.4-polygon-offset (formerly a glean test)
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
Cc: mesa-stable at lists.freedesktop.org
commit 8ae88105b60be613126ea07492ffd9712e5e71eb
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Aug 10 02:28:01 2015 +0200
radeonsi: enable VS_OUT_MISC_SIDE_BUS_ENA
This is recommended for better performance.
Diag tests always enable this.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit e7a52a5cb810de49a8282cb9f9caea5d554c3348
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Aug 10 01:50:11 2015 +0200
radeonsi: add support for gl_PrimitiveID in the fragment shader
It must be obtained from the VS.
The GS scenario A must be enabled for PrimID to be generated for the VS.
+ 4 piglits
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 8e11be0ddb0920633c5fab8d6a6460b7591a2627
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Aug 10 00:52:21 2015 +0200
radeonsi: move VGT_GS_MODE to the VS state
The VS will want to select GS scenario A here (VS with PrimitiveID).
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit bdc564b942ba292a897ea0d7d37f4bcafc236129
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Aug 12 11:39:24 2015 -0400
freedreno/a4xx: format updates
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 500025a23784877c8a61d8b3c7a8eab6fddf242a
Author: Rob Clark <robclark at freedesktop.org>
Date: Tue Aug 11 16:47:16 2015 -0400
freedreno/a3xx+a4xx: add texture buffer object support
Basic texture buffer support. Should be straightforward to add first/
last_element support. And with a bit of work in ir3 emulate larger
texture buffer sizes. But this seems to be enough for stk gl31 render
paths.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit fb07c49f4883b12cef37748271d99e2fcf217a72
Author: Rob Clark <robclark at freedesktop.org>
Date: Tue Aug 11 16:33:14 2015 -0400
ttn: add buffer texture type
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit aab3912f21508b0681962c68fdaca1435c06b2ea
Author: Rob Clark <robclark at freedesktop.org>
Date: Tue Aug 11 16:11:04 2015 -0400
freedreno/ir3: 'keeps' need neighbors found too
This shows up with a glamor shader, which does a TXF and uses the result
for conditional kill. Before we wouldn't group the fanin (collect)
neighbors which need to be allocated adjacently at RA, resulting in
badness.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 6e04020dd7784bb44d5e04b41efce342f80840cf
Author: Rob Clark <robclark at freedesktop.org>
Date: Tue Aug 11 16:09:48 2015 -0400
freedreno/ir3/print: print left/right neighbors too
When debugging compiler, this is useful to see.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 0667962103034d7426c763a7793ce22baab46c8e
Author: Rob Clark <robclark at freedesktop.org>
Date: Tue Aug 11 11:47:46 2015 -0400
freedreno/ir3: use nir pass to lower const to scalar
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 8885f2befaea68ce7f9d550c9b9ff5ae77524406
Author: Rob Clark <robclark at freedesktop.org>
Date: Tue Aug 11 08:48:34 2015 -0400
freedreno/a4xx: point-size and spritelist fixes
a4xx needs similar treatment as 995f55a6
Also fixup a few point-size and vpsrepl issues and drop fix_blit_fp()
hack previously needed for mem2gmem.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit f72fead4a28d5d8a16bbc20781218ea7df0b9c9a
Author: Rob Clark <robclark at freedesktop.org>
Date: Mon Aug 10 20:41:45 2015 -0400
freedreno: cap cleanups
Move a few things around to group stuff that is common to a3xx/a4xx
together. Also, introduce is_ir3() for things that are more specific to
the compiler / shader-ISA than to the gpu generation.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 81d2fd91a90e5b2fd9fd74792a7a7c329f0e4d29
Author: Rob Clark <robclark at freedesktop.org>
Date: Mon Aug 10 06:58:37 2015 -0400
mesa: add NV_read_{depth,stencil,depth_stencil} extensions
These extensions allow reading depth/stencil for GLES contexts, which is
useful for tools like apitrace.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 078aef0e97bf7e0cc8fae4d541d5035ff6c29ad7
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Aug 6 14:26:47 2015 -0700
i965/shader: Don't use OptimizeForAOS for NIR vec4 vertex shaders
Shader-db results for vec4 programs using NIR on HSW:
total instructions in shared programs: 1838157 -> 1828469 (-0.53%)
instructions in affected programs: 275978 -> 266290 (-3.51%)
helped: 2827
HURT: 244
GAINED: 0
LOST: 0
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Eduardo Lima Mitev <elima at igalia.com>
commit 91698d1206b86ef1710291213145275a2dd06dd7
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Fri Aug 7 16:37:47 2015 -0700
mesa/teximage: report the correct function which triggered the error
This function would always report that a dimension or size error occurred
in glTexImage even when it was called from glCompressedTexImage. Replace
the static string with the dynamically determined caller name.
Reviewed-by: Tapani Palli <tapani.palli at intel.com>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
commit 5f1d5b1c7857f8680b47a7a450ee9e4530e22c6f
Author: Oded Gabbay <oded.gabbay at gmail.com>
Date: Wed Aug 12 18:22:53 2015 +0300
mesa/formats: don't byteswap when building array formats
Because we build here an array format, we don't need to swap the
bytes for big endian.
If it isn't an array format, the bytes will be swapped in
_mesa_format_convert.
v2: remove temp variable
Signed-off-by: Oded Gabbay <oded.gabbay at gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
commit e3eb91af804f449005a2ff535c805eaa1d579d99
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Aug 10 01:32:23 2015 -0700
mesa/formats: Don't flip channels of null array formats
Before, if we encountered an array format of 0 on a BE system, we would
flip all the channels even though it's an invalid format. This would
result in a mostly invalid format with a swizzle of yyyy or wwww. Instead,
we should just return 0 if the array format stashed in the format info is
invalid.
Cc: "10.6 10.5" <mesa-stable at lists.freedesktop.org>
commit 28d1a506c8d09fa66170978c85566c34cbf1cc0a
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Sun Aug 9 23:45:44 2015 -0700
mesa/formats: Fix swizzle flipping for big-endian targets
The swizzle defines where in the format you should look for any given
channel. When we flip the format around for BE targets, we need to change
the destinations of the swizzles, not the sources. For example, say the
format is an RGBX format with a swizzle of xyz1 on LE. Then it should be
wzy1 on BE; however, the code as it was before, would have made it 1zyx on
BE which is clearly wrong.
Reviewed-by: Iago Toral <itoral at igalia.com>
Reviewed-by: Oded Gabbay <oded.gabbay at gmail.com>
Cc: "10.6 10.5" <mesa-stable at lists.freedesktop.org>
commit 3941539179b72fe25b6dffd1aacc0722d198a5ca
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Sat Aug 8 09:00:21 2015 -0700
mesa/formats: Only do byteswapping for packed formats
Reviewed-by: Iago Toral <itoral at igalia.com>
Cc: "10.6 10.5" <mesa-stable at lists.freedesktop.org>
commit 02a4fe22b137d4bc8378bedd8319109fd23a50e3
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Aug 11 15:21:03 2015 -0700
configure.ac: Always define __STDC_LIMIT_MACROS.
... which ensures that we get defines like LONG_MAX in C++.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91591
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 2265321834608c26b2989a5a1f65bb375826a779
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Aug 10 18:50:48 2015 -0700
i965: Optimize brw_inst_set_bits() and brw_compact_inst_set_bits().
Cuts about 2k of .text.
text data bss dec hex filename
5017141 197160 27672 5241973 4ffc75 i965_dri.so before
5014981 197160 27672 5239813 4ff405 i965_dri.so after
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 9fa70fef22bd458fbeb95a3b0ebb5f7919cba7f0
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Aug 10 16:57:58 2015 -0700
i965: Optimize brw_inst_bits() and brw_compact_inst_bits().
Cuts about 1k of .text.
text data bss dec hex filename
5018165 197160 27672 5242997 500075 i965_dri.so before
5017141 197160 27672 5241973 4ffc75 i965_dri.so after
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 1e53df70642a970fa1bdf5e6b7d64f2c0a4699c7
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Tue Aug 11 19:00:03 2015 +0100
docs: add news item and link release notes for 10.6.4
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit d32c45ca7bd5a81b312504ba99cdab3d748251f7
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Tue Aug 11 18:54:18 2015 +0100
docs: add sha256 checksums for 10.6.4
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit 99793e2541510fe208d29e69fedf97a6fff006f8)
commit c4b4bad68a90510406c0bef97039f7d0b4f8f5fe
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Tue Aug 11 16:39:10 2015 +0100
docs: add release notes for 10.6.4
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit 6b2fcee64edadbd4db2293f5f4fc1a70e80c7251)
commit b88f14702d9c02a34d517f95fe840527961631cd
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Aug 8 14:03:54 2015 +0200
gallium/radeon: fix r600g build if LLVM is disabled
MESA_LLVM_VERSION_PATCH is undefined.
Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Tested-by: Benjamin Bellec <b.bellec at gmail.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 50545882113b389decc3f05771764f6c62213af3
Author: Grazvydas Ignotas <notasas at gmail.com>
Date: Mon Aug 10 00:42:35 2015 +0300
r600g: use a bitfield to track dirty atoms
r600 currently has 73 atoms and looping through their dirty flags has
become costly because checking each flag requires a pointer
dereference before the read. To avoid having to do that add additional
bitfield which can be checked really quickly thanks to tzcnt instruction.
id field was added to struct r600_atom but that doesn't affect memory
usage for both 32 and 64 bit CPUs because it was stuffed into padding.
The performance improvement is ~2% for benchmarks that can have FPS in
the thousands but is hardly measurable in "real" programs.
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit c58534c1384dc63bb1b13eb37c06bdb4652c13ff
Author: Grazvydas Ignotas <notasas at gmail.com>
Date: Mon Aug 10 00:42:34 2015 +0300
r600g: don't mark unused atom dirty
On evergreen config_state is not used, so don't mark it dirty.
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit 85adde30a4bb3e8e5ca44983308364559ff140ab
Author: Grazvydas Ignotas <notasas at gmail.com>
Date: Mon Aug 10 00:42:33 2015 +0300
r600g: use a helper to add an initialized atom
Instead of writing to rctx->atoms directly use a helper to take
advantage of assert checks.
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit 3206d4ed44e761186fee3c679801e57f8ce923cb
Author: Grazvydas Ignotas <notasas at gmail.com>
Date: Mon Aug 10 00:42:32 2015 +0300
gallium/radeon: use helper functions to mark atoms dirty
This is analogous to r300_mark_atom_dirty() used by r300, and will
be used by later patches. For common radeon code, appropriate helper
is called through a function pointer.
No functional changes.
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit 3c04a90e91a64a4a09d77c76c6ddcaca949e9b0e
Author: Francisco Jerez <currojerez at riseup.net>
Date: Fri May 1 17:00:02 2015 +0300
docs: Mark ARB_shader_image_load_store as done on i965.
commit d03c65793a5ee31f1138cbd0fba6fac6cd942428
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu May 7 18:56:01 2015 +0300
i965: Expose ARB_shader_image_load_store.
Reviewed-by: Paul Berry <stereotype441 at gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 13a04abc277089275217dce119e18acf4d4ce52d
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 27 14:33:06 2015 +0300
i965/fs: Clamp image array indices to the array bounds on IVB.
This fixes the spec at arb_shader_image_load_store@invalid index bounds
piglit tests on IVB, which were causing a GPU hang and then a crash
due to the invalid binding table index result of the array index
calculation. Other generations seem to behave sensibly when an
invalid surface is provided so it doesn't look like we need to care.
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit a47ae8de2cf30fbe45318a18a2ea032f30ab7d10
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 27 16:26:52 2015 +0300
i965/fs: Translate image load, store and atomic NIR intrinsics.
v2: Move array coordinate workaround into the surface builder.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 912ef52c29fdc373889594b963cc93c89fa9e3f7
Author: Francisco Jerez <currojerez at riseup.net>
Date: Sun Jun 28 21:16:31 2015 +0300
i965/fs: Handle image uniforms in NIR programs.
v2: Move the image_params array back to brw_stage_prog_data.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 4af27145fe2fec6586ce95e80a76cdcbfe933db1
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue May 5 21:07:15 2015 +0300
i965: Implement logic to set up and upload an image uniform.
v2: Move the image_params array back to brw_stage_prog_data.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 84431c1f1d343c85f3b7fa265293a1d245ba9cf3
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue May 5 21:05:45 2015 +0300
i965: Teach type_size() about the size of an image uniform.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit caae52561dabb2d20f2369c547e660d078974285
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Jul 30 15:46:40 2015 +0300
i965/fs: Implement image load, store and atomic.
v2: Drop VEC4 suport.
v3: Rebase.
v4: Move array coordinate workaround into the surface builder.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 7e8be000101cc6fe3846745b559f2d785430e253
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Jul 30 15:51:58 2015 +0300
i965/fs: Import image format conversion primitives.
Define bitfield packing, unpacking and type conversion operations in
terms of which the image format conversion code will be implemented.
These don't directly know about image formats: The packing and
unpacking functions take a 4-tuple of bit shifts and a 4-tuple of bit
widths as arguments, determining the bitfield position of each
component. Most of the remaining functions perform integer, fixed
point normalized, and floating point type conversions, mapping between
a target type with per-component bit widths given by a parameter and a
matching native representation of the same type.
v2: Drop VEC4 suport.
v3: Rebase.
v4: Fix clamping of negative floats in the unsigned case of
emit_convert_to_scaled().
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 26ca81ce3029cbd2531f52635258aecae19bf185
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Apr 22 16:45:28 2015 +0300
i965/fs: Import image format metadata queries.
Define some utility functions to query the bitfield layout of a given
image format and whether it satisfies a number of more or less
hardware-specific properties.
v2: Drop VEC4 suport.
v3: Add SKL support.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 86dbd8af40deaa99aedf011e863b908173e63012
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Jul 23 19:32:08 2015 +0300
i965/fs: Import code to transform image coordinates into surface coordinates.
Accounting for the padding required for 1D arrays in certain cases.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 1a37619763a99b78aa574aca0058eda86de7a0dc
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Apr 22 16:44:18 2015 +0300
i965/fs: Import image memory offset calculation code.
Define a function to calculate the memory address of the image
location given by a vector of coordinates. This is required in cases
where we need to fall back to untyped surface access, which take a raw
memory offset and know nothing about surface coordinates, type
conversion or memory tiling and swizzling. They are still useful
because typed surface reads don't support any 64 or 128-bit formats on
IVB, and they don't support any 128-bit formats on HSW and BDW.
The tiling algorithm is implemented based on a number of parameters
which are passed in as uniforms and determine whether the surface
layout is X-tiled, Y-tiled or untiled. This allows binding surfaces
of different tiling layouts to the pipeline without recompiling the
program.
v2: Drop VEC4 suport.
v3: Rebase.
v4: Add plenty of comments (Jason).
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit fb19df7a626d02cb54614d4610af2d14720a2ef3
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Apr 22 16:43:51 2015 +0300
i965/fs: Import image access validity checks.
These utility functions check whether an image access is valid.
According to the spec an invalid image access should have no effect on
the image and yield well-defined results. Typically the hardware
implements correct bounds and surface checking by itself, but in some
cases (typed atomics on IVB and untyped messages elsewhere) we need to
implement it in software to work around lacking hardware support.
v2: Drop VEC4 suport.
v3: Rebase.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 3569742ec458c0a881857d9deb782c1e11f195d8
Author: Francisco Jerez <currojerez at riseup.net>
Date: Fri Nov 22 16:00:33 2013 -0800
i965: Define implementation constants for ARB_shader_image_load_store.
Reviewed-by: Paul Berry <stereotype441 at gmail.com>
v2: Drop VS support pre-Gen8, drop GS support.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 786e0853bebc3c4ab073bdbb48eec8ba5ea93842
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Feb 9 21:04:53 2015 +0200
i965/gen7-8: Set up early depth/stencil control appropriately for image load/store.
v2: Store early fragment test mode in brw_wm_prog_data instead of
getting it from core mesa data structures (Ken).
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit ac7664e493655e290783c23a0412b9c70936da50
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 13 14:21:07 2015 +0300
i965/gen7-8: Poke the 3DSTATE UAV access enable bits.
v2: Set the PS UAV-only bit on HSW (Ken).
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit acb6d90dc809283d9839685852f19f6b301b23d3
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue Feb 3 17:14:10 2015 +0200
i965/gen7: Enable fragment shader dispatch if the program has image uniforms.
Shaders with image uniforms may have side effects. Make sure that
fragment shader threads are dispatched if the shader has any image
uniforms.
v2: Use brw_stage_prog_data::nr_image_params to find out if the shader
has image uniforms instead of checking core mesa data structures
(Ken).
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 47f9b07e4cf79a8249c6f9f09148a6a0b4fabacc
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 20 17:13:17 2015 +0300
i965: Hook up image state upload.
v2: Add CS support. Move the image_params array back to
brw_stage_prog_data.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Acked-by: Jason Ekstrand <jason at jlekstrand.net>
commit 868f1ba0a4e6e3057be5b8c2458db4773cf82034
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 13 17:19:29 2015 +0300
i965: Reserve enough parameter entries for all image uniforms used in the program.
v2: Add CS support.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
commit 87a3e02d9bec689e110f820bba7b125b3e801fdd
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jan 21 17:34:49 2015 +0200
i965: Define and initialize image parameter structure.
This will be used to pass image meta-data to the shader when we cannot
use typed surface reads and writes. All entries except surface_idx
and size are otherwise unused and will get eliminated by the uniform
packing pass. size will be used for bounds checking with some image
formats and will be useful for ARB_shader_image_size too. surface_idx
is always used.
v2: Add CS support. Move the image_params array back to
brw_stage_prog_data.
v3: Improve documentation.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
commit 3144844f5ca89cd5743bc9b0ac142ccf862af557
Author: Francisco Jerez <currojerez at riseup.net>
Date: Sat May 2 16:58:24 2015 +0300
i965: Implement surface state set-up for shader images.
v2: Add SKL support.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 2cdb24a7c2238843d23b468275d479553f537e7e
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue May 12 15:56:54 2015 +0300
i965: Fix brw_memory_barrier() for SKL.
This works as-is on SKL, only the assertion needs to be relaxed.
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
commit f9094691378722304dd94deb76ad013bd65c7a5b
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue May 12 16:10:07 2015 +0300
i965: Add SKL support to brw_miptree_get_horizontal_slice_pitch().
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit fe55ab2d12202236ba5bf9beae09803dfe97a7ac
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Sun Aug 9 14:44:30 2015 +1000
glsl: Add missing spec quote about atomic counter in structs
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
commit 87cea61b9e2681e5365e989c7fa7a0298e4005fa
Author: Alex Deucher <alexander.deucher at amd.com>
Date: Mon Aug 10 15:35:21 2015 -0400
radeonsi: add new OLAND pci id
Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
Cc: mesa-stable at lists.freedesktop.org
commit 3fa1ca34cc0134bd16b3315a0695703c9f684bd4
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Aug 10 17:41:36 2015 -0400
nouveau: no need to do tnl wakeup, state updates are always hooked up
A TNL state update now requires a DrawBuffer to be set, which it isn't
early on in context creation. Since we init swtnl from context init,
this caused crashes.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91570
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.6" <mesa-stable at lists.freedesktop.org>
commit 8a688bee83ced46eb4bff741f05d2da033c07ade
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Aug 10 11:52:50 2015 -0700
i965/fs: Make resolve_source_modifiers consistent with the vec4 version
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 7068a6409c897e44cd98377df310691592ef6d0d
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Aug 10 11:48:14 2015 -0700
i965/vec4_visitor: Make some function arguments const references
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 1bb339493cd892c8065266b93a296a84b1dfce9b
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Jul 31 08:36:35 2015 -0700
i965/fs: Don't do redundant RA setup on IVB+
Acked-by: Matt Turner <mattst88 at gmail.com>
commit 0ac65abb466578aafbc753189cdc40fd9a6000b8
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Jul 31 08:35:57 2015 -0700
i965/fs: Use dispatch_width instead of reg_width in alloc_reg_sets
reg_width is kind of an outdated concept.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit bdcc8f32304b67cd9c87f5f285c1faa00c51d3ad
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Jul 30 20:53:04 2015 -0700
ra: Delete the conflict lists in ra_set_finalize
They are never used after the set is finalized so there's no reason to keep
them around.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 7539ac7fe2077f7634250dcb34497e1ac643b0df
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Jul 30 20:49:22 2015 -0700
ra: Refactor ra_set_finalize
All this commit does is change an early return to an if with an else
clause.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit c1d9b3ae0bb0f1222719d7737dd9986e437bf5b9
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Aug 3 15:21:59 2015 -0700
i965/vec4_nir: Properly handle integer multiplies on BDW+
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 1d658cf8795383dbef127e46f3740b516bfe21b9
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Aug 3 14:37:41 2015 -0700
i965/vec4_nir: Do boolean source modifier resolves on BDW+
On BDW+, the negation source modifier on NOT, AND, OR, and XOR, is actually
a boolean negate and not an integer negate. However, NIR's soruce
modifiers are the integer version. We have to resolve it with a MOV prior
to emitting the actual instruction. This is basically the same thing we do
in the FS backend.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 5e1c1c2fcbdfb96a973ae3fd196e341ab2d41833
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Aug 3 10:00:38 2015 -0700
i965/vec4-nir: Handle boolean resolvese on ILK-
The analysis code was already there and running, we just weren't doing
anything with the result of it yet.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 1d4e698466bdea735c5f06c2658322bdc527efce
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Aug 3 16:25:18 2015 -0700
i965/nir: Don't mark bany or ball instructions for resolve
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 17c978166185a7d3a9759f828a4370c1f2169776
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Aug 3 14:12:35 2015 -0700
i965/nir: Use nir_op_info.output_type for determining when to resolve
Previously, we were explicitly listing every instruction that needs a
resolve. However, those instructions were precicely the ones that returned
booleans so there's no reason why we shouldn't just have that check. Also,
all of the reduction opcodes such as bany and ball were missing so it
didn't properly flag stuff on vec4. If an opcode gets added in the future
that returns a bool but doesn't need a resolve, we can special-case that.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 9901aeb1c74648cbe1aa1d18d590a689c844cbad
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Sun Aug 9 22:03:00 2015 -0700
mesa/format_utils: Add src_bits == dst_bits cases to unorm_to_unorm
This better ensures that the src_bits == dst_bits case gets optimized away.
Reviewed-by: Neil Roberts <neil at linux.intel.com>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit 7e5d56394bd53607d0158b49f36ac1428acb7954
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Aug 2 16:22:43 2015 +0200
gallium/radeon: add a debug flag not to use write combining (v2)
v2: just clear the flag before the allocation
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 7bfe8cf4a487aec4870df23f6f72c828f1caaa49
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Aug 5 18:14:49 2015 -0400
freedreno/a4xx: add s8/z32/z32_s8x24 support
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit fcb8a04c9ddcb46b7b8cca21e1203674ec04dde2
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Aug 5 14:21:06 2015 -0400
freedreno: update generated headers
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 2d6a889e8b786cd76d6711627c10be50615c2b62
Author: Rob Clark <robclark at freedesktop.org>
Date: Sun Aug 9 09:03:25 2015 -0400
freedreno/a4xx: fix vpsrepl for blit shaders
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit d2f669e6c72a16dede22f107c3b015ec0516bc56
Author: Rob Clark <robclark at freedesktop.org>
Date: Mon Aug 10 07:11:56 2015 -0400
freedreno/a4xx: clear cached fp when switching blit prog
For gmem restore (mem2gmem), we swap blit programs, in order to have a
different frag shader for depth vs color restore. But we weren't
actually clearing the cached fp, so it would not actually change the
frag shader as expected.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 6dabf455970f3a1fdbf384a53621ebe2bcd7545e
Author: Rob Clark <robclark at freedesktop.org>
Date: Sun Aug 9 08:38:25 2015 -0400
freedreno/a3xx: clear cached fp when switching blit prog
For gmem restore (mem2gmem), we swap blit programs, in order to have a
different frag shader for depth vs color restore. But we weren't
actually clearing the cached fp, so it would not actually change the
frag shader as expected.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 08f2dfe3430789085c165ce7c546d5afd2e295c2
Author: Marta Lofstedt <marta.lofstedt at intel.com>
Date: Mon Aug 10 13:48:11 2015 +0300
mesa/es3.1: Allow Multisampled FrameBufferTextures
GLES 3.1 must be allowed to use multisampled framebuffer textures.
Signed-off-by: Marta Lofstedt <marta.lofstedt at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit b6d014f0ba010f0e61be43abdceb5f2201028a04
Author: Marta Lofstedt <marta.lofstedt at intel.com>
Date: Mon Jun 15 13:50:21 2015 +0200
mesa/es3.1: Pass sample count check for multisampled textures
v3 : Removed space in comment.
Signed-off-by: Marta Lofstedt <marta.lofstedt at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 2ac171a7db4e4ad2fa902e62bf18bc1f67e91643
Author: Oded Gabbay <oded.gabbay at gmail.com>
Date: Tue Aug 4 21:39:32 2015 +0300
mesa: clear existing swizzle info before bitwise-OR
This patch fixes a bug in big-endian treatment, where the previous
swizzle info wasn't cleared before a new swizzle info was inserted into
the format field using a bitwise-OR operation.
v2: use MESA_ARRAY_FORMAT_SWIZZLE_*_MASK instead of numeric constants
v3: align according to coding style
Signed-off-by: Oded Gabbay <oded.gabbay at gmail.com>
CC: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 1eaa29cb300e927409281ef0a9413072766eaa3d
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Sun Aug 9 22:36:37 2015 +0100
util: Use LONG_MAX instead of LONG_BIT.
More portable. Based on Roland Scheidegger's idea.
Tested with roundevent_test on Linux, MinGW, and MSVC.
https://bugs.freedesktop.org/show_bug.cgi?id=91591
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 497a22a727d3606c7327eb72efbf0d2c03607f0a
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Sun Aug 9 11:55:28 2015 +0100
scons: Build roundevent_test.
Reviewed-by: Roland Scheidegger <sroland at vmware.co>
commit 21ccdbdb5dd87b2ee66c4e78b011ec4df29efb98
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Sun Aug 9 11:25:41 2015 +0100
util: Cope with LONG_BIT not being defined on Windows.
Neither MSVC nor MinGW defines LONG_BIT. For MSVC this was not a problem as
it doesn't define __x86_64__ macro (it's GCC specific.)
However on Windows long type is guaranteed to be 32bits.
Also add an #error, as GCC will just warn, not throw any error, when no
value is returned.
Trivial.
commit eb643db30e1bdf5171d0a012674016c317925b6e
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Sun Aug 9 11:21:03 2015 +0100
gallium: GCC 4.9 allows to include tmmintrin.h without -msse3.
Fixes build with MinGW x86_64 build with GCC 4.9, due to conflicting
definition _mm_shuffle_epi8 of u_sse.h and system headers.
Trivial.
commit 512aa0647f328fff69b3ce328b6466f2da8b7c4d
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Fri Aug 7 13:07:40 2015 +0100
util: Rename PURE to ATTRIBUTE_PURE.
To avoid collission with windows.h's PURE macro.
We could consider eventually renaming to __pure, but that would require
further care, so it's left to the future.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 27141f984d6401dc466f0e9b0c5da2a9248045e3
Author: Boyan Ding <boyan.j.ding at gmail.com>
Date: Sat Aug 8 17:23:28 2015 +0800
egl/x11: Fix driver_name acquisition
We don't need to free driverName string from dri2 reply, on the other
hand, the driver name acquired from loader doesn't need duplication.
Fixes: 45e110bad9d (egl/x11: trust our loader over the xserver for the
drivername)
Reported-by: Timothy Arceri <t_arceri at yahoo.com.au>
Signed-off-by: Boyan Ding <boyan.j.ding at gmail.com>
[Emil Velikov: use brackets for both branches of conditional]
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit a1adf0b3fe428a4bf690f166c2697d8c7ea2dcb0
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Fri Aug 7 13:46:30 2015 -0700
i965/skl: (trivial) Remove invalid comment about thread counts
This should have been a part of:
commit 7eaacc1678195738fab3bb98870828611cae066d
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Wed Jul 29 12:35:24 2015 -0700
i965/skl: Add production thread counts and URB size
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
commit ffadfbf5d076638fa4022106cfe989bc5a145f20
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Wed Aug 5 13:58:46 2015 +0100
i965: Fix HW binding tables editing
Since the introduction of new gl_shader_stages in
commit a2af956963b6bc4d29f37485e44c98008d2ef077
Author: Fabian Bieler <fabianbieler at fastmail.fm>
Date: Fri Mar 7 10:19:09 2014 +0100
mesa: add tessellation shader enums
the translation table for the stage into the HW binding table edit
command was broken, and so we used illegal commands. Fix the array
initialisation to be impervious to changes in the gl_shader_stages enum
and add the asserts that would have caught the issue earlier.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
Cc: Jordan Justen <jordan.l.justen at intel.com>
Cc: Matt Turner <mattst88 at gmail.com>
Cc: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit ba651967a201b48f380cd30495e271317c1d8522
Author: Alexander von Gluck IV <kallisti5 at unixzen.com>
Date: Fri Aug 7 12:55:40 2015 -0500
egl/dri2: Fix include path of u_atomic.h introduced e7e29189
This was causing a failure to build on SCons due to a missing
-Isrc/egl. Instead of adding in that path, lets just -Isrc/
and include "utils/u_atomic.h".
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 6de9a03bed400fca5672ef0c13c0039bbe94a679
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Aug 7 19:20:48 2015 +0100
egl/x11: don't crash if dri2_dpy->conn is NULL
Identical to commit 60e9c35b3a0(egl/x11: bail out if we cannot fetch
the xcb connection) but for the swrast codepath.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 2c7b6cf512a775a37677b1e467d2af952c449dae
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Jul 29 17:19:07 2015 +0100
egl/x11: auth with xserver before attempting to open the dri module
No real change, apart from keeping the calls to the underlying winsys
(x11) next to each other. Just like platform_wayland.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 45e110bad9d5d31eb67d7d32937aa5a752108df8
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Jul 29 17:19:06 2015 +0100
egl/x11: trust our loader over the xserver for the drivername
This is a port of commit 7bd95ec437a(dri2: Trust our own driver name
lookup over the server's.) from glx/dri2.
v2: Add newline between code and multiline comment. (Matt)
Cc: Julien Isorce <julien.isorce at gmail.com>
Reported-by: Julien Isorce <julien.isorce at gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit faf0f811e3f9fb724a89c463c0cb6a0d61715f95
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Jul 29 17:19:05 2015 +0100
egl/x11: open the device from within dri2_x11_connect()
Allows us, with the next commit, to use alternative driver_name rather
than the one from xserver.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit beddb0a2371059829b20240058931b8c9fd5be40
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Jul 29 17:19:04 2015 +0100
egl/x11: fetch the device_name prior to driver_name
With the follow up commits we're about to further reshuffle things. Thus
we'll honour our our driver_name lookup (src/loader), and use the one
provided by xserver as a fall-back.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit bf66988b08786c123804c2be8846a6a21cf200ad
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Jul 29 17:19:03 2015 +0100
egl/x11: remove dri2_dpy->conn checks
If the connection is NULL we won't be able to get here.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 60e9c35b3a0384860ffcb01d902a69ee13254eb9
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Jul 29 17:19:02 2015 +0100
egl/x11: bail out if we cannot fetch the xcb connection
The documentation of xcb_connection_has_error() does not mention
what will happen, if NULL is fed to the function.
Upon closer look (props to Matt), it seems that we'll crash as the
implementation dereferences conn.
This will also allow us to remove the dri2_dpy->conn checking with the
next commit.
v2: Reword commit message as per Matt's findings.
Acked-by: Alex Deucher <alexander.deucher at amd.com>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 75ce7919d6496981013a21a7055c668e47e7bed2
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Jul 17 12:52:27 2015 +0100
vc4: add missing nir include, to fix the build
Cc: 10.6 <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 4fa0cd17b77039ab67e81991002b4d5947298278
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Jul 17 12:41:24 2015 +0100
vc4: automake: remove unused include
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit a97f1b697b01dca9f72d8559f8269188d76dccc9
Author: Serge Martin (EdB) <edb+mesa at sigluy.net>
Date: Fri Aug 7 10:40:31 2015 +0200
clover: Stub missing CL 1.2 functions.
As sugested by Tom a long time ago
and in order to be able to create Piglit tests
v2:
replace NOT_SUPPORTED_BY_CL_1_1 macro with an inline function
remove extra space in clLinkProgram arg
v3:
use __func__
v4:
back to a macro, it make more sense to use it with __func__
[ Francisco Jerez: Rename to CLOVER_NOT_SUPPORTED_UNTIL and pass the
minimum API version required by the entry point so the error
messages don't become stale when support for additional CL versions
is introduced. ]
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 0508861f29f2d3b79fb803353e4ea8ab32654bc4
Author: Marta Lofstedt <marta.lofstedt at intel.com>
Date: Tue Jun 23 13:03:13 2015 +0200
mesa: NULL check InfoLog
When a program is compiled, but linking failed the sh->InfoLog
could be NULL. This is expoloited by OpenGL ES 3.1 conformance tests.
Signed-off-by: Marta Lofstedt <marta.lofstedt at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit a0b7c1c86e028309e639368b2b556b755761f68f
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Tue Aug 4 10:06:41 2015 +0200
i965/vec4: Fix indentation in vec4_visitor::evaluate_spill_costs
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit f246aa6bcab57f85a143cbfe7e9de24237921249
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Fri Jul 31 14:36:30 2015 +0200
i965/vec4: do not predicate scratch writes for BRW_OPCODE_SEL instructions
The dst is always written, in this case the predicate is only used to select
the value to write, so if we are spilling the dst we always want to write
whatever value we selected to scratch.
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 42d283a0cc928a9e3ecddf1a90f9417ef1a34392
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Wed Aug 5 21:05:52 2015 +1000
glsl: remove stage ref generation for transform feedback
Stage ref cannot be queried for transform feedback.
Also simplify the build_stageref function by passing the
correct mode for uniforms.
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 6dea2456ca82d2c62afbd90327d265c5e78fca9c
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Jul 15 21:14:24 2015 +0200
winsys/radeon: add a specific error message for cs_submit -> -ENOMEM
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
commit 42d9f6323a523d786fc3797587fdf63048becceb
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Apr 30 16:07:12 2015 +0200
winsys/radeon: add an interface for contexts
Same idea as in libdrm_amdgpu.
A command stream can only be created for a specific context and it's always
submitted to that context.
This will mainly be used by amdgpu and it's required by the GPU reset status
query too.
(radeon only has a basic version of the query and thus doesn't need this)
Reviewed-by: Christian König <christian.koenig at amd.com>
commit 592ce6e2d1b2c804a95cb00c06e7bbb9d83f554b
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Aug 6 23:41:38 2015 +0200
gallium/radeon: unify buffer_wait and buffer_is_busy in the winsys interface
The timeout parameter covers both cases.
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
commit 8118d3719aee5fdf313c33dbf3256dd78ff46bea
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Aug 3 21:43:36 2015 +0200
radeonsi: rename enable_s3tc -> enable_compressed_formats
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
commit a3723fb9e32ab114dcffcf74946def92647c5f03
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Jul 20 00:15:59 2015 +0200
gallium/radeon: add DRM and LLVM version to the renderer string
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit a3e81f819c20dd50d551de9b7e1280b2bd9c18de
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Jul 16 14:40:00 2015 +0200
radeonsi: always flush framebuffer caches at the beginning of IBs
better safe than sorry
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
commit 0615ad1c70777b515d00aa5b0c41b1073ad5a2d1
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jun 27 14:49:34 2015 +0200
radeonsi: don't count the exact needed CS space if the CS is large enough
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
commit 6d6208a431f6a01a22f892c71258fd3567d969b6
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed May 6 19:34:09 2015 +0200
radeonsi: don't crash when cleaning up after an incomplete context
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
commit 9f78e27fc60b3473b708ab4ca04e4ebd6be6cf4e
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu Aug 6 10:59:15 2015 -0700
i965: Rename MIPTREE_LAYOUT_ALLOC_* -> MIPTREE_LAYOUT_TILING_*.
Ben suggested that I rename MIPTREE_LAYOUT_ALLOC_ANY_TILED since it
needed to include no tiling at all, but the name
MIPTREE_LAYOUT_ALLOC_ANY is pretty nondescriptive. We can avoid
confusion by replacing "ALLOC" with "TILING" in the identifiers.
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit 1c175fc2e3a685b531920dec247086463ab9a154
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Aug 4 22:58:08 2015 -0700
i965: Correct a mistake that always forced texture tiling.
Regression since commit 3a31876600, when tiling modes were moved into
layout_flags.
The relevant enum values are
MIPTREE_LAYOUT_ALLOC_YTILED = 1 << 5
MIPTREE_LAYOUT_ALLOC_XTILED = 1 << 6
MIPTREE_LAYOUT_ALLOC_ANY_TILED = MIPTREE_LAYOUT_ALLOC_YTILED |
MIPTREE_LAYOUT_ALLOC_XTILED
MIPTREE_LAYOUT_ALLOC_LINEAR = 1 << 7
so the expression (layout_flags & MIPTREE_LAYOUT_ALLOC_ANY_TILED) can
never produce a value of MIPTREE_LAYOUT_ALLOC_LINEAR.
The enum this replaced was
enum intel_miptree_tiling_mode {
INTEL_MIPTREE_TILING_ANY,
INTEL_MIPTREE_TILING_Y,
INTEL_MIPTREE_TILING_NONE,
};
where "ANY" means "Y" or "NONE" (i.e., linear). As such, remove the
unused (and worse, unhandled) MIPTREE_LAYOUT_ALLOC_XTILED and redefine
MIPTREE_LAYOUT_ALLOC_ANY_TILED to mean what it did before.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91513
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit 3d551c5c7036b650124f23e4e2e3f40b9a8ad426
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Aug 5 18:51:24 2015 -0700
i965: Request a miptree with no tiling intel_miptree_map_blit().
Regression since commit 3a31876600, when tiling modes were moved into
layout_flags.
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit 30a7e0c021c3a77c20c6f041dc80b7dc90ad238f
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Aug 2 21:12:18 2015 +0200
radeonsi: add a HUD query showing the number of shaders created
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 70f5e49ba5ca8eb063a0d7db94fbef1585b21b2d
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Aug 2 16:57:39 2015 +0200
radeonsi: add a HUD query showing the number of compiler invocations
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 028528215a8a6d0a5945256cc67709eef2e68189
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Aug 2 17:28:20 2015 +0200
gallium/radeon: display cumulative results for some driver queries
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 18501ff468db2091fde6029f4ec674b8365513e6
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Aug 2 17:47:38 2015 +0200
gallium/radeon: switch the buffer-wait-time query to microseconds
This display the units in the HUD.
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 0257e1fbd24e2ab442996296e49e2ebe4c0f07b1
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Aug 2 17:09:01 2015 +0200
gallium/radeon: change some driver query types to Hz
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit dbfeb0ec12d6550e68de1bcd164e422e79bccf2d
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Aug 2 18:11:55 2015 +0200
gallium/hud: automatically print % if max_value == 100
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 4e2a3e0376ca4fe39ca05e80557edfaa12e93e2b
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Aug 2 18:11:09 2015 +0200
gallium/hud: fix printing % next to panes
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit cbad30344d6e0b1ccc9fc8d5a8e6560e97dd9188
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Aug 2 18:00:57 2015 +0200
gallium/hud: replace assertions with clamping the unit index
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 97a65d90fe88e6b4b4a42d866b23e73ce72f6dc2
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Aug 2 17:24:30 2015 +0200
gallium,hud: allow displaying cumulative values instead of average
The cumulative value is useful for queries like the number of shader
compilations.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 130a03e360e6aebe93e86b1d522ebf22371aa2d4
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Aug 2 17:08:29 2015 +0200
gallium/hud: fix printing byte units
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 6b47b8978101897cc0dab8f2017e3aa25d31582d
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Aug 2 17:06:17 2015 +0200
gallium,hud: add support for Hz units in driver queries
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 60159bcfc66a067b50da06f5cabfa20d72e898ed
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Aug 3 01:34:32 2015 +0200
radeonsi: before storing tess levels, load them from LDS instead of temporary
Also use only one store if stride <= 4.
All the fetches from and stores to temporaries can be removed now.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91461
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit c2a5d1dcb14acbd2db4a674453a8622d4b9a572a
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Aug 2 22:01:25 2015 +0200
winsys/radeon: loosen up the requirements for how much memory IBs can use
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit cc59c78b0aa202f1a76a8708ec318e19a8502c9c
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Jul 31 17:26:08 2015 +0200
gallium/radeon: always use the llvm. prefix in intrinsic names
Acked-by: Michel Dänzer <michel.daenzer at amd.com>
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
commit 567394112d904096abff1d994ab952f475dfb444
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Jul 31 11:45:13 2015 +0200
radeon/winsys: increase the IB size for VM
Luckily, there is a kernel query, so use the size from that.
It currently returns 256KB. It can be increased in the kernel.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit d587742650c262dea8007474b9956fd65472f8b2
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jun 27 14:19:41 2015 +0200
gallium/radeon: allow the winsys to choose the IB size
Picked from the amdgpu branch.
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 57245cce52d544c61f03fc966850f0f94e8118d5
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Jul 31 02:39:02 2015 +0200
gallium/radeon: suspend timer queries between IBs
When we are measuring the time spent in a draw call, an unexpected flush
can distort the result.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit b2eb13d602f71f19216284a584834cdaa2550eb3
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Jul 30 16:14:03 2015 +0200
st/mesa: implement DrawTransformFeedbackStream
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit 7d3939f0de7dcb5e68eca638d5832c683a124775
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Jul 30 16:11:50 2015 +0200
mesa: save which transform feedback buffer is associated with which stream
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit c63e8b1193fd380e999b8ef258a20e57884820f4
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Jul 30 15:43:09 2015 +0200
vbo: pass the stream from DrawTransformFeedbackStream to drivers
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit 115964052b25a958b2ad4ec42ae07133b2768cf9
Author: Brian Paul <brianp at vmware.com>
Date: Mon Aug 3 15:06:42 2015 -0600
mesa: handle no-op cases sooner in _mesa_[Client]ActiveTexture()
If the new texture unit is the current texture unit, we can return
before error checking.
Reviewed-by: Eric Anholt <eric at anholt.net>
commit ee977183dcb543c919d0d70dde610cb191d5a3ea
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue Aug 4 19:07:19 2015 +0300
i965/fs: Lower arithmetic instructions with register regions of unsupported width.
This extends the SIMD lowering pass to enforce the hardware limitation
that no directly-addressed source may read more than 2 physical GRFs.
One can easily go over this limit when doing 64-bit arithmetic
(e.g. FP64 or extended-precision integer MULs) or SIMD32, so it's nice
to be able to just emit an instruction of the intended execution size
from the visitor and let the lowering pass deal with this restriction
transparently.
Some hardware arithmetic instructions are not handled here, including
all instructions that use the accumulator implicitly (which the SIMD
lowering pass deliberately doesn't handle), instructions with
non-per-channel sources (e.g. LINE or PLANE) and SEND-like
instructions, which need special handling most likely as virtual
opcodes.
Reviewed-by: Connor Abbott <connor.w.abbott at intel.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
commit 42a18ca76057621ae7d8812b29ea2245d6ff282d
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Aug 5 16:29:30 2015 +0300
i965/fs: Fix fs_inst::regs_read() for sources in the ATTR file.
Otherwise it would crash on Gen8 with scalar VS. The issue can easily
be reproduced with the following patch, but I don't see any reason why
it wouldn't be possible to end up with an ATTR argument here even
without it.
CC: mesa-stable at lists.freedesktop.org
Reviewed-by: Connor Abbott <connor.w.abbott at intel.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
commit e77a4a9b1f66de383043df95aada40fd5a004913
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue Aug 4 19:08:45 2015 +0300
i965/fs: Implement nir_op_imul/umul_high in terms of MULH.
And get rid of another no16() call.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 3b48a0eeda20f5cf2dbc8de5e36f8fe3461f41bf
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Aug 6 14:04:00 2015 +0300
i965/fs: Lower the MULH virtual instruction.
Translate MULH into the MUL/MACH sequence. This does roughly the same
thing that nir_emit_alu() used to do but we can now handle 16-wide by
taking advantage of the SIMD lowering pass. The force_sechalf
workaround near the bottom is required because the SIMD lowering pass
will emit instructions with non-zero quarter control and we need to
make sure we avoid that on integer arithmetic instructions with
implicit accumulator access due to a known hardware bug on IVB.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 2e731264382954beb1192cd7cc62e16e0b8e7978
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Aug 5 16:47:18 2015 +0300
i965/fs: Indent the implementation of 32x32-bit MUL lowering by one level.
In order to make room for the code that will lower the MULH virtual
instruction. Also move the hardware generation and execution type
checks into the same branch, they are going to have to be different
for MULH.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit f5b37fb1acad9cf044b7b6d4fa5f2582bd8bc7f4
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Aug 5 16:43:37 2015 +0300
i965/fs: Lower 32x32 bit multiplication on BXT.
AFAIK BXT has the same annoying alignment limitation as CHV on the
source register regions of 32x32 bit MULs, give it the same treatment.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 8f5d0988ea2ccaba7f049f113b652f331524d2a6
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue Aug 4 19:04:55 2015 +0300
i965: Define virtual instruction to calculate the high 32 bits of a multiply.
This instruction will translate to the MUL/MACH sequence that computes
the high 32-bits of the result of a 64-bit multiply. Before Gen8
integer operations that used the accumulator were limited to 8-wide,
but the SIMD lowering pass can easily be hooked up to sidestep this
limitation, we just need a virtual opcode to represent the MUL/MACH
sequence in the IR.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit f7ac4ef4eeea737115d0b574fed7ecae46426072
Author: Michel Dänzer <michel.daenzer at amd.com>
Date: Wed Aug 5 18:17:14 2015 +0900
glsl: Initialize patch member of glsl_struct_field
There is apparently a subtle difference in C++ between
F f;
and
F f();
The former will use the default constructor. If there is no default
constructor specified, the compiler provides one that simply invokes the
default constructor for each field. For built-in basic types, the
default constructor does nothing. The later will, according to
http://stackoverflow.com/questions/2417065/does-the-default-constructor-initialize-built-in-types)
perform value-initialization of the type. For built-in types this means
initializing to zero.
The per_vertex_accumulator constructor is:
per_vertex_accumulator::per_vertex_accumulator()
: fields(),
num_fields(0)
{
}
This is the second form of constructor, so the glsl_struct_field
objects were previously zero initialized. With the addition of an empty
default constructor in commit 7ac946e5, per_vertex_accumulator::fields
receive no initialization.
Fixes a bunch of random (mostly tessellation related) piglit failures
since commit 7ac946e5 ("glsl: Add constuctors for the common cases of
glsl_struct_field").
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91544
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 2c61d583f8c931fc9834dd852b1c960c95acefb5
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Wed Aug 5 20:27:24 2015 +1000
nir: add missing type to type_size_vec4()
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 03b7221dbb93e2439f30b2e0918f6215eb741979
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Wed Jul 29 16:01:27 2015 +0200
mesa: Add missing check of format and type in glTexSubImageXD on GLES 3.0
Argument validation for glTexSubImageXD is missing a check of format and type
against texture object's internal format when profile is OpenGL-ES 3.0+.
This patch also groups together all format and type checks on GLES into a
new function texture_format_error_check_gles(), to factorize similar
code in texture_format_error_check().
Fixes 2 dEQP tests:
* dEQP-GLES3.functional.negative_api.texture.texsubimage2d
* dEQP-GLES3.functional.negative_api.texture.texsubimage3d
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 4b07e9a033ddb6733eba206b5bd47a2373756f7d
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Wed Jul 29 16:01:28 2015 +0200
mesa: Fix error returned by glCopyTexImage2D() upon an invalid internal format
Page 161 of the OpenGL-ES 3.1 (PDF) spec, and page 207 of the OpenGL 4.5 (PDF),
both on section '8.6. ALTERNATE TEXTURE IMAGE SPECIFICATION COMMANDS', states:
"An INVALID_ENUM error is generated if an invalid value is specified for
internalformat".
It is currently returning INVALID_OPERATION error because
_mesa_get_read_renderbuffer_for_format() is called before the internalformat
argument has been validated. To fix this, we move this call down the validation
process, after _mesa_base_tex_format() has been called. _mesa_base_tex_format()
effectively serves as a validator for the internal format.
Fixes 1 dEQP test:
* dEQP-GLES3.functional.negative_api.texture.copyteximage2d_invalid_format
Fixes 1 piglit test:
* spec at oes_compressed_etc1_rgb8_texture@basic
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Cc: 10.6 <mesa-stable at lists.freedesktop.org>
commit 5d64cae8427b090c42d6d38da7fb474b3ddd4eb0
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Wed Jul 29 16:01:26 2015 +0200
mesa: Validate target before resolving tex obj in glTex(ture)SubImageXD
Currently, glTexSubImageXD attempt to resolve the texture object
(by calling _mesa_get_current_tex_object()) before validating the given
target. However, that method explicitly states that target must have been
validated before calling it, so it never returns a user error.
The target validation occurs later when texsubimage_error_check() is called.
This patch reorganizes target validation, taking it out from the error check
function and into a point before the texture object is resolved.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Cc: 10.6 <mesa-stable at lists.freedesktop.org>
commit b38a50f1e3edae6079c91f73a8d9c63a2dbf512a
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Wed Jul 29 16:01:23 2015 +0200
mesa: Fix errors values returned by glShaderBinary()
Page 68, section 7.2 'Shader Binaries" of the of the OpenGL ES 3.1,
and page 88 of the OpenGL 4.5 specs state:
"An INVALID_VALUE error is generated if count or length is negative.
An INVALID_ENUM error is generated if binaryformat is not a supported
format returned in SHADER_BINARY_FORMATS."
Currently, an INVALID_OPERATION error is returned for all cases.
Fixes 1 dEQP test:
* dEQP-GLES3.functional.negative_api.shader.shader_binary
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Cc: 10.6 <mesa-stable at lists.freedesktop.org>
commit 784bea5a38c219a5ab587ff1ddce8879d4f7dce1
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Tue Aug 4 11:09:35 2015 +0300
mesa: do not modify args when errors with GetProgramResourceName
Original purpose of these lines was to be more friendly against
GUI tools using the extension. However conformance suite explicitly
checks that buffers are not modified in error conditions.
Fixes:
ES31-CTS.program_interface_query.buff-length
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
commit 18c5cdb9433b472d9aad13175295a848bce03185
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Mon Aug 3 08:48:32 2015 +0300
glsl: add variable mode check to build_stageref
Currently stage reference mask is built using the variable name
only. However it can happen that input of one stage has same name
as output from another stage. Adding check of variable mode makes
sure we do not pick wrong variable.
Fixes some subcases from
ES31-CTS.program_interface_query.no-locations
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
commit 7d88413ade2c41054f79b20338253aacf1ac341d
Author: Frank Binns <frank.binns at imgtec.com>
Date: Fri Jul 31 09:11:47 2015 +0100
dri: set the __DRI_API_OPENGL bit based on max gl compat version
This matches similar behaviour for the __DRI_API_OPENGL_CORE bit.
Signed-off-by: Frank Binns <frank.binns at imgtec.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit b2c5986ea1c8e66c4e0a05bcacbcf28c27f5b183
Author: Frank Binns <frank.binns at imgtec.com>
Date: Fri Jul 31 09:11:45 2015 +0100
egl: Add eglQuerySurface surface type check for EGL_LARGEST_PBUFFER attrib
Calling eglQuerySurface on a window or pixmap with the EGL_LARGEST_PBUFFER
attribute resulted in the contents of the 'value' parameter being modified.
This is the wrong behaviour according to the EGL spec, which states:
"Querying EGL_LARGEST_PBUFFER for a pbuffer surface returns the
same attribute value specified when the surface was created with
eglCreatePbufferSurface. For a window or pixmap surface, the
contents of value are not modified."
Avoid this from happening by checking that the surface type is EGL_PBUFFER_BIT
before modifying the contents of the parameter.
Cc: <mesa-stable at lists.freedesktop.org>
Signed-off-by: Frank Binns <frank.binns at imgtec.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit cfc3200a35647026a0b5cf188f378ce33802044b
Author: Frank Binns <frank.binns at imgtec.com>
Date: Fri Jul 31 09:11:46 2015 +0100
egl/dri: Add error info needed for EGL_EXT_image_dma_buf_import extension
Update the DRI image interface error codes to reflect the needs of the
EGL_EXT_image_dma_buf_import extension. This means updating the existing error
code documentation and adding a new __DRI_IMAGE_ERROR_BAD_ACCESS error code
so that drivers can correctly reject unsupported pitches and offsets. Hook
the new error code up in EGL to return EGL_BAD_ACCESS.
Cc: <mesa-stable at lists.freedesktop.org>
Signed-off-by: Frank Binns <frank.binns at imgtec.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit ee47d13abbc6770b4e6513c894ede56b1e846785
Author: Eric Anholt <eric at anholt.net>
Date: Mon Aug 3 17:36:47 2015 -0700
vc4: Use nir_lower_load_const_to_scalar().
commit 6c28ee20410afe97dd441b0c9c680b26eb4072fc
Author: Eric Anholt <eric at anholt.net>
Date: Mon Aug 3 17:20:33 2015 -0700
nir: Add a nir_lower_load_const_to_scalar() pass.
This is useful to increase the CSE opportunities for a scalar backend. It
avoids regressions when dropping vc4's custom CSE implementation.
v2: Cleanups by Matt (decl in the for loop, and unreachable()).
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 45248d3640f5a0356085e26c44548bf3af5dec0f
Author: Eric Anholt <eric at anholt.net>
Date: Mon Aug 3 19:08:37 2015 -0700
vc4: Don't bother de-SSAing values that aren't part of phi webs.
We can just support them the same way we do load_const's SSA values.
commit a70f63ab20d8bf922a307a92020237b1dec36314
Author: Eric Anholt <eric at anholt.net>
Date: Fri Jul 31 09:12:48 2015 -0700
nir: Add algebraic opt for no-op iand.
I lazily generated some of these in VC4 NIR lowering.
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 63eac5de8fd0e091d07f866a42584c057ca4bfa9
Author: Eric Anholt <eric at anholt.net>
Date: Fri Jul 31 17:08:46 2015 -0700
vc4: Don't bother saturating the dst color for blending.
Since we just pulled it out of the destination as 8-bit unorm, we know
it's in [0, 1] already.
shader-db:
total instructions in shared programs: 100040 -> 98208 (-1.83%)
instructions in affected programs: 14084 -> 12252 (-13.01%)
commit cc8fb2904673588d31b660dbfaf692615b5202dd
Author: Eric Anholt <eric at anholt.net>
Date: Fri Jul 31 11:46:56 2015 -0700
vc4: Make r4-writes implicitly move to a temp, and allocate temps to r4.
Previously, SFU values always moved to a temporary, and TLB color reads
and texture reads always lived in r4. Instead, we can have these results
just be normal temporaries, and the register allocator can leave the
values in r4 when they don't interfere with anything else using r4.
shader-db results:
total instructions in shared programs: 100809 -> 100040 (-0.76%)
instructions in affected programs: 42383 -> 41614 (-1.81%)
commit 9b403c0756ecf806a8ff768bd73a4cbf42986bdb
Author: Eric Anholt <eric at anholt.net>
Date: Fri Jul 31 10:02:45 2015 -0700
vc4: Drop a dead prototype.
commit eae9c3286e2990879c6a01df3c9042b1e4031d5c
Author: Eric Anholt <eric at anholt.net>
Date: Tue Aug 4 17:18:43 2015 -0700
Revert "nir: Use a single bit for the dual-source blend index"
This reverts commit ab5b7a0fe659ff6f9c1885d5cb047b6531959506. We use more
than one bit of value in tgsi_to_nir.
commit d6d7515bec2e7421dcbc17f31f94613643599e33
Author: Rob Clark <robclark at freedesktop.org>
Date: Sat Aug 1 16:17:49 2015 -0400
freedreno/a4xx: add independent blend function support
needed for MRT
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 054526e49abb5e7fd49fed6f589cff6f1ab4c9f6
Author: Rob Clark <robclark at freedesktop.org>
Date: Fri Jul 31 15:32:58 2015 -0400
freedreno/a4xx: MRT support
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit b37a97c97d6477d5062a75a0313162ed324a36ed
Author: Rob Clark <robclark at freedesktop.org>
Date: Fri Jul 31 14:34:19 2015 -0400
freedreno: move the half-precision logic into core
Both a3xx and a4xx need the same logic to decide if half-precision can
be used for blit shaders. So move it to core and simplify things a bit
with a helper that considers all render targets.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 5ca032a9a8ece0a8a43151f988215484da3c1811
Author: Rob Clark <robclark at freedesktop.org>
Date: Fri Jul 31 12:07:24 2015 -0400
freedreno: simplify/cleanup resource status tracking
Collapse dirty/reading bools into status bitmask (and drop writing which
should really be the same as dirty). And use 'used_resources' list for
all tracking, including zsbuf/cbufs, rather than special casing the
color and depth/stencil buffers.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit c7deea51d2b611564c91e146fbd1ed0b547f65c0
Author: Rob Clark <robclark at freedesktop.org>
Date: Fri Jul 31 10:54:23 2015 -0400
freedreno: fix stream-out caps vec4->components
Should be in units of components, not vec4's
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit a221f8d9ebb4ef43a83ef638458d1338dfe1e517
Author: Rob Clark <robclark at freedesktop.org>
Date: Fri Jul 31 09:36:31 2015 -0400
freedreno: small bit of cleanup about max rendertargets
We hard-coded 4 or 8 as the max in various places. Switch it all to a
define since the limit will go up with a4xx (and maybe even again in the
future?)
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 5f247a9656cb8a0eccdc98ef5911ed15c1248dfb
Author: Matt Turner <mattst88 at gmail.com>
Date: Sun Jul 12 18:05:58 2015 -0700
glx: Use _mesa_lroundevenf() in glPixelStoref().
Functional change in which way half-way cases are rounded from towards
positive-infinity to even. The spec says "the passed value is rounded to
the nearest integer". Removes another case of bad half-up rounding.
commit 680de24545d23d0c2b699020267ca484f81a04a9
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Jun 29 09:38:34 2015 -0700
util: Use SSE intrinsics in _mesa_lroundeven{f,}.
gcc actually generates this for us now that we use -fno-math-errno
(which is weird, since lrintf()/lrint() don't set errno) but clang still
does not. Presumably helps MSVC as well.
Reduced .text size by 8.5k with gcc before -fno-math-errno.
text data bss dec hex filename
4935850 195136 26192 5157178 4eb13a i965_dri.so before
4927225 195128 26192 5148545 4e8f81 i965_dri.so after
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit 3c050222b0d5b47c885ca72f3c7af22c0d28b5ad
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu Jun 25 21:43:30 2015 -0700
mesa: Use _mesa_lroundevenf() in some more places.
commit 996349cb190154ebdc8cc9f23e5f8f9aabbd6b4d
Author: Vinson Lee <vlee at freedesktop.org>
Date: Wed Jul 29 20:32:41 2015 -0700
vl/mpeg12: Silence GCC unused-variable warning.
vl/vl_mpeg12_bitstream.c: In function 'decode_slice':
vl/vl_mpeg12_bitstream.c:928:19: warning: unused variable 'extra' [-Wunused-variable]
unsigned extra = vl_vlc_get_uimsbf(&bs->vlc, 1);
^
Signed-off-by: Vinson Lee <vlee at freedesktop.org>
Reviewed-by: Christian König <christian.koenig at amd.com>
commit e23cbaadaac0c67a72b10e3dd14b75abc19ab3c5
Author: Alejandro Seguà <alesegdia at gmail.com>
Date: Mon Aug 3 02:15:20 2015 +0200
glsl: replace old hash table with new and faster one
The util/hash_table was intended to be a fast hash table
replacement for the program/hash_table see 35fd61bd99c1 and
72e55bb6888ff.
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
commit 7ac946e546bba440f87ce95ef022745201744f9c
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Thu Jul 30 06:00:56 2015 -0700
glsl: Add constuctors for the common cases of glsl_struct_field
Fixes a giant pile of GCC warnings:
builtin_types.cpp:60:1: warning: missing initializer for member 'glsl_struct_field::stream' [-Wmissing-field-initializers]
I had to add a default constructor because a non-default constructor
was added. Otherwise the only constructor would be the one with
parameters, and all the plases like
glsl_struct_field foo;
would fail to compile.
I wanted to do this in two patches. All of the initializers of
glsl_struct_field structures had to be converted to use the
constructor because C++ apparently forces you to do one or the other:
builtin_types.cpp:61:1: error: could not convert '{glsl_type::float_type, "near", -1, 0, 0, 0, GLSL_MATRIX_LAYOUT_INHERITED, 0, -1}' from '<brace-enclosed initializer list>' to 'glsl_struct_field'
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
commit 93977d3a151675946c03ec28102c651691cdb0bd
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Thu Jun 25 10:45:34 2015 -0700
i965: Make gen7_upload_ps_state static
It is only ever called from within the same file.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
commit 7a12e646d3874f4ff755e05cfb27560d11d075a7
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Thu Jun 25 08:43:13 2015 -0700
i965: Remove extern declaration for nonexistent state atom
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
commit d302f51a1ee949fae5dc53f3c872c2712021caf7
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Thu Jun 25 08:20:01 2015 -0700
i965: Trivial formatting changes in gen7_vs_state.c
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
commit f917a65b3eeaf0e201bd7e695a5d13403e7ad487
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Thu Jun 25 08:20:01 2015 -0700
i965: Trivial formatting changes in gen6_multisample_state.c
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
commit 07433760e3311ff17c0f909514ececdae9f6e9c6
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Thu Jun 25 08:20:01 2015 -0700
i965: Trivial formatting changes in brw_misc_state.c
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
commit 680d09b072af7ea1541cfd4fbc62c83e8bd02d0d
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Thu Jun 25 08:20:01 2015 -0700
i965: Trivial formatting changes in brw_draw_upload.c
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
commit 5b6218395c303ff82a19294c05c63c7b92d24e3f
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Thu Jun 18 18:45:44 2015 -0700
i965: Trivial formatting changes in brw_draw.c
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
commit 2b81cefb3fec3c5c17e7ef9f95c9681abfad5386
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Jun 10 17:09:16 2015 -0700
i965: Trivial formatting changes in brw_wm.c
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Acked-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
commit da1b1bf85cdc691ec27f379de84dec495cdd51e0
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Wed Jul 15 09:32:17 2015 +0200
i965/nir: Do not scalarize phis in non-scalar setups
Significantly reduces register pressure in some piglit tests.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 34d162260f513a7eaec12611e3859bb34230cf33
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jul 8 16:08:17 2015 +0200
i965/vec4: Handle uniform and GRF array access on vertex programs (NIR)
When the NIR-vec4 pass is enabled, handles uniform and GRF array access
on ARB_vertex_program like it is done on vertex shaders.
When the old IR-vec4 pass is used, emit_program_code() emits pull constant
loads directly instead of using relative addressing, hence to call to
move_uniform_array_access_to_pull_constants() is not needed and it is enough
to call to split_uniform_registers().
The patch also calls to move_grf_array_access_to_scratch() like it is
done for shaders, however I suspect this is a no-op for vertex programs and
we could remove it.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 82f2e706bfd646b91bc0b8beecdff4e54b1f7b04
Author: Antia Puentes <apuentes at igalia.com>
Date: Mon Jun 29 14:21:38 2015 +0200
i965/nir/vec4: Handle uniforms on vertex programs
The implementation takes into account that on ARB_vertex_program
only a single nir variable is generated to support all the uniform data.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 90825e3ca977057c8f3d6ad2d1aa38277cc3ff11
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jul 8 12:44:15 2015 +0200
i965/vec4: Enable NIR-vec4 pass on ARB_vertex_programs
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 287b006a673dabe3e21cc207a1b4622ef91a877e
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Wed Jul 1 10:12:10 2015 +0200
i965/nir/gs: Implement support for gl_InvocationID system value
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 7eced3aa863394c6e74ac3f037ed1cf9c481fe37
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Mon Jul 13 15:51:17 2015 +0200
i965/gs/gen6: Refactor ir_emit_vertex and ir_end_primitive for gen6
So the implementation is independent of GLSL IR and the visit methods of the
gen6 GS visitor. This way we will be able to reuse that implementation directly
from the NIR vec4 backend.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 1836201fde1826c82f579fb132455c8df4176ecd
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Mon Jun 29 14:08:11 2015 +0200
i965/nir/gs: Implement EmitVertex and EndPrimitive
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 551af29d2d8be33b66641fe47ee5156489c16132
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Mon Jun 29 13:52:30 2015 +0200
i965/nir/gs: Handle geometry shaders inputs
Outputs from the vertex shader become array inputs in the geomtry shader,
but the arrays are interleaved, so we need to map our inputs accordingly.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 7ade42755f8900aaf67073214c073419f734e7a8
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Mon Jun 29 13:37:31 2015 +0200
i965/gs: Refactor ir_emit_vertex and ir_end_primitive
So the implementation is independent of GLSL IR and the visit methods of the
vec4 visitor. This way we will be able to reuse that implementation directly
from the NIR vec4 backend.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 38fc4a91cd5c04fdd5921b8776f8e203513ab517
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Wed Jul 1 09:51:25 2015 +0200
i965/nir: Enable NIR-vec4 pass on geometry shaders
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 418c004f802e63ca4e9f3456a46498d2fc543854
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Thu Jun 11 12:32:26 2015 +0200
nir: Fix output swizzle in get_mul_for_src
Avoid copying an overwritten swizzle, use the original values.
Example:
Former swizzle[] = xyzw
src->swizzle[] = zyxx
The expected output swizzle = zyxx but if we reuse swizzle in the loop,
then output swizzle would be zyzz.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 19cf934f7f18237e1a212b0a019026d5d36c6fac
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Mon Jul 6 15:08:15 2015 +0200
i965/nir/vec4: Add implementation of nir_emit_texture()
Uses the nir structure to get all the info needed (sources,
dest reg, etc), and then it uses the common
vec4_visitor::emit_texture to emit the final code.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 1343f403b2d08a0877f17133abb6dccf0f51127b
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Mon Jul 6 14:33:21 2015 +0200
i965/ir/vec4: Refactor visit(ir_texture *ir)
Splitted in two. The emission is moved to a new vec4_visitor
method, vec4_visitor::emit_texture, ir order to be reused
on the nir path.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 0d43d27df742ad95a086580bae2ee08a0bc00e69
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Sat May 23 23:42:58 2015 +0200
i965/vec4: Add a new dst_reg constructor accepting a brw_reg_type
This is useful for the upcoming texture support in NIR->vec4 pass,
as we found several cases where the brw_type is available, but not
the glsl_type.
Without this new constructor, the alternative would be:
dst_reg reg(MRF, <reg>)
reg.type = <brw_type>
reg.writemask = <mask>
Adding a new constructor makes code easier to read.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit c15eea2afa7a295992cde949b8e2a5d4552f6290
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Mon Jul 6 13:31:05 2015 +0200
i965/vec4: Change vec4_visitor::swizzle_result() method to allow reuse
This patch changes the signature of swizzle_result() to accept lower
level arguments. The purpose is to reuse it in the upcoming NIR->vec4
pass.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 57182332b84b58fed6641314def67450893b7419
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Thu Jun 18 12:12:21 2015 +0200
i965/vec4: Change vec4_visitor::gather_channel() method to allow reuse
This patch changes the signature of gather_channel() to accept the gather
component directly instead of fetching it internally from ir_texture.
This will allow reuse in the upcoming NIR->vec4 pass.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 72c8d7721feb966cf8530a3ee2642f0b842dc0f8
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Thu Jun 18 11:31:54 2015 +0200
i965/vec4: Change vec4_visitor::emit_mcs_fetch() method to allow reuse
This patch changes the signature of emit_mcs_fetch() to accept lower level
arguments. The purpose is to reuse it in the upcoming NIR->vec4 pass.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 434481f3155040217c3e5a8da98dab4248435f0e
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Thu Jun 18 09:37:33 2015 +0200
i965/vec4: Move is_high_sample() method to vec4_visitor class
The is_high_sample() method is currently accessible only in the implementation of
vec4_visitor. Since we need to reuse it in the upcoming NIR->vec4 pass, lets make
it a method of the class instead.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit db8a6de571bb72ef43209a415e5492001a87b1d8
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Wed Jun 17 10:59:10 2015 +0200
i965/nir: Add new utility method brw_glsl_base_type_for_nir_type()
This method returns the glsl_base_type corresponding to a nir_alu_type.
It will factorize code currently present in fs_nir, that can be reused
in vec4_nir on its upcoming emit_texture support.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 583c1c61703826002ba0f202e8ef7bc2c822ef1d
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Wed Jun 17 10:20:19 2015 +0200
i965/nir/vec4: Implement nir_emit_jump
This implementation is taken as-is from fs_nir.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 9b4a6fa4c09d36e0e5c00309e6ea37300ea38f78
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 10:10:44 2015 +0200
i965/nir/vec4: Mark as unreachable ops that should be already lowered
NIR ALU operations:
* nir_op_fabs
* nir_op_iabs
* nir_op_fneg
* nir_op_ineg
* nir_op_fsat
should be lowered by lower_source mods
* nir_op_fdiv
should be lowered in the compiler by DIV_TO_MUL_RCP.
* nir_op_fmod
should be lowered in the compiler by MOD_TO_FLOOR.
* nir_op_fsub
* nir_op_isub
should be handled by ir_sub_to_add_neg.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 16072834babc487f78472f7e7b59d35249a3aac8
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 10:08:27 2015 +0200
i965/nir/vec4: Implement vector "any" operation
Adds NIR ALU operations:
* nir_op_bany2
* nir_op_bany3
* nir_op_bany4
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit fa4e3c3c9f6f3a72a032499fccaa6e222d6a7fa4
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 10:06:44 2015 +0200
i965/nir/vec4: Implement the dot product operation
Adds NIR ALU operations:
* nir_op_fdot2
* nir_op_fdot3
* nir_op_fdot4
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 96106e2a9f214d98fc2e99c65398f95d41a3b879
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 10:05:29 2015 +0200
i965/nir/vec4: Implement conditional select
Adds NIR ALU operations:
* nir_op_bcsel
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit b38fcd0aea8d17919ecd9cc7afc518cfb2c01c27
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 09:52:43 2015 +0200
i965/nir/vec4: Implement linear interpolation
Adds NIR ALU operation:
* nir_op_flrp
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 314474872b77f291132a01f7c1df2788586fc943
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 10:01:07 2015 +0200
i965/vec4: Return the emitted instruction in emit_lrp()
Needed in the NIR backend to set the "saturate" value of the
instruction.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit b64bd1fdc37eed1bb62d2b32ad22f0f77501f7f2
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 09:51:10 2015 +0200
i965/nir/vec4: Implement floating-point fused multiply-add
Adds NIR ALU operation:
* nir_op_ffma
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit d12e165dbb403c3cf86ab7f1b8f28ab6188b479f
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 09:49:31 2015 +0200
i965/nir/vec4: Implement "shift" operations
Adds NIR ALU operations:
* nir_op_ishl
* nir_op_ishr
* nir_op_ushr
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 798cb33a256f703ecaf56d4443e12055484d4bcc
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 09:47:41 2015 +0200
i965/nir/vec4: Implement the "sign" operation
Follows the vec4_visitor IR implementation but
sets the saturate value in addition.
Adds NIR ALU operations:
* nir_op_fsign
* nir_op_isign
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 8e1e6facbf828258a9a8ca09da846d1baa21d984
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 09:44:25 2015 +0200
i965/nir/vec4: Implement bit operations
Same implementation than the IR case.
Adds NIR ALU operations:
* nir_op_bitfield_reverse
* nir_op_bit_count
* nir_op_ufind_msb
* nir_op_ifind_msb
* nir_op_find_lsb
* nir_op_ubitfield_extract
* nir_op_ibitfield_extract
* nir_op_bfm
* nir_op_bfi
* nir_op_bitfield_insert
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 0e874985ce50d902535e1eb766bd252c921b5d8f
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 09:29:04 2015 +0200
i965/nir/vec4: Implement pack/unpack operations
* Lowered floating-point pack and unpack operations are not valid in VS.
* Pack and unpack 2x16 operations should be handled by lower_packing_builtins.
* Adds NIR ALU operations:
* nir_op_pack_half_2x16
* nir_op_unpack_half_2x16
* nir_op_unpack_unorm_4x8
* nir_op_unpack_snorm_4x8
* nir_op_pack_unorm_4x8
* nir_op_pack_snorm_4x8
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 3f10c2f3d73ae41ff83afcdbe225121b8336f499
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 09:23:10 2015 +0200
i965/nir/vec4: "noise" ops should already be lowered
Marked them as unreachable.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit fa4731f4a53aa21e53a62f42f3afdc19b0ce4c8e
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 09:21:30 2015 +0200
i965/nir/vec4: Implement "bool<->int,float" format conversion
Used the same implementation than the vec4_visitor NIR.
Adds NIR ALU operations:
* nir_op_b2i
* nir_op_b2f
* nir_op_f2b
* nir_op_i2b
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit f14199a8fb802f6672d559fa958a5ee84e3e13f1
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 09:07:20 2015 +0200
i965/nir/vec4: Implement logical operators
Adds NIR ALU operations:
* nir_op_inot
* nir_op_ixor
* nir_op_ior
* nir_op_iand
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 51aeafaf96b3b349e007ad05738bc1e05663fedf
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 09:01:28 2015 +0200
i965/nir/vec4: Implement non-equality ops on vectors
Adds NIR ALU operations:
* nir_op_bany_fnequal2
* nir_op_bany_inequal2
* nir_op_bany_fnequal3
* nir_op_bany_inequal3
* nir_op_bany_fnequal4
* nir_op_bany_inequal4
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 8be4b876c90192c3a5e6fcc9b526f43a3f7bfc11
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 00:55:24 2015 +0200
i965/nir/vec4: Implement equality ops on vectors
Adds NIR ALU operations:
* nir_op_ball_fequal2
* nir_op_ball_iequal2
* nir_op_ball_fequal3
* nir_op_ball_iequal3
* nir_op_ball_fequal4
* nir_op_ball_iequal4
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 84d4a9dc2ca3d98f19cc9125a5ff1ac1225f360d
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 00:49:42 2015 +0200
i965/nir/vec4: Implement non-vector comparison ops
Adds NIR ALU operations:
* nir_op_flt
* nir_op_ilt
* nir_op_ult
* nir_op_fge
* nir_op_ige
* nir_op_uge
* nir_op_feq
* nir_op_ieq
* nir_op_fne
* nir_op_ine
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit b9c41affcf67f30d7f6c74c17ea34bc42756d56d
Author: Antia Puentes <apuentes at igalia.com>
Date: Fri Apr 17 17:58:35 2015 +0200
i965/nir: Add utility method for comparisons
This method returns the brw_conditional_mod value used when emitting
comparative ALU operations.
It could be moved to brw_nir in the future to reuse it in fs_nir backend.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit dae6025e8efdfb759458a3243c8cd1588f485135
Author: Antia Puentes <apuentes at igalia.com>
Date: Tue Apr 14 12:04:24 2015 +0200
i965/nir/vec4: Derivatives are not allowed in VS
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 5e6f1c38a591fa39cff1c32a2cfdda927145756a
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 00:34:57 2015 +0200
i965/nir/vec4: Implement min/max operations
Adds NIR ALU operations:
* nir_op_fmin
* nir_op_imin
* nir_op_umin
* nir_op_fmax
* nir_op_imax
* nir_op_umax
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit d53098393e3929b0c8d82f56144c7497b184f5b7
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 00:32:58 2015 +0200
i965/vec4: Return the emitted instruction in emit_minmax()
Needed in the NIR backend to set the "saturate" value of the
instruction.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 7553a51a68c0b2030265fe741f9c511b65047914
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 00:25:02 2015 +0200
i965/nir/vec4: Implement various rounding functions
Adds NIR ALU operations:
* nir_op_ftrunc
* nir_op_fceil
* nir_op_ffloor
* nir_op_ffrac
* nir_op_fround_even
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 0ce159ec7fbcdf00c488b77f63e565e89ef6cab5
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 00:22:14 2015 +0200
i965/nir/vec4: Implement carry/borrow for addition/subtraction
Adds NIR ALU operations:
* nir_op_uadd_carry
* nir_op_usub_borrow
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 62cef7b0723ad6ca49ed06a6899a5852e41359e8
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 00:10:18 2015 +0200
i965/nir/vec4: Implement more math operations
Adds NIR ALU operations:
* nir_op_frcp
* nir_op_fexp2
* nir_op_flog2
* nir_op_fexp
* nir_op_flog
* nir_op_fsin
* nir_op_fcos
* nir_op_idiv
* nir_op_udiv
* nir_op_umod
* nir_op_ldexp
* nir_op_fsqrt
* nir_op_frsq
* nir_op_fpow
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 068a41b349e8bc30293c44d96553184f7562949f
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 00:04:09 2015 +0200
i965/vec4: Return the last emitted instruction in emit_math()
Needed in the NIR backend to set the "saturate" value of the
instruction.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 9acebf146184c35e6897b91fff414c5295d47996
Author: Antia Puentes <apuentes at igalia.com>
Date: Tue Jun 16 23:50:46 2015 +0200
i965/nir/vec4: Implement multiplication
Implementation based on the vec4_visitor IR implementation
for the operations ir_binop_mul and ir_binop_imul_high.
Adds NIR ALU operations:
* nir_op_fmul
* nir_op_imul
* nir_op_imul_high
* nir_op_umul_high
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 0675842b56a956befbac4a3b912823e73a95a500
Author: Antia Puentes <apuentes at igalia.com>
Date: Tue Jun 16 23:48:46 2015 +0200
i965/nir/vec4: Implement the addition operation
Adds NIR ALU operations:
* nir_op_fadd
* nir_op_iadd
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 4f39b547da4f9949d1b1f9f0df07d08951f0358d
Author: Antia Puentes <apuentes at igalia.com>
Date: Tue Jun 16 23:04:32 2015 +0200
i965/nir/vec4: Implement int<->float format conversion ops
Adds NIR ALU operations:
* nir_op_f2i
* nir_op_f2u
* nir_op_i2f
* nir_op_u2f
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit e4f02f47e70d384531ac68e6d33a62fdcdbd1f28
Author: Antia Puentes <apuentes at igalia.com>
Date: Tue Jun 16 22:58:15 2015 +0200
i965/nir/vec4: Lower "vecN" instructions and mark them unreachable
This enables NIR pass "lower_vec_to_movs" on shaders that work on vec4.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 79154d99d6e760b1daf327b4594dded18f1d4191
Author: Antia Puentes <apuentes at igalia.com>
Date: Tue Jun 16 22:52:29 2015 +0200
i965/nir/vec4: Implement single-element "mov" operations
Adds NIR ALU operations:
* nir_op_imov
* nir_op_fmov
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 9e5d827f455f3c72af6cb8d60b97890bab8d5ad0
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Thu Jun 25 09:52:35 2015 +0200
i965/nir: Disable alu_to_scalar pass on non-scalar shaders
Disables nir_lower_alu_to_scalar when the shader stage being processed work
on vec4 vectors, like the upcoming NIR->vec4 backend.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit ef1b30ae637e613b384541324c199d2dbe6b44bd
Author: Antia Puentes <apuentes at igalia.com>
Date: Tue Jun 16 22:30:16 2015 +0200
i965/nir/vec4: Prepare source and destination registers for ALU operations
This patch resolves and initializes the destination and the source
registers that are common to most ALU operations.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 168bbfa6ff22a586ad6307c187cfa3b8fff5f227
Author: Antia Puentes <apuentes at igalia.com>
Date: Tue Jun 16 22:10:32 2015 +0200
i965/nir/vec4: Implement loading values from an UBO
Based on the vec4_visitor IR implementation for the ir_binop_load_ubo
operation. Notice that unlike the vec4_visitor IR, adding the !=0
comparison for UBO bools is not needed here because that comparison is
already added by the nir_visitor when processing the ir_binop_load_ubo
(in UBOs "true" is any value different from zero, but for us is ~0).
Adds NIR instrinsics:
* nir_intrinsic_load_ubo_indirect
* nir_intrinsic_load_ubo
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 98d07022f5312967bdfd54069869c8d6c65117a7
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Tue Jun 16 22:03:17 2015 +0200
i965/nir/vec4: Implement atomic counter intrinsics (read, inc and dec)
The implementation is based on its fs_nir counterpart.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit e6cafb5dfdef8d8d25ee1e3375304cf35897d1f7
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Tue Jun 16 21:55:14 2015 +0200
i965/nir/vec4: Implement load_uniform intrinsic
For the indirect case we need to take the index delivered by
NIR and compute the parent uniform that we are accessing (the one
that we uploaded to a surface) and the constant offset into that
surface.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit e76e8caecd30799500357a45468329f033a93932
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Tue Jun 16 21:36:49 2015 +0200
i965/nir/vec4: Implement intrinsics that load system values
These include:
nir_intrinsic_load_vertex_id_zero_base
nir_intrinsic_load_base_vertex
nir_intrinsic_load_instance_id
The source register is fetched from the nir_system_values map initialized
during nir_setup_system_values stage.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 662c4c99065381b8e265310d176cfdef6698ca57
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Tue Jun 16 21:31:49 2015 +0200
i965/nir/vec4: Implement store_output intrinsic
This implementation is based on the current URB setup in vec4_visitor, which
requires the output register to be stored in the output_reg array at variable's
original shader location index. But since nir_lower_io() pass uses the value
in var->data.driver_location, we need to put there var->data.location instead,
prior to calling nir_lower_io(), so that we end up with the correct index
in const_index[0].
The driver_location is not used at all, so this patch also disables the
nir_assign_var_locations pass on non-scalar shaders.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 11ed02e1c81a2aa71b22b1d6847f58e41fd89271
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Tue Jul 21 20:21:21 2015 +0200
i965/vec4: Make sure that register types always match during emit_urb_slot()
Instead of relying on backends (currently vec4_visitor and soon NIR-vec4) to
store registers in output_reg with the correct type, this patch makes sure
that the common code in emit_urb_slot() always emit MOVs from output registers
using the same type on source and destination.
Since the actual type is not important, only that they match, we default to
float.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 167cb9663adc8c7c61807e503f66e85f955e7d5f
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Tue Jun 16 21:24:21 2015 +0200
i965/nir/vec4: Implement load_input intrinsic
The source register is fetched from the nir_inputs map built during
nir_setup_inputs stage.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit afe085a0ca01f659c69456018e5f5076c9dde47d
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Tue Jun 16 20:25:55 2015 +0200
i965/nir/vec4: Implement loop statements (nir_cf_node_loop)
This is taken as-is from fs_nir.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 5c0436dbf87fef76ba67456f215d9285c38f1816
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Tue Jun 16 20:16:15 2015 +0200
i965/nir/vec4: Implement conditional statements (nir_cf_node_if)
The same we do in the FS NIR backend, only that here we need to consider
the number of components in the condition and adjust the swizzle
accordingly.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit f3187ea31ede6bc181ee561573d127aa2e485657
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Tue Jun 16 17:43:02 2015 +0200
i965/nir/vec4: Add get_nir_dst() and get_nir_src() methods
These methods are essential for the implementation of the NIR->vec4 pass. They
work similar to their fs_nir counter-parts.
When processing instructions, these methods are invoked to resolve the
brw registers (source or destination) corresponding to the NIR sources
or destination. It uses the map of NIR register index to brw register for
all registers locally allocated in a block.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 97e205fd35bf77fd761caf24c611ff72cc0d85e2
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Fri Apr 17 18:10:50 2015 +0200
i965/nir: Move brw_type_for_nir_type() to brw_nir to allow reuse
Upcoming NIR->vec4 pass can benefit from this method, so lets move it up.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit f7152525374015594e037fa11bb64e1c7174829b
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Wed Jul 1 16:10:49 2015 +0200
i965/nir/vec4: Implement load_const intrinsic
Similar to fs_nir backend, a nir_local_values map will be filled with
newly allocated registers as the load_const instrinsic instructions are
processed. Later, get_nir_src() will fetch the registers from this map
for sources that are ssa.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit a5a3287f7392356386aa305c791d94b6d5dde6cc
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Tue Jun 16 20:53:28 2015 +0200
i965/vec4: Add auxiliary func to build a writemask from a component size
New method brw_writemask_for_size() will return a writemask with the first
'size' components activated.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 6e58fc56a5a396020cd299db11895120ec3da520
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Fri Jul 3 08:23:33 2015 +0200
i965/nir: Dot not assign direct uniform locations first for vec4-based shaders
In the vec4 backend we want uniform locations to be assigned consecutively
since that way the offsets produced by nir_lower_io are exactly what we
need to implement nir_intrinsic_load_uniform. Otherwise we would need a
mapping to match the output of nir_lower_io to the actual uniform registers
we need to use.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 01f6235020f9f0c2bc1a6e6ea9bd15c22fb2bcf5
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Thu Jun 18 13:52:21 2015 +0200
nir/nir_lower_io: Add vec4 support
The current implementation operates in scalar mode only, so add a vec4
mode where types are padded to vec4 sizes.
This will be useful in the i965 driver for its vec4 nir backend
(and possbly other drivers that have vec4-based shaders).
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 5e839727ed2378a01d3b657bad83abd4728e8da6
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Wed Jul 22 09:35:28 2015 +0200
i965/nir: Pass a is_scalar boolean to brw_create_nir()
The upcoming introduction of NIR->vec4 pass will require that some NIR
lowering passes are enabled/disabled depending on the type of shader
(scalar vs. vector).
With this patch we pass a 'is_scalar' variable to the process of
constructing the NIR, to let an external context decide how the shader
should be handled.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 59006d3ad3ed5d29e84afa5931f425344e2ef658
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Wed Jul 22 09:34:35 2015 +0200
i965/nir/vec4: Add shader function implementation
It basically allocates registers local to a function in a nir_locals map,
then emits all its control-flow blocks.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 4023b55fdd7005a8a100637c229a1c40648cdd2b
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Tue Jun 16 17:08:04 2015 +0200
i965/nir/vec4: Add setup for system values
Similar to other variable setups, system values will initialize the
corresponding register inside a 'nir_system_values' map, which will then
be queried later when processing the different system value intrinsics
for the appropriate register.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 01c5617c8edc2f392363e9f8861d62a9fc9aa973
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Tue Jun 16 17:01:29 2015 +0200
i965/vec4: Redefine make_reg_for_system_value() to allow reuse in NIR->vec4 pass
The new virtual method is more flexible, it has a signature:
dst_reg *make_reg_for_system_value(int location, const glsl_type *type);
v2 (Jason Ekstrand):
Use the new version in unit tests so make check passes again
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 195156e571e851273c135847f91ed73b3bfc1914
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Tue Jun 16 14:30:31 2015 +0200
i965/nir/vec4: Add setup of uniform variables
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit b929acb6a8659fdc06623b766bdf59904d8a3558
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Tue Jun 16 13:50:43 2015 +0200
i965/nir/vec4: Add setup of input variables in NIR->vec4 pass
This implementation sets up a map of input variable offsets to source registers
that are already initialized with the corresponding register offset.
This map will then be queried when processing load_input intrinsic operations,
to obtain the correct register source from which the input data will be loaded.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 78e7ce2b7329f8cc3f771afbf39d3fa662e02d9e
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Tue Jun 16 13:39:48 2015 +0200
i965/vec4: Move type_size() method to brw_vec4_visitor class
The type_size() method is currently accessible only in the implementation
of vec4_visitor. Since we need to reuse it in the upcoming NIR->vec4 pass,
lets make it a method of the class instead.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 47d68908f2c3ad3e9011a2cf910b04cd3300673a
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Tue Jun 16 12:26:39 2015 +0200
i965/nir/vec4: Select between new nir_vec4 or current vec4_visitor code-paths
The NIR->vec4 pass will be activated if both the following conditions are met:
* INTEL_USE_NIR environment variable is defined and is positive (1 or true)
* The stage is vertex shader (support for geometry shaders and
ARB_vertex_program will be added later).
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit abf4fa3c03ebe5716c90c8a310945c3621cf598f
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Tue Jun 16 12:08:09 2015 +0200
i965/nir/vec4: Add implementation placeholders for a new NIR->vec4 pass
This patch will add a brw_vec4_nir.cpp file filled with entry point methods to
the main functionality, following a structure similar to brw_fs_nir.cpp.
Subsequent patches in this series will be adding the implementations for these
methods, incrementally.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 594fc0f85953d11c455e7ab549308a773b312d70
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu Jun 25 16:47:52 2015 -0700
mesa: Replace F_TO_I() with _mesa_lroundevenf().
I'm not sure what the true meaning of "The rounding mode may vary." is,
but it is the case that the IROUND() path rounds differently than the
other paths (and does it wrong, at that).
Like _mesa_roundeven{f,}(), just add an use _mesa_lroundeven{f,}() that
has known semantics.
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit f55c408067a3ea3529fcf7cbbaa1a041a4a8849d
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Jul 31 12:19:46 2015 -0700
mesa: Add -fno-trapping-math to CFLAGS.
Cuts about 1k of .text size.
text data bss dec hex filename
4983676 197808 26328 5207812 4f7704 i965_dri.so before
4982522 197800 26328 5206650 4f727a i965_dri.so after
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit 875458b778e8d389e00f42269e716a3cb2761fab
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Jul 31 12:18:37 2015 -0700
mesa: Add -fno-math-errno to CFLAGS.
Cuts about 9k of .text size.
text data bss dec hex filename
4992804 197808 26328 5216940 4f9aac i965_dri.so before
4983676 197808 26328 5207812 4f7704 i965_dri.so after
Also, Darwin's libm does not ever set errno, so if we care about those
systems we shouldn't rely on errno anyway.
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit 44e90f2a556a9b8ede12ae18a7cfa3a71e32d40c
Author: Zoltan Gilian <zoltan.gilian at gmail.com>
Date: Thu Jul 30 20:11:51 2015 +0200
r600,compute: force tiling on 2D and 3D texture compute resources
To circumvent a problem occuring when LINEAR_ALIGNED array mode is
selected on a TEXTURE_2D RAT.
This configuration causes MEM_RAT STORE_TYPED to write to incorrect
locations.
commit be3622dce383cb930a233b88bb056adb026dce1f
Author: Zoltan Gilian <zoltan.gilian at gmail.com>
Date: Thu Jul 30 23:35:09 2015 +0200
clover: handle setKernelArg errors
commit aa46fba7e61a77bb3b029c7a483b5a2a2a73ff4d
Author: Zoltan Gilian <zoltan.gilian at gmail.com>
Date: Mon Jul 27 11:27:12 2015 +0200
clover: fix image resource depth and array_size
commit ab5b7a0fe659ff6f9c1885d5cb047b6531959506
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Sun Aug 2 14:57:38 2015 +1000
nir: Use a single bit for the dual-source blend index
The only values allowed are 0 and 1, and the value is checked before
assigning.
This is a copy of 8eeca7a56c that seems to have been made to the glsl
ir type after it was copied for use in nir but before nir landed.
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 9ef5b7a23348291893a6bf61fcce7a306e787add
Author: Zoltan Gilian <zoltan.gilian at gmail.com>
Date: Mon Jul 27 11:34:07 2015 +0200
clover: pass image attributes to the kernel
Read-only and write-only image arguments are recognized and
distinguished.
Attributes of the image arguments are passed to the kernel as implicit
arguments.
commit d2cd2c69b20fcb3f1fc3b7671745c5c84ef200cb
Author: Zoltan Gilian <zoltan.gilian at gmail.com>
Date: Mon Jul 27 11:21:07 2015 +0200
clover: move find_kernels to functions
commit cf5667108b2cdd6f37e1a561c18fb5c757258f06
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Sun Aug 2 11:40:26 2015 +1000
mesa: fix type for array indexing validation
parse_program_resource_name returns -1 when the index is invalid this needs to
be tested before assigning the value to the unsigned array_index.
In link_varyings.cpp (the other place parse_program_resource_name is used) after
the -1 check is done the value is just assigned to an unsigned variable so it
seems long is just used so we can return the -1 rather than actually expecting
index values to be ridiculously large.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 704e764f06e8e6ec75484e28271e502bbc4cf06a
Author: Marta Lofstedt <marta.lofstedt at intel.com>
Date: Mon May 11 15:03:56 2015 +0200
mesa/es3.1: Allow multisampled textures for GLES 3.1
GLES 3.1 must be allowed to create multisampled textures.
Signed-off-by: Marta Lofstedt <marta.lofstedt at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 2253a296c9ad7b11f9844640024c5f0784e4e528
Author: Marta Lofstedt <marta.lofstedt at intel.com>
Date: Mon May 11 15:03:55 2015 +0200
mesa/es3.1: Allow query of GL_TEXTURE_MULTISAMPLE
GLES 3.1 must allow a query for GL_TEXTURE_MULTISAMPLE.
Signed-off-by: Marta Lofstedt <marta.lofstedt at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 0fe81a25f7102d78dbe8f7e89d2b024b1741da1c
Author: Marta Lofstedt <marta.lofstedt at intel.com>
Date: Mon May 11 15:03:53 2015 +0200
mesa/es3.1: Allow enable of GL_SAMPLE_MASK
GLES 3.1 must be able to enable GL_SAMPLE_MASK.
Signed-off-by: Marta Lofstedt <marta.lofstedt at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit d74645d3acc815f6129b4cb20e6570c127d5ab2b
Author: Marta Lofstedt <marta.lofstedt at intel.com>
Date: Mon May 11 15:03:52 2015 +0200
mesa/es3.1: Allow textures with target GL_TEXTURE_2D_MULTISAMPLE
GLES 3.1 should be able to bind a texture with the target
GL_TEXTURE_2D_MULTISAMPLE.
Signed-off-by: Marta Lofstedt <marta.lofstedt at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit a4bde371c7172fd775dea4377f9bccc3a38992c0
Author: Marta Lofstedt <marta.lofstedt at intel.com>
Date: Mon May 11 15:03:51 2015 +0200
mesa/es3.1: Allow GL_DEPTH_STENCIL_TEXTURE_MODE
GLES 3.1 must support the parameter GL_DEPTH_STENCIL_TEXTURE_MODE.
Signed-off-by: Marta Lofstedt <marta.lofstedt at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 4f8e4a95dbd806bc735bf93dda245be2bb2ea454
Author: Marta Lofstedt <marta.lofstedt at intel.com>
Date: Mon May 11 15:03:50 2015 +0200
mesa/es3.1: Allow GL_SAMPLE_MASK
GLES 3.1 should be allowed to enable GL_SAMPLE_MASK.
Signed-off-by: Marta Lofstedt <marta.lofstedt at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 2e0179e2b3b9ea369816597f789a5bda7e0c46b5
Author: Marta Lofstedt <marta.lofstedt at intel.com>
Date: Mon May 11 15:03:49 2015 +0200
mesa/es3.1: Allow binding GL_DRAW_INDIRECT_BUFFER with gles 3.1
Signed-off-by: Marta Lofstedt <marta.lofstedt at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit de59a40f6898e20a61ac4ea0e5995334f6ed2932
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Aug 2 15:19:19 2015 +0200
r600g: re-enable single-sample fast clear
Fixed by the CB_SHADER_MASK fix.
Tested-by: Dieter Nützel <Dieter at nuetzel-hh.de>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit d4ad4c20617f45f71152e292ee39f020ef352bfd
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Aug 2 15:18:36 2015 +0200
r600g: fix the CB_SHADER_MASK setup
This fixes the single-sample fast clear hang.
Cc: 10.6 <mesa-stable at lists.freedesktop.org>
Tested-by: Dieter Nützel <Dieter at nuetzel-hh.de>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit 828d20bdb79c4b6e6cb761017ad030bd875f9ac2
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Aug 2 15:17:30 2015 +0200
r600g: fix the single-sample fast clear setup
No effect, but this is what we should be doing.
Tested-by: Dieter Nützel <Dieter at nuetzel-hh.de>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit 08fd736a45c98bd0acd96dfc1a61e6a695d2703c
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Jul 16 19:55:42 2015 +0200
radeonsi: flush if the memory usage for an IB is too high
Picked from the amdgpu branch.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
commit 4d7e0fa8c731776ad5d630f37b36c535f1907371
Author: Igor Gnatenko <i.gnatenko.brain at gmail.com>
Date: Tue Jul 7 13:05:04 2015 +0300
opencl: use versioned .so in mesa.icd
We must have versioned library in mesa.icd, because ICD loader would
fail if the mesa-devel package wasn't installed.
Cc: "10.6" <mesa-stable at lists.freedesktop.org>
Reported-by: Fabian Deutsch <fabian.deutsch at gmx.de>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=73512
Signed-off-by: Igor Gnatenko <i.gnatenko.brain at gmail.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Michel Dänzer <michel.daenzer at amd.com>
commit 2b831334e95e80e1a53dcce2fab21b012d3384c7
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Jul 30 15:18:54 2015 +0100
includes/GL: remove duplicated extension declarations from glx.h
All three of GLX_NV_float_buffer, GLX_EXT_texture_from_pixmap and
GLX_MESA_query_renderer have been in glxext.h for a while now.
As such we can drop this workaround/hack from the header.
v2: Remove the comment about GLX_NV_float_buffer.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com> (v1)
commit 6f2d88927a77f902157704d16b70b1265e0ca357
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Jul 29 18:13:50 2015 +0100
docs: rename/bump 10.7.0 release notes to 11.0.0
Recently a few drivers have grown OpenGL 4+ support so we might as
well go all the way to... 11 ;-)
v2: Don't forget to update the version file (Ilia)
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 1307be519b8785249ee863a22115930299ff642a
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Jul 29 15:44:32 2015 +0100
winsys/radeon: don't leak the fd when it is 0
Earlier commit added an extra dup(fd) to fix a ZaphodHeads issue.
Although it did not consider the (very unlikely) case where we might end
up with the valid fd == 0.
Fixes: 28dda47ae4d(winsys/radeon: Use dup fd as key in drm-winsys hash
table to fix ZaphodHeads.)
Cc: 10.6 <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Reviewed-by: Mario Kleiner <mario.kleiner.de at gmail.com>
commit eb3e2562a4bf728082818b46dcae1ab88340786e
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Jul 10 12:28:23 2015 +0100
configure.ac: check for mkostemp()
We can make use of it over mkstemp + fcntl in the egl/wayland code.
Cc: Axel Davy <axel.davy at ens.fr>
Suggested-by: Matt Turner <mattst88 at gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 175d9752796bbcc52f1df90b1466c879bccfc406
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Jul 10 12:27:06 2015 +0100
egl/wayland: use drmGetNodeTypeFromFd helper instead of opencoding it
Cc: Axel Davy <axel.davy at ens.fr>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Boyan Ding <boyan.j.ding at gmail.com>
commit 5567494403938940f61d44888c436a20a6635ef3
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Jul 10 12:24:11 2015 +0100
egl/wayland: use designated initializers
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
commit 720125ff99a8563d1f5991bd7428b8d884f1f618
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Jul 10 11:22:13 2015 +0100
egl: remove ifdef $(egl_extension) compile guards
All of these are already defined in the headers provided.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit fa109d02dda118f756903b663879375c06353ae7
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Jul 10 11:01:55 2015 +0100
egl/wayland: libdrm is a hard requirement, treat it as such
Prompt at configure time if it's missing otherwise we'll fail later on
in the build. Remove ambiguous HAVE_LIBDRM guard.
Cc: 10.6 <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 57c670a823e55f5dd1fb2eb3d15e7db0a4f5c07a
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Jul 10 11:01:35 2015 +0100
egl: consolidate ifdef HAVE_LIBDRM blocks
Move the code around rather than having it scattered. No functional
change.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
commit b0a929960384ffebf3b4f693fa0db4231ed897d4
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Jul 10 00:16:21 2015 +0100
configure.ac: null,android,gdi are not valid egl-platforms
... and update the documentation to reflect reality.
null and gdi are gone, and surfaceless is a recent addition.
v2: s/platforms/platform/ (spotted by Thomas)
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
commit 5d29eaef85c15663cde317c2df58ea81637c53f9
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Aug 1 00:51:00 2015 +0200
Revert "gallium/radeon: re-enable unsafe math for graphics shaders"
This reverts commit 8559f6ce62a9d5b52fa8189ba2352cd48bdabccf.
It causes hangs in DOTA 2 Reborn.
commit a40179f47ba11e78097ae1a839df6f3911a6749f
Author: EdB <edb+mesa at sigluy.net>
Date: Fri Jul 31 19:14:45 2015 +0200
clover: make dispatch matches functions def
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 8477dd7c2e4416838c54da75a769109b4c5cc48e
Author: Vinson Lee <vlee at freedesktop.org>
Date: Wed Jul 29 20:17:36 2015 -0700
gallivm: Fix GCC unused-variable warning.
lp_bld_tgsi_soa.c: In function 'lp_emit_immediate_soa':
lp_bld_tgsi_soa.c:3065:18: warning: unused variable 'size' [-Wunused-variable]
const uint size = imm->Immediate.NrTokens - 1;
^
Signed-off-by: Vinson Lee <vlee at freedesktop.org>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit bafdafa7b2e6649791188b5acf235ba166ceae50
Author: Adam Jackson <ajax at redhat.com>
Date: Fri Jul 31 13:36:21 2015 -0400
glx: Fix missing bit decl for EXT_texture_integer
Missing from:
commit b15aba940a3b6fc7c9bebc692968e7e9b72b9f29
Author: Adam Jackson <ajax at redhat.com>
Date: Tue Jul 21 11:43:42 2015 -0400
glx: Fix image size computation for EXT_texture_integer (v2)
Signed-off-by: Adam Jackson <ajax at redhat.com>
commit 616355160d3ee6edff3429b1abef82f0706dad3d
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Jul 29 10:47:51 2015 -0700
glsl: Initialize parse-state in constructor of lower_subroutine.
Static analysis tools don't like partial object initializations.
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit b15aba940a3b6fc7c9bebc692968e7e9b72b9f29
Author: Adam Jackson <ajax at redhat.com>
Date: Tue Jul 21 11:43:42 2015 -0400
glx: Fix image size computation for EXT_texture_integer (v2)
Without this this extension basically can't work in indirect contexts,
TexImage2D will compute the image size as 0 and we'll send no image data
to the server.
v2: Add EXT_texture_integer to the client extension list too (Ian)
Reviewed-by: Eric Anholt <eric at anholt.net>
Signed-off-by: Adam Jackson <ajax at redhat.com>
commit 30509788641a413742098f21a4ee0087b1f86e18
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Jul 30 17:38:44 2015 +0200
radeonsi: copy *8_SNORM bits exactly in resource_copy_region
Disabling the FP16 mode didn't help.
If needed, we can use this trick for blits too, but not for scaled blits.
+ 4 piglits
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 64d3130994bde98b0be44a5c54511e376b6d994e
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Jul 28 11:39:35 2015 +0200
r600g: early exit in r600_clear if there's nothing to do
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit f9c4953f99e75e45bc4f0f07315ee643b62b0c23
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Jul 28 11:39:35 2015 +0200
radeonsi: early exit in si_clear if there's nothing to do
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 190a40580fdfccf00db93f5c8f15bbf16914be2c
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Jul 27 19:01:21 2015 +0200
radeonsi: fix a regression since the resource_copy_region cleanup
Broken since:
46b2b3b - radeonsi: don't change pipe_resource in resource_copy_region
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91444
Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer at amd.com>
commit 3ca21320583a4c0ba9bee755935df5e1f1637fdf
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Jul 26 21:08:18 2015 +0200
radeonsi: fix broken st/nine from merging tessellation
st/nine uses GENERIC slots greater than 60.
commit 2d3ae154ba36546485468b9552e6da905b42aaa4
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jul 25 01:25:07 2015 +0200
radeonsi: move CP DMA functions to their own file
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 3063c5e3d3fefdc5eed7600882bd08f56bf86db8
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jul 25 16:15:48 2015 +0200
radeonsi: add a debug flag that disables printing ISA in shader dumps
commit 2dcbd427da74c8f2b6f46e789924a7ced67be260
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jul 25 16:15:48 2015 +0200
radeonsi: add a debug flag that disables printing TGSI in shader dumps
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit ac19a896d3de13b7d064d01c575f46f4191ef37c
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jul 25 16:15:48 2015 +0200
radeonsi: add a debug flag that disables printing the LLVM IR in shader dumps
This is for shader-db and should reduce size of shader dumps.
commit 7dd1f45bc41c4a936b0ff84400840524bb9f8871
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jul 11 00:17:48 2015 +0200
radeonsi: store shader disassemblies in memory for future users
This will be used by the new ddebug pipe. I'm including it now to avoid
conflicts with other patches.
commit 1bbe40836306549414408bb7f30b9288c020db75
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jul 25 12:17:19 2015 +0200
radeonsi: don't use llvm.AMDIL.fraction for FRC and DFRAC
There are 2 reasons for this:
- LLVM optimization passes can work with floor
- there are patterns to select v_fract from floor anyway
There is no change in the generated code.
commit 8559f6ce62a9d5b52fa8189ba2352cd48bdabccf
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jul 25 12:01:07 2015 +0200
gallium/radeon: re-enable unsafe math for graphics shaders
This reverts commit 4db985a5fa9ea985616a726b1770727309502d81.
The grass no longer disappears, which was the reason the commit was reverted.
This might affect tessellation. We'll see.
Totals from affected shaders:
SGPRS: 151672 -> 150232 (-0.95 %)
VGPRS: 90620 -> 89776 (-0.93 %)
Code Size: 3980472 -> 3920836 (-1.50 %) bytes
LDS: 67 -> 67 (0.00 %) blocks
Scratch: 1357824 -> 1202176 (-11.46 %) bytes per wave
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
commit 12a197b2d58125e4dbe2942204df1bbe3258e54b
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jul 25 17:24:08 2015 +0200
gallium/radeon: don't use rsq_action
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit 681dbcf69040883e91423df56fcb34f4fee57110
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jul 25 17:12:39 2015 +0200
gallium/radeon: move r600-specific code to r600g
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
commit 9a4c57afe48c391bb335f74c88b447f83704b413
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jul 25 16:53:29 2015 +0200
gallium/radeon: remove unused variables and old comments
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit b9dad585e66b1031bdcbb148a19524ee2705baf7
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jul 25 11:26:18 2015 +0200
gallium/radeon: remove build_intrinsic and build_tgsi_intrinsic
duplicated now
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit 0c805b6240769891d55db601f91b8dd84d69d43d
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jul 25 11:17:48 2015 +0200
gallivm: add LLVMAttribute parameter to lp_build_intrinsic
This will help remove some duplicated code from radeon.
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit 488a83637fe726d445775ee301e42003f749cb9f
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jul 25 15:55:45 2015 +0200
gallium/util: clear up that debug_get_flags_option returns a 64-bit mask
Reviewed-by: Kai Wasserbäch <kai at dev.carbon-project.org>
commit b0528118dfb1af00e7d08cdb637191b80c14c2ba
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jul 25 00:53:16 2015 +0200
radeonsi: completely rework updating descriptors without CP DMA
The patch has a better explanation. Just a summary here:
- The CPU always uploads a whole descriptor array to previously-unused memory.
- CP DMA isn't used.
- No caches need to be flushed.
- All descriptors are always up-to-date in memory even after a hang, because
CP DMA doesn't serve as a middle man to update them.
This should bring:
- better hang recovery (descriptors are always up-to-date)
- better GPU performance (no KCACHE and TC flushes)
- worse CPU performance for partial updates (only whole arrays are uploaded)
- less used IB space (no CP_DMA and WRITE_DATA packets)
- simpler code
- hopefully, some of the corruption issues with SI cards will go away.
If not, we'll know the issue is not here.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 781dc7c0e1f41502f18e07c0940af949a78d2792
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Jul 30 14:45:57 2015 +0300
i965/fs: Fix regression with SIMD8 VS since b5f1a48e234d47b24df38cb562cffb8941d43795.
With num_direct_uniforms == 0 there's no space allocated in the
param_size array for the one block of direct uniforms -- On the FS
stage this would be a harmless no-op because it would simply re-set
one of the param_size entries allocated for the sampler units to zero,
but on the VS stage it has been reported to cause memory corruption
followed by a crash -- Surprising how a full piglit run on Gen8 didn't
catch it.
Reported-and-reviewed-by: "Lofstedt, Marta" <marta.lofstedt at intel.com>
commit 383558c56427b0e8b4e56cce8737771ad053f753
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Thu Jul 30 19:16:32 2015 -0700
i965/gen9: Add hs, ds, and cs thread + urb info
For SKL: These are the production values.
For BXT: These are low estimates to enable platforms.
This patch was originally part of
i965/skl: Add production thread counts and URB size
but was split out at Jordan's request (which I found to be reasonable).
Note on stable inclusion: 10.6 does not care about hs, and ds. It does care
about cs, but since Jordan was the one that asked me to extract it, I'll leave
it up to him to deal with a backport to stable is required.
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 3cb58010037bad24890785007fd8f47d67249f2f
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Thu Jul 30 19:12:15 2015 -0700
i965/bxt: Use more conservative thread counts
Since we really do not know what may occur in the future, pick a more
conservative value for thread counts until we know better what values are
correct. As far as I can tell, the old values will work fine, but some of the
registers seem to indicate that going even lower is possible and the purpose of
having early support is to enable as many configurations that can possibly
exist (we can trim things down after platforms begin shipping later).
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 7eaacc1678195738fab3bb98870828611cae066d
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Wed Jul 29 12:35:24 2015 -0700
i965/skl: Add production thread counts and URB size
This patch adjusts the SKL values to the best known values we have.
v2: Remove HS/DS/CS fields. Adding this makes most sense to add to the
GEN9_FEATURES macro, however, doing that would require updating BXT values, and
Jordan requested I not do that. Conveniently, this request makes a lot of sense
wrt to stable backport as HS, and DS do not even exist there.
Cc: mesa-stable at lists.freedesktop.org
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 7830e465a5f446616ce49a7f8219256a5503a68b
Author: Eric Anholt <eric at anholt.net>
Date: Thu Jul 30 11:16:13 2015 -0700
vc4: Lower uniform loads to scalar in NIR.
This also moves the vec4-to-byte-addressing math into NIR, so that
algebraic has a chance at it.
commit 5a8c57b52287ba2bb8faa4447e7d1cc46ef1a3d4
Author: Eric Anholt <eric at anholt.net>
Date: Wed Jul 29 17:27:54 2015 -0700
vc4: Move some FS input lowering into NIR.
commit 13ddd48b97474c261ef2d7412629748d6d91f2ad
Author: Eric Anholt <eric at anholt.net>
Date: Wed Jul 29 17:29:39 2015 -0700
vc4: Move program keys to the header file.
I want to be able to inspect them from other files for lowering passes in
NIR.
commit 27f728cdc5d90f63839fbeb1942e6f27339b102a
Author: Eric Anholt <eric at anholt.net>
Date: Wed Jul 29 17:16:26 2015 -0700
vc4: Lower NIR inputs to scalar as well.
For now this is just scalarizing, but it also means we'll get to dump a
bunch of QIR-based lowering in a moment.
commit b85f6ae4b24ee50948f14a9effa982eb0b9b3681
Author: Eric Anholt <eric at anholt.net>
Date: Wed Jul 29 15:52:18 2015 -0700
vc4: Start adding a NIR-based output lowering pass.
For now, this just splits up store_output intrinsics to be scalars, and
drops unused outputs in the coordinate shader. My goal is to be able to
drop a bunch of my VC4-specific optimization by letting NIR handle it.
commit c93ffd661a46f0f6d20c9ec2e97d4d9393e28111
Author: Eric Anholt <eric at anholt.net>
Date: Wed Jul 29 12:16:50 2015 -0700
vc4: Mark our shaders as single-threaded.
I had my understanding of this bit flipped. We're using the full register
space, so we need to say so.
commit df3005de189f5120bc06f6cba35ecaf5c4503229
Author: Eric Anholt <eric at anholt.net>
Date: Wed Jul 29 14:41:22 2015 -0700
vc4: Avoid leaking indirect array access UBOs.
commit 86541cf8cea77f4b887dd061e7d6e3e4767f86fd
Author: Eric Anholt <eric at anholt.net>
Date: Wed Jul 29 14:40:10 2015 -0700
vc4: Avoid overflowing various static tables.
commit d0173bce371e3aafa732600c1456a9282ff5d900
Author: Eric Anholt <eric at anholt.net>
Date: Wed Jul 29 12:20:33 2015 -0700
vc4: Fix return values from recent validation changes.
commit a5b3b24958b5e4344e7d8d1e029dbf7e5afb183c
Author: Kai Wasserbäch <kai at dev.carbon-project.org>
Date: Thu Jul 30 20:32:36 2015 +0200
docs: trivial cleanup of GL3.txt, remove redundant radeonsi entries.
Follow-up to 1b2b0e42ce47bfd1fcb5513ed2c23b9bb7a5a5b8
Signed-off-by: Kai Wasserbäch <kai at dev.carbon-project.org>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 518abd0bbe1886550b43c62679a2ebd41e8199e9
Author: Dave Airlie <airlied at gmail.com>
Date: Thu Jul 30 20:44:50 2015 +1000
st/mesa: don't draw instead of asserting in transform feedback
if we get a request to take the count from feedback, but there
is no buffer to take it from, just draw as if we got 0 vertices
so nothing.
This fixes this assert killing the ogl conform, and a piglit
test I've sent.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit fdb84876134ed074563b842eae20fd10dbe9e8d6
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Sat Jul 4 08:35:35 2015 +1000
mesa: remove now unused _mesa_get_uniform_location
Cc: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 7f5f7d15fbbd3d306e43e1e9ff215750b8aaa7bf
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Sat Jul 25 12:39:43 2015 +1000
mesa: remove now unused subscript validations
Cc: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 8cd2f88845acd45ebcbaae2e68a8a47b3c17e6d5
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Sat Jul 25 12:33:53 2015 +1000
mesa: fix and simplify resource query for arrays
This removes the need for multiple functions designed to validate an array
subscript and replaces them with a call to a single function.
The change also means that validation is now only done once and the index
is retrived at the same time, as a result the getUniformLocation code can
be simplified saving an extra hash table lookup (and yet another
validation call).
This chage also fixes some tests in:
ES31-CTS.program_interface_query.uniform
V3: rebase on subroutines, and move the resource index array == 0
check into _mesa_GetProgramResourceIndex() to simplify things further
V2: Fix bounds checks for program input/output, split unrelated comment fix
and _mesa_get_uniform_location() removal into their own patch.
Cc: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 3a21e4bd263002dd600e7a693536c93f68b285a5
Author: Neil Roberts <neil at linux.intel.com>
Date: Wed Jul 29 17:40:37 2015 +0100
i965/bxt: Don't use brw_device_info_skl_early on BXT
Previously it could end up using the “SKL early†device on BXT
depending on the revision number. This would probably break things
because for example has_llc would be wrong.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 75a96cedf7b0e5613560be0962dec973a4d2f2fe
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Sat Jul 4 15:43:15 2015 +1000
glsl: set stage flag for structs and arrays in resource list
This fixes the remaining failing tests in:
ES31-CTS.program_interface_query.uniform-types
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 1b2b0e42ce47bfd1fcb5513ed2c23b9bb7a5a5b8
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Jul 29 10:51:46 2015 +0100
docs: consolidate radeonsi in GL3.txt
move into DONE for GL4.0 and GL4.1
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit af1e6aa75b7f518cc6b08717fa8844370be3f05c
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Jul 22 01:24:39 2015 +0100
radeonsi: enable GL4.1 and update documentation (v2)
This enables GL4.1 for radeonsi, and updates the
docs in the correct places.
v2: enable only for llvm 3.7 which has fixes in place.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 3c73c418713adec52389e2723e38bf47df13a24b
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Jul 20 02:37:14 2015 +0100
radeonsi: add GS multiple streams support (v2)
This is the final piece for ARB_gpu_shader5,
The code is based on the r600 code from Glenn Kennard,
and myself.
While developing this, I'm not 100% sure of all the calculations
made in the GS registers, this is why the max_stream is worked
out there and used to limit the changes in registers. Otherwise
my initial attempts either regressed GS texelFetch tests
or primitive-id-restart. The current code has no regressions
in piglit.
This commit doesn't enable ARB_gpu_shader5, since that just
bumps the glsl level to 4.00, so I'll just do a separate patch
for 4.10.
v1.1: fix bug introduced in rebase.
v2: Address Marek's review comments,
remove my llvm stream code for simpler C,
move gsvs_ring and gs_next_vertex to arrays.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit c73a13e9538cab1772b71fb5599e4944c540412e
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Wed Jul 29 10:15:03 2015 -0700
Delete unused functions in format parser
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Neil Roberts <neil at linux.intel.com>
commit 92994742d079bffdc4c25fdc5a22c7438b7da9c7
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Wed Jul 29 09:57:26 2015 -0700
i965: Change the type of max_{vs, hs, ...}_threads variables to unsigned
Fixes following compiler warning:
brw_cs.cpp:386:27: warning: comparison between signed and unsigned
integer expressions [-Wsign-compare]
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 2484263fe97cebc9fa7a5c9de04c757dc6cc7713
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Wed Jul 29 09:41:18 2015 -0700
Delete duplicate function is_power_of_two() and use _mesa_is_pow_two()
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 8413822c8cfaf9110625c1a4a66ee916c2a916e3
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Wed Jul 29 20:45:09 2015 +0100
gallium/auxiliary: Ensure c99_math.h is included.
As it is needed for exp2.
Trivial.
commit 2b916c6e47862d82b5545e962ebb83b811904c3b
Author: Roland Scheidegger <sroland at vmware.com>
Date: Wed Jul 29 22:20:04 2015 +0200
c99_math: (trivial) implement exp2 for MSVC too
Unsurprisingly doesn't build otherwise with old msvc.
commit e933d545997de9e50a8ed5247722c1c786bf4858
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Tue Jul 28 19:52:49 2015 -0700
i965/bxt: Support 3src simd16 instructions
This is easily accomplished by moving simd16 3src to GEN9_FEATURES.
v2: small cleanup to make it more similar to GEN8_FEATURES
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit c0731a1b14dc7385f4238b4508b88bfca2ef43cf
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Jul 22 16:04:28 2015 +0100
targets/dri: scons: add missing link against libdrm
Otherwise the final dri module will have (additional) unresolved
symbols.
Cc: Brian Paul <brianp at vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviwed-by: Jose Fonseca <jfonseca at vmware.com>
commit 4fc86f183eee43117925499d8d1315be481ba636
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Jul 17 18:18:20 2015 +0100
svga: scons: remove unused HAVE_SYS_TYPES_H define
There isn't a single instance in mesa that
mentions HAVE_SYS_TYPES_H, other than this file.
Cc: Jose Fonseca <jfonseca at vmware.com>
Acked-by: Brian Paul <brianp at vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 23bba717e1178d54927c4968a0466d706a630432
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Jul 15 21:29:21 2015 -0700
glsl: Avoid double promotion.
commit a562313f378a056c8d886e418b518063ab077c39
Author: Matt Turner <mattst88 at gmail.com>
Date: Sun Jul 12 23:15:42 2015 -0700
mesa: Avoid double promotion.
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 7adc9fa1f1d12683c5855bf5854dec814629093d
Author: Matt Turner <mattst88 at gmail.com>
Date: Sun Jul 12 23:15:32 2015 -0700
mesa/math: Avoid double promotion.
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 076f73edb34f2a83092c6c8ad04b53def2792bb8
Author: Matt Turner <mattst88 at gmail.com>
Date: Sun Jul 12 23:15:19 2015 -0700
program: Avoid double promotion.
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 04aa8b58a09e3b415916fa569111c1f76d07a8d5
Author: Matt Turner <mattst88 at gmail.com>
Date: Sun Jul 12 23:15:10 2015 -0700
swrast: Avoid double promotion.
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit c92b2a1d7b286de8641512970a87c94809fbbc3f
Author: Matt Turner <mattst88 at gmail.com>
Date: Sun Jul 12 23:15:01 2015 -0700
tnl: Avoid double promotion.
There are a couple of unrelated changes in t_vb_lighttmp.h that I hope
you'll excuse -- there's a block of code that's duplicated modulo a few
trivial differences that I took the liberty of fixing.
commit 2b47ef715ad33f6c4a4881b10240d792ba9e60b2
Author: Matt Turner <mattst88 at gmail.com>
Date: Sun Jul 12 23:14:54 2015 -0700
vbo: Avoid double promotion.
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit b568a5f6a8c6bb07b27e9badce01a8a73ba56c03
Author: Matt Turner <mattst88 at gmail.com>
Date: Sun Jul 12 18:01:54 2015 -0700
util: Avoid double promotion.
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 29ef7a9f19265308e7852c0f8920e0f520f08df3
Author: Matt Turner <mattst88 at gmail.com>
Date: Sun Jul 12 18:01:42 2015 -0700
gallium/auxiliary: Avoid double promotion.
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 4251ccb47b79c719918e7c372aebb6b2d9719922
Author: Matt Turner <mattst88 at gmail.com>
Date: Sun Jul 12 12:37:00 2015 -0700
nir: Avoid double promotion.
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit c1da15709a0c0c2775bd9e534f67c60f7dc95ce8
Author: Matt Turner <mattst88 at gmail.com>
Date: Sun Jul 12 00:13:45 2015 -0700
i965: Use float calculations when double is unnecessary.
Literals without an f/F suffix are of type double, and implicit
conversion rules specify that the float in (float op double) be
converted to a double before the operation is performed. I believe float
execution was intended (in nearly all cases) or is sufficient (in the
case of gen7_urb.c).
Removes a lot of float <-> double conversion instructions and replaces
many double instructions with float instructions which are cheaper.
text data bss dec hex filename
4928659 195160 26192 5150011 4e953b i965_dri.so before
4928315 195152 26192 5149659 4e93db i965_dri.so after
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit c67ce2bd3b27a26d7f5665f296d307c0de39b720
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Jul 13 15:19:54 2015 -0700
gallium/auxiliary: Use exp2(x) instead of pow(2.0, x).
commit b73782bf184b7053026e8dda54800d48e64e20da
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Jul 13 15:19:33 2015 -0700
program: Use exp2(x) instead of pow(2.0, x).
commit f8a647883a14694f1b758c12187b3f35b9d039a7
Author: Matt Turner <mattst88 at gmail.com>
Date: Sat Jul 11 22:46:19 2015 -0700
mesa: Use floats for viewport bounds.
ARB_viewport_array specifies that DEPTH_RANGE consists of double-
precision parameters (corresponding commit d4dc35987), and a preparatory
commit (6340e609a) added _mesa_get_viewport_xform() which returned
double-precision scale[3] and translate[3] vectors, even though X, Y,
Width, and Height were still floats.
All users of _mesa_get_viewport_xform() immediately convert the double
scale and translation vectors into floats (which were floats originally,
but were converted to doubles in _mesa_get_viewport_xform(), sigh).
i965 at least cannot consume doubles (see SF_CLIP_VIEWPORT). If we want
to pass doubles to hardware, we should have a different function that
does that.
Acked-by: Mathias Froehlich <Mathias.Froehlich at web.de>
commit ecc559218d0a544f8a5f878c500f125c2d588d82
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Jul 15 21:28:56 2015 -0700
c99_math: Implement exp2f for MSVC.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 5c7fd670459ebff452adeec335c77854af903842
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Jul 15 20:54:46 2015 -0700
glsl: Remove MSVC implementations of copysign and isnormal.
Non-Gallium parts of Mesa require MSVC 2013 which provides these.
commit 02425d3ec2af6945a03583cadcaa5f3f330bbc0e
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 27 18:51:01 2015 +0300
i965/fs: Make the default builder 64-wide before entering the optimization loop.
Not a typo. Replace the default builder with one of bogus width to
catch cases in which optimization passes assume that the default
dispatch width is good enough. The execution controls of instructions
emitted during optimization should in general match the original code
that is being manipulated. Many of the problems fixed in this series
were caught by the assertions introduced in this patch.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 4529916dfd227af6c4e151f45261db22157fe45f
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 27 18:42:31 2015 +0300
i965/fs: Don't set exec_all on instructions wider than the original in lower_simd_width.
This could have led to somewhat increased bandwidth usage for lowered
texturing instructions on Gen4 (which is the only case in which
lower_width may be greater than inst->exec_size). After the previous
patches the invariant mentioned in the comment should no longer be
assumed by any of the other optimization and lowering passes, so the
exec_all() call shouldn't be necessary anymore.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit eaba922582cfdccc7b198f9b23d8bd3c26197d03
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 27 18:28:39 2015 +0300
i965/fs: Initialize a builder explicitly in the gen4 send dependency work-arounds.
Instead of relying on the default one. This shouldn't lead to any
functional changes because DEP_RESOLVE_MOV overrides the execution
size of the instruction anyway and other execution controls are
irrelevant.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 8b838fa9f01f7ee13fd9fc3e6545a677397f8023
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Jul 10 19:49:49 2015 -0700
i965/cfg: Assert that cur_do/while/if pointers are non-NULL.
More.. like in commit 4d93a07c.
commit 9da9adcfd7df45a0a337e0fbf482f60ff5566499
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Jul 29 11:01:08 2015 -0400
nvc0/ir: cache vertex out base so that we don't recompute again
The global CSE pass stinks and is unable to pull this out. Easy enough
to handle it here and avoid generating unnecessary special register
loads (which can allegedly be quite slow).
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit ad75620863392b2164a415186087beb831ccfa4c
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Jul 29 09:37:14 2015 -0400
nvc0/ir: output base for reading is based on laneid
PFETCH retrieves the address for incoming vertices, not output vertices
in TCS. For output vertices, we must use the laneid as a base.
Fixes barrier piglit test, which was failing for entirely non-barrier
reasons, but rather that it was (a) trying to draw multiple patches and
(b) the incoming patch size was not the same as the outgoing patch size.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit e42d2948d3c58b86d3770d296b96fafcd1218858
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jul 29 15:37:52 2015 +0300
Revert "pipe-loader: simplify pipe_loader_drm_probe"
This reverts commit a27ec5dc460b91dc44675f48cddbbb2631ee824f. It
breaks the intended behaviour of pipe_loader_probe() with ndev==0 as
relied upon by clover to query the number of devices available to the
pipe loader in the system.
Acked-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 5e645e68d6672cac2872fa509fb22bc2581f4b67
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 27 19:18:51 2015 +0300
i965/fs: Switch opt_cse() to the fs_builder constructor from instruction.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 992cda2c8a452ec86386a0f98eaf522afe206695
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 27 18:41:18 2015 +0300
i965/fs: Switch lower_logical_sends() to the fs_builder constructor from instruction.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 930ebb258524762c765fa864ef7063bd8bb754a1
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 27 18:34:43 2015 +0300
i965/fs: Switch lower_load_payload() to the fs_builder constructor from instruction.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit a0b192d3d9fa64f6f8bff5f1e456e40e72f4875e
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 27 20:14:41 2015 +0300
i965/fs: Don't rely on the default builder to create a null register in emit_spill.
It's not guaranteed to have the same width as the instruction
generating the spilled variable.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit bfad71606a987f14f20d2c3607846648f8537f2b
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 27 18:15:44 2015 +0300
i965/fs: Set up the builder execution size explicitly in opt_sampler_eot().
opt_sampler_eot() was relying on the default builder to have the same
width as the sampler and FB write opcodes it was eliminating, the
channel selects didn't matter because the builder was only being used
to allocate registers, no new instructions were being emitted with it.
A future commit will change the width of the default builder what will
break this assumption, so initialize it explicitly here.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 09039f4bc120481219d01ed17e1552ca8ad66455
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 27 19:20:50 2015 +0300
i965/fs: Initialize a builder explicitly in opt_peephole_predicated_break().
This wasn't taking into account the execution controls of the original
instruction, but it was most likely not a bug because control flow
instructions are typically full width.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit e1f4724097d1074ec9afdc9ce9ad024add125923
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 27 19:27:30 2015 +0300
i965/fs: Set execution controls explicitly in opt_peephole_sel().
Emit the SELs and MOVs with the same execution controls as the
original MOVs, and the CMP with the same execution controls as the IF.
Also explicitly check that the execution controls of any pair of MOVs
being folded into a SEL are compatible (which is almost always going
to be the case), since otherwise it would seem wrong to initialize the
builder object below from the then_mov instruction only.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit ff463af436bcf07430807512c9f0bf0f627288ce
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 27 18:38:59 2015 +0300
i965/fs: Set execution controls correctly in lower_integer_multiplication().
lower_integer_multiplication() was ignoring the execution controls of
the original MUL instruction. Fix it by using the new fs_builder
constructor.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit ce90227c71c8cbe6ca4317f1873ff12c70081c4c
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 27 17:55:49 2015 +0300
i965/fs: Set execution controls correctly for lowered pull constant loads.
demote_pull_constants() was ignoring the execution size and channel
selects of the instruction that wanted the constant, which doesn't
matter for uniform pull constant loads because all channels get the
same scalar value, but it might for varying pull constant loads. Fix
it by using the new fs_builder() constructor that takes care of
setting execution controls compatible with the instruction passed as
argument.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 53077aee6670022e634a4775d8abbb59c458b7d7
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 27 19:09:45 2015 +0300
i965/fs: Set the execution size of the MOVs correctly in opt_combine_constants().
The execution size was being left equal to the default of 8/16, which
AFAICT would have overwritten components other than the one we wanted
to initialize and could potentially have corrupted other registers.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 6f7dea0b3212aa4ce49fcf9e94bf7aab130eeab2
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 27 17:54:46 2015 +0300
i965/fs: Define a new fs_builder constructor taking an instruction as argument.
We have a number of optimization passes that repeat the same pattern
before inserting new instructions into the program based on some
previous instruction: They point the default builder at the original
instruction, then call exec_all() and group() to select the same
execution controls the original instruction had, and then maybe call
annotate() to clone the debug annotation from the original
instruction.
In fact an optimization pass missing any of these steps is likely to
be broken if the intention was to emit new code based on a preexisting
instruction, so let's make it easy for passes to do the right thing by
having an fs_builder constructor that automates the task of setting up
a builder to emit a given instruction provided as argument.
The following patches fix all cases I've found in which we weren't
explicitly initializing the execution controls of the emitted
instructions, and clean-up optimization passes which were already
doing the right thing to use the new constructor.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 7cb60d770fc24bf00b6f7e5898cca1426e55c026
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 27 16:25:55 2015 +0300
i965/fs: Translate memory barrier NIR intrinsics.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit b5f1a48e234d47b24df38cb562cffb8941d43795
Author: Francisco Jerez <currojerez at riseup.net>
Date: Sun Jun 28 21:15:28 2015 +0300
i965/fs: Execute nir_setup_uniforms, _inputs and _outputs unconditionally.
Images take up zero uniform slots in the nir_shader::num_uniforms
calculation, but nir_setup_uniforms needs to be executed even if the
program has no non-image uniforms so the driver-specific image
parameters are uploaded. nir_setup_uniforms is a no-op if there are
really no uniforms, so checking the num_uniform count is useless in
any case.
The nir_setup_inputs and _outputs changes shouldn't lead to any
functional change, they are just meant to preserve the symmetry
between them and nir_setup_uniforms.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 3e5a90792d14aeb599dd236f830e6e344b35c905
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue May 5 22:12:03 2015 +0300
i965/fs: Don't overwrite fs_visitor::uniforms and ::param_size during the SIMD16 run.
Image variables need to allocate additional uniform slots over
nir_shader::num_uniforms. nir_setup_uniforms() overwrites the values
imported from the SIMD8 visitor and then exits early before entering
the nir_shader::uniforms loop, so image uniforms are never re-created.
Instead leave the imported values alone, they *must* be the same for
the uniform layout of both runs to be compatible.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit ea0ac53f059c418d5797c495b87020f2ca2ec842
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jun 29 16:50:49 2015 +0300
i965/fs: Drop unused untyped surface read and atomic emit methods.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 854c4d8b37416d3e5593099a8e5441f3cf861173
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue May 5 20:52:58 2015 +0300
i965/fs: Revisit NIR atomic counter intrinsic translation.
Rewrite the NIR atomic counter intrinsics translation code making use
of the recently introduced surface builder. This will allow the
removal of some of the functionality duplicated between the visitor
and surface builder.
v2: Drop VEC4 suport.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 1aab58f39450213ea2ac43549eefb8acd1e6584a
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Apr 30 19:31:44 2015 +0300
i965/fs: Import surface message builder helper functions.
Implement helper functions that can be used to construct and send
untyped and typed surface read, write and atomic messages to the
shared dataport unit easily.
v2: Drop VEC4 suport.
v3: Reimplement in terms of logical send opcodes.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 03846696ce2deaaaff42b2acd7745b51a7f115f2
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 13 15:39:03 2015 +0300
i965/fs: Handle zero-size allocations in fs_builder::vgrf().
This will be handy to avoid some ugly ternary operators in the next
patch, like:
fs_reg reg = (size == 0 ? null_reg_ud() : vgrf(..., size));
Because a zero-size register allocation is guaranteed not to ever be
read or written we can just return the null register. Another
possibility would be to actually allocate a zero-size VGRF what would
involve defining a zero-size register class in the register allocator
and a considerable amount of churn.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 3352724dfa4eb5c93290db92ae99d26d9b89e630
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue Jul 14 18:42:57 2015 +0300
i965/fs: Implement lowering of logical surface instructions.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 086d29f4d747bbcfe37beeb18ba77fb2cb84dbdc
Author: Francisco Jerez <currojerez at riseup.net>
Date: Sat Jul 18 16:16:19 2015 +0300
i965/fs: Hook up SIMD lowering to unroll surface instructions of unsupported width.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 7a594a95a930f1658062e4d86d0f37d491b372b3
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue Jul 21 18:45:32 2015 +0300
i965/fs: Define logical typed and untyped surface opcodes.
Each logical variant is largely equivalent to the original opcode but
instead of taking a single payload source it expects its arguments
separately as individual sources, like:
typed_surface_write_logical null, coordinates, source, surface,
num_coordinates, num_components
This patch defines the opcodes and usual instruction boilerplate,
including a placeholder lowering function provided mainly as
documentation for their source registers.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 3af2623da5167aa686bcb2cff01d27058a507026
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 20 17:38:15 2015 +0300
i965: Lift the constness restriction on surface indices passed to untyped ops.
v2: Update NIR atomic intrinsic handling too (Ken).
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit a0c02d2bbb765b0e997ad524d8e51838e529d9c0
Author: Francisco Jerez <currojerez at riseup.net>
Date: Sun Jun 28 21:04:17 2015 +0300
i965: Define the setup_vector_uniform_values() backend_visitor interface.
This cleans up the VEC4 implementation of setup_uniform_values()
somewhat and will avoid duplication of the image uniform upload code
by having a common interface to upload a vector of uniforms on either
back-end.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit bd0d6a9cce8b28357888bb261fac639e2833c51f
Author: Francisco Jerez <currojerez at riseup.net>
Date: Fri Jul 24 16:51:14 2015 +0300
i965/fs: Remove the emit_texture_gen*() fs_visitor methods.
This is now dead code.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 59979b133dd16bf46803f87e78677eba944cc757
Author: Francisco Jerez <currojerez at riseup.net>
Date: Fri Jul 17 18:23:31 2015 +0300
i965/fs: Reimplement emit_mcs_fetch() in terms of logical sends.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit ba78a5007171afaa5f2d76d71be131f01a5b5023
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 13 16:07:45 2015 +0300
i965/fs: Reimplement emit_texture() in terms of logical send messages.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 4be99438e6e40280f9dc071882ce3bfbfabadb4a
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 13 21:19:52 2015 +0300
i965/fs: Hook up SIMD lowering to handle texturing opcodes of unsupported width.
This should match the set of cases in which we currently call fail()
or no16() from the emit_texture_*() methods and the ones in which
emit_texture_gen4() enables the SIMD16 workaround.
Hint for reviewers: It's not a big deal if I happen to have missed
some case here, it will just lead to an assertion failure down the
road which is easily fixable, however being stricter than necessary
won't cause any visible breakage, it would just decrease performance
silently due to the unnecessary message splitting, so feel free to
double-check that all cases listed here already cause a SIMD8/16
fall-back with the current texturing code -- You may want to skip over
the Gen5-6 cases though if you don't have pencil and paper at hand.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 2cd466f6c3192015ea1794afc57eb453d7f13818
Author: Francisco Jerez <currojerez at riseup.net>
Date: Sat Jul 18 17:09:37 2015 +0300
i965/fs: Implement lowering of logical texturing opcodes on Gen4.
Unlike its Gen5 and Gen7 counterparts this patch isn't a plain
refactor of the previous Gen4 texturing code, it's more of a rewrite
largely based on emit_texture_gen4_simd16(). The reason is that on
the one hand the original emit_texture_gen4() code didn't seem easily
fixable to be SIMD width-invariant and had plenty of clutter to
support SIMD-width workarounds which are no longer required. On the
other hand emit_texture_gen4_simd16() was missing a number of
SIMD8-only opcodes. This should generalize both and roughly match
their current behaviour where there is overlap.
Incidentally this will fix the following piglits on Gen4:
arb_shader_texture_lod.execution.arb_shader_texture_lod-texgrad
arb_shader_texture_lod.execution.tex-miplevel-selection *gradarb 2d
arb_shader_texture_lod.execution.tex-miplevel-selection *gradarb 3d
arb_shader_texture_lod.execution.tex-miplevel-selection *projgradarb 2d
arb_shader_texture_lod.execution.tex-miplevel-selection *projgradarb 2d_projvec4
arb_shader_texture_lod.execution.tex-miplevel-selection *projgradarb 3d
Acked-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 501134b9fe02633ca0cdda66a9b670ae38e791f7
Author: Francisco Jerez <currojerez at riseup.net>
Date: Sat Jul 18 16:52:06 2015 +0300
i965/fs: Implement lowering of logical texturing opcodes on Gen5-6.
This should be largely equivalent to emit_texture_gen5() except for
slight codestyle changes and the use i965 opcodes instead of the
ir_texture_opcode enum, see "i965/fs: Implement lowering of logical
texturing opcodes on Gen7+." for the mapping between them.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 03582f95b256e483fc1b0d78bd6a49203a448a23
Author: Francisco Jerez <currojerez at riseup.net>
Date: Fri Jul 17 18:50:27 2015 +0300
i965/fs: Lower SHADER_OPCODE_TXF_UMS/MCS_LOGICAL too on Gen7+.
These weren't being handled by emit_texture_gen7() but we can easily
lower them here for consistency with other texturing opcodes.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 8be01e3548bdd900b7cadb5c9a77e52b01151cfe
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 13 18:08:51 2015 +0300
i965/fs: Implement lowering of logical texturing opcodes on Gen7+.
This should be largely equivalent to emit_texture_gen7() except that
we now get i965 sampling opcodes directly rather than
ir_texture_opcode enum values. The mapping is as follows:
- ir_tex -> SHADER_OPCODE_TEX
- ir_txb -> FS_OPCODE_TXB
- ir_txl -> SHADER_OPCODE_TXL
- ir_txd -> SHADER_OPCODE_TXD
- ir_txf -> SHADER_OPCODE_TXF
- ir_txf_ms -> SHADER_OPCODE_TXF_CMS
- ir_txs -> SHADER_OPCODE_TXS
- ir_query_levels -> SHADER_OPCODE_TXS too, the visitor will make
sure that the provided lod value is zero in this
case.
- ir_lod -> SHADER_OPCODE_LOD
- ir_tg4 -> SHADER_OPCODE_TG4_OFFSET if the offset value is not
immediate, SHADER_OPCODE_TG4 otherwise.
Other than that there are only minor changes and style fixes like the
implementation now being factored out in static functions to improve
encapsulation.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit a69332a31243a7733dab926b765964ba6df827b2
Author: Francisco Jerez <currojerez at riseup.net>
Date: Fri Jul 24 16:41:19 2015 +0300
i965/fs: Fix misleading comment regarding the message header in emit_texture_gen7.
This hasn't been overallocating space for the header for a long time.
It still leaves the header uninitialized though until the generator
fixes it.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit fc2273a3400963e478582ee1efbfc8cdaae3eae7
Author: Francisco Jerez <currojerez at riseup.net>
Date: Fri Jul 17 18:46:21 2015 +0300
i965/fs: Pass a BAD_FILE header source to LOAD_PAYLOAD in emit_texture_gen7().
So that it's left uninitialized by LOAD_PAYLOAD, we only need to
reserve space for it in the message since it will be initialized
implicitly by the generator.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 44a8cf488e0370d7e5abe363c1fd2d21247a6e32
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 13 15:33:04 2015 +0300
i965/fs: Fix opt_zero_samples() for texturing ops not matching dispatch_width.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 8fbb3d3569e6d353dee6e558eb9fd961b5a8a12c
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 13 15:42:20 2015 +0300
i965/fs: Use exec_size instead of dispatch_width to determine the message variant.
dispatch_width is global for a single compilation and doesn't
necessarily match the desired execution width if we had to lower the
original full-width instruction due to hardware limitations. These
were all inside a Gen4-specific branch so this patch shouldn't have
any effect on more recent hardware.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 33deff4f0582d2c073d34d4d6ec8344d2b1fbf7d
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue Jul 21 18:42:27 2015 +0300
i965/fs: Define logical texture sampling opcodes.
Each logical variant is largely equivalent to the original opcode but
instead of taking a single payload source it expects the arguments
separately as individual sources, like:
tex_logical dst, coordinates, shadow_c, lod, lod2,
sample_index, mcs, sampler, offset,
num_coordinate_components, num_grad_components
This patch defines the opcodes and usual instruction boilerplate,
including a placeholder lowering function provided mostly as
documentation for their source registers.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit f18792aa10cedba2034762eade816c4c77ca46c6
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Jul 16 16:12:48 2015 +0300
i965/fs: Reimplement emit_single_fb_write() in terms of logical framebuffer writes.
The only non-trivial thing it still has to do is figure out where to
take the src/dst depth values from and predicate the instruction if
discard is in use. The manual SIMD unrolling logic in the dual-source
case goes away because this is now handled transparently by the SIMD
lowering pass.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
commit 59e7e6f7a21f13ff8963cf21af2e969f1f7961f5
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 13 17:59:34 2015 +0300
i965/fs: Implement lowering of logical framebuffer writes.
This does essentially the same thing as
fs_visitor::emit_single_fb_write(), with some slight differences:
- We don't have to worry about exec_size and use_2nd_half anymore,
16-wide sources have already been lowered to 8-wide thanks to the
previous commit and the manual argument unzipping is no longer
required.
- The src/dst_depth and sample_mask values are now explicit sources
of the instruction instead of being taken from the visitor state
directly. The same goes for the kill-pixel mask that will be
passed to the instruction explicitly as predicate.
- Everything is now done in static functions to improve
encapsulation.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
commit 633938afd349f2b423146969688c11f1e29ca17a
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 13 21:19:28 2015 +0300
i965/fs: Hook up SIMD lowering to unroll FB writes of unsupported width.
This shouldn't have any effect because we don't emit logical
framebuffer writes yet.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit cecf738b0fbe8ebafe304c717e847f1d3f41d3ca
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 13 14:49:27 2015 +0300
i965/fs: Remove the FS_OPCODE_SET_OMASK pseudo-opcode.
This is now unused.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 98b0122e0a194e0d6c5d3eb05fd3f29a5286b3b3
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jul 15 17:31:04 2015 +0300
i965/fs: Don't attempt to copy the useless half of oMask for SIMD8 FB writes.
There's no need to initialize the wrong half of oMask in the payload
when we're doing an 8-wide framebuffer write because it will be
ignored by the hardware anyway. By doing it this way we can let the
SIMD lowering pass split the sample_mask source as a regular
per-channel source, otherwise we would have to introduce some sort of
per-instruction source query or use fs_inst::header_size for the
lowering pass to be able to find out whether some source is
header-like, and leave the source untouched in that case.
As a bonus this achieves the same purpose as the previous code without
making use of the SET_OMASK pseudo-instruction, which will be removed
in a future commit.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit b1abfc49476f0277ddee0df269b56fc3de714c4b
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jul 15 18:50:59 2015 +0300
i965/fs: Move up Gen6 no16 check to emit_fb_writes().
And update the comment.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit b145855df624d0031eb2399503389948ebfcdd26
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jul 15 18:49:55 2015 +0300
i965/fs: Move up prog_data->uses_omask assignment up to brw_codegen_wm_prog().
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 6bd991a1377862e3b1b9c05e835289fff9d6785f
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jul 15 17:05:27 2015 +0300
i965/fs: Simplify control flow in emit_single_fb_write().
Flatten the if ladder to match the way that the ordering of these
fields is specified in the hardware documentation a bit more closely.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 1ad928ed9f4e7723f709f91d18d17726c92f0b7b
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jul 15 16:42:57 2015 +0300
i965/fs: Fix slight layering violation in emit_single_fb_writes().
In cases where the color0 argument wasn't being provided,
emit_single_fb_writes() would take the alpha channel directly from the
visitor state instead of taking it from its arguments. This sort of
hack didn't fit nicely into the logical send-message approach because
all parameters of the instruction have to be visible to the SIMD
lowering pass for it to be able to split them into halves at all.
Fix it by using LOAD_PAYLOAD in fs_visitor::emit_fb_writes() to
provide an actual color0 vector with undefined contents except for the
alpha component to match the previous behavior when no color buffers
are enabled.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit f68ec2baf49e37f9ce4fffe95f13177eb7225015
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 13 15:40:18 2015 +0300
i965/fs: Make sure that the type sizes are compatible during copy propagation.
It's surprising that we weren't checking for this already. A future
patch will cause code like the following to be emitted:
MOV(16) tmp<1>:uw, src
MOV(8) dst<1>:ud, tmp<8,8,1>:ud
The second MOV comes from the expansion of a LOAD_PAYLOAD header copy,
so I don't have control over its types. Copy propagation will happily
turn this into:
MOV(8) dst<1>:ud, src
Which has different semantics. Fix it by preventing propagation in
cases where a single channel of the instruction would span several
channels of the copy (this requirement could in fact be relaxed if the
copy is just a trivial memcpy, but this case is unusual enough that I
don't think it matters in practice).
I'm deliberately only checking if the type of the instruction is
larger than the original, because the converse case seems to be
handled correctly already in the code below.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit fa75f2d56616cba81014d4fc02931dcfaedaf5b9
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 13 15:41:34 2015 +0300
i965/fs: Honour the instruction force_sechalf and exec_size fields for FB writes.
We were previously guessing the half based on the EOT flag which seems
rather gross.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit a9f31a032b0a1068a4e2ceed9ed4680ecf13e28b
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 27 16:14:36 2015 +0300
i965/fs: Define logical framebuffer write opcode.
The logical variant is largely equivalent to the original opcode but
instead of taking a single payload source it expects its arguments
that make up the payload separately as individual sources, like:
fb_write_logical null, color0, color1, src0_alpha,
src_depth, dst_depth, sample_mask, num_components
This patch defines the opcode and usual instruction boilerplate,
including a placeholder lowering function provided mainly as
self-documentation.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 8368939e5d94f8d4ae55a1f22a755922ee77132b
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 13 21:15:31 2015 +0300
i965/fs: Implement pass to lower instructions of unsupported SIMD width.
This lowering pass implements an algorithm to expand SIMDN
instructions into a sequence of SIMDM instructions in cases where the
hardware doesn't support the original execution size natively for some
particular instruction. The most important use-cases are:
- Lowering send message instructions that don't support SIMD16
natively into SIMD8 (several texturing, framebuffer write and typed
surface operations).
- Lowering messages that don't support SIMD8 natively into SIMD16
(*cough*gen4*cough*).
- 64-bit precision operations (e.g. FP64 and 64-bit integer
multiplication).
- SIMD32.
The algorithm works by splitting the sources of the original
instruction into chunks of width appropriate for the lowered
instructions, and then interleaving the results component-wise into
the destination of the original instruction. The pass is controlled
by the get_lowered_simd_width() function that currently just returns
the original execution size making the whole pass a no-op for the
moment until some user is introduced.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
v2: Reverse order of the source transformations and split_inst emit
call to make the code a bit easier to understand.
commit 86ae788baefefdb2fa77fe3c242ad2d81c8e834e
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Jul 16 15:58:56 2015 +0300
i965/fs: Fix return value of fs_inst::regs_read() for BAD_FILE.
Typically BAD_FILE sources are used to mark a source as not present
what implies that no registers are read. This will become much more
frequent with logical send opcodes which have a large number of
sources, many of them optionally used and marked as BAD_FILE when they
aren't applicable. It will prove to be useful to be able to rely on
the value of regs_read() regardless of whether a source is present or
not.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 5a5607a16ce7bf5eace2cf4b267af304aef05e90
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue Jul 14 19:32:03 2015 +0300
i965/fs: Add builder emit method taking a variable number of source registers.
And start using it in fs_builder::LOAD_PAYLOAD(). This will be used
to emit logical send message opcodes which have an unusually large
number of arguments.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 1dd3543ac1bebe089bfe3a8ae5efbe3f564e1144
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 13 17:44:58 2015 +0300
i965/fs: Add stub lowering pass for logical send-message opcodes.
This pass will house ad-hoc lowering code for several send
message-like virtual opcodes that will represent their logically
independent arguments as separate instruction sources rather than as a
single payload blob. This pass will basically just take the separate
arguments that are supposed to be part of the payload and concatenate
them to construct a message in the form required by the hardware.
Virtual instructions in separate-source form will eventually allow
some simplification of the visitor code and make several
transformations easier like lowering SIMD16 instructions to SIMD8
algorithmically in cases where the hardware doesn't support the former
natively.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit fb7eba97d7235d49ac712a21fb51009c86f3bc64
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue Jul 21 17:28:39 2015 +0300
i965/fs: Factor out source components calculation to a separate method.
This cleans up fs_inst::regs_read() slightly by disentangling the
calculation of "components" from the handling of message payload
arguments. This will also simplify the SIMD lowering and logical send
message lowering passes, because it will avoid expressions like
'regs_read * REG_SIZE / component_size' which are not only ugly, they
may be inaccurate because regs_read rounds up the result to the
closest register multiple so they could give incorrect results when
the component size is lower than one register (e.g. uniforms). This
didn't seem to be a problem right now because all such expressions
happen to be dealing with per-channel GRFs only currently, but that's
by no means obvious so better be safe than sorry.
v2: Split PIXEL_X/Y and LINTERP into separate case blocks.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 24d74b66883da1955f8c2223367d41470d99df6d
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue Jul 28 12:07:56 2015 +0300
i965/fs: Simplify instruction rewrite loop in the register coalesce pass.
For some reason the loop that rewrites all occurrences of the
coalesced register was iterating over all possible offsets until it
would find one that compares equal to the offset of a source or
destination of any instruction in the program. Since the mapping
between old and new offsets is already available in the regs_to_offset
array and we know that the whole register has been coalesced we can
just look it up.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 170200e0fcb0b16d20bff86e1258e0a1b2034c10
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 13 14:20:32 2015 +0300
i965/fs: Fix rewrite of the second half of 16-wide coalesced registers.
The register coalesce pass wasn't rewriting the destination and
sources of instructions that accessed the second half of a coalesced
register previously copied with a 16-wide MOV instruction. E.g.:
| ADD (16) vgrf0:f, vgrf0:f, 1.0:f
| MOV (16) vgrf1:f, vgrf0:f
| MOV (8) vgrf2:f, vgrf0+1:f { sechalf }
would get incorrectly register-coalesced into:
| ADD (16) vgrf1:f, vgrf1:f, 1.0:f
| MOV (8) vgrf2:f, vgrf0+1:f { sechalf }
The reason is that the mov[i] pointer was being left equal to NULL for
every other register. The fact that we've made it to the rewrite loop
implies that the whole register will be coalesced, so it doesn't seem
right not to update something that uses it depending on whether mov[i]
is NULL or not. Fixes an amount of texturing and image_load_store
piglit tests on my SIMD-lowering branch.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit d0a42b457fb905ce2cc12bb05110ef63656221c9
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue Jul 28 11:25:59 2015 +0300
i965/fs: Detect multi-register MOVs correctly in register_coalesce.
register_coalesce() was considering the exec_size of the MOV
instruction alone to decide whether the register at offset+1 of the
source VGRF was being copied to inst->dst.reg_offset+1 of the
destination VGRF, which is only a valid assumption if the move has a
32-bit execution type. Use regs_read() instead to find out the number
of registers copied by the instruction.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 2294ba9565fbae49f1fc77ca171e9d6aafa34005
Author: Dave Airlie <airlied at redhat.com>
Date: Thu Jul 9 16:34:59 2015 +1000
radeon: add support for streams to the common streamout code. (v2)
This adds to the common radeon streamout code, support
for multiple streams.
It updates radeonsi/r600 to set the enabled mask up.
v2: update for changes in previous patch.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 3f0e7c28fe5252f0613b548efd1cbf8e4bc0eb9a
Author: Dave Airlie <airlied at redhat.com>
Date: Sun Jul 26 01:27:17 2015 +0100
radeon: move streamout buffer config to streamout enable function. (v2)
This will be used here later.
v2: update atom sizes
add check for old vs new enabled mask
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 19d88e3f9f621643ba0524ff37e9a33272353941
Author: Fabio Pedretti <fabio.ped at libero.it>
Date: Tue Jul 28 20:53:25 2015 +0200
docs: consolidate nvc0 status
commit cb1cfb710c5a30f2e9b9ea1bca9d7ae0f23bcdfc
Author: Marta Lofstedt <marta.lofstedt at intel.com>
Date: Thu Jul 23 16:38:38 2015 +0200
mesa/es3.1: enable GL_ARB_explicit_uniform_location for GLES 3.1
Signed-off-by: Marta Lofstedt <marta.lofstedt at intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit 49db765debf9d1a810810935fafc3eef229e1511
Author: Marta Lofstedt <marta.lofstedt at intel.com>
Date: Wed Jul 29 10:10:40 2015 +0300
mesa/es3.1: enable GL_ARB_compute_shader for GLES 3.1
Signed-off-by: Marta Lofstedt <marta.lofstedt at intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit 49021e5058130db299ac6843e34c5f5c53e565ad
Author: Marta Lofstedt <marta.lofstedt at intel.com>
Date: Mon Jul 27 15:22:51 2015 +0200
mesa/es3.1: enable GL_ARB_texture_gather for GLES 3.1
Signed-off-by: Marta Lofstedt <marta.lofstedt at intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit c561b2faa80d07eedfe201ffdbb3f7746e33a049
Author: Marta Lofstedt <marta.lofstedt at intel.com>
Date: Mon Jul 27 15:22:50 2015 +0200
mesa/es3.1: enable GL_ARB_texture_multisample for GLES 3.1
Signed-off-by: Marta Lofstedt <marta.lofstedt at intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit cd14fcbca0a1dcecfdbee97a3524123ba87f901d
Author: Marta Lofstedt <marta.lofstedt at intel.com>
Date: Thu Jul 23 16:38:34 2015 +0200
mesa/es3.1: enable GL_ARB_shader_atomic_counters for GLES 3.1
Signed-off-by: Marta Lofstedt <marta.lofstedt at intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit 9ec50dc6bb192818dde221e561fb6be6c4bd417b
Author: Marta Lofstedt <marta.lofstedt at intel.com>
Date: Mon Jul 27 15:22:49 2015 +0200
mesa/es3.1: enable GL_ARB_shader_image_load_store for GLES 3.1
Signed-off-by: Marta Lofstedt <marta.lofstedt at intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit d1bb3b4910e6c02344550b8982aa8442cd7efd29
Author: Marta Lofstedt <marta.lofstedt at intel.com>
Date: Thu Jul 23 16:38:32 2015 +0200
mesa/es3.1: Add ES 3.1 handling to get.c and get_hash_generator.py
Signed-off-by: Marta Lofstedt <marta.lofstedt at linux.intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit c00d093c8f247c41f9122143c49ffa93865a0ded
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Tue Feb 10 16:40:40 2015 +0100
mesa: Return INVALID_ENUM in glClearBufferiv() when buffer is not color or stencil
Page 497 of the PDF, section '17.4.3.1 Clearing Individual Buffers' of the
OpenGL 4.5 spec states:
"An INVALID_ENUM error is generated by ClearBufferiv and
ClearNamedFramebufferiv if buffer is not COLOR or STENCIL."
Fixes 1 dEQP test:
* dEQP-GLES3.functional.negative_api.buffer.clear_bufferiv
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 055e3a3f87d8be5374902d2ae6fecb0eb5c66714
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Jul 28 18:45:32 2015 -0700
i965: Use real stage in "Unsupported form of variable indexing" warning.
Other stages can be miserably slow too!
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit e235ca159f5f6de2bd29616fdda5c02dc69b0d7f
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Jul 22 20:08:23 2015 -0700
glsl: Fix a bug where LHS swizzles of swizzles were too small.
A simple shader such as
vec4 color;
color.xy.x = 1.0;
would cause ir_assignment::set_lhs() to generate bogus IR:
(swiz xy (swiz x (constant float (1.0))))
We were setting the number of components of each new RHS swizzle based
on the highest channel used in the LHS swizzle. So, .xy.y would
generate (swiz xy (swiz xx ...)), while .xy.x would break.
Our existing Piglit test happened to use .xzy.z, which worked, since
'z' is the third component, resulting in an xxx swizzle.
This patch sets the number of swizzle components based on the size of
the LHS swizzle's inner value, so we always have the correct number
at each step.
Fixes new Piglit tests glsl-vs-swizzle-swizzle-lhs-[23].
Fixes ir_validate assertions in in Metro 2033 Redux.
v2: Move num_components updating completely out of update_rhs_swizzle
(suggested by Timothy Arceri). Simplify.
Cc: mesa-stable at lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
commit e17056f5a20beb752a530180fce1aba0e68877b6
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Fri Jul 3 10:19:23 2015 +0300
glsl: verify location when dual source blending
Same check is made for glBindFragDataLocationIndexed but it was missing
when using layout qualifiers.
Fixes following Piglit test:
arb_blend_func_extended-output-location
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
commit b868971e786b849e70675852a0043538bcce0739
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Mon Jul 27 13:29:20 2015 +0300
glsl: move max_index calc to assign_attribute_or_color_locations
Change function to get all gl_constants for inspection, this is used
by follow-up patch.
v2: rebase, update function documentation
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
commit 2e04492a142102823dfb8fc8599cfd417b84c97a
Author: Eric Anholt <eric at anholt.net>
Date: Tue Jul 28 11:00:58 2015 -0700
vc4: Skip re-emitting the shader_rec if it's unchanged.
It's a bunch of work for us to emit it (and its uniforms), more work for
the kernel to validate it, and additional work for the CLE to read
it. Improves es2gears framerate by about 50%.
Signed-off-by: Eric Anholt <eric at anholt.net>
commit aefec4fa226d06e4b414170739be18dd24d3eed7
Author: Eric Anholt <eric at anholt.net>
Date: Tue Jul 28 19:59:45 2015 -0700
vc4: Drop unused vpm_offset value.
It's been dead since we started doing VS/CS attr offset setup during
shader compile.
commit 1f5e070dd7ddd344a913f2f5daddebb4c51abb8a
Author: Eric Anholt <eric at anholt.net>
Date: Tue Jul 28 10:20:10 2015 -0700
vc4: Simplify vc4_use_bo and make sure it's not a shader.
Since the conversion to keeping validated shaders around for the BO's
lifetime, we haven't been checking that rendering doesn't happen to
shaders. Make vc4_use_bo check that always, and just don't use it for the
VC4_MODE_SHADER case (so now modes are unused)
commit 044f7bbda077ea7029fb1004183b29127307bd84
Author: Eric Anholt <eric at anholt.net>
Date: Tue Jul 28 10:11:08 2015 -0700
vc4: Keep the validated shader around for the simulator execution.
This more closely matches the kernel behavior on shader validation now.
commit 22954db71cd1d8d9ef6e5a16f568e4b3c7845777
Author: Eric Anholt <eric at anholt.net>
Date: Tue Jul 28 09:51:37 2015 -0700
vc4: Make the object be the return value from vc4_use_bo().
Drops 40 bytes of code from validation.
commit cbb7477e8a796211b664ff7e47334cb1b642556d
Author: Eric Anholt <eric at anholt.net>
Date: Tue Jul 28 00:29:31 2015 -0700
vc4: Ensure that the bin CL is properly capped by increment/flush.
We don't want anything to appear after we've kicked off the render (and
thus job flush), since that might then get written out to the tile
allocation state.
Signed-off-by: Eric Anholt <eric at anholt.net>
commit 601733da6708722ceedd35afc7727c28779012f7
Author: Eric Anholt <eric at anholt.net>
Date: Tue Jul 28 00:05:33 2015 -0700
vc4: Drop NV shader reloc validation.
It wasn't validating enough, and we don't need the packet.
commit 95faf2c6397ce231e94176d18cf8fd2c3265bb8a
Author: Eric Anholt <eric at anholt.net>
Date: Mon Jul 27 23:23:57 2015 -0700
vc4: Fix raster surface shadow updates under DRI2.
Glamor asks GBM for the handle of the BO, then flinks it itself. We
were marking the bo non-private in the flink and dmabuf (DRI3) paths,
but not the GEM handle path. As a result, non-pageflipping DRI2
swapbuffers (EGL apps, in particular) were never updating the texture.
commit b0193adbe9403545b0d9f7c7f24a1c30f1491a48
Author: Eric Anholt <eric at anholt.net>
Date: Mon Jul 27 23:15:39 2015 -0700
vc4: Fix bus errors on dumping CL on hardware.
The kernel can't fixup unaligned float traps for us, so deref as a
uint32_t first.
commit 736c6f3cfc2c69e3c29268d4ebb7110dd36ac97f
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Jul 23 17:26:56 2015 -0700
meta/copy_image: Stash off the scissor
The meta CopyImageSubData path uses BlitFramebuffers to do the actual copy.
The only thing that can affect BlitFramebuffers other than the currently
bound framebuffers is the scissor so we need to save that off and reset it.
If we don't do this, applications that use a scissor together with
CopyImageSubData will get accidentally scissored copies.
Tested-by: Markus Wick <markus at selfnet.de>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit bf4019a1c89755af94218055e86544f7823dc4ac
Author: Dave Airlie <airlied at redhat.com>
Date: Thu Jul 9 16:33:59 2015 +1000
radeon: add streamout status 1-3 queries.
This adds support for queries against the non-0 vertex streams.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 5142564734bd68f165b02e29e384ebbcf91cce38
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Jul 28 20:41:16 2015 +0200
st/mesa: remove st_context::missing textures and get_passthrough_fs
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 72f31c63d7b73abcdf47bc303d09987f299aff7a
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jul 25 17:26:10 2015 +0200
st/mesa: remove st_finalize_textures atom
It only checks fragment textures and ignores other shaders, which makes it
incomplete, and textures are already finalized in update_single_texture.
There are no piglit regressions.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 6ca3ff982a9e6a54286158b457d479715be5ab17
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jul 25 20:25:18 2015 +0200
st/mesa: add shader dumping for shader-db
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 768b4a25b95b95989dae3ff2f5a06172a2f4ab85
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Jul 23 21:57:19 2015 +0200
st/mesa: fix GLSL 1.30 texture shadow functions with the GL_ALPHA depth mode (v2)
Fixes piglit:
spec at glsl-1.30@execution at fs-texture-sampler2dshadow-10
spec at glsl-1.30@execution at fs-texture-sampler2dshadow-11
v2: use st_shader_stage_to_ptarget
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 82546729e3533c9a5ec0392585a60833bd93acca
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date: Mon Jul 27 11:01:47 2015 +1000
r600,radeonsi: GL_ARB_conditional_render_inverted
By using 'Tobias Klausmann' piglit test-suite patch. We obtain
a full 12/12 passes using this patch. By 'faking' to claim
support for this extension we obtain 7 fails and 5 passes.
Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Tested-by: Furkan Alaca <falaca at gmail.com>
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit aa25a2c1ba2ea14efdab405707f15dace323cd48
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Jul 17 04:44:18 2015 +0100
radeonsi: add support for interpolateAt functions (v2)
This is part of ARB_gpu_shader5, and this passes
all the piglit tests currently available.
v2: use macros from the fine derivs commit.
add comments.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 56f1f47eda881d6281e9c7531bc17e72b25d9bb9
Author: Chad Versace <chad.versace at intel.com>
Date: Tue Jun 23 15:48:40 2015 -0700
i965: Support importing R8 and GR88 dma_bufs
EGL_EXT_image_dma_buf_import now supports those formats.
Tests:
- Tested by Piglit ext_image_dma_buf_import-transcode-nv12-as-r8-gr88.
- Tested by Peter in Kodi/XBMC to obtain 60fps NV12 transcode at 4K.
Tested-by: Peter Frühberger <peter.fruehberger at gmail.com>
Signed-off-by: Chad Versace <chad.versace at intel.com>
commit fd865d56d2229d8c5d7ea893ac1dba525d88e647
Author: Chad Versace <chad.versace at intel.com>
Date: Tue Jun 23 15:48:17 2015 -0700
egl: Add support for DRM_FORMAT_R8, RG88, and GR88
The Kodi/XBMC developers want to transcode NV12 to RGB with OpenGL shaders,
importing the two source planes through EGL_EXT_image_dma_buf_import. That
requires importing the Y plane as an R8 EGLImage and the UV plane as either an
RG88 or GR88 EGLImage.
This patch teaches the driver-independent part of EGL about the new
formats. Real driver support is left for follow-up patches.
The new formats landed in airlied's kernel branch 'drm-next' on July 24.
Tested-by: Peter Frühberger <peter.fruehberger at gmail.com>
Signed-off-by: Chad Versace <chad.versace at intel.com>
commit 313940b03cf7c857143b9e3ec0ab969ce4472c83
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Tue Jul 28 02:37:51 2015 -0400
nvc0/ir: trim out barrier sync for non-compute shaders
It seems like they're never necessary, and actively cause harm. This
fixes some of the barrier-related piglits.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit ab63610a3603ae1e40a36d238b5938621bb9e8cc
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Tue Jul 28 02:00:20 2015 -0400
nvc0/ir: fix barrier emission
immediate arguments require a flag to be set for each one
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 7850774f2118ae87c7e6a4f6c17751e405edfb34
Author: Eric Anholt <eric at anholt.net>
Date: Wed Jul 22 12:14:40 2015 -0700
vc4: Add support for ARB_draw_elements_base_vertex.
Gallium exposes it unconditionally, so do our best to support it. It
fails on the negative index cases, but those seem unlikely to be used in
the wild.
commit 98a4b111fbb9e3ae45e907ddd4d2407e5ab669ec
Author: Rob Clark <robclark at freedesktop.org>
Date: Sat Jul 25 12:53:23 2015 -0400
freedreno/ir3: add transform-feedback support
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 96d4db683f90f02e72d34ece544de7eedfa873ee
Author: Rob Clark <robclark at freedesktop.org>
Date: Sat Jul 25 13:51:16 2015 -0400
freedreno/ir3: track "keeps" in ir
Previously we had a fixed array to track kills, since they don't
generate an SSA value, and then cheated by stuffing them in the
outputs array before sending things through depth/sched/etc. But
store instructions will need similar treatment. So convert this
over to a more general array of instructions that must be kept
and fix up the places that were previously relying on kills being
in the output array.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 020301baccc77e5753ead1e890c0cf24a9675517
Author: Rob Clark <robclark at freedesktop.org>
Date: Sat Jul 25 13:48:07 2015 -0400
freedreno/ir3: add support for store instructions
For store instructions, the "dst" register is a read register, not a
written register. (Ie. it is the address to store to.) Lets not
confuse register allocation, scheduling, etc, with these details.
Instead just leave a dummy instr->regs[0], and take "dst" from
instr->regs[1] and srcs following.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit a240748de52f2e469e91b60d29ae872828a594d7
Author: Rob Clark <robclark at freedesktop.org>
Date: Sat Jul 25 12:48:18 2015 -0400
freedreno/ir3: cleanup driver-param stuff
Add 'enum ir3_driver_param' to track driver-param slots, and a
create_driver_param() helper to avoid having the knowledge about
where driver params are placed in const regs spread throughout
the code as we add additional driver-params.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit be8a8ebe578267ab24e343c3c1347936a221468e
Author: Rob Clark <robclark at freedesktop.org>
Date: Sat Jul 25 10:56:39 2015 -0400
freedreno: add transform-feedback state
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit bda1354aac9d32e236048af4d353d5530f644c34
Author: Rob Clark <robclark at freedesktop.org>
Date: Sun Jul 26 13:30:26 2015 -0400
freedreno: add resource tracking support for written buffers
With stream-out (transform-feedback) we have the case where resources
are *written* by the gpu, which needs basically the same tracking to
figure out when rendering must be flushed.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 65d36a109a7dd333c15180a0f30ad919eb01d78f
Author: Rob Clark <robclark at freedesktop.org>
Date: Fri Jul 24 17:07:23 2015 -0400
freedreno/a3xx+a4xx: add support for vtxcnt semantic
This will be used for stream-out (transform-feedback)
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 1b1ef6b4573ab9f21abd5fb374bc74d03390146d
Author: Rob Clark <robclark at freedesktop.org>
Date: Fri Jul 24 17:06:01 2015 -0400
freedreno/ir3: add stream-output support to cmdline compiler
A bit hard-coded configuration at the moment, but sufficient for now.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 810763deb514c3fec41c3e95761de34e6211d291
Author: Rob Clark <robclark at freedesktop.org>
Date: Fri Jul 24 16:42:10 2015 -0400
freedreno/ir3: drop unused create_input() arg
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 56462a30080c1f25a81ae566d59a25d2ad6bb809
Author: Rob Clark <robclark at freedesktop.org>
Date: Fri Jul 24 13:07:33 2015 -0400
freedreno/ir3: move emit_const to ir3
Details of the cmdstream packets are different between a3xx and a4xx,
but the logic about the layout of const registers is the same, as that
is dictated by the ir3 shader compiler. So rather than duplicating
logic that is tightly coupled to ir3 between a3xx and a4xx, move this
into ir3 and use per-generation callbacks for to build the cmdstream
packets.
This should make it easier to pass additional const regs (such as for
transform feedback). And it also keeps the layout internal to ir3 in
case we want to make the layout more dynamic some day.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 0815729d964f4e8e6e263acf70b5b91577de027a
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Jul 23 15:51:13 2015 -0400
freedreno/ir3: bit of shader API refactoring
Since for transform-feedback, we'll need more than just the TGSI
tokens from the state object, just pass the entire state object to
ir3_shader_create(). This also cleans things up a bit for some
day in the future when we could take shader either as TGSI or
directly NIR (for ex, glsl2nir or spirv2nir paths). In the same
spirit, drop extra args from ir3_compile_shader_nir() (since it
can anyways get what it needs from the ir3_shader_variant).
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit bc5e2bec303acd7fd962996bf369be5ce0e15cd2
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Jul 23 15:31:13 2015 -0400
freedreno/ir3: updated cat6 encoding
Sync updated cat6 encoding from freedreno.git, needed to properly encode
store instructions.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 4b15cb6daa29d4bdd268eac6c2e40fb1503e98fa
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Jul 25 01:06:20 2015 -0400
glsl: enable conservative depth, ssbo based on GLSL version
Add in missed version checks in the GLSL parser
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit d69da58e84448188808488ad1c1c0181b5630a74
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sun Jul 26 15:20:31 2015 +0100
docs: add news item and link release notes for mesa 10.6.3
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 11516b8bd1af2709b74a135787b43de55fe6238e
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sun Jul 26 15:18:24 2015 +0100
docs: Add checksums for mesa 10.6.3 tarballs
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit ccef8901de421eae5dcc8affa14218d46cc06593)
commit e1dcd158785606d4e7e9ca5513732b7e6e7b93d9
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sun Jul 26 14:38:58 2015 +0100
Add release notes for 10.6.3
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit ddc976368fef367e464472ebcc2ac4fd89eb9fd8)
commit bb9d59aed5b01133f4c8e9f131a83b45fce91fdc
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Jul 17 05:35:30 2015 +0100
radeonsi: add fine derivate control (v2.1)
This adds support for fine derivatives and enables
ARB_derivative_control on radeonsi.
(just fell out of my working out interpolation)
v2: cleanup some bits, write a comment
v2.1: take Michel's comment from the mailing list
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 9deb614cacbeca3e99724f08254ab1789f34b56c
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Jul 24 00:54:08 2015 +0200
radeonsi: fix GLSL textureGrad(samplerCube*) functions
+4 piglits
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit e39ece0d7856d0532a0f011cd5cb17bc85ee82e2
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Jul 24 19:47:06 2015 +0200
st/mesa: don't ignore texture buffer state changes
Fixes piglit:
spec at arb_texture_buffer_range@ranges-2
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Brian Paul <brianp at vmware.com>
commit a818faa6ddcfa6cd90a24b70c49ec76573954111
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Jul 11 12:47:03 2015 -0400
nvc0: fix geometry program revalidation of clipping params
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Cc: mesa-stable at lists.freedesktop.org
commit 7b40d92f0d0661c05c1afa59555905b2c37e594f
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Jul 13 09:12:18 2015 +0100
radeonsi: ubo indexing support (v2)
This is required as part of ARB_gpu_shader5.
no backend changes are required for this, or if
any are, it's the same ones as for samplers.
v2: use get_indirect_index (Marek)
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit b0654e368b1741083055efd281b981db4fb5724b
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Jul 13 00:07:09 2015 +0100
radeonsi: add support for indirect samplers (v2)
This adds the frontend support, however the llvm
backend produces the wrong pattern, however
we can conditionalise enabling ARB_gpu_shader5
on whatever version of llvm we fix this in.
v2: drop unneeded sampler_indirect checks (Marek)
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 4b6c1efb225777231459de54903484367d0b1ca1
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Jul 17 04:43:09 2015 +0100
radeonsi: split out interpolation input selection
This is prep work for using it in the interpolation code
later.
Also add storage for the input interpolation mode so we
can pick it up later.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 730e8c4410d73bf9db2c1768af8cf6e98e24cc73
Author: Dave Airlie <airlied at redhat.com>
Date: Thu Jul 16 04:38:41 2015 +0100
radeonsi: separate out load sample position
This is prep work for reusing this in the interpolation
code later.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit b42444ffed87114e82522dd81d3e5540c21a128c
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Jul 24 17:06:22 2015 -0400
glsl: recognize ARB_shading_language_420pack to be enabled with 4.20+
The 420pack extension enables various GLSL rules that need to be applied
to any GLSL 4.20+ shader even if the extension is not explicitly
enabled.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit f8059c9f3fdd270370737c9eff369eb6d14caa0b
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Jul 23 20:18:57 2015 -0400
mesa: fix error checking for getting zero-sized texture images
Commit 17f714836 (mesa: rearrange texture error checking order) moved
the width/height/depth == 0 allowance before checking if the image was
there. This was in part due to depth having to be == 1 for 2D images and
width having to be == 1 for 1D images. Instead relax the height/depth
checks to also accept 0 as valid.
With this change,
bin/arb_direct_state_access-get-textures
starts passing again.
Fixes: 17f714836 (mesa: rearrange texture error checking order)
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 56980f107ef64d0a5bfc5d292cc891661e47d0f0
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Fri Jun 26 15:39:40 2015 -0700
mesa: Fix typo in a comment
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
commit a9cbb2c722615e11818066cbe33006c5cfc43381
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Fri Jun 12 14:58:46 2015 -0700
meta: Use _mesa_need_rgb_to_luminance_conversion() in decompress_texture_image()
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 4b8745680ff45cd7adc7896c06263e14b8d347ce
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Fri Jun 12 14:42:57 2015 -0700
mesa: Change the signature of _mesa_need_rgb_to_luminance_conversion()
This allows us to handle cases when texImage->_BaseFormat doesn't match
_mesa_format_get_base_format(texImage->Format). _BaseFormat is what we
care about in this function.
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit aa40546b2de4cd572af02d31fd5c7d4045505ea2
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Tue May 12 05:46:04 2015 -0700
meta: Fix reading luminance texture as rgba in _mesa_meta_pbo_GetTexSubImage()
After recent addition of pbo testing in piglit test getteximage-luminance,
it fails on i965. This patch makes a sub test pass.
This patch adds a clear color operation to meta pbo path, which I think is
better than falling back to software path.
V2: Fix color mask for GL_LUMINANCE_ALPHA
Cc: <mesa-stable at lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit be405ee334ec758a2609d8780221f4f1a1ed3343
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Thu Jun 11 17:23:34 2015 -0700
meta: Use _mesa_need_luminance_to_rgb_conversion() in decompress_texture_image()
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit c59c0f8a42652603da7f89e3270897cb685fe76b
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Thu Jun 11 16:48:26 2015 -0700
mesa: Add a helper function _mesa_need_luminance_to_rgb_conversion()
Cc: <mesa-stable at lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 9fff00d387cacf7820c344324820cab764541762
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Fri Jun 12 12:11:01 2015 -0700
meta: Use _mesa_unpack_format_to_base_format() to handle integer formats
Replace a call to mesa_base_tex_format() that handles only internal
formats with a call to the new _mesa_unpack_format_to_base_format()
function that handles allowed unpack formats and does not care for
internal formats at all.
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 0127580647ee23d543228f0b7f42bd688e76f2bd
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Fri Jun 12 12:09:05 2015 -0700
mesa: Add a helper function _mesa_unpack_format_to_base_format()
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit bbbefec7323d0a338346233ab4ab715bcf4e1b78
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Thu Jun 11 16:44:45 2015 -0700
mesa: Set green, blue channels to zero only for formats with these components
This is an optimization which avoids setting pixel transfer operations
when not required. _mesa_ReadPixels falls back to slower path if
transfer operations are set.
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit ca4e17e03e9aeaa04fe6bb04bfe2d6f97991005b
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Wed May 6 05:43:08 2015 -0700
meta: Don't do fragment color clamping in _mesa_meta_pbo_GetTexSubImage
_mesa_meta_pbo_GetTexSubImage() uses _mesa_meta_BlitFrameBuffer(),
which will do fragment clamping if enabled. But fragment clamping
doesn't affect ReadPixels and GetTexImage.
Without this patch, piglit test arb_color_buffer_float-clear fails,
when forced to use the meta pbo path.
v2: Apply this fix to both glReadPixels and glGetTexImage.
Cc: <mesa-stable at lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 0d207905e675b778739236072e7a4dfba7cd7959
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Wed May 20 10:22:45 2015 -0700
meta: Abort meta pbo path if readpixels need signed-unsigned conversion
Meta pbo path for ReadPixels rely on BlitFramebuffer which doesn't support
signed to unsigned integer conversions and vice versa.
Without this patch, piglit test fbo_integer_readpixels_sint_uint fails, when
forced to use the meta pbo path.
v2: Make need_signed_unsigned_int_conversion() a static function. (Iago)
Bump up the comment and the commit message. (Jason)
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Cc: <mesa-stable at lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Iago Toral <itoral at igalia.com>
commit 1252d53c19ec005c17ca666cecb7db072d77e5ce
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Wed May 20 10:21:39 2015 -0700
meta: Fix transfer operations check in meta pbo path for readpixels
Currently used ctx->_ImageTransferState check is not sufficient
because it doesn't include the read color clamping enabled with
GL_CLAMP_READ_COLOR. So, use the helper function
_mesa_get_readpixels_transfer_ops().
Also, transfer operations don't affect glGetTexImage(). So, do
the check only for glReadPixles.
Without this patch, arb_color_buffer_float-readpixels test fails, when
forced to use meta pbo path.
V2: Add a comment and bump up the commit message.
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Cc: <mesa-stable at lists.freedesktop.org>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 7974e23be9ff7586e5250cff321b6ec7749ecc44
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Tue May 19 17:44:52 2015 -0700
mesa: Turn get_readpixels_transfer_ops() in to a global function
This utility function is utilized in a later patch.
Cc: <mesa-stable at lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 013d731a67538a2eb8f508fa54bb86191f0e5491
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Tue Jul 21 11:12:57 2015 +0100
i965: Use updated kernel interface for accurate TIMESTAMP reads
I was mistaken, I thought we already had fixed this in the kernel a
couple of years ago. We had not, and the broken read (the hardware
shifts the register output on 64bit kernels, but not on 32bit kernels) is
now enshrined into the ABI. I also had the buggy architecture reversed,
believing it to be 32bit that had the shifted results. On the basis of
those mistakes, I wrote
commit c8d3ebaffc0d7d915c1c19d54dba61fd1e57b338
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Wed Apr 29 13:32:38 2015 +0100
i965: Query whether we have kernel support for the TIMESTAMP register once
Now that we do have an extended register read interface for always
reporting the full 36bit TIMESTAMP (irrespective of whether the hardware
is buggy or not), make use of it and in the process fix my reversed
detection of the buggy reads for unpatched kernels.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Martin Peres <martin.peres at linux.intel.com>
Cc: Kenneth Graunke <kenneth at whitecape.org>
Cc: Michał Winiarski <michal.winiarski at intel.com>
Cc: Daniel Vetter <daniel at ffwll.ch>
Tested-and-acked-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Daniel Vetter <daniel at ffwll.ch>
commit 30f97b5e52b324d501c56df8902d294fb755a5b7
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Thu Jul 23 10:38:36 2015 +0200
glsl/glcpp: fix SIGSEGV when checking error condition for macro redefinition
Commit a6e9cd14c does not take into account than node_{a,b}->next could be NULL
in some circumstances, such as in a shader containing this code:
#define A 1 /* comment */
#define A 1 /* comment */
This patch fixes the segmentation fault for cases like that.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91290
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Cc: mesa-stable at lists.freedesktop.org
commit 24a7d4e437e27c758c2848e887ceaf1d4a55ae50
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Jul 24 00:21:28 2015 -0400
nvc0/ir: per-patch vars are in a separate address space
There's no need to attempt to avoid overlapping generic i/o with patch
i/o. By the same token, we can't merge patch and non-patch loads/stores.
This fixes at least the
tes-both-input-array-*-index-rd
tessellation variable-indexing tests.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 9d60793a03e40e1d139b78fce0144cad57438741
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Jul 23 23:03:53 2015 -0400
nvc0/ir: kepler can't do indirect shader input/output loads directly
There's a special AL2P instruction (called AFETCH in nv50 ir) which
computes a "physical" value to be used with indirect addressing with ALD.
Fixes
tcs-input-array-*-index-rd
tcs-output-array-*-index-wr
varying-indexing tessellation tests on Kepler.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 22c9339abf00c2ecf40e0d8fd740faafba3ec37b
Author: Vinson Lee <vlee at freedesktop.org>
Date: Tue Jul 21 21:50:29 2015 -0700
radeon: Silence GCC unused-but-set-variable warnings.
radeon_fbo.c: In function 'radeon_map_renderbuffer_s8z24':
radeon_fbo.c:162:9: warning: variable 'ret' set but not used [-Wunused-but-set-variable]
int ret;
^
radeon_fbo.c: In function 'radeon_map_renderbuffer_z16':
radeon_fbo.c:200:9: warning: variable 'ret' set but not used [-Wunused-but-set-variable]
int ret;
^
radeon_fbo.c: In function 'radeon_map_renderbuffer':
radeon_fbo.c:242:8: warning: variable 'ret' set but not used [-Wunused-but-set-variable]
int ret;
^
radeon_fbo.c: In function 'radeon_unmap_renderbuffer':
radeon_fbo.c:419:14: warning: variable 'ok' set but not used [-Wunused-but-set-variable]
GLboolean ok;
^
Signed-off-by: Vinson Lee <vlee at freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 00fb21e744b045cc9f945021305b85595c35dd69
Author: Rhys Kidd <rhyskidd at gmail.com>
Date: Wed Jul 22 22:14:00 2015 -0600
doxygen: Link GLvector4f struct members properly, avoiding invalid XML/HTML warning
Signed-off-by: Rhys Kidd <rhyskidd at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit bc893e3dad74622b971e295f60a022f179ca9942
Author: Rhys Kidd <rhyskidd at gmail.com>
Date: Wed Jul 22 22:14:00 2015 -0600
doxygen: Correct grammatical typo in math/m_vector.h
Signed-off-by: Rhys Kidd <rhyskidd at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 28db89fa8b3f59d35032c0576fbd0c74739b3c87
Author: Brian Paul <brianp at vmware.com>
Date: Thu Jul 23 10:04:13 2015 -0600
mesa: minor clean-ups in shaderapi.c
80-column wrapping. Move break statements. Indentation fixes.
commit dd86fbeaaa136c4ddfd255286f4975d869e799a0
Author: Brian Paul <brianp at vmware.com>
Date: Thu Jul 23 07:47:25 2015 -0600
mesa: fix _mesa_error() compiler warnings in shaderapi.c
Fix many instances of:
main/shaderapi.c: In function '_mesa_GetSubroutineUniformLocation':
main/shaderapi.c:2176:7: warning: format not a string literal and no format arguments [-Wformat-security]
_mesa_error(ctx, GL_INVALID_OPERATION, api_name);
^
Ideally, many of these error messages should be improved to indicate
which argument is incorrect as we do in other parts of Mesa.
Reviewed-by: Kai Wasserbäch <kai at dev.carbon-project.org>
Tested-by: Kai Wasserbäch <kai at dev.carbon-project.org>
commit 43b69aad195f5abfc2c8c75bfa2ff31e5b99fbab
Author: Brian Paul <brianp at vmware.com>
Date: Thu Jul 23 07:43:11 2015 -0600
st/mesa: remove unused 'samp' function parameters
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit d7cb3f76f5c175c95ffbbec40eea5976493f8681
Author: Brian Paul <brianp at vmware.com>
Date: Thu Jul 23 07:41:09 2015 -0600
st/mesa: add comments on a few sampler view functions
Trivial.
commit 3afa40e43368b29ca99018999936336c3879fa4d
Author: Brian Paul <brianp at vmware.com>
Date: Wed Jul 22 07:53:01 2015 -0600
mesa: do more thorough target checking in compressed_subtexture_target_check()
When we're error-checking the target, we also need to check if the
corresponding extension is supported.
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit 05a44ab32832efe61a252ef4ac2d128c1101c286
Author: Brian Paul <brianp at vmware.com>
Date: Wed Jul 22 07:42:12 2015 -0600
mesa: another target fix in compressed_subtexture_target_check()
The previous fix added GL_TEXTURE_CUBE_MAP_ARRAY but we also need
to support GL_TEXTURE_CUBE_MAP (via DSA).
So in the end, GL_TEXTURE_3D is the only (legal) target for
glCompressedTex*SubImage3D() which needs additional compression
format checking. GL_TEXTURE_2D_ARRAY, GL_TEXTURE_CUBE_MAP_ARRAY
and GL_TEXTURE_CUBE_MAP are basically 2D images which support all
compressed formats.
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit 81e2c256e921ad4f5c13bb0d95bbe0ad232ec37c
Author: Brian Paul <brianp at vmware.com>
Date: Wed Jul 22 07:32:36 2015 -0600
mesa: simplify format check in compressed_subtexture_target_check()
Lose the invalidformat local variable.
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit dbefffa5b4c438008d44db106b5774f575cb495f
Author: Brian Paul <brianp at vmware.com>
Date: Tue Jul 21 18:42:41 2015 -0600
mesa: initialize variables to silence compiler warnings
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 319b83b3ee2629f443a8734256bbf33b3fb4a7a9
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Jul 24 12:02:57 2015 +1000
apiexec: remove leading gl from shader subroutine interfaces
Remove the gl at the start, stared at this for a while
yesterday, totally missed it.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91441
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 0a51acbb467bce5afddc7edf53db426ac697ccf1
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Jul 23 16:57:25 2015 -0400
docs: remove expanded ARB_dsa notes
This doesn't provide much value since it's all done. The qbo interaction
is fairly trivial.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit 7e0036a49258326cc2d875f2960d18c6b3665036
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Jul 23 21:41:38 2015 -0400
nvc0/ir: tess factors are now sysvals, adapt codegen to expect that
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 7c4768540dacab8a4853f1310413cb976b5fb351
Author: Dave Airlie <airlied at redhat.com>
Date: Thu Jul 23 11:19:15 2015 +1000
docs/GL3.txt: ARB_shader_precision
This extension is about setting expectation on GL4.1 implementations
rather than actually enforcing things. So once you support GLSL 410
then you support this in theory.
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 80511d176a49e754a18ce585bab413db7af63bf7
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Jul 21 14:22:11 2015 +1000
i965: add support for ARB_shader_subroutine
This just adds some missing pieces to nir/i965,
it is lightly tested on my Haswell.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 17f71483698a4e134a0c85ef0aa3da80fdfdb180
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Jul 22 12:59:46 2015 -0400
mesa: rearrange texture error checking order
This moves the width/height/depth == 0 check to the front and avoids
doing any other checking when that is the case.
Also moves the dimensions check after the format/type checks so that we
don't bail out with success on a width/height/depth == 0 request when
the format/type don't match.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91425
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit c844afe94eaecc66e00cc4869f700ac1236bdc89
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Jul 22 12:39:47 2015 -0400
mesa: adjust error message when there's a missing teximage
The current message makes it seem like the zoffset is invalid.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit a6f39ec1c568c38e7ef42d60eaf6c9ab8397af2a
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Jul 23 21:51:48 2015 +0200
Revert "Match swrast modes more loosely."
This reverts commit f3728a16c9c6a02fc1f44b8069b0060e2358f22e.
It broke glxgears on radeonsi. The window was just black.
commit d6b50ba980b733a82fefe2a0f115635a359c445f
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Thu Jul 23 16:54:02 2015 +0100
gallivm: Fix profile build.
commit c6267ebd6c8a73d51a0c82d0f516177c70e05c81
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Wed Jul 22 13:21:24 2015 +0100
gallium/util: Stop bundling our snprintf implementation.
Use MSVCRT functions instead. Their semantics are slightly
different but they can be made to work as expected.
Also, use the same code paths for both MSVCRT and MinGW.
https://bugs.freedesktop.org/show_bug.cgi?id=91418
Reviewed-by: Brian Paul <brianp at vmware.com>
commit f3728a16c9c6a02fc1f44b8069b0060e2358f22e
Author: Tom Hughes <tom at compton.nu>
Date: Tue Jun 2 13:40:37 2015 +0100
Match swrast modes more loosely.
https://bugs.freedesktop.org/show_bug.cgi?id=90817
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit b469cf10efd4734038dcab294f23ca38e9fc7a97
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Thu Jul 23 16:25:21 2015 +0200
mesa: Fix error in target validation of glCompressedTex(ture)SubImage3D() calls
Basically, two different target error checks are chained consecutively, and the
second one is executed regardless the result of the first one. This produces an
incorrect error if the first check fails but is overrided by the second.
This patch conditions the execution of the second check to a successful pass of
the first one.
Fixes 1 dEQP test:
* dEQP-GLES3.functional.negative_api.texture.compressedtexsubimage3d
Reviewed-by: Laura Ekstrand <laura at jlekstrand.net>
commit a3b53beaa0351cf1322c6e1a580dc7cc3d0cad0c
Author: Tom Stellard <thomas.stellard at amd.com>
Date: Mon Jul 20 11:24:13 2015 -0400
gallivm: Add ifdefs so raw_debug_stream is only defined when used
Its only use is to implement a custom version of LLVMDumpValue
on some Windows and embedded platforms.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 9f7a68feafc86a51a7c5165672b29cb7182da738
Author: Tom Stellard <thomas.stellard at amd.com>
Date: Mon Jul 20 06:49:05 2015 -0700
gallivm: Don't use raw_debug_ostream for dissasembling
All LLVM API calls that require an ostream object have been removed from
the disassemble() function, so we don't need to use this class to wrap
_debug_printf() we can just call this function directly.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 6d8e466792c284e79125bab33fcfb0872d0df2c3
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Jul 23 03:39:13 2015 -0400
docs: mark off tess for nvc0
commit 88818c4cd6de9d8855a9ba3c3a85306d42f5e9d3
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Jul 22 20:34:30 2015 -0400
gk110/ir: fake BAR support
Makes things sorta work until we figure out the real way to do this.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit fd092328e1e05fe4a3fc82a2e79bdba884bc798d
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun May 17 00:45:12 2015 -0400
nvc0/ir: cleanup private enums that have graduated to gallium
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit da89e75d9c6399c8fb0286460c91a77778c0eec9
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Apr 30 02:00:20 2015 -0400
nvc0/ir: allow tess eval output loads to be CSE'd
These only happen for gl_TessCoord which are constant.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 77672cdb64e9c19e974fe5985050709fc317498e
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Jul 23 02:27:04 2015 -0400
nvc0/ir: add hazard for 2nd dim of vfetch/load indirect argument
Apparently a multi-word load can potentially overwrite the indirect
sources, so make sure that RA picks different registers for those.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 7cf2bffe8254de6808202d866598ec4c9afe1a51
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Feb 21 03:12:54 2015 -0500
nvc0/ir: patch vertex count is stored in the upper bits
commit e3e2df01bf855f3b435e03224a762649081c6558
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Jul 20 16:23:16 2014 -0400
nvc0/ir: add support for reading outputs in tess control shaders
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 71744c069264d32e6eb9d095350300b42633a1f8
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Jul 20 13:36:37 2014 -0400
nvc0/ir: set perPatch flag on load/stores to per-patch varyings
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit c2350fb3dbb1b8d348125e22758da266c15bc198
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Jul 20 13:12:38 2014 -0400
nvc0/ir: populate info structure based on new tess properties
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 59438a4d0e8ffd7cc4c741d00eff0c87d9813b5f
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Jul 20 12:17:46 2014 -0400
nvc0/ir: mark varyings as per-patch based on semantic name
Also add proper handling for PATCH semantics
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 4b2a58a523715c28c96267286054baf511e15303
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Jul 12 22:08:44 2014 -0400
nvc0: TESSCOORD comes in as a sysval, not an input
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit c8e5337a9a240befcc953695c8822b0749c7a042
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Jul 20 15:50:43 2014 -0400
nvc0: add handling for set_tess_state callback
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit d1ffdebce6d03497fa6c2e4c8eb754e9075e29f4
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun May 17 00:40:20 2015 -0400
nvc0: add support for setting patch vertices at draw time
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit b9ea557fd04da9eb199388c14d64862d18118de3
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Jun 21 13:35:53 2015 -0400
nvc0: support MAX_SHADER_PATCH_VARYINGS
commit f97c14f9e4ff5ae2b7313eb0098f99816fead71d
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Jul 12 15:40:14 2014 -0400
nvc0: preliminary tess support
Uncomment the various functionality that was already there and add in
obvious missing bits that parallel vp/gp/fp functionality.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 65d84daf29adb0da779e9b49291cb4e26f021e1e
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Jul 22 11:04:52 2015 +1000
docs/GL3.txt: update ARB_shader_subroutine status.
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit c3fad009c54fb526d236fd10f4377ce7fbb54459
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Apr 20 10:30:53 2015 +1000
st/mesa: enable shader subroutine
since this touches drivers, only enable it on gallium
for now for drivers reporting GLSL 1.30 or above.
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit a922c279930ec1ab34506ca2e24d8a62a297ea33
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Apr 20 10:29:42 2015 +1000
st/mesa: add subroutine bits (v1.1)
Just add support for the subroutine type to the
glsl->tgsi convertor.
v1.1: add subroutine to int support.
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 6f57fda494a6b4ccf30cab000ca28154fbabcb78
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Apr 20 10:29:12 2015 +1000
mesa: fill out the ARB_shader_subroutine APIs
This fleshes out the APIs, using the program resource
APIs where they should match.
It also sets the default values to valid subroutines.
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 3f4f3e2d4877e1e2bda064cc323fb7b3667e12fe
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Apr 20 10:28:40 2015 +1000
program: add subroutine uniform support (v1.1)
Add support for the subroutine uniform type ir->mesa.cpp
v1.1: add subroutine to int to switch
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 0a18f160159b93c57943e5cb4d9d9a78a5b72996
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Apr 20 10:27:58 2015 +1000
program_resource: add subroutine support (v3.1)
This fleshes out the ARB_program_query support for the
APIs that ARB_shader_subroutine introduces, leaving
some TODOs for later addition.
v2: reworked for lots of the ARB_program_interface_query
entry points and tests
v3: use common function to test for subroutine support
v3.1: add tess, fix missing breaks
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 60266863d80bb2af94fa5c189ccd23ee20607ea9
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Apr 20 10:27:36 2015 +1000
glsl: add uniform and program resource support (v2)
This adds linker support for subroutine uniforms, they
have some subtle differences from real uniforms, we also hide
them and they are given internal uniform names.
This also adds the subroutine locations and subroutine uniforms
to the program resource tracking for later use.
v1.1: drop is_subroutine_def
v2: handle explicit location properly, ARB_explicit_location
has a lot of language for subroutine shaders.
Calculate a link time the number of compatible subroutines
for a uniform, to make program resource easier later.
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 44ea8b9b8edc5f59da546683fe64129a1c1be449
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Jul 21 14:59:01 2015 +1000
mesa/mtypes: add gl_subroutine_function and uniform storage to shader (v2)
This adds the necessary storage for subroutine info to gl_shader.
v2: add comments, rename one member
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 7dd429e8f74302d44af00d051e59911439152369
Author: Dave Airlie <airlied at redhat.com>
Date: Thu Apr 23 13:34:14 2015 +1000
glsl/ir: add subroutine lowering pass (v2.3)
This lowers the enhanced ir_call using the lookaside table
of subroutines into an if ladder. This initially was done
at the AST level but it caused some ordering issues so a separate
pass was required.
v2: clone return value derefs.
v2.1: update for subroutine->int convert.
v2.2: add a clone for the array index
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 65ac360823ee12ac2d1f3bb6758d352fcd0d9210
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Jun 1 10:55:47 2015 +1000
glsl: add ast/parser support for subroutine parsing storage (v3.2)
This is the guts of the GLSL parser and AST support for
shader subroutines.
The code creates a subroutine type in the parser, and
uses that there to validate the identifiers. The parser
also distinguishes between subroutine types/function prototypes
/uniforms and subroutine defintions for functions.
Then in the AST conversion it recreates the types, and
stores the subroutine definition info or subroutine info
into the ir_function along with a side lookup table in
the parser state. It also converts subroutine calls into
the enhanced ir_call.
v2: move to handling method calls in
function handling not in field selection.
v3: merge Chris's previous parser patches in here, to
make it clearer what's changed in one place.
v3.1: add more documentation, drop unused include
v3.2: drop is_subroutine_def
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 884df9ef834d6b77226d0dfd778c5317365a2394
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Apr 24 10:47:03 2015 +1000
glsl/ir: allow ir_call to handle subroutine calling
This adds a ir_variable which contains the subroutine uniform
and an array rvalue for the deref of that uniform, these
are stored in the ir_call and lowered later.
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 30681c3bb80ad78392f1740aa915efa072c837e8
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Apr 20 10:22:57 2015 +1000
glsl/ir: add subroutine information storage to ir_function (v1.1)
We need to store two sets of info into the ir_function,
if this is a function definition with a subroutine list
(subroutine_def) or if it a subroutine prototype.
v1.1: add some more documentation.
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit d8a250ce5edc3da092ede6d62d433fbb37aa6cf6
Author: Dave Airlie <airlied at redhat.com>
Date: Thu Jul 23 10:23:36 2015 +1000
mesa: add function to check if shader subroutines are enabled.
This checks if core profile and shader subroutine extension
is enabled.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 670b9e56da588581c90d6c68f0a55ecd9153504d
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Apr 20 10:20:06 2015 +1000
mesa: add inline conversion functions for ARB_shader_subroutine (v2)
This handles converting the shader stages to the internal
prefix along with the program resource interfaces.
v2: add tess support
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit f73ef824869dbb1f91c32ad563c95ca917f40c12
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Jul 21 14:52:40 2015 +1000
glsl: don't eliminate subroutine types.
This stops dead code from removing subroutines types,
we need these for the queries to work properly.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 57f24299b7fe0f7b20c2a3cf1e94c747825b568d
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Apr 20 10:16:55 2015 +1000
glsl/types: add new subroutine type (v3.2)
This type will be used to store the name of subroutine types
as in subroutine void myfunc(void);
will store myfunc into a subroutine type.
This is required to the parser can identify a subroutine
type in a uniform decleration as a valid type, and also for
looking up the type later.
Also add contains_subroutine method.
v2: handle subroutine to int comparisons, needed
for lowering pass.
v3: do subroutine to int with it's own IR
operation to avoid hacking on asserts (Kayden)
v3.1: fix warnings in this patch, fix nir,
fix tgsi
v3.2: fixup tests
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
Signed-off-by: Dave Airlie <airlied at redhat.com>
tests: fix warnings
commit d16ff8ac783874c8ee74ef796b1c853829ff237d
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Sun Aug 10 21:38:23 2014 +1200
glsl: Make `subroutine` a reserved keyword
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 24b0e5068348aacabbd3e0012de95d34866e4b99
Author: Dave Airlie <airlied at redhat.com>
Date: Thu Jul 23 10:49:12 2015 +1000
dispatch_sanity: add shader subroutine to fix make check
Add the shader subroutine to the core only API list,
and fixup dispatch_sanity to suit.
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit cc172fddf3fc37991c6d85f2d8e4f6dc63a62809
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Sun Aug 10 21:31:06 2014 +1200
glsl: Add extension plumbing and define for ARB_shader_subroutine
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 25d6f56c08801909e784f81e9b9ced48977630f4
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Sun Aug 10 21:07:33 2014 +1200
mesa: Add glGet support for ARB_shader_subroutine implementation limits
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 4c7b007104c63475ec080d0777a41603c78786f6
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Sun Aug 10 20:43:45 2014 +1200
mesa: Add extension tracking for arb_shader_subroutine (v2)
v2: [airlied]: merge version check update.
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit b8f3e316bca2c9abd3c885a9447ecf29446d0ccb
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Sun Aug 10 20:38:53 2014 +1200
glapi: Add ARB_shader_subroutine functions and enums (v2)
v2: fix output="true" and LENGTH typo
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 2ffe9b542116580571b157de8a89476b22694ea9
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Sun Aug 10 21:00:34 2014 +1200
mesa: Add stubs for ARB_shader_subroutine entrypoints
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 2ca1f767818b02354735b58cef896abb8677e4ed
Author: Dave Airlie <airlied at redhat.com>
Date: Thu Jul 23 10:39:47 2015 +1000
dispatch_sanity.cpp: remove commented out tess entries
These entries were put in the GL4.0 section, so removed the commented
out ones.
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 18955e8a80ee2b344eaf3eb1d24eed90f6ba8334
Author: Dave Airlie <airlied at redhat.com>
Date: Thu Jul 23 11:13:36 2015 +1000
glsl/tests: fix varying_test since tess changes.
This fixes make check since the tess changes.
Tested-by: Michel Dänzer <michel.daenzer at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit b406c34a65677cac2517336d93ab279c3d35fce6
Author: Dave Airlie <airlied at redhat.com>
Date: Thu Jul 23 10:39:26 2015 +1000
i965: fix warning since tess merge.
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit bac12c8948681a23fd1a8f8a6bbb5523ccfe0939
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Feb 22 18:46:53 2015 +0100
radeonsi: enable tessellation, update GL3.txt & release notes
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit a193c4978b0b536266afc7887457ab11473671d7
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon May 18 14:41:35 2015 +0200
radeonsi: add scratch buffer support for tessellation shaders
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 12df9a7876ed0e6cfffb7871dc37bf66c95edca3
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Feb 22 18:16:02 2015 +0100
radeonsi: update invariant registers for tessellation
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 99bf47f603502cd6f3a6040ba17c0881e3b0c15f
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Feb 22 18:10:38 2015 +0100
radeonsi: add assertions into draw_vbo and check tessellation
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 5aa5f9082347941fd8ac2fc3e94cd91aa1489982
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Feb 22 18:09:18 2015 +0100
radeonsi: set the rasterization primitive type for tessellation
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 3344699243b856c3bc7b8ea08a949d2e3274e871
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Feb 22 18:07:51 2015 +0100
radeonsi: set VGT_LS_HS_CONFIG for tessellation
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 09d02fa463b7207464c99ca887e253476fde851e
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Feb 22 18:06:34 2015 +0100
radeonsi: update IA_MULTI_VGT_PARAM for tessellation
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 74c1001d13f07538e349c157598f9de83f252c49
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Feb 22 18:01:18 2015 +0100
radeonsi: add derived tessellation state
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit db267a04ceee51ca1698c3a68127508fa1e31c86
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon May 18 01:59:37 2015 +0200
radeonsi: implement a fixed-function tessellation control shader and its state
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit b6f4fdf6a9238bdb9e0589eafb22396da347b792
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Feb 22 17:25:37 2015 +0100
radeonsi: set up a ring buffer for tessellation factors
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit ebfd9e007191d582e22d252e9ff9b93fe4f8c593
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Feb 22 17:07:34 2015 +0100
radeonsi: add tessellation shader states
ls_rsrc# will be emitted as part of the derived tessellation state
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit aa2fa6723a0f8ab86ce2e55b1ac093f2cffd87c6
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Feb 22 16:07:04 2015 +0100
radeonsi: update si_get_vs_info and si_get_vs_state for tessellation
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit fff16e4ad2cf51749e01e04805908effe49217d1
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Feb 22 15:09:35 2015 +0100
radeonsi: add shader code generation for tessellation
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 4805685b6fe6efb7891dbc6dbab6ae4edce7e19e
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Oct 6 13:19:53 2014 +0200
radeonsi: implement TGSI_OPCODE_BARRIER
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 59b3556f4c69f0e6e5430ca6ab384d2ac9372bfc
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Sep 19 00:16:12 2014 +0200
radeonsi: program VGT_SHADER_STAGES_EN for tessellation
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit d9d0de4d289fa0b18bf23c85586e0111d64bf3b7
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Sep 18 23:39:44 2014 +0200
radeonsi: add translation of PATCH primitives
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 55b6f1caaeef4fa81fcc34d552aee4f0448417bb
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Sep 18 22:54:40 2014 +0200
radeonsi: add support for tessellation shader resources and samplers
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit d1f43a7e5b889b30106c4db55ec1caac1ed6ca4a
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Sep 18 22:50:52 2014 +0200
radeonsi: add code for creating, binding and destroying tessellation shaders
This doesn't do anything yet.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit c2670463fd50f5b74066f0e0ab8f9a31dcb37429
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Sep 18 22:26:02 2014 +0200
radeonsi: add debug flags for dumping tessellation shaders
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 3ce91c727f2a00a05f414351266b0b45d677611e
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Sep 15 23:34:28 2014 +0200
radeonsi: rework how shader pointers to descriptors are set
This is mainly needed for tessellation where a VS can be bound as VS, ES,
or LS, and TES (tess. evaluationshader) can be bound as VS or ES or neither.
Therefore we need the ability to move pointers to descriptors between
shaders arbitrarily.
The idea is that the context has a mapping from PIPE_SHADER_x to
SPI_SHADER_USER_DATA_x. After a shader is enabled or disabled,
si_shader_change_notify should be called to update this mapping accordingly.
There is a dirty flag for each shader pointer, but only one emit function
for all pointers in the whole context, whose code and logic is separated
from descriptors.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 57b6f8d9f9bfafd931974eae6942663e2ba6db02
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Feb 22 14:54:54 2015 +0100
radeonsi: rename build_streamout_store -> build_tbuffer_store_dwords
It will be reused later.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit f66844820e3ae2403d66d3275b1bf3e77087189c
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Feb 22 14:46:20 2015 +0100
radeonsi: separate primitive ID computation
Support for new shader stages will be added here.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit aa1f2af572a0285e9f5779e17b2d753119e0ec85
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Feb 22 14:33:49 2015 +0100
radeonsi: move declaring streamout parameters to its own function
It will be reused later.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 2ecb06b946ff8bf4a96de79ab81926fa1bf5a93f
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Oct 6 00:17:42 2014 +0200
radeonsi: make ES2GS offset sgpr location dynamic
It will have a different location in the tessellation evaluation shader.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 1bc0fba572363f5460be7343cff8b8b7a315d755
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Mar 3 15:11:27 2015 +0100
gallium/radeon: expose emit_fetch
Radeonsi will use this.
commit a3be59b4a91e25d47535f192194ff669cfe2ef6e
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Oct 5 20:20:18 2014 +0200
gallium/radeon: expose LLVM functions implementing emit_store
emit_store will be reimplemented for tessellation control shader outputs
where only radeon_llvm_saturate will be used, but radeonsi will want to
fall back to radeon_llvm_emit_store for other register types.
This exposes both functions.
commit 7626ad8d6daad147bf9a1a82fa4c3ac9e2d3347c
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Feb 22 19:50:42 2015 +0100
st/mesa: enable tessellation if the driver supports it
commit bda9094f1d69817ed1a51677d38e157ec3b37826
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon May 18 12:49:10 2015 +0200
st/mesa: set default tessellation levels
commit 82f7fad96691480b9ffdeb3e8e1b3345ede713ef
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Sep 7 18:36:06 2014 -0400
st/mesa: add barrier support
commit 8f40428afbbfa9080964df3cd4f38f24122c4c5e
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Jul 21 20:45:29 2014 -0400
st/mesa: disable copy propagation for tessellation shaders
This can't work due to shared inputs and outputs and barriers.
commit f4c13fad6550f42524786c70b6f13fc510abaf0b
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Jul 21 18:49:40 2014 -0400
st/mesa: set vertices_per_patch when drawing
commit 37d1809dd7cdfedbee4fcfef148fcdb1c7b43068
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Jul 13 15:02:53 2014 -0400
st/mesa: add 2d indexing support to outputs
commit c9998617a8f40ad7e65aca9c581f5bcc7f1d0f4c
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Feb 22 20:47:31 2015 +0100
st/mesa: handle tessellation 2D varyings correctly
commit 05c847433f5a3f3b2032bef32284ad7d6a2db850
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Jul 12 20:09:06 2014 -0400
st/mesa: lower gl_TessLevel from float[] to vecn
commit d00e2763b153c212e8f01af610ae305606044bcc
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Jul 12 17:28:24 2014 -0400
st/mesa: query shader CAPs for tessellation
The MaxTessPatchComponents query added by Marek.
commit 40bc1c32d2fb42207ea860053045fa49e45d80b9
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Jul 12 17:15:51 2014 -0400
st/mesa: add texture updates for tessellation programs
commit bda79139d4579b5105c45561401960a82bab2f7e
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Jul 12 17:10:59 2014 -0400
st/mesa: handle constbufs/ubos for tessellation shaders
commit a58a66fe8577940cf07530b6235a386950ae04f7
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Feb 22 20:44:39 2015 +0100
st/mesa: add conversion for tessellation shaders
Based on code from Ilia Mirkin <imirkin at alum.mit.edu>.
commit ba9fb96f86344f1631b82114bb0ce6f926d3853a
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Jul 11 22:11:21 2014 -0400
st/mesa: add tessellation shader states
additional fixes by Marek
commit df4ee8ef366c60ad41502d4e45e0347c1ef1e348
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Jun 16 13:07:04 2015 +0200
mesa: implement GL_IS_PER_PATCH
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 0af240e9401c12f4237f4a36a2474fe2cc590404
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jun 13 13:50:12 2015 +0200
glsl: use separate varying slots for patch varyings
The idea is to allow 32 normal varyings and 32 patch varyings,
a total of 64. Previously, only a total of 32 was allowed.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit d07023894434325de850faabf005224f7b8ef4b8
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat May 16 21:12:54 2015 +0200
glsl: fix locations of 2-dimensional varyings without varying packing (v2)
v2: renamed producer/consumer_type -> producer/consumer_stage
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 41acdae2e9eedb697a0f91815e201daf92d74ab4
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Oct 4 00:13:42 2014 +0200
glsl: don't demote tess control shader outputs
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 3a4b87f26d6c8c12eb119d72bf46461a7a384ab9
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Oct 4 00:15:33 2014 +0200
glsl: disable varying packing between tessellation shaders
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit d5787e7eef7c42e4a90cbd89dee81efbf1491487
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Jun 16 02:43:55 2015 +0200
glsl: allow indexing of gl_out with a non-const if length isn't known
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 19f46d0540d9557a4d458ceb72f27ece28fa935e
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Fri Sep 12 21:27:26 2014 +1200
glsl: allow redeclaration of TCS gl_out[]
Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 8cf72972ce2fc7df83d0572745968bbcb41a8c92
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Sun Sep 7 21:42:50 2014 +1200
glsl: validate restrictions on use of barrier()
With the exception of always-taken switch cases (which are
indistinguishable from straight line code in our IR), this
disallows use of the builtin barrier() function in all the
places it may not appear.
Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 799afadf51ad1ff0775a1bf7b4f3954a8d368b09
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Jun 14 20:14:22 2015 +0200
glsl: allow barrier() in tessellation control shaders
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit df16e0dd63dfeb7d5086339113ff7d7197010847
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Tue Sep 9 19:25:02 2014 +1200
glsl: analyze TES usage of gl_ClipDistance
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 0e94f350eeecd84cd5f15b10837b285bc9120684
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Sun Sep 7 18:19:15 2014 +1200
glsl: push vertex count determination down one level
We have the prog here, so we don't need the caller to work this out for
us.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 567f1b2ee89bf05f0600e9e79847140555f0a035
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Jul 21 21:59:37 2014 -0400
glsl: pass shader stage to lower_output_reads and handle tess control
Tessellation control outputs can be read in directly without first
having been written. Accessing these will require some special logic
anyways, so just let them through.
V2: Never lower tess control output reads, whether patch or not -- both
can be read back by other threads.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 61846f222fffeba846f9f7277aba9cc7d48323ed
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Mon Sep 1 20:48:09 2014 +1200
glsl: properly size unsized arrays in tess stages
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit d563946a4064d50f6fa7ce5e9e8ccb1479d1205e
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Sun Aug 31 19:35:46 2014 +1200
glsl: restrict indexing for writes to TCS outputs to gl_InvocationID
Marek: handle ir_swizzle
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit da7adb99e85fc6efa7f0e570ab93bd7b625975ae
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Sun Aug 17 22:37:16 2014 +1200
glsl: add builtin constants for ARB_tessellation_shader
Limits from other extensions added by Marek.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit b7f98f9f094090c6e8a24407dab67e4873c68694
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Sun Aug 24 16:46:40 2014 +1200
glsl: allow nonconst indexing of arrays where we can work out an implicit size
Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 64a0ae88b971e549852348b169de48d1d0b0869d
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Mon Aug 18 21:51:46 2014 +1200
glsl: relax unsized input/output block arrays for TCS/TES
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit 2abbe941e1bfaf494eb739b9fb81503736298f14
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Jun 16 01:32:28 2015 +0200
glsl: add the tessellation extension to the list for the "layout" qualifier
This is technically not needed, but it makes the compiler return a better
error message if tessellation is used with GLSL < 1.50.
Instead of:
error: syntax error, unexpected NEW_IDENTIFIER, expecting $end
It returns:
error: #version 150 layout qualifier `triangles' used
And the tessellation spec says:
OpenGL 3.2 and GLSL 1.50 are required.
So it makes perfect sense.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit fb800b3dcd32ddb6f57143b46105d677eb01da80
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu May 28 23:24:08 2015 +0200
glsl: don't lower variable indexing on non-patch tessellation inputs/outputs
There is no way to lower them, because the array sizes are unknown
at compile time.
Based on a patch from: Fabian Bieler <fabianbieler at fastmail.fm>
v2: add comments
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit 0cfac917554aeb46bd78ba5b5f5ee1c8ed1d68bc
Author: Fabian Bieler <fabianbieler at fastmail.fm>
Date: Thu Mar 20 22:34:42 2014 +0100
glsl: make stand-alone compiler work with tessellation shaders.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit c53aa26379ccee9d53fe1d1ea9bfa26d4d469618
Author: Fabian Bieler <fabianbieler at fastmail.fm>
Date: Thu Mar 20 22:37:37 2014 +0100
glsl: add "in" or "out" prefix to name when flattening interface blocks
This is to prevent a name conflict in tessellation shaders built-in interface
blocks.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit 73a9a1539a85ae8fe22e11b4064105d588597736
Author: Fabian Bieler <fabianbieler at fastmail.fm>
Date: Mon Mar 10 17:55:36 2014 +0100
glsl: lower gl_TessLevel* from float[n] to vecn.
Similar to gl_ClipDistance -> gl_ClipDistanceMESA
v2: - renamed is_mesa_var to lowered_builtin_array_variable
- moved LowerTessLevel into gl_constants
- cosmetic changes in lower_tess_level.cpp
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 54f29502972cdd33302e69e029c8d07fb31b7bdf
Author: Fabian Bieler <fabianbieler at fastmail.fm>
Date: Thu Mar 20 22:33:05 2014 +0100
glsl: make lower_clip_distance work with tessellation shaders.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit 7c758c5a216b0a72a089c4fe9b4facde0e7b2726
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Sun Sep 21 13:33:14 2014 +1200
glsl: allow linking of tessellation shaders.
Marek: require a tess eval shader if a tess control shader is present
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit 1009b3311febe3909e82d4b5be38ceecad6afcc1
Author: Fabian Bieler <fabianbieler at fastmail.fm>
Date: Wed Mar 5 13:43:17 2014 +0100
glsl: add the patch in/out qualifier (v2)
v2: Dropped some unrelated reordering in glsl_parser.yy as Ken suggested.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 1036b024d4c8ce2376ac41219dfda01d5a59b3ef
Author: Fabian Bieler <fabianbieler at fastmail.fm>
Date: Thu Mar 20 22:41:40 2014 +0100
glsl: add tessellation shader defines and built-in variables.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 497eb295838baccde1420adfcc4ef7e8fdddd774
Author: Fabian Bieler <fabianbieler at fastmail.fm>
Date: Thu Mar 20 22:44:43 2014 +0100
glsl: add tessellation shader parsing support (v2)
v2: Fixed things that Ken suggested.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 206af9d049cab6e794db5abf63e3d11281343423
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu May 28 22:08:55 2015 +0200
mesa: don't allow drawing with tess ctrl shader and without tess eval shader
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 3d528e7c476f25f24bca35d09d1f4c2b00123234
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Apr 22 23:05:34 2015 +0200
mesa: handle tessellation shaders in use_shader_program
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 882413f1c5926503550a42554a83f57f85fec82d
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Jun 14 01:21:02 2015 +0200
mesa: add program interface queries for tessellation shaders
Based on a patch by Chris Forbes <chrisf at ijw.co.nz>.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 550a570c5325cc64a547fe4d6e1e75af2d0e9587
Author: Fabian Bieler <fabianbieler at fastmail.fm>
Date: Fri Mar 7 10:39:39 2014 +0100
mesa: add misc tessellation shader stuff
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 6823d713c68dfb5679a7c96d06f72c31f755d686
Author: Fabian Bieler <fabianbieler at fastmail.fm>
Date: Fri Mar 7 10:39:18 2014 +0100
mesa: add tessellation shader getters (v3)
Tessellation dependencies added by Marek.
v2: require tessellation in addition to atomics/images for some glGet queries
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit cb0c12512cf83ac412ecc78d4d4c5318c46c9b22
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jun 13 23:06:06 2015 +0200
mesa: allow setting of patch parameters.
Based on a patch from Fabian Bieler <fabianbieler at fastmail.fm>.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit e32e546c17932161e5417a952db3fb7a19cdc93c
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Sun Sep 21 12:08:22 2014 +1200
mesa: require VS if TCS or TES is present in pipeline
Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit a30cc2882934ef25f41e1e41eb56d0b768f00b26
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Sun Sep 21 11:16:06 2014 +1200
mesa: allow tess stages in glUseProgramStages
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 6435b2909e4f1b82268a1c5769c0c228cda768e0
Author: Fabian Bieler <fabianbieler at fastmail.fm>
Date: Fri Mar 7 10:33:54 2014 +0100
mesa: support tess stages in glGetProgramPipelineiv
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 5852b5d2fa02d7716c2fbf859d058a2881416e9c
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jun 13 22:26:56 2015 +0200
mesa: take tessellation into account when validating GS input primitive mode
I've reported the bug in the Khronos bugzilla.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 8e758c3a74a35f8ee6c5969d5bb5f788b4ef4337
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Sun Sep 21 12:37:47 2014 +1200
mesa: allow drawing of patch primitives
Cosmetic changes and fixes by Marek.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit fa602c208815c3e4d757072cadc00e617e30b933
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu May 28 19:11:07 2015 +0200
mesa: add _mesa_has_tessellation
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit a894ed82931840713aac25634ed469ac65889bfa
Author: Fabian Bieler <fabianbieler at fastmail.fm>
Date: Mon Mar 10 11:58:37 2014 +0100
mesa: add misc tessellation shader support
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 78d3054980edd1a12e56ad0362e889915cff335b
Author: Fabian Bieler <fabianbieler at fastmail.fm>
Date: Fri Mar 7 10:28:03 2014 +0100
mesa: add tessellation shader init functions.
Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit bb97cc66c149d0782ec269aab29700252fda9db0
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Sun Sep 21 12:41:07 2014 +1200
mesa: add tessellation shader state and limits
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit a2af956963b6bc4d29f37485e44c98008d2ef077
Author: Fabian Bieler <fabianbieler at fastmail.fm>
Date: Fri Mar 7 10:19:09 2014 +0100
mesa: add tessellation shader enums
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit df3860a3e3269bfe77562058fd87b39ae2f57fcc
Author: Fabian Bieler <fabianbieler at fastmail.fm>
Date: Fri Mar 7 10:13:16 2014 +0100
mesa: add tessellation shader structs
Marek: remove unused members, cleanup
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit e2b59a39cbb64f6759f463f7bad162f5f03807b4
Author: Fabian Bieler <fabianbieler at fastmail.fm>
Date: Fri Mar 7 09:59:11 2014 +0100
mapi: add ARB_tessellation_shader
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 5ead448719f39d27bfbf4cabf138324dfee34a4f
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Jun 16 22:13:34 2015 +0200
drirc: drop support for Heaven 3.0, fixes tessellation in 4.0
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 6b37643b820b32c3e15e4a8661448a11af8321dd
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Jul 16 15:27:34 2015 +0200
winsys/radeon: implement buffer_unmap
This has been a no-op due to performance concerns. From now on, drivers
should decide when they don't want to unmap, not the winsys.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 5e3974338ed7ea49a41405f8c2e4bcd5fd1f5c80
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Jul 16 14:54:50 2015 +0200
gallium/radeon: remove buffer_unmap calls that can potentially decrease perf
buffer_unmap is currently a no-op on radeon and done correctly on amdgpu.
I plan to fix it for radeon, but before that, all occurences of buffer_unmap
that can negatively affect performance in the future must be removed.
There are 2 reasons for removing buffer_unmap calls:
- There is a likelihood that buffer_map will be called again, so we don't
want to unmap yet.
- The buffer is being released, which automatically unmaps it.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 0aa2446e2c18e4a54ccf8555a8ff3426e4eb3ded
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Jul 16 14:42:38 2015 +0200
radeonsi: remove switch statement in si_create_context
and make si_init_config static
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 46b2b3bda8d962fce02838e09c742ac06fbec45f
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Jul 16 13:17:14 2015 +0200
radeonsi: don't change pipe_resource in resource_copy_region
Copied from r600g. pipe_resource can be shared by multiple threads, so we
shouldn't change it.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 50a957c5de842b18e10c361f7b0310aa46bb483f
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Jul 10 23:35:55 2015 +0200
radeonsi: upload shader rodata after updating scratch relocations
Cc: 10.5 10.6 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit e4d738f6c6b98a78830c10ab7b89704d847637a5
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Jul 10 23:29:04 2015 +0200
radeonsi: remove redundant parameter in si_shader_binary_read
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 2369dc83826c7b1f413ff78f55e460c38d7a0660
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Jul 5 16:57:58 2015 +0200
cso: eliminate some sampler function wrappers
commit 68dcbf4c4679ad4e62d55e4f2632311aeef38eed
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Jul 12 16:12:59 2015 +0200
gallium/tests: use cso_set_samplers
commit 85f5722f70075e7a93b7a6cc41abee1bc493f4e2
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Jul 12 15:52:44 2015 +0200
gallium/util: use cso_set_samplers
commit 5ef1782b9ff8aa06f5b7fdbc7ade3e80131d1fda
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Jul 5 16:54:44 2015 +0200
st/mesa: use cso_set_samplers
commit 4ef7d93a941257b18506eae056631e8f4a11f893
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Jul 5 16:34:59 2015 +0200
cso: remove clip state handling
There is no need for this.
v2: handle redundant clip state changes in st/mesa
commit b7492a1f45866a01b00263f9e252ddc3835304e9
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Jul 5 16:32:49 2015 +0200
cso: only allow saving and restoring fragment sampler states
commit 4e8bbed926729fe280701412d85aff64ab79856c
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Jul 5 16:10:54 2015 +0200
cso: drop inefficient checking for redundant sampler state changes
Drivers can do this better, because they can skip redundant state changes
at per-slot granularity.
commit 3639d66a473591e21aa2ec7692c95c827b479632
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Jul 5 15:53:10 2015 +0200
cso: only allow saving and restoring fragment sampler views
Not needed for other shader stages.
commit 2d8213bfa9023b47a5fd6599596e1b02fdcdd4f6
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jul 4 13:18:11 2015 +0200
gallium/util: improve dump functions
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 8141b4cee514bb673e394f6fbe2cbe02e5b0faf2
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jul 4 13:17:07 2015 +0200
tgsi: allow dumping to a file directly
commit d082c5324914212f76e45be497229c7a0681f706
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Jul 16 17:14:07 2015 +0200
st/mesa: don't call st_validate_state in BlitFramebuffer
None of the draw states are used here.
This fixes a crash in piglit: ext_framebuffer_blit/blit-early
Calling st_manager_validate_framebuffers is the minimum requirement here.
Cc: mesa-stable at lists.freedesktop.org
commit 2f50fc040c223339dc14f2975c45d35dd4513c13
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Apr 29 17:57:46 2015 +0200
docs/relnotes: document new EGL extensions and EGL 1.5
commit 1828357629721e53a305a29047c0eb18be10915b
Author: Anatoli Antonovitch <anatoli.antonovitch at amd.com>
Date: Wed Jun 10 14:47:03 2015 +0200
st/dri: enable 3D textures and sRGB colorspace for EGL
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit 4f57ccd02d4c5f214c7e59e7302c1dc650cff31d
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Jun 10 14:45:58 2015 +0200
egl,dri_interface: use DRI2rendererQueryExtension to enable 3D textures & sRGB
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit c2c2e9ab604793c6e01f85497f3f5bf645f962fa
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Jun 10 02:49:29 2015 +0200
egl: implement EGL_KHR_gl_colorspace (v2)
v2: add missing "break"
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 956ebf41aca6b74052cf6876cc479b404777700c
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Jun 10 01:49:36 2015 +0200
st/dri: expose sRGB visuals (v2)
v2: The fix for the darkness in Ubuntu Unity is in the hunk
with the 4-line comment.
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit b06a6852ff782bb20d9e91a3a67eccb92e856ed3
Author: Dylan Baker <baker.dylan.c at gmail.com>
Date: Thu Jul 2 10:25:41 2015 -0700
glapi: fix argument parsing in glX_proto_recv.py
One of the plugins I use with vim "helpfully" added an underscore to the
front of mode for kicks.
Obviously this isn't a feature used very often because it's been broken
since d986cb7c70db (since May 20th), and no one has noticed.
Signed-off-by: Dylan Baker <dylanx.c.baker at intel.com>
commit 461b4b103f545027beb59c1d747c85892c6c1f63
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Tue Jul 21 15:34:19 2015 +0100
egl: android: remove DRM_GRALLOC_TOP hack
Now that the drm_gralloc module exports the correct includes we can get
rid of this hack.
Cc: Chih-Wei Huang <cwhuang at android-x86.org>
Cc: Eric Anholt <eric at anholt.net>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Tested-by: Varad Gautam <varadgautam at gmail.com>
commit e2ef659c2ed36cca5a5c4a09440edb227eedcf60
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Tue Jul 14 00:28:46 2015 +0100
egl: remove old makefile.sources
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit 1040a861a80486502c7ac86a258741d5cdf6459a
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Tue Jul 14 00:28:10 2015 +0100
android: rework the EGL build
See previous two commits for details.
v2: Don't forget git mv, bring back DRM_GRALLOC_TOP. Spotted by Varad.
Cc: Chih-Wei Huang <cwhuang at android-x86.org>
Cc: Eric Anholt <eric at anholt.net>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
Tested-by: Varad Gautam <varadgautam at gmail.com>
commit e7e29189e27bb404bf84d757a8f1dd617126808a
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Tue Jul 14 02:04:30 2015 +0100
scons: rework the EGL build
The scons equivalent of the previous commit - just fold the almost
identical driver + main Sconscripts.
Cc: Alexander von Gluck IV <kallisti5 at unixzen.com>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit e3420396124c75ec9679c4d1cf3a42c185207e5a
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Tue Jul 14 01:58:33 2015 +0100
automake: rework the EGL build
Simplify things by merging the two makefiles. This way we can combine
the duplicated HAVE_PLATFORM_ checks, and build the library without
having a separate static library.
v2: use $() when referencing variables, use correct define (Matt)
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 0399d7ab3f69624b7f0b7b39e948432959fe270e
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Tue Jun 30 22:43:50 2015 +0100
gbm: do not build intermittent libgbm_dri static library
The only user of it (libgbm.la) immediately links it. Just build it
directly into the library.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 8e5e18ac286f0782380c72cebffd4c54c98e4ccb
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Jul 13 22:35:25 2015 +0100
egl: automake: remove unused HAVE_XCB_DRI2 define
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit a1202807dccc6e2ac02ff52639a49f6c2d06648d
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Tue Jul 14 01:58:12 2015 +0100
egl: remove unused _EGL_DRIVER_SEARCH_DIR define
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 0b915856bac4871b90c101b44a2830b9a0e22e05
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Jul 13 22:16:11 2015 +0100
egl/haiku: remove unused DEFAULT_DRIVER_DIR define
Cc: Alexander von Gluck IV <kallisti5 at unixzen.com>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit c17e01748e9efc2d638b7b5bc9d4344521334f48
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Tue Jul 14 01:57:23 2015 +0100
egl: remove final Windows specific workaround
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 3593f37fd7b599e217bd1f894ac671a14a058b8d
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Tue Jul 14 00:19:54 2015 +0100
egl: remove custom string functions
Support for Windows has been removed for a while now, and virtually
every POSIX compliant system provides strcasecmp, strdup and snprintf.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit d62879565a5c8479c3cfea513aa4e90f0d90b304
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Jul 13 23:36:19 2015 +0100
egl: remove _EGL_PLATFORM_WINDOWS enum
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 32debea337755cf15550844955b14c29bb3006fa
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Jul 13 22:05:46 2015 +0100
egl: remove final references of platform_null
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit dc1ece3748f3a97d685c9c72ad26684fd35f1944
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Jul 13 22:20:38 2015 +0100
egl: remove flatten HAVE_SHARED_GLAPI
It is simply not possible to use the dri backend without shared glapi,
as the alternative provider (libGL) is not always present. We have fixed
the build for a while now, so we can rip this out.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 78674631a2d0ff1eb538470e2a1d516201361f03
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Tue Jul 14 01:52:51 2015 +0100
egl: remove the non-haiku scons build
It has been broken since 2011 with commit c98ea26e16b(egl: Make
egl_dri2 and egl_glx built-in drivers.). When the backends got merged
into the main library each entry point was guarded by a
_EGL_BUILT_IN_DRIVER_* define.
As the define was missing, the linker kindly removed the whole of the
dri2 backend, thus we did not notice any errors due to the unresolved
link to xcb and friends.
Cc: Chia-I Wu <olv at lunarg.com>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit ce2a4bd541241dade00a36e9f2d8e5ca16c6ff03
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Jul 13 21:12:01 2015 +0100
dri/common: remove unused drm_version variable
As of last commit the only user of it (radeon/r200) no longer uses it.
As such let's remove it and cleanup the nasty hacks that we had in place
to support this.
v2: Leave LIBDRM_CFLAGS around.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com> (v1)
Reviewed-by: Marek Olšák <marek.olsak at amd.com> (v1)
commit 5284e9e2c4922479b28db96ae88121a053a6e66b
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Jul 9 18:06:14 2015 +0100
radeon,r200: allow hyperz for radeon DRM module v2
The original code only half considered hyperz as an option. As per
previous commit "major != 2 cannot occur" we can simply things, and
allow users to set the option if they choose to do so.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 48926da0f7a1d1656bfbaf9d5344cc1fa0b6e089
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Jul 9 17:34:30 2015 +0100
radeon,r200: remove support for UMS radeon DRM module
As mentioned by Michel Dänzer
"FWIW though, any code which is specific to radeon DRM major version 1
can be removed, because that's the UMS major version."
and Marek Olšák
"major != 2" can't occur. You don't have to check the major version at
all and you can just assume it's always 2."
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit bf6247f608969c3f1fa987e297c6063c02896b5a
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Jul 9 17:29:57 2015 +0100
radeon,r200: remove unused variable texmicrotile
Dead since at least 2009 with commit ccf7814a315(radeon: major cleanups
removing old dead codepaths.)
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit 66d77cd71c6359cddfd21c128afe95bad860e231
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Jul 8 01:44:31 2015 +0100
scons: don't build the kms-dri winsys
Same as previous commit - unused (gbm is not a thing outside the
autotools build).
v2: Remove trailing HAVE_LIBDRM.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit a29a8b92ff05f3a63dd3b6ae8c7d0e07f039c0ad
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Tue Jul 7 21:02:40 2015 +0100
android: don't build the kms-dri winsys
GBM (the only user of kms-dri) is currently not available under Android.
Considering we have no way of testing/using this let's not bother
building it for now.
Cc: Chih-Wei Huang <cwhuang at linux.org.tw>
Cc: Eric Anholt <eric at anholt.net>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit fe1503fe38602c91e030ca206cb392a26a343f91
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Tue Jul 7 16:04:27 2015 +0100
android: dri: correctly set HAVE_LIBDRM
Set the macro if we're not building swrast alone.
Cc: Eric Anholt <eric at anholt.net>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Chih-Wei Huang <cwhuang at linux.org.tw>
commit 787995bffb52d955f3046618286d831b76b72119
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Tue Jul 7 15:59:32 2015 +0100
swrast: remove unneeded __NOT_HAVE_DRM_H define
No longer applicable since the cleanup of dri_interface.h.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 9ab5b644ef64ee23f88a6687cc541ee4e745234a
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Tue Jul 7 15:57:41 2015 +0100
dri/common: use HAVE_LIBDRM over __NOT_HAVE_DRM_H
See previous commit message for details.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 1c328b8aa79b0644160082b7e9e02df18ab3ca48
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Tue Jul 7 15:42:15 2015 +0100
loader: use HAVE_LIBDRM instead of ! __NOT_HAVE_DRM_H
Double negatives in English language are normally avoided, plus the
former seems cleaner and more consistent.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 72c784347bf66b61385cb57bb666033e5234ba69
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Jul 22 16:34:15 2015 +0100
st/dri: unwrap/remove __NOT_HAVE_DRM_H magic
With the dri_interface.h clean of the macro, we can remove the final
only st/dri specific use of the very same.
Seemingly it was incorrectly used, as the build-time presence of dri2 is
not libdrm specific. At run-time, the code is already limited to dri2
use-cases plus returning true, when the extension is not present (or too
old) will likely lead to a crash as one tries to use it shortly after
the dri_with_format() call.
As a side effect this gives us a nice cleanup the builds.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 0efd773f719dd2deddb4b6703edf022b294cd349
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Tue Jul 7 15:13:46 2015 +0100
dri_interface: drop __NOT_HAVE_DRM_H magic
v2: use HAVE_LIBDRM macro.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 816e4c1b5e2887c45ffa69d41c8106e7b31977fb
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Jul 22 16:22:44 2015 +0100
dri/swrast: automake: add LIBDRM_CFLAGS
With the follow up commit we'll remove the __NOT_HAVE_DRM_H macro. As
requested by Ian HAVE_LIBDRM will be used instead, which will lead to
swrast including drm.h when libdrm package is available, even though we
don't need/make use of the header.
As the define is added after the AM_CFLAGS we cannnot use -UHAVE_LIBDRM,
but instead let's just add LIBDRM_CFLAGS. The latter of which will
expand to NULL when the libdrm package is not around.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 16f6d432de07dcb537dafd0c9f3ef7614891ed6b
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Jul 9 21:19:15 2015 +0100
configure.ac: do not set HAVE_DRI(23) when libdrm is missing
These conditionals are used to guard both dri modules and loader(s).
Currently if we try to build the gallium swrast dri module (without glx)
on a system that's missing libdrm the build will fail.
v2: Make sure we assign prior to checking the have_libdrm variable.
Cc: 10.6 <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit fe4290200942b1103cdc1a238876143b61b731f0
Author: Brian Paul <brianp at vmware.com>
Date: Wed Jul 22 08:04:49 2015 -0600
mesa: fix typo s/glGetTextImage/glGetTexImage/
Trivial.
commit 800efb0690e962750b9a072bcbab279fdaae24a1
Author: Michel Dänzer <michel.daenzer at amd.com>
Date: Wed Jul 22 16:11:39 2015 +0900
radeonsi: Flush when we're asked to return a fence but don't have one yet
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit fcc1949cc4d97d8ed714020d5b86b31b70eca774
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Sat Jul 4 08:34:32 2015 +1000
mesa: fix misleading comment
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit 13322a6590b9e64a9a9f8dd304898e9ab6bedd49
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Wed Jun 17 23:03:52 2015 +1000
mesa: fix active sampler conflict validation
The type stored in gl_uniform_storage is the type of a single array
element not the array type so size was always 1.
V2: Dont validate sampler units pointing to 0
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit 09c440c718992d48ef118c1aad6929ad215ccd3b
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Fri Jul 3 08:45:30 2015 +1000
glsl: check for leading zeros in array index validation
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit 7fccebf9803973c7403318da20afe23e80b5b59f
Author: Brian Paul <brianp at vmware.com>
Date: Tue Jul 21 18:44:07 2015 -0600
swrast: remove unneeded & operators in _swrast_choose_texture_sample_func()
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 300926def04afc76d67ce964f10247b2e787c5dc
Author: Brian Paul <brianp at vmware.com>
Date: Tue Jul 21 18:44:07 2015 -0600
mesa: move check for no-op glShadeModel call earlier
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit d323f26830c1ce7e157cfeeb4f1e38b1a4d19d31
Author: Brian Paul <brianp at vmware.com>
Date: Tue Jul 21 18:44:07 2015 -0600
mesa: move check for no-op glAlphaFunc call earlier
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 61ed88b1ddf8aea6f74518bcae5c13d9bf4ae822
Author: Brian Paul <brianp at vmware.com>
Date: Tue Jul 21 18:44:07 2015 -0600
mesa: move check for no-op glFrontFace call earlier
If the new mode matches the current mode, there can be no error.
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 24799c422365f609403ccde0759c77b0179328d3
Author: Brian Paul <brianp at vmware.com>
Date: Tue Jul 21 18:35:38 2015 -0600
mesa: s/GLint/GLsizei/ for consistency
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit b94367ba8d14ea999d2b81cb24db21fa72d4bab8
Author: Brian Paul <brianp at vmware.com>
Date: Tue Jul 21 18:35:38 2015 -0600
docs: document that GL_ARB_get_texture_sub_image is completed
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 89212f9d06cbd5dd7cebefe7b4e535692525e3e9
Author: Brian Paul <brianp at vmware.com>
Date: Tue Jul 21 18:35:38 2015 -0600
mesa: enable GL_ARB_get_texture_sub_image for all drivers
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 48f9f0bfdd6bfb0ab4844cf005c1534c86cd3836
Author: Brian Paul <brianp at vmware.com>
Date: Tue Jul 21 18:35:38 2015 -0600
mesa: add API dispatch for GL_ARB_get_texture_sub_image
This adds the new glGetTextureSubImage() and
glGetCompressedTextureSubImage() functions. Also update the
dispatch sanity test program.
v2: remove stray brace, move xi:include line in gl_API.xml, fix extension
number typo, s/program/texture/ in xml file.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 2494f91fb82eb545fd59ed4c9850ff378fc0c591
Author: Brian Paul <brianp at vmware.com>
Date: Tue Jul 21 18:35:38 2015 -0600
mesa: add new _mesa_Get[Compressed]TextureSubImage() functions
Simple implementations in terms of get_[compressed_]texture_image().
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit a92f0277d854d6ac5dd524134f113632c990b1b0
Author: Brian Paul <brianp at vmware.com>
Date: Tue Jul 21 18:35:38 2015 -0600
mesa: overhaul the glGetCompressedTexImage code
Same idea as the previous patch.
v2: a few clean-ups spotted by Ilia
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit f20cfc5a409b69d5ae3d10a870d90e0b4e493ddf
Author: Brian Paul <brianp at vmware.com>
Date: Tue Jul 21 18:35:38 2015 -0600
mesa: overhaul the glGetTexImage code
1. Reorganize the error checking code.
2. Lay groundwork for getting sub images by passing image offset and
dimensions to the error checking code.
3. Implement _mesa_GetnTexImageARB(), _mesa_GetTexImage() and
_mesa_GetTextureImage() all in terms of get_texture_image().
v2: pass offset/width/height/depth arguments to the error checking
function, avoid using magic width/height/depth values.
v3: remove unused bufSize param to get_texture_image()
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 613f1e00b8f8493a0cac7dbeec6647ce3a5a0355
Author: Brian Paul <brianp at vmware.com>
Date: Tue Jul 21 18:35:38 2015 -0600
mesa: 80-column wrapping in texgetimage.c
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 2a95fd153158e20e6b44548d4f247a5763713fb3
Author: Brian Paul <brianp at vmware.com>
Date: Tue Jul 21 18:35:38 2015 -0600
mesa: replace Driver.GetCompressedTexImage() w/ GetCompressedTexSubImage()
For now, pass offsets of zero and width/height/depth equal to the
whole image.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 5bfc360e40680b3fe2b6f74ac487fa76502559e3
Author: Brian Paul <brianp at vmware.com>
Date: Tue Jul 21 18:35:38 2015 -0600
mesa: make _mesa_get_[compressed_]texture_image() static
These functions are only called from teximage.c
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 1ad305b612f389fb04c6d51847427d5ec72fae03
Author: Brian Paul <brianp at vmware.com>
Date: Tue Jul 21 18:35:38 2015 -0600
mesa: plumb offset/size parameters through GetTexSubImage code
Needed for GL_ARB_get_texture_sub_image. But at this point, the
offsets are always zero and the sizes match the whole texture image.
v2: Fixes, suggestions from Laura Ekstrand:
* Fix calls to ctx->Driver.UnmapTextureImage() to pass the correct
slice value.
* Added comments and assertions to check zoffset+depth<=tex->Depth before
the 'img' loops.
* Added a new zoffset==0 assert in get_tex_memcpy().
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit e693fc299f1f78502b9201f1e1e8f333566c9fb6
Author: Brian Paul <brianp at vmware.com>
Date: Tue Jul 21 18:35:38 2015 -0600
mesa: replace Driver.GetTexImage with GetTexSubImage()
The new driver hook has x/y/zoffset and width/height/depth parameters
for the new glGetTextureSubImage() function.
The meta code and gallium state tracker are updated to handle the
new parameters.
Callers to Driver.GetTexSubImage() pass in offsets=0 and sizes equal
to the whole texture size.
v2: update i965 driver code, s/GLint/GLsizei/ in GetTexSubImage hook
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 096371879098c315bc054b6fe1ef6f4b8f18554f
Author: Brian Paul <brianp at vmware.com>
Date: Tue Jul 21 18:35:38 2015 -0600
meta: add offset, width, height parameters to decompress_texture_image()
In preparation for decompressing texture sub images.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 2a2c9469425bc794c98dcf57237457ba41d10ce2
Author: Brian Paul <brianp at vmware.com>
Date: Tue Jul 21 18:35:38 2015 -0600
meta: handle subimages in _mesa_meta_setup_texture_coords()
v2: fix depth, total_depth mix-up in meta.h, per Laura Ekstrand.
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit d7bd9fa1a363c288324d73fbde86f2257dfc0a15
Author: Brian Paul <brianp at vmware.com>
Date: Tue Jul 21 18:35:38 2015 -0600
mesa: assorted whitespace, formatting fixes in teximage.c
Trivial.
commit 98a6c5ea1129f18ed5f097fad5bbebc86eb0e862
Author: Brian Paul <brianp at vmware.com>
Date: Tue Jul 21 18:35:38 2015 -0600
mesa: allow GL_TEXTURE_CUBE_MAP_ARRAY case for glCompressedTexSubImage3D()
Since s3tc works for cube maps and 2D arrays, it should also work for
cube arrays. NVIDIA's driver supports this too. Seems like the spec
should say this.
This is a minor follow-on fix for the commit "mesa: fix up some texture
error checks".
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit 4c7196b684fe384599c1a02bf20aec7b6447968d
Author: Jonathan Gray <jsg at jsg.id.au>
Date: Thu Jul 16 01:17:37 2015 +1000
mesa: include stdarg.h for va_list
Include stdarg.h for va_list. Unbreaks the build on OpenBSD:
In file included from mesa/program/dummy_errors.c:24:
../src/mesa/main/errors.h:85: error: expected declaration specifiers or '...' before 'va_list'
Signed-off-by: Jonathan Gray <jsg at jsg.id.au>
Acked-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit a2a1a5805fd617e7f3cc8be44dd79b50da07ebb9
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Jul 20 19:58:43 2015 -0400
gallium: replace INLINE with inline
Generated by running:
git grep -l INLINE src/gallium/ | xargs sed -i 's/\bINLINE\b/inline/g'
git grep -l INLINE src/mesa/state_tracker/ | xargs sed -i 's/\bINLINE\b/inline/g'
git checkout src/gallium/state_trackers/clover/Doxyfile
and manual edits to
src/gallium/include/pipe/p_compiler.h
src/gallium/README.portability
to remove mentions of the inline define.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Acked-by: Marek Olšák <marek.olsak at amd.com>
commit 958b5c31116f46a81249d11033164354ec158556
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Tue Jul 21 21:58:08 2015 +0200
nvc0: force cache flush when binding a new ubo
This fixes the following piglit test:
ext_transform_feedback-immediate-reuse-uniform-buffer
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit a62ccdec622ea43a7cdbf572a32dfae19ba9c904
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Tue Jul 21 21:35:43 2015 +0200
nv50: force cache flush when binding a new ubo
This fixes the following piglit test:
ext_transform_feedback-immediate-reuse-uniform-buffer
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 912921059d137085faef676504bea265328bdde4
Author: Vinson Lee <vlee at freedesktop.org>
Date: Mon Jul 20 21:52:40 2015 -0700
st/mesa: Silence GCC unused-variable warning.
Silence a release build warning.
st_glsl_to_tgsi.cpp: In function 'pipe_error st_translate_program(gl_context*, uint, ureg_program*, glsl_to_tgsi_visitor*, const gl_program*, GLuint, const GLuint*, const GLuint*, const ubyte*, const ubyte*, const GLuint*, const GLuint*, GLuint, const GLuint*, const GLuint*, const ubyte*, const ubyte*, boolean, boolean)':
st_glsl_to_tgsi.cpp:5461:36: warning: unused variable 'pscreen' [-Wunused-variable]
struct pipe_screen *pscreen = st->pipe->screen;
^
Signed-off-by: Vinson Lee <vlee at freedesktop.org>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 5b4a7ec8f1d2eee12895541bb5c7d15382370884
Author: Adam Jackson <ajax at redhat.com>
Date: Tue Jul 21 12:08:20 2015 -0400
r600/sb: Fix an &/&& mistake
gcc says:
sb/sb_sched.cpp: In member function 'bool r600_sb::alu_group_tracker::try_reserve(r600_sb::alu_node*)':
sb/sb_sched.cpp:492:7: warning: suggest parentheses around operand of '!' or change '&' to '&&' or '!' to '~' [-Wparentheses]
if (!trans & fbs)
It happens to be harmless; if fbs is ever non-zero, it will be VEC_210,
which is 5, so (!trans & 5) == 1 and the branch works as expected. But
logical AND is clearly what was meant.
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Signed-off-by: Adam Jackson <ajax at redhat.com>
commit 545dec5b3efeab7691ab3eb1436747048f241cf9
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Fri Jul 17 14:14:29 2015 -0700
Revert "i965/gen9: Plugin the code for selecting YF/YS tiling on skl+"
Commit c9dbdc0 introduced some dead code which is supposed to be used
once we have Yf/Ys tiling working and performing better. Ken reported
the issue that static analysis tool now shows warnings due to the dead
code. To fix these warnings, this patch reverts the changes made in
commit c9dbdc0.
It'll be better to add the Yf/Ys tiling selection code later, when we
are ready to use it.
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
commit fadf34773527779eef4622b2586d87ec00476c0f
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 13 15:52:28 2015 +0300
i965: Fix stride field for the result of emit_uniformize().
This is essentially the same problem fixed in an earlier patch for
immediates. Setting the stride to zero will be particularly useful
for my future SIMD lowering pass, because we will be able to just
check whether the stride of a source register is zero and skip
emitting the copies required to unzip it in that case.
Instead of setting stride to zero in every caller of emit_uniformize()
I've changed the function to return the result as its return value
(previously it was being written into a caller-provided destination
register), because this way we can enforce that the result is used with
the correct regioning from the function itself.
The changes to the prototype of its VEC4 counterpart are mainly for
the sake of symmetry, VEC4 registers don't have stride.
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit 9383664a9cbc5bc4858fc50d7fa565f43028d779
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 13 15:29:39 2015 +0300
i965/fs: Fix stride field for uniforms.
This fixes essentially the same problem as for immediates. Registers
of the UNIFORM file are typically accessed according to the formula:
read_uniform(r, channel_index, array_index) =
read_element(r, channel_index * 0 + array_index * 1)
Which matches the general direct addressing formula for stride=0:
read_direct(r, channel_index, array_index) =
read_element(r, channel_index * stride +
array_index * max{1, stride * width})
In either case if reladdr is present the access will be according to
the composition of two register regions, the first one determining the
per-channel array_index used for the second, like:
read_indirect(r, channel_index, array_index) =
read_direct(r, channel_index,
read(r.reladdr, channel_index, array_index))
where:
read(r, channel_index, array_index) = if r.reladdr == NULL
then read_direct(r, channel_index, array_index)
else read_indirect(r, channel_index, array_index)
In conclusion we can handle uniforms consistently with the other
register files if we set stride to zero. After lowering to a GRF
using VARYING_PULL_CONSTANT_LOAD in demote_pull_constant_loads() the
stride of the source is set to one again because the result of
VARYING_PULL_CONSTANT_LOAD is generally non-uniform.
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit 5f8d9ae5a54961deb02eb52e924a84b99b60f035
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 13 14:50:24 2015 +0300
i965/fs: Fix stride for immediate registers.
When the width field was removed from fs_reg the BROADCAST handling
code in opt_algebraic() started to miss a number of trivial
optimization cases resulting in the ugly indirect-addressing sequence
to be emitted unnecessarily for some variable-indexed texturing and
UBO loads regardless of one of the sources of BROADCAST being
immediate. Apparently the reason was that we were setting the stride
field to one for immediates even though they are typically uniform.
Width used to be set to one too which is why this optimization used to
work previously until the "reg.width == 1" check was removed.
The stride field of vector immediates is intentionally left equal to
one, because they are strictly speaking not uniform. The assertion in
fs_generator makes sure that immediates have the expected stride as
consistency check.
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit b298311d517017834841e53b7e641738e6067cdc
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Mon Jul 20 12:58:12 2015 +0200
i965/vec4: Fix liveness analysis with BRW_OPCODE_SEL
We only consider a vgrf defined by a given block if the block writes to it
unconditionally. So far we have been checking this by testing that the
instruction is not predicated, however, in the case of BRW_OPCODE_SEL,
the predication is used to select the value to write, not to decide if
the write is actually done. The consequence of this was increased life
spans for affected vgrfs, which could lead to additional register pressure.
Since NIR generates selects for conditional writes this was causing massive
register pressure in a handful of piglit and dEQP tests that had a large
number of select operations with the NIR-vec4 backend.
Fixes the following piglit tests with the NIR-vec4 backend:
spec/glsl-1.50/execution/variable-indexing/vs-output-array-vec4-index-wr-before-gs
spec/glsl-1.50/execution/variable-indexing/gs-input-array-vec4-index-rd
spec/glsl-1.50/execution/variable-indexing/vs-output-array-vec2-index-wr-before-gs
spec/glsl-1.50/execution/variable-indexing/vs-output-array-vec3-index-wr-before-gs
spec/glsl-1.50/execution/variable-indexing/vs-output-array-float-index-wr-before-gs
Fixes 80 dEQP tests with the NIR-vec4 backend in the following category:
dEQP-GLES3.functional.ubo.*
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 2f11e92cef51c88a09bc778e2ceca4ab50cf0017
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Jul 18 01:22:00 2015 -0700
mesa: Rename _mesa_lookup_enum_by_nr() to _mesa_enum_to_string().
Generated by sed; no manual changes.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit cd0dec0d9dfab642c51774c3f5788cbdf00b8c9b
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Mon Jul 20 21:32:43 2015 +0200
nouveau: use bool instead of boolean
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Acked-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 4be30fcd058209966fc72fbfa51bbe881c307ed5
Author: Tom Stellard <thomas.stellard at amd.com>
Date: Mon Jul 20 15:12:56 2015 +0000
gallivm: Initialize LLVM Modules's DataLayout to an empty string.
This fixes crashes in llvmpipe with LLVM 3.8 and also some piglit tests
on radeonsi that use the draw module.
This is just a temporary solution. The correct solution will require
creating a TargetMachine during gallivm initialization and pulling the
DataLayout from there. This will be a somewhat invasive change, and it
will need to be validatated on multiple LLVM versions.
https://llvm.org/bugs/show_bug.cgi?id=24172
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit 5b7dd4d41900e3c795af134e0fad59cac9e0e7b4
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Thu Jul 16 23:05:05 2015 +0200
nvc0: add a missing parameter to nvc0_set_shader_images()
This fixes a compilation warning introduced in commit 05a12c5
(gallium: add interface for writable shader images).
While we are at it, fix indentation and rename parameters according to
the gallium interface.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit c2cb771354d2d738e0ab3ca7c8008748c5f57953
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Mon Jul 20 18:47:17 2015 +0200
nouveau: always align buffers to 0x100
Only constbufs must be aligned to 0x100, but since all buffers can be
rebinded as constant buffers they must be also aligned.
This patch prevents this behaviour by aligning everything to 256-byte
increments at buffer creation.
This fixes dmesg fails for the following piglit test:
ext_transform_feedback-immediate-reuse-uniform-buffer -auto -fbo
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 19a6214b0ff707ae52e9624c263b7d6c1c20e6d3
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Mon Jul 13 13:34:31 2015 +0200
nv50: limit the maximum number of samplers to 16
NV50_3D_BIND_TSC only allows to bind 16 samplers, and since we don't
want to do anything with NV50_3D_BIND_TSC2, just limit the maximum
number of samplers to 16 like for nvc0.
This fixes dmesg fails with the following piglit test:
max-samplers
But the test still fails.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 6d207b8e3548cd7832a5edc7b847a5e7d06c0925
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Mon Jul 13 12:52:57 2015 +0200
nv50: turn samples counts off during blit
Fixes the following piglit test:
occlusion_query_meta_no_fragments
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit d246a96bbc4253a8339a505df97742fd252ebc55
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Mon Jul 13 12:51:21 2015 +0200
nv50: add nesting support for occlusion queries
This is loosely based on nvc0.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 8ba1982b1e37aa69680e243fe391254211ae273a
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Fri Jul 17 11:54:34 2015 +0200
i965/nir/fs: removed unneeded support for global variables
As functions are inlined, and nir_lower_global_vars_to_local gets
run, all global variables are lowered to local variables.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 801d41fa43eba996c6bd7c071282ad15e51609d3
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Jul 20 00:19:56 2015 -0400
nv50: fix max level clamping on G80
It appears that the G80 did not have support for the sampler view
first/last clamping. Put the view's last level in the place of the
texture's so that it doesn't go past what the sampler view allows.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org
commit 8c8a71f0d125bb655b17a32914ffecf8d159593b
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Jul 18 19:02:29 2015 -0400
gm107/ir: fix indirect txq emission
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org
commit 346ce0b98832e33d5411200002571b3edea9e2bb
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Jul 18 18:38:42 2015 -0400
nvc0/ir: don't worry about sampler in txq handling
There's no need to deal with samplers for texture size queries. That
code also was accidentally setting an invalid sIndirectSrc position, but
it can now just be removed.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org
commit 20e484afa4874e87cd18daffd66286bb893cf3fb
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Jul 18 16:43:17 2015 -0400
nvc0/ir: fix txq on indirect samplers
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org
commit 670914ea7cf7808ff37ca54db2844f711436031c
Author: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
Date: Wed May 20 18:02:44 2015 +0300
i965: Disable resource streamer in BLORP
Switch off hardware-generated binding tables and gather push
constants in the blorp. Blorp requires only a minimal set of
simple constants. There is no need for the extra complexity
to program a gather table entry into the pipeline.
Cc: kenneth at whitecape.org
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
commit fc65b6eb610f4b1e42930cae7594131fa9ea566e
Author: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
Date: Wed Oct 2 16:37:20 2013 +0300
i965: Upload binding tables in hw-generated binding table format.
When hardware-generated binding tables are enabled, use the hw-generated
binding table format when uploading binding table state.
Normally, the CS will will just consume the binding table pointer commands
as pipelined state. When the RS is enabled however, the RS flushes whatever
edited surface state entries of our on-chip binding table to the binding
table pool before passing the command on to the CS.
Note that the the binding table pointer offset is relative to the binding table
pool base address when resource streamer instead of the surface state base address.
v2: Fix possible buffer overflow when allocating a chunk out of the
hw-binding table pool (Ken).
v3: Remove extra newline and add missing brace around if-statement (Matt).
v4: Fix broken INTEL_DEBUG=shader_time for hw-generated binding tables.
Document PRM WaStateBindingTableOverfetch workaround.
Cc: kenneth at whitecape.org
Cc: mattst88 at gmail.com
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
commit 2133980bc7dff52bdeb142301184e464d113ce7c
Author: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
Date: Fri Jul 17 12:20:18 2015 +0300
i965: Implement interface to edit binding table entries
Unlike normal software binding tables where the driver has to manually
generate and fill a binding table array which are then uploaded to the
hardware, the resource streamer instead presents the driver with an option
to fill out slots for individual binding table indices. The hardware
accumulates the state for these combined edits which it then automatically
flushes to a binding table pool when the binding table pointer state
command is invoked.
v2: Clarify binding table edit bit aligment (Topi).
v3: Make comments and function names more clearer (Ken).
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
commit 190756482e62cb57e2bc8c798181e5f0171726fb
Author: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
Date: Wed Apr 15 13:04:45 2015 +0300
i965: Enable hardware-generated binding tables on render path.
This patch implements the binding table enable command which is also
used to allocate a binding table pool where where hardware-generated
binding table entries are flushed into. Each binding table offset in
the binding table pool is unique per each shader stage that are
enabled within a batch.
Also insert the required brw_tracked_state objects to enable
hw-generated binding tables in normal render path.
v2: - Use MOCS in binding table pool alloc for GEN8
- Fix spurious offset when allocating binding table pool entry
and start from zero instead.
v3: - Include GEN8 fix for spurious offset above.
v4: - Fixup wrong packet length in enable/disable hw-binding table
for GEN8 (Ville).
- Don't invoke HW-binding table disable command when we dont
have resource streamer (Chris).
v5: - Reorder the state cache invalidate flush so it happens in-between
enabling hw-generated binding tables and the previous sw-binding
table GPU state (Chris).
v6: - Do the same fix in v5 for gen7_disable_hw_binding_tables().
- Adhere to coding guidelines and make comments more informative.
Cc: kenneth at whitecape.org
Cc: syrjala at sci.fi
Cc: chris at chris-wilson.co.uk
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
commit 090529af1828817344e0850ef27eebd1f096eb5f
Author: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
Date: Tue Jul 2 11:48:22 2013 -0400
i965: Enable resource streamer for the batchbuffer
Check first if the hardware and kernel supports resource streamer. If this
is allowed, tell the kernel to enable the resource streamer enable bit on
MI_BATCHBUFFER_START by specifying I915_EXEC_RESOURCE_STREAMER
execbuffer flags.
v2: - Use new I915_PARAM_HAS_RESOURCE_STREAMER ioctl to check if kernel
supports RS (Ken).
- Add brw_device_info::has_resource_streamer and toggle it for
Haswell, Broadwell, Cherryview, Skylake, and Broxton (Ken).
v3: - Update I915_PARAM_HAS_RESOURCE_STREAMER to match updated kernel.
v4: - Always inspect the getparam.value (Chris Wilson).
v5: - Fold redundant devinfo->has_resource_streamer check in context create
into init screen.
Cc: kenneth at whitecape.org
Cc: chris at chris-wilson.co.uk
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
commit ccf9598ad7681f5c9c87e9ca8bf856fcb5198b45
Author: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
Date: Mon May 18 14:32:17 2015 +0300
i965: Define HW-binding table and resource streamer control opcodes
v2: Use macros for HW binding table edits (Topi)
v3: Add Broadwell support.
v4: Make hardware binding table bit definitions even more clearer (Ken)
Cc: kenneth at whitecape.org
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
commit ff7896a398f55baefd00e695c8f45f2ffa57bceb
Author: Eric Anholt <eric at anholt.net>
Date: Fri Jul 17 10:01:48 2015 -0700
vc4: Switch to using a separate ioctl for making shaders.
This gives the kernel a chance to validate and lock down the data,
without having to deal with mmap zapping.
With this, GLBenchmark stops on a texture relocations, because we'd
recycled a shader BO as another shader and failed to revalidate, since we
weren't clearing the cached validation state on mmap faults.
commit e42cfe5d032e97e0444df39421a9f93f84452d68
Author: Roland Scheidegger <sroland at vmware.com>
Date: Fri Jul 17 18:01:01 2015 +0200
mesa: fix up some texture error checks
In particular, we were incorrectly accepting s3tc (and lots of others)
for CompressedTexSubImage3D (but not CompressedTexImage3D) calls with 3d
targets. At this time, the only allowed formats for these calls are the
bptc ones, since none of the specific extensions allow it (astc hdr would).
Also, fix up a bug in _mesa_target_can_be_compressed - 3d target needs to
be allowed for bptc formats.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 27aa31fab40783356207ba5dabd839b430496e7b
Author: Eric Anholt <eric at anholt.net>
Date: Fri Jul 17 11:52:09 2015 -0700
vc4: Fix printing of shader-db debug when shader-db isn't turned on.
commit 5341349dde6f5c70af188e48ef0082e6e7d5361f
Author: Eric Anholt <eric at anholt.net>
Date: Fri Jul 17 11:22:40 2015 -0700
vc4: Add debugging on texture relocation validation failures.
commit be7adc2ecad0d04037cb0c99754703dde86ee73a
Author: Eric Anholt <eric at anholt.net>
Date: Thu Jul 16 14:30:28 2015 -0700
vc4: Also consider uniform 0 in uniform lowering.
The hash table considers key 0 to be the empty key.
commit 90dfabc3b5ce5b485a1bbcd7e815a72588f7153d
Author: Eric Anholt <eric at anholt.net>
Date: Fri Jul 10 16:30:27 2015 -0700
vc4: Use the pure/const attributes on a bunch of our QPU functions.
On a release build, this makes the rest of vc4_qpu_validate.c go away
(the compiler didn't know that our qpu helper function calls had no
side effects).
commit be1f49bda90425b7fd009ac177b307e61da0f994
Author: Eric Anholt <eric at anholt.net>
Date: Fri Jul 10 16:25:26 2015 -0700
mesa: Detect and provide macros for function attributes pure and const.
These are really useful hints to the compiler in the absence of link-time
optimization, and I'm going to use them in VC4.
I've made the const attribute be ATTRIBUTE_CONST unlike other function
attributes, because we have other things in the tree #defining CONST for
their own unrelated purposes.
v2: Alphabetize.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org> (v1)
commit bde4c8ec1fd69e312fe21e36c8ce07139916811a
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Tue Jun 30 13:42:15 2015 -0700
i965/fs: don't make unused payload registers interfere
Before, we were setting payload_last_use_ip for unused payload
registers to 0, which made them interfere with whatever the first
instruction wrote to due to the workaround for SIMD16 uniform arguments.
Just use -1 to mean "unused" instead, and then skip setting any
interferences for unused payload registers.
instructions in affected programs: 0 -> 0
helped: 0
HURT: 0
GAINED: 1
LOST: 0
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Signed-off-by: Connor Abbott <connor.w.abbott at intel.com>
commit 18e73bf7f8b12022e02db3230ee109657581900b
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Tue Jun 30 13:38:20 2015 -0700
i965/fs: remove special case in setup_payload_interference()
regs_read() will handle LINTERP for us since the previous commit. In
addition, we were being too conservative, since it will only read 2
registers on SIMD8.
instructions in affected programs: 9061 -> 8893 (-1.85%)
helped: 10
HURT: 0
GAINED: 0
LOST: 0
All of the changes were due to spills being eliminated, mostly in KSP
shaders.
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Signed-off-by: Connor Abbott <connor.w.abbott at intel.com>
commit c4a2217e79ac78c59cec3eb97542ceb819f92a44
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Mon Feb 2 14:23:35 2015 -0800
i965/fs: Mark last used ip for all regs read in the payload
If a source register in the push constant registers uses more than one
register, then we wouldn't update payload_last_use_ip for subsequent
registers.
Unlike most uniform data pushed into registers, the CS gl_LocalInvocationID
data varies per execution channel. Therefore for SIMD16 mode, we have vec16
data in the payload. In this case we then need to mark 2 registers in
payload_last_use_ip as last used by the instruction. There's a similar
situation for the z and w coordinates of gl_FragCoord for fragment shaders,
where it had only happened to work before because of some bogus interferences
which the next commit removes.
(Connor: added bit about gl_FragCoord to commit message)
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Connor Abbott <connor.w.abbott at intel.com>
commit 9f344b908a95440d215f29c0b05b8ea8dba2839e
Author: Connor Abbott <connor.w.abbott at intel.com>
Date: Wed Jul 1 09:58:47 2015 -0700
i965/fs: fix regs_read() for LINTERP
The second source always stays within the same SIMD8 register.
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Signed-off-by: Connor Abbott <connor.w.abbott at intel.com>
commit eaf799ddff9f2583d6dee5a0db36fa0a1162fde6
Author: Connor Abbott <connor.w.abbott at intel.com>
Date: Wed Jul 15 12:01:20 2015 -0700
nir: add nir_foreach_instr_safe_reverse()
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Signed-off-by: Connor Abbott <connor.w.abbott at intel.com>
commit 8eea091747c9b12b21688b738145632b90d923cb
Author: Connor Abbott <connor.w.abbott at intel.com>
Date: Wed Jul 15 12:00:47 2015 -0700
nir: add nir_instr_is_first() and nir_instr_is_last() helpers
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Signed-off-by: Connor Abbott <connor.w.abbott at intel.com>
commit 01cdbba341b47972a743e7f192d3554010d0da84
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Thu Jul 16 15:07:05 2015 -0700
i965/cs: Use dispatch width of 8 for cs terminate payload setup
This prevents an assertion failure in brw_fs_live_variables.cpp,
fs_live_variables::setup_one_write: Assertion `var < num_vars' failed.
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 7e337859ff98a0caf00fd201a5389933d42d0baa
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Thu Jul 16 15:04:43 2015 -0700
i965/cs: Return 1 for regs_read on CS_OPCODE_CS_TERMINATE
This prevents an assertion failure in brw_fs_live_variables.cpp,
fs_live_variables::setup_one_read: Assertion `var < num_vars' failed.
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 4b17f0d9f58637300b0748d1fb702a7e4d51979f
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Jul 4 19:15:16 2015 -0700
program: Allow redundant OPTION ARB_fog_* directives.
A fragment program from "Pixel Piracy" contains redundant OPTION
directives:
!!ARBfp1.0
OPTION ARB_precision_hint_fastest;
OPTION ARB_fog_exp2;
OPTION ARB_precision_hint_fastest;
OPTION ARB_fog_exp2;
...
We already allow redundant ARB_precision_hint_fastest directives, but
disallow the redundant (yet consistent) ARB_fog_exp2 directives, failing
to compile the program.
The specification seems to contradict itself - the main text says that
only one fog application option may be specified, but then backpedals,
indicating the intent is to disallow /contradictory/ flags. One of the
issues suggests that specifying contradictory ones is stupid, but
allowed, and only the last one should take effect.
Accepting multiple redundant (but consistent) directives seems harmless,
and like a reasonable interpretation of the specification. It also
fixes a fragment program found in the wild.
Cc: mesa-stable at lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 3a31876600cb5c4d90c998ecb5635c602eeb2bd1
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Tue Jul 14 09:56:09 2015 -0700
i965: Push miptree tiling request into flags
With the last few patches a way was provided to influence lower layer miptree
layout and allocation decisions via flags (replacing bools). For simplicity, I
chose not to touch the tiling requests because the change was slightly less
mechanical than replacing the bools.
The goal is to organize the code so we can continue to add new parameters and
tiling types while minimizing risk to the existing code, and not having to
constantly add new function parameters.
v2: Rebased on Anuj's recent Yf/Ys changes
Fix non-msrt MCS allocation (was only happening in gen8 case before)
v3: small fix in assertion requested by Chad
v4: Use parens to get the order right from v3.
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit ef42352ff4e1feeea7338db73f540038c6755472
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Thu Jul 16 16:52:08 2015 -0700
Revert "i965: Push miptree tiling request into flags"
This reverts commit 51e8d549e110f86cb7107cf712843aebd956fb9a.
commit 51e8d549e110f86cb7107cf712843aebd956fb9a
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Tue Jul 14 09:56:09 2015 -0700
i965: Push miptree tiling request into flags
With the last few patches a way was provided to influence lower layer miptree
layout and allocation decisions via flags (replacing bools). For simplicity, I
chose not to touch the tiling requests because the change was slightly less
mechanical than replacing the bools.
The goal is to organize the code so we can continue to add new parameters and
tiling types while minimizing risk to the existing code, and not having to
constantly add new function parameters.
v2: Rebased on Anuj's recent Yf/Ys changes
Fix non-msrt MCS allocation (was only happening in gen8 case before)
v3: small fix in assertion requested by Chad
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com> (v2)
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com> (v2)
Reviewed-by: Chad Versace <chad.versace at intel.com> (v2)
commit 4bddd82bf3dae44c2b75cef34e9e85e15d63df7f
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue Jul 14 15:43:44 2015 +0300
i965/fs: Factor out universally broken calculation of the register component size.
This in principle simple calculation was being open-coded in a number
of places (in a series I haven't yet sent for review there will be a
couple more), all of them were subtly broken in one way or another:
None of them were handling the HW_REG case correctly as pointed out by
Connor, and fs_inst::regs_read() was handling the stride=0 case rather
naively. This patch solves both problems and factors out the
calculation as a new fs_reg method.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit b00cd6e4a0f9a84d514f428428be348900236e2e
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Jul 9 21:42:28 2015 +0300
i965: Implement nir_op_uadd_carry and _usub_borrow without accumulator.
This gets rid of two no16() fall-backs and should allow better
scheduling of the generated IR. There are no uses of usubBorrow() or
uaddCarry() in shader-db so no changes are expected. However the
"arb_gpu_shader5/execution/built-in-functions/fs-usubBorrow" and
"arb_gpu_shader5/execution/built-in-functions/fs-uaddCarry" piglit
tests go from 40 to 28 instructions. The reason is that the plain ADD
instruction can easily be CSE'ed with the original addition, and the
b2i negation can easily be propagated into the source modifier of
another instruction, so effectively both operations are performed with
just one instruction.
v2: Rely on carry_to_arith() and borrow_to_arith() to lower these
(Ilia Mirkin).
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 3ee2daf23dc91b8dfc017b5c89c10ab1376ba4df
Author: Francisco Jerez <currojerez at riseup.net>
Date: Fri Jul 10 19:18:39 2015 +0300
i965: Implement b2f and b2i using negation.
Booleans are represented as 0/-1 on modern hardware which means we can
just negate them to convert them into a numeric type. Negation has
the benefit that it can be implemented using a source modifier which
can easily be propagated into some other instruction. shader-db
results on HSW:
total instructions in shared programs: 6349082 -> 6346693 (-0.04%)
instructions in affected programs: 40948 -> 38559 (-5.83%)
helped: 123
HURT: 1
GAINED: 1
LOST: 0
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 8fba933ca2dd3c3487281135a9063b6ca9bed359
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Jul 5 15:00:22 2015 +0200
gallium: add interface for writable shader buffers
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 05a12c53a308965aba1c00f0caf36d8e0f32e035
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Jul 5 14:48:33 2015 +0200
gallium: add interface for writable shader images
PIPE_CAPs will be added some other time.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit b73bec0ecd43861337daf9663e242d2b44f36dbd
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Jul 5 14:34:13 2015 +0200
gallium: add new limits for shader buffers and images
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit f9f79d29ce75c681c46bdbac5aa3f19ee1adb93b
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Jul 5 13:51:16 2015 +0200
gallium: add BIND flags for R/W buffers and images
PIPE_CAPs and TGSI support will be added later. The TGSI support should be
straightforward. We only need to split TGSI_FILE_RESOURCE into TGSI_FILE_IMAGE
and TGSI_FILE_BUFFER, though duplicating all opcodes shouldn't be necessary.
The idea is:
* ARB_shader_image_load_store should use set_shader_images.
* ARB_shader_storage_buffer_object should use set_shader_buffers(slots 0..M-1)
if M shader storage buffers are supported.
* ARB_shader_atomic_counters should use set_shader_buffers(slots M..N)
if N-M+1 atomic counter buffers are supported.
PIPE_CAPs can describe various constraints for early DX11 hardware.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 26222932c013da3688e39dc831179659cc65c39a
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Jun 12 14:24:17 2015 +0200
gallium: add PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit af768922cafa3eb3e78a2fdfee90380a74c79460
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jul 1 16:32:24 2015 +0300
i965/gen9: Use custom MOCS entries set up by the kernel.
Instead of relying on hardware defaults the i915 kernel driver is
going program custom MOCS tables system-wide on Gen9 hardware. The
"WT" entry previously used for renderbuffers had a number of problems:
It disabled caching on eLLC, it used a reserved L3 cacheability
setting, and it used to override the PTE controls making renderbuffers
always WT on LLC regardless of the kernel's setting. Instead use an
entry from the new MOCS tables with parameters: TC=LLC/eLLC, LeCC=PTE,
L3CC=WB.
The "WB" entry previously used for anything other than renderbuffers
has moved to a different index in the new MOCS tables but it should
have the same caching semantics as the old entry.
Even though the corresponding kernel change ("drm/i915: Added
Programming of the MOCS") is in a way an ABI break it doesn't seem
necessary to check that the kernel is recent enough because the change
should only affect Gen9 which is still unreleased hardware.
v2: Update MOCS values for the new Android-incompatible tables
introduced in v7 of the kernel patch.
Cc: 10.6 <mesa-stable at lists.freedesktop.org>
Reference: http://lists.freedesktop.org/archives/intel-gfx/2015-July/071080.html
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit 7e0180d57d330bd8d3047e841086712376b2a1cc
Author: EdB <edb+mesa at sigluy.net>
Date: Tue Jul 7 17:58:56 2015 +0200
clover: little OpenCL status code logging clean
s/build_error/compile_error in order to match the stored OpenCL status code.
Make program::build catch and log every OpenCL error.
Make tgsi error triggering uniform with the llvm one.
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 7b9ebf879b6f35038996805a641667f00d93c4b7
Author: Renaud Gaubert <renaud at lse.epita.fr>
Date: Sat Jul 11 19:38:10 2015 +0200
glsl: avoid compiler's segfault when processing operators with void arguments
This is done by returning an rvalue of type void in the
ast_function_expression::hir function instead of a void expression.
This produces (in the case of the ternary) an hir with a call
to the void returning function and an assignment of a void variable
which will be optimized out (the assignment) during the optimization
pass.
This fix results in having a valid subexpression in the many
different cases where the subexpressions are functions whose
return values are void.
Thus preventing to dereference NULL in the following cases:
* binary operator
* unary operators
* ternary operator
* comparison operators (except equal and nequal operator)
Equal and nequal had to be handled as a special case because
instead of segfaulting on a forbidden syntax it was now accepting
expressions with a void return value on either (or both) side of
the expression.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85252
Signed-off-by: Renaud Gaubert <renaud at lse.epita.fr>
Reviewed-by: Gabriel Laskar <gabriel at lse.epita.fr>
Reviewed-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
commit 779cabfc7d022de8b7b9bc7fdac0caffa8646c51
Author: Roland Scheidegger <sroland at vmware.com>
Date: Thu Jul 16 03:55:59 2015 +0200
r200: fix some potential big endian issues
The formats chosen (both by texture format choser, fbo storage allocation)
are different for big endian not just for rgba8 but also lower bit width
formats (why I don't actually know). Even the function to test for renderable
formats used different formats, however the actual colorbuffer setup did not.
And the blitter did not take that into account neither.
Untested (what could possibly go wrong...).
Same as for r100.
Acked-by: Marek Olšák <marek.olsak at amd.com>
commit d21320f6258b2e1780a15c1ca718963d8a15ca18
Author: Roland Scheidegger <sroland at vmware.com>
Date: Thu Jul 16 03:18:20 2015 +0200
radeon: fix some potential big endian issues
The formats chosen (both by texture format choser, fbo storage allocation)
are different for big endian not just for rgba8 but also lower bit width
formats (why I don't actually know). Even the function to test for renderable
formats used different formats, however the actual colorbuffer setup did not.
And the blitter did not take that into account neither.
Untested (what could possibly go wrong...).
Acked-by: Marek Olšák <marek.olsak at amd.com>
commit 882476fea3ba4fdd05d21582eeb968f84523fb9a
Author: Roland Scheidegger <sroland at vmware.com>
Date: Sat Jul 11 20:03:27 2015 +0200
radeon/r200: mark state atoms as dirty after blits
Blit submits lots of packets which are usually handled by state atoms, so
these must be dirtied.
Not sure if this fixes anything, but it was a concern raised by bug 51658
(with this all issues there seen as actual bugs should be fixed, with the
exception of the patch to upload non-used texenv state atoms which I just
don't understand).
Acked-by: Marek Olšák <marek.olsak at amd.com>
commit 26c1361ac386bd5b108d79289a3f82d15b01d014
Author: Roland Scheidegger <sroland at vmware.com>
Date: Thu Jul 16 03:06:47 2015 +0200
r200: fix fbo rendering by disabling optimized texture format chooser
It is rather unfortunate that we don't know if a texture is going to be used
as a rt later, and we lack the means to do something about a format chosen
which we can't render to directly, so disable this and always chose renderable
format for rgba8 textures.
This addresses an issue raised on (old) bug,
https://bugs.freedesktop.org/show_bug.cgi?id=51658 with gnome-shell, don't
know if that's still applicable but it might fix other things as well.
Acked-by: Marek Olšák <marek.olsak at amd.com>
commit 642f289824dc9a07e8209c905badef31b4841ae1
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Tue Jul 7 12:23:33 2015 -0700
i965: Fix 32 bit build warnings in intel_get_yf_ys_bo_size()
Along with fixing the type of pitch parameter, patch also changes
the types of few local variables and function return type.
Warnings fixed are:
intel_mipmap_tree.c:671:7: warning: passing argument 3 of
'intel_get_yf_ys_bo_size' from incompatible pointer type
intel_mipmap_tree.c:563:1: note: expected 'uint64_t *' but
argument is of type 'long unsigned int *'
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit f11c6f09cf36909ff399353b20195a31cf0f1907
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Jul 8 19:00:48 2015 -0700
i965: Optimize batchbuffer macros.
Previously OUT_BATCH was just a macro around an inline function which
does
brw->batch.map[brw->batch.used++] = dword;
When making consecutive calls to intel_batchbuffer_emit_dword() the
compiler isn't able to recognize that we're writing consecutive memory
locations or that it doesn't need to write batch.used back to memory
each time.
We can avoid both of these problems by making a local pointer to the
next location in the batch in BEGIN_BATCH().
Cuts 18k from the .text size.
text data bss dec hex filename
4946956 195152 26192 5168300 4edcac i965_dri.so before
4928956 195152 26192 5150300 4e965c i965_dri.so after
This series (including commit c0433948) improves performance of Synmark
OglBatch7 by 8.01389% +/- 0.63922% (n=83) on Ivybridge.
Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
commit 131573df7aea0b10e97d9d5db0d26d89f8dfef54
Author: Matt Turner <mattst88 at gmail.com>
Date: Sat Jul 11 14:36:25 2015 -0700
i965: Add and use USED_BATCH macro.
The next patch will replace the .used field with an on-demand
calculation of batchbuffer usage.
Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
commit 09348c12fceba59c22219fe3272260eb8ea6051e
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Jul 8 18:59:51 2015 -0700
i965: Split batch emission from relocation functions.
So that everything writing to the batch between BEGIN_BATCH() and
ADVANCE_BATCH() goes through OUT_BATCH.
Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
commit fbf3aebf1f33fbec559c5b69bdf3b5dec6031612
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Jul 8 18:56:52 2015 -0700
i965: Move BEGIN_BATCH() into same control flow as ADVANCE_BATCH().
BEGIN_BATCH() and ADVANCE_BATCH() will contain "do {" and "} while (0)"
respectively to allow declaring local variables used by intervening
OUT_BATCH macros. As such, BEGIN_BATCH() and ADVANCE_BATCH() need to be
in the same control flow.
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
commit 141e1eb29fe80ad341e718147a1277cc3b1b9c11
Author: Brian Paul <brianp at vmware.com>
Date: Wed Jul 15 06:15:06 2015 -0600
osmesa: fix OSMesaPixelsStore typo
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91337
Cc: 10.6 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 7124feba1b879deb88dbf2baf600ed42309d9839
Author: Eric Anholt <eric at anholt.net>
Date: Tue Jul 14 12:32:04 2015 -0700
vc4: Cache the texture p1 for the sampler.
Cuts another 12% of vc4_uniforms.o, in exchange for computing it at
CSO creation time.
commit 0f4d2b0a2dd3fa39426f2789bf2a8fc939adf001
Author: Eric Anholt <eric at anholt.net>
Date: Tue Jul 14 12:18:40 2015 -0700
vc4: Cache texture p0/p1 setup for the sampler view.
In exchange for a bit of space and computation in CSO setup, we cut
vc4_uniform.c (draw time) code size by 4.8%.
commit 1835ce6e35e6a186c2ba1bdf39b73783a2cb2ad5
Author: Eric Anholt <eric at anholt.net>
Date: Tue Jul 14 12:21:23 2015 -0700
vc4: Move uniforms handling to a separate file.
The rest of vc4_program.c is about compiling, while this is about
uniform emit at draw time.
commit 9476b11d6edc67403dd7c5aaddbc375400e02425
Author: Eric Anholt <eric at anholt.net>
Date: Tue Jul 14 11:54:15 2015 -0700
vc4: Fix some -Wdouble-promotion warnings.
No code generation changes from this, but it'll be useful to have this
next time I go checking -Wdouble-promotion.
commit 320089dbd63de3ac1bd3d42ee8cec41837486d8c
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Thu Jun 11 19:17:03 2015 -0700
i965/cs: Initialize GPGPU Thread Count
This field should always be set for gen8. In the bdw PRM, Volume 2d:
Command Reference: Structures under INTERFACE_DESCRIPTOR_DATA, DWORD
6, Bits 9:0, Number of Threads in GPGPU Thread Group:
"This field should not be set to 0 even if the barrier is disabled,
since an accurate value is needed for proper pre-emption."
In the HSW PRM, the it doesn't mention that it must always be set, but
it should not hurt.
Reported-by: Kristian Høgsberg <krh at bitplanet.net>
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit cd7dd45bfec9ad68719c5e4e04b66ea4bcc1a2c1
Author: Eric Anholt <eric at anholt.net>
Date: Fri Jul 10 17:00:34 2015 -0700
vc4: Fix compiler warnings on release builds.
commit 1e80c9fab98d7de216937a47f8e231f3beb78403
Author: Eric Anholt <eric at anholt.net>
Date: Fri Jul 10 17:01:37 2015 -0700
vc4: Add better debug for register allocation failure.
commit 3df78928786134874eafa6f68186c8edbbdd3ae7
Author: Eric Anholt <eric at anholt.net>
Date: Fri Jul 10 16:11:23 2015 -0700
vc4: Drop reloc_count tracking for debug asserts on non-debug builds.
Cuts another 88 bytes of compiled code.
commit 7432017f65174e82a3de7afef3e4e6f60932356c
Author: Eric Anholt <eric at anholt.net>
Date: Thu Jul 9 22:51:06 2015 -0700
vc4: Rework cl handling to be friendlier to the compiler.
Drops 680 bytes of code, from avoiding a bunch of extra updates to the
next pointer in the struct.
commit a0d3915663fb7cbd3c1a5561450e256e00ecf11b
Author: Eric Anholt <eric at anholt.net>
Date: Fri Jul 10 14:46:42 2015 -0700
vc4: Make a helper function for getting the current offset in the CL.
I needed to rewrite this a bit for safety checking in the next commit.
Despite being a static inline of the same thing that was being done, we
lose 36 bytes of code for some reason.
commit 748bf459b46b44e184ee1d425ce612da61a0800e
Author: Eric Anholt <eric at anholt.net>
Date: Thu Jul 9 22:48:17 2015 -0700
vc4: Drop separate cl*_reloc_hindex().
Now that RCL generation is in the kernel, we don't have any other
callers. Oddly, the compiler generates another 8 bytes of code for
this, but the simplification is worth it.
commit e4c540f6d09390013a9cb66060a29f236ad7dcfc
Author: Eric Anholt <eric at anholt.net>
Date: Thu Jul 9 22:42:22 2015 -0700
vc4: Store reloc pointers as pointers, not offsets.
Now that we don't resize the CL as we build (it's set up at the top by
vc4_start_draw()), we can store the pointers instead of offsets from
the base. Saves a bit of math in emitting relocs (about 60 bytes of
code).
commit ab80519b3cd08401dff2d07343064a27f32b33ca
Author: Eric Anholt <eric at anholt.net>
Date: Mon Jun 29 22:32:03 2015 -0700
vc4: Add perf debug for when we wait on BOs.
commit 759ed0bd03818c912e7f1fa62bafc50ef52ef291
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Jul 13 15:40:41 2015 -0700
i965: Mark constant static data as const.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit ea633db65ffa684ea5237b8cb5bd96fbc1a7769a
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Wed Jul 8 17:30:44 2015 +0200
glsl: Lower shader storage buffer object loads to GLSL IR instrinsics
Extend the existing lower_ubo_reference pass to also detect SSBO loads
and lower them to __intrinsic_load_ssbo intrinsics.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 1966ea57728a1c05300982ddd83de989e363613c
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Wed Jul 8 17:03:06 2015 +0200
glsl: Lower shader storage buffer object writes to GLSL IR instrinsics
Extend the existing lower_ubo_reference pass to also detect SSBO writes
and lower them to __intrinsic_store_ssbo intrinsics.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 2a66ee6fc1fa1e64f2d9a22271187d4462d9e042
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Fri Apr 24 11:17:15 2015 +0200
glsl: Don't do copy propagation on buffer variables
Since the backing storage for these is shared we cannot ensure that
the value won't change by writes from other threads. Normally SSBO
accesses are not guaranteed to be syncronized with other threads,
except when memoryBarrier is used. So, we might be able to optimize
some SSBO accesses, but for now we always take the safe path and emit
the SSBO access.
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 5dfea83ee6bf85fb3962679d043eb06b33bfd4c1
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Fri Apr 24 11:15:48 2015 +0200
glsl: Don't do constant variable on buffer variables
Since the backing storage for these is shared we cannot ensure that
the value won't change by writes from other threads. Normally SSBO
accesses are not guaranteed to be syncronized with other threads,
except when memoryBarrier is used. So, we might be able to optimize
some SSBO accesses, but for now we always take the safe path and emit
the SSBO access.
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 0b1111d985714816fad20c99b4e6ea762df17b46
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Fri Apr 24 11:14:17 2015 +0200
glsl: Don't do constant propagation on buffer variables
Since the backing storage for these is shared we cannot ensure that
the value won't change by writes from other threads. Normally SSBO
accesses are not guaranteed to be syncronized with other threads,
except when memoryBarrier is used. So, we might be able to optimize
some SSBO accesses, but for now we always take the safe path and emit
the SSBO access.
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 5360ff30c4de966422fde6a574e3959c81bf5037
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Mon Apr 6 10:19:50 2015 +0200
glsl: Do not kill dead assignments to buffer variables or SSBO declarations.
If we kill dead assignments we lose the buffer writes.
Also, we never kill UBO declarations even if they are never referenced
by the shader, they are always considered active. Although the spec
does not seem say this specifically for SSBOs, it is probably implied
since SSBOs are pretty much the same as UBOs, only that you can write
to them.
v2:
- Fix the comment (Jordan)
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 3ad92589f29466383c0218aa4a73bff52019c4be
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Mon Apr 6 09:37:58 2015 +0200
glsl: Don't do tree grafting on buffer variables
Otherwise we can lose writes into the buffers backing the variables.
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 173ed05a6d9e851b2b7b2f9f2d8993e5da115c40
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Thu Mar 19 11:42:33 2015 +0100
mesa: Implement _mesa_BindBufferRange for target GL_SHADER_STORAGE_BUFFER
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 8a1d58bd6129d61ec4efb79cc6f2b61ac777b85b
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Thu Mar 19 11:37:43 2015 +0100
mesa: Implement _mesa_BindBufferBase for target GL_SHADER_STORAGE_BUFFER
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 7b0d0a2bf2d147c6024ff1a4b1eaaad955e7d297
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Thu Mar 19 11:21:52 2015 +0100
mesa: Implement _mesa_BindBuffersRange for target GL_SHADER_STORAGE_BUFFER
v2:
- Fix error message (Jordan)
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 0aa83f3e90a5ca547593631bc1557412e5305bdd
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Thu Mar 19 10:47:17 2015 +0100
mesa: Implement _mesa_BindBuffersBase for target GL_SHADER_STORAGE_BUFFER
v2:
- Add space before const (Jordan)
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit e72f5ef50211c3ce31abaab4ed1bf82df2884157
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Thu Mar 19 10:31:23 2015 +0100
mesa: Implement _mesa_DeleteBuffers for target GL_SHADER_STORAGE_BUFFER
v2:
- Remove the extra spaces (Jordan)
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 98a1a2c7302526d649a727d63400407727d7aad9
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Thu Mar 19 11:50:51 2015 +0100
mesa: Initialize and free shader storage buffers
v2:
- Fix indention, used tabs instead of whitespaces. (Jordan)
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 2747d566f187cdab5d6bdc508e460a76e5cbd6c4
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Thu Mar 19 10:22:00 2015 +0100
glsl: fix error messages in invalid declarations of shader storage blocks
Due to GL_ARB_shader_storage_buffer_object extension, shader storage blocks
have the same limitations as uniform blocks.
This patch fixes the corresponding error messages.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 9f651dbf7924938a8aa2c9c940ae3ed1366d6198
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Wed Mar 18 10:52:53 2015 +0100
glsl: buffer variables cannot be defined outside interface blocks
Section 4.3.7 "Buffer Variables", GLSL 4.30 spec:
"Buffer variables may only be declared inside interface blocks
(section 4.3.9 “Interface Blocksâ€), which are then referred to as
shader storage blocks. It is a compile-time error to declare buffer
variables at global scope (outside a block)."
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 20b2907db7b93656cbafe1d24302498e5817dbe2
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Wed Mar 18 10:25:10 2015 +0100
glsl: shader buffer variables cannot have initializers
Section 4.3.7 "Buffer Variables" of the GLSL 4.30 spec:
"Buffer variables cannot have initializers."
v2:
- Rewrite error message (Jordan)
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit fa0a86c057ac9bff9b208f93db75c5ce5bd7136f
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Wed Mar 18 09:02:51 2015 +0100
glsl: enable binding layout qualifier usage for shader storage buffer objects
See GLSL 4.30 spec, section 4.4.5 "Uniform and Shader Storage Block
Layout Qualifiers".
v2:
- Add whitespace in an error message. Delete period '.' at the end of that
error message (Jordan).
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit c717604dc4b5119fa9091241535c3efd1370438c
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Thu May 14 12:37:07 2015 +0200
mesa: add MaxShaderStorageBlocks to struct gl_program_constants
v2:
- Set MaxShaderStorageBlocks to 8.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit cd50906e0334d7ad0102e5733a152d55d672776b
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Thu Mar 19 10:15:30 2015 +0100
mesa: Add shader storage buffer support to struct gl_context
This includes the array of bindings, the current buffer bound to the
GL_SHADER_STORAGE_BUFFER target and a set of general limits and default
values for shader storage buffers.
v2:
- Use spec values for the new defined constants (Jordan)
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit df89ed1591c9d1c55e79fe8effb976c21b172a7d
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Mon Mar 23 11:19:12 2015 +0100
glsl: Identify active uniform blocks that are buffer blocks as such.
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit a78a589efc5440443439d474e45fa1ef8b79178c
Author: Kristian Høgsberg <krh at bitplanet.net>
Date: Wed May 13 11:17:23 2015 +0200
glsl: link buffer variables and shader storage buffer interface blocks
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 84fc5fece006f2bd95287496e32482ac08bfd399
Author: Kristian Høgsberg <krh at bitplanet.net>
Date: Wed May 13 10:53:46 2015 +0200
glsl: Implement parser support for 'buffer' qualifier
This is used to identify shader storage buffer interface blocks where
buffer variables are declared.
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 6b09598d63b8b6069b230fbe8283c75cf86f711a
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Mon May 18 15:47:18 2015 +0200
nir: add nir_var_shader_storage
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 1146696f75ea0f2b49e6379c2a62602dfeb51190
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Fri Jun 5 09:11:53 2015 +0200
mesa: rename is_in_uniform_block to is_in_buffer_block
Since this now checks if a variable is inside a uniform or a shader
storage block.
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 18feaa8f36b311c443fd56666507ec1768fb9582
Author: Kristian Høgsberg <krh at bitplanet.net>
Date: Wed May 13 10:41:55 2015 +0200
glsl: Add ir_var_shader_storage
This will be used to identify buffer variables inside shader storage
buffer objects, which are very similar to uniforms except for a few
differences, most important of which is that they are writable.
Since buffer variables are so similar to uniforms, we will almost always
want them to go through the same paths as uniforms.
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 3095ee9b8bd4154cc63b6332c21b16954555e241
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Tue Mar 17 12:17:27 2015 +0100
mesa: define ARB_shader_storage_buffer_object extension
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 75df8f00192415eb4ad378708ff3745390931b4e
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Tue Jul 14 07:41:26 2015 +1000
glsl: free interface_types
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 431a0658616575953868f6d16bb9641306cceea8
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Tue Jul 14 07:37:59 2015 +1000
glsl: replace some more old hash_table uses
The util/hash_table was intended to be a fast hash table
replacement for the program/hash_table see 35fd61bd99c1 and 72e55bb6888ff.
This change replaces some more uses of the old hash table.
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 7a50bf6c7f7729f5eee3ddf7aa9b38a81873f2c6
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Jul 10 21:27:13 2015 +0100
auxiliary/vl: use the correct screen index
Inspired (copied) from Marek's commit for egl/x11
commit 0b56e23e7f3(egl/dri2: use the correct screen index)
v2: Fix copy/pasta errors.
Cc: 10.6 <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 10a7b579fdc0e3f3b38920ae5c103c058cc63eec
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Tue Jul 7 14:44:11 2015 +0100
radeon: remove dri_mirror state
Most of the data stored(duplicated) was unused, and for the one that is
follow the approach set by other drivers.
This eliminates the use of legacy (dri1) types.
Cc: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 82b9b2e523ad53f54d5620f47f7aea4f11397b81
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Tue Jul 7 14:13:33 2015 +0100
i915: remove unused driFd variable
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit a025e539e430b7bbfae9b786bd79d0d608f1acf8
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Jul 6 09:42:01 2015 +0100
i965: bump libdrm requirement to 2.4.61 and drop in-tree workaround
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit c505064b2cea14c9da115a26e9326b9c0c7dca3b
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Jul 13 20:01:39 2015 +0100
bugzilla_mesa.sh: sort the bugs list by number
v2: Use change sed/sort based on Ilia's suggestion.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 9027d53b2a00b3073f904cc3cb995e8953e41036
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Tue Jun 30 14:37:19 2015 +0100
radeonsi: directly include radeon/* headers
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit dd50ccf0f4dcba2fd586d5b5c58750259e29c357
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Jun 29 14:03:22 2015 +0100
auxiliary/vl: use loader_open_device() over open()
The former handles O_CLOEXEC (and the lack of it) appropriately.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit cc32d25454c382a971e81ae584a4296fdf492e70
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Jun 29 14:01:39 2015 +0100
pipe-loader: use loader_open_device() rather than open()
The former handles O_CLOEXEC (and the lack of it) appropriately.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 132031b110a9fd652f3c9d5727502134ef9c22c1
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Jun 29 13:28:33 2015 +0100
pipe-loader: remove pipe_loader_sw_probe_xlib
It was only useful for st/egl, although I've never got to merging the
pipe-loader and inline-helpers before it was removed. There are no users
for it ATM.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit c73d30dfe90d9aa096fc64024612a6543bd748c7
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Jun 29 13:08:06 2015 +0100
automake: remove empty GALLIUM_PIPE_LOADER_LIBS
Cc: Rob Clark <robclark at freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit abc20120e4aa5a3782f40f7d4a7c6a4f953fca9c
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Jun 29 13:02:21 2015 +0100
automake: pipe-loader: remove the 'client' pipe-loader
Was only around as opencl's pipe-loader wanted to link against xcb in
some cases.
Cc: Rob Clark <robclark at freedesktop.org>
Cc: Tom Stellard <thomas.stellard at amd.com>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 0959d7312d37dd9841cbf7a53cb40b3cfa6e5fc9
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Jun 29 12:44:44 2015 +0100
pipe-loader: remove pipe_loader_drm_probe_fd() x_auth argument
No longer used by anyone, as of last commit.
Cc: Tom Stellard <thomas.stellard at amd.com>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit a27ec5dc460b91dc44675f48cddbbb2631ee824f
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Tue Jun 30 15:53:27 2015 +0100
pipe-loader: simplify pipe_loader_drm_probe
Do not iterate and (attempt to) open the render device, if we're over
the requested number of devices.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 69a1b9959e59653da262185c4e2cf57d24939b19
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Jun 29 12:36:45 2015 +0100
pipe-loader: drop support for non-render node devices
Render nodes have been around for quite some time. Removing support via
the master/primary node allows us to clean up the conditional
compilation and simplify the build greatly.
For example currently we the pipe-loader, which explicitly links against
xcb and friends (for X auth) if found at compile-time. That
would cause problems as one will be forced to use X/xcb, even if it's a
headless system that is used for opencl.
v2: Clarify the linking topic in the commit message.
Cc: Tom Stellard <thomas.stellard at amd.com>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit de5c2b6f2b53924bceab6f4b8255d8e9dcad21b4
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Jul 13 09:11:20 2015 +0100
radeonsi: direct emit intrinsic for DFRAC.
Michel reported this still failed, and this fixed it
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 4cbf0a0ccf2fb4545b206066b756fd9a07acab92
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Jul 1 04:58:24 2015 +0100
radeonsi: ARB_gpu_shader_fp64 + ARB_vertex_attrib_64bit support.
This adds the translation from TGSI to AMDGPU llvm backend, for the
64-bit opcodes. The backend pretty much handles everything for us
fine. There is one patch required for SI DFRAC support, that I know
off.
[airlied: fixed missing comma, updated relnotes]
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 8108de4774f2542a8fe65de71b82221821f73434
Author: Guillaume Desmottes <guillaume.desmottes at collabora.co.uk>
Date: Fri Apr 17 15:13:36 2015 +0200
loader: don't leak udev_enumerate
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90073
Signed-off-by: Guillaume Desmottes <guillaume.desmottes at collabora.co.uk>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit f7008ebcdc4d936e8b2b1a317d870e907e4d369f
Author: Guillaume Desmottes <guillaume.desmottes at collabora.co.uk>
Date: Fri Apr 17 15:13:35 2015 +0200
dri3_open: don't leak the reply
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90073
Signed-off-by: Guillaume Desmottes <guillaume.desmottes at collabora.co.uk>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 5d219908ce045805647b85d1d302b58887e63c1b
Author: Rhys Kidd <rhyskidd at gmail.com>
Date: Sat Jun 27 13:14:38 2015 +1000
doxygen: Remove doxygen_sqlite3.db with 'make clean'
Signed-off-by: Rhys Kidd <rhyskidd at gmail.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 6cc29cf5e2c21dc0937b2c794758be61d3281324
Author: Rhys Kidd <rhyskidd at gmail.com>
Date: Sat Jun 27 13:14:37 2015 +1000
doxygen: Add doxygen_sqlite3.db to .gitignore
Signed-off-by: Rhys Kidd <rhyskidd at gmail.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 846c60fc7df587a24d5bf0835497aa25034538b3
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Jul 11 20:36:44 2015 +0100
docs: add news item and link release notes for mesa 10.6.2
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 6dfce109c27b4e15373adcbbde981140912001ae
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Jul 11 20:33:16 2015 +0100
docs: Add sha256 checksums for the 10.6.2 release
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit 89cbd91b17989ec7eb1cb93ac427a84dca56cd79)
commit 66d354384505fd5ef67b8683db94e8967aba338b
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Jul 11 19:46:49 2015 +0100
Add release notes for the 10.6.2 release
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit 9643cce94c8a1938e3342fb83d025a1e5c2aa79b)
commit ad2c3905d3460a6ddfc6756fc58a78332d82e72f
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Jul 1 06:31:13 2015 +0100
tgsi: add DFMA to the opcode infer functions.
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit e70d0515603df081916f6f31bb9e0455298b10cc
Author: Dave Airlie <airlied at redhat.com>
Date: Thu Jul 9 15:49:56 2015 +1000
r600g: move sampler/ubo index registers before temp reg
temp_reg needs to be last, as we increment things
away from it, otherwise on cayman some tests were overwriting
the index regs.
Fixes 2 piglit with ARB_gpu_shader5 forced on cayman.
Reviewed-by: Glenn Kennard <glenn.kennard at gmail.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit c397bd14077b760125604426a99aba00d6193788
Author: Dave Airlie <airlied at redhat.com>
Date: Thu Jul 9 15:22:09 2015 +1000
r600g: fix sampler/ubo indexing on cayman
Cayman needs a different method to upload the CF IDX0/1
This fixes 31 piglits when ARB_gpu_shader5 is forced on
with cayman.
Reviewed-by: Glenn Kennard <glenn.kennard at gmail.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 1bfa25e88d21f95b9e176232bb091af77c294578
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Jul 10 16:42:18 2015 -0400
nv50, nvc0: enable at least one color RT if alphatest is enabled
Fixes the following piglits:
fbo-alphatest-nocolor
fbo-alphatest-nocolor-ff
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org
commit 4fe15717ce2fc0b1c239d3d7bf9a7bb04fb50dd5
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Jun 25 10:08:06 2015 -0700
i965: Remove special case for layered drawbuffer attachments.
When binding a layered texture, the layer is already 0. There's no need
to special case this.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 6be024f44dea7df6608e5a3111deffc61dbf6d6d
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Jun 25 09:17:38 2015 -0700
i965/gen6: Set up layer constraints properly for depth buffers.
This ports over Chris Forbes' equivalent fixes in gen7_misc_state.c
from commit 77d55ef4819436ebbf9786a1e720ec00707bbb19.
No Piglit changes on Sandybridge.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit f3a620e2a63956a37367b9e393d4c1ecd41e5d43
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Apr 22 17:46:08 2015 -0700
i965: Label the repclear shader "meta repclear" rather than "meta clear".
Color clears can be performed via two separate shaders - one is the
generic "meta clear" shader (in meta.c); the other is the i965 specific
"repclear" shader (in brw_meta_fast_clear.c).
Giving them separate names makes them distinguishable when reading
INTEL_DEBUG=shader_time output.
v2: Call it "meta repclear", as suggested by Jason.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit a078e13a7cfba9275bea2a1c7f80ac54bcf40036
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Jul 1 17:01:54 2015 -0700
i965: Fix indentation in emit_control_data_bits().
The last patch left the code indented too far.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 0edb084f9d0444c451a08fd2ed7daee2eb8a6f4a
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Jul 1 17:01:24 2015 -0700
i965/gs: Move vertex_count != 0 check up a level; skip one caller.
Paul's original code had emit_control_data_bits() skip the URB write if
vertex_count was 0. This meant wrapping every control data write in a
conditional write.
We accumulate control data bits in a single UD (32-bit) register. For
simple shaders that don't emit many vertices, the control data header
will be <= 32-bits long, so we only need to write it once at the end of
the shader.
For shaders with larger headers, we write out batches of control data
bits at EmitVertex(), when (vertex_count * bits_per_vertex) % 32 == 0.
On the first EmitVertex() call, the above expression will evaluate to
true simply because vertex_count == 0. But we want to avoid emitting
the control data bits, because we haven't accumulated 32-bits worth yet.
In other words, the vertex_count != 0 check is really only necessary in
the EmitVertex() batching case, not the end-of-thread case.
This saves a CMP/IF/ENDIF in every shader that uses EndPrimitive() or
multiple streams. The only downside is that a shader which emits no
vertices at all will execute an additional URB write---but such shaders
are pointless and not worth optimizing.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 0fae4e451bc60de1138729d20e03100e93cc6f38
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Wed Jul 8 21:26:02 2015 +1000
glsl: use set rather than old hash table for ir_validate
When the new hash table implementation was added to Mesa it claimed to be much
faster, see commits 35fd61bd99c1 and 72e55bb6888ff.
The set implementation follows the same implementation strategy so this should
be faster and there was no need to store a data field.
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 75784243df1f5bb0652fb243b37d69f36d493a86
Author: Chad Versace <chad.versace at intel.com>
Date: Thu Jul 9 18:46:21 2015 -0700
mesa: Fix generation of git_sha1.h.tmp for gitlinks
Don't assume that $(top_srcdir)/.git is a directory. It may be a
gitlink file [1] if $(top_srcdir) is a submodule checkout or a linked
worktree [2].
[1] A "gitlink" is a text file that specifies the real location of
the gitdir.
[2] Linked worktrees are a new feature in Git 2.5.
Cc: "10.6, 10.5" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 15d3524ad24a698095cc542cf9a527c8a8615f78
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Jul 2 18:07:27 2015 -0400
freedreno/a4xx: occlusion query support
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 2b7a54452fbb7e6436aa4ecc700cb2fe2f96ad86
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Jul 9 18:14:36 2015 -0400
freedreno: update generated headers
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit e44845472a4e04e7b6a82ab6c768f9648729d7e9
Author: Rob Clark <robclark at freedesktop.org>
Date: Sun Jul 5 20:17:56 2015 -0400
freedreno/ir3/sched: fixup new instr's block
If we split addr/pred, the original instruction could have originated
from a different block. If we don't fixup the block ptr we hit asserts
later (in debug builds).
NOTE: perhaps we don't want to try to preserve addr/pred reg's across
block boundaries.. this at least needs some thought in case addr/pred
writes end up inside a conditional block..
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit a1a6f007823f203755fb54a1f3b7f53ae6cbfef0
Author: Rob Clark <robclark at freedesktop.org>
Date: Sun Jul 5 19:53:10 2015 -0400
freedreno/ir3/ra: fix failed assert for a0/p0
The address and predicate register are special, they don't get assigned
in RA. So do a better job of ignoring them rather than hitting later
asserts.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 65b2ae510bb07b75f583ecedfd59766621e1cb43
Author: Rob Clark <robclark at freedesktop.org>
Date: Sun Jul 5 18:23:25 2015 -0400
freedreno/ir3: shader-db traces
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 422296e38d04789cc4ca336b46979b44abd19b5d
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Jul 2 18:15:43 2015 -0400
freedreno: fix crash in fd_invalidate_resource()
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit ab3ba21f979605b90b2fb44482138732b42514b0
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Jul 8 14:51:46 2015 -0400
vc4: unref old fence
Some, but not all, state trackers will explicitly unref (and set to
NULL) the previous *fence before calling pipe->flush(). So driver
should use fence_ref() which will unref the old fence if not NULL.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Acked-by: Eric Anholt <eric at anholt.net>
commit 749dced4b363963b2230a18b0776fa92653116b8
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Jul 8 14:51:10 2015 -0400
ilo: unref old fence
Some, but not all, state trackers will explicitly unref (and set to
NULL) the previous *fence before calling pipe->flush(). So driver
should use fence_ref() which will unref the old fence if not NULL.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Acked-by: Chia-I Wu <olvaffe at gmail.com>
commit 7e0a26defe65dad7ffc8e7a95b5577be51feb2bc
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Jul 8 14:48:01 2015 -0400
freedreno: unref old fence
Some, but not all, state trackers will explicitly unref (and set to
NULL) the previous *fence before calling pipe->flush(). So driver
should use fence_ref() which will unref the old fence if not NULL.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit f60354ee72fdee988fd604994e8b8c8d75fe78be
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Jul 8 15:00:51 2015 -0400
gallium: clarify reference counting for fence
Nowhere was it spelled out that the state tracker may expect the pipe
driver to unref the old fence.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 0a8af6361eecaba0f34a668328746924b61caa6a
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Jul 8 13:30:22 2015 -0400
xa: don't leak fences
XA was never unref'ing last_fence in the various call paths to
pipe->flush(). Add this to xa_context_flush() and update the other
open-coded calls to pipe->flush() to use xa_context_flush() instead.
This fixes a memory leak reported with xf86-video-freedreno.
Reported-by: Nicolas Dechesne <nicolas.dechesne at linaro.org>
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit f12302b89836a24255674a251f7a6902b4e9af7c
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sun Jun 28 21:16:29 2015 -0700
i965/vs: Get rid of brw_vs_compile completely.
After tearing it out another level or two, and just passing the key and
vp directly, we can finally remove this struct. It also eliminates a
pointless memcpy() of the key.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 64390967c1abc326875e495f233afec6e685db72
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Jun 29 22:07:37 2015 -0700
i965/vs: Remove 'c'/vs_compile from vec4_vs_visitor.
At this point, the brw_vs_compile structure only contains the key and
gl_vertex_program pointer. We may as well pass and store them directly;
it's simpler and more convenient (key-> instead of vs_compile->key...).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 13372a0ce746cde6fa6e0aa3c5130e4227f123e0
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sun Jun 28 21:02:15 2015 -0700
i965/vec4: Move c->last_scratch into vec4_visitor.
Nothing outside of vec4_visitor uses it, so we may as well keep it
internal.
Commit db9c915abcc5ad78d2d11d0e732f04cc94631350 for the vec4 backend.
(The empty class will be going away soon.)
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 8524deb8c8fc37abc2cb2717be64a533746a92f9
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sun Jun 28 20:55:25 2015 -0700
i965/vec4: Move total_scratch calculation into the visitor.
This is more consistent with how we do it in the FS backend, and reduces
a tiny bit of duplication. It'll also allow for a bit more tidying.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit dc776ffb900b21421158ef8efbd675bdd47593bc
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sun Jun 28 20:45:47 2015 -0700
i965/vec4: Move perf_debug about register spilling into the visitor.
This patch makes us only issue the performance warning about register
spilling if we actually spilled registers. We also use scratch space
for indirect addressing and the like.
This is basically commit c51163b0cf7aff0375b1a5ea4cb3da9d9e164044 for
the vec4 backend.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 0163c99e8f6959b5d6c7a937a322127cfdf9315f
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Jun 29 21:58:47 2015 -0700
i965/vec4: Plumb log_data through so the backend_shader field gets set.
Jason plumbed this through a while back in the FS backend, but
apparently we were just passing NULL in the vec4 backend.
This patch passes brw in as intended.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 308c0bf74307af0f3385cdcbb00aa0534ec3e5da
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Mar 12 10:43:23 2015 -0700
i965: Switch on shader stage in nir_setup_outputs().
Adding new shader stages to a switch statement is less confusing than an
if-else-if ladder where all but the first case are fragment shader
specific (but don't claim to be).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 04a57a7ee92403a1d9e01eada69f1ab133fc0b47
Author: Brian Paul <brianp at vmware.com>
Date: Thu Jul 9 16:58:04 2015 -0600
tgsi: whitespace fixes in tgsi_parse.c
Trivial.
commit 1f02a82c8bcac67ced81243631bad6ee1bb810ee
Author: Brian Paul <brianp at vmware.com>
Date: Wed Jul 8 18:05:27 2015 -0600
gallium: fix comment typo in p_shader_tokens.h
commit 27d8a690c41748b39c65d1ff51bb63e9f860bae1
Author: Brian Paul <brianp at vmware.com>
Date: Wed Jul 8 15:56:15 2015 -0600
gallium/docs: s/treaded/treated/ typo in tgsi.rst
Trivial.
commit a2dde3a8dabbbd45fb3155771bc1802866ff5f61
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Jul 7 23:33:57 2015 -0700
util: Don't link to SHA1 library if shader-cache is disabled.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit c04339486a26b7bee3575bf30dde4f7152a70211
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Jul 7 18:51:30 2015 -0700
i965: Set brw->batch.emit only #ifdef DEBUG.
It's only used inside #ifdef DEBUG. Cuts ~1.7k of .text, and more
importantly prevents a larger code size regression in the next commit
when the .used field is replaced and calculated on demand.
text data bss dec hex filename
4945468 195152 26192 5166812 4ed6dc i965_dri.so before
4943740 195152 26192 5165084 4ed01c i965_dri.so after
And surround the emit and total fields with #ifdef DEBUG to prevent
such mistakes from happening again.
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 0166b4c165271bd7525a91049e58e390cb596c60
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Thu Jul 9 10:35:19 2015 -0700
i965/hsw: Implement end of batch workaround
This patch can cause an infinite recursion if the previous patch titled, "i965:
Track finished batch state" isn't present (backporters take notice).
v2: Sent out the wrong patch originally. This patches switches the order of
flushes, doing the generic flush before the CC_STATE, and the required
workaround flush afterwards
v3: Only perform workaround for render ring
Add text to the BATCH_RESERVE comments
v4 (By Ken): Rebase; update citation to mention PRM and Wa name; combine two
blocks.
http://otc-mesa-ci.jf.intel.com/job/bwidawsk/171/
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 2cfa64e159a68998b76bdbcd20f8c7810379fce0
Author: Christian König <christian.koenig at amd.com>
Date: Mon Jun 29 10:19:36 2015 +0200
st/vdpau: fix mixer size checks
We need to check what the 3D pipe is able to handle for the mixer, not what
the decoder is able to decode. This fixes output of resolutions like 720x1280.
Signed-off-by: Christian König <christian.koenig at amd.com>
CC: mesa-stable at lists.freedesktop.org
commit bbfdf5c17b695c31915e293e1ec858cbcb340894
Author: Christian König <christian.koenig at amd.com>
Date: Fri May 29 15:10:31 2015 +0200
vl: cleanup video buffer private when the decoder is destroyed
Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=90728
Signed-off-by: Christian König <christian.koenig at amd.com>
CC: mesa-stable at lists.freedesktop.org
commit adc816a1e41812e6489a5bc388f80de65504be5b
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Mon Jul 6 23:34:23 2015 +0200
nv50: avoid segfault with enabled but unbound vertex attrib
Before validating vertex arrays we need to check if a VBO is present.
Checking if vb->buffer is not NULL fixes the issue.
Fixes the following piglit test:
gl-3.1-vao-broken-attrib
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit ec151e2f72bd4a239573770aea563d47d0268708
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Mon Jul 6 22:06:08 2015 +0200
nvc0: fix wrong use of BLIT_SRC_Y_INT for 2D texture copy
According to nv50, this should be src->ms_y instead of src->ms_x. This
code is here since 2012, so it's probably a typo error which has never
been detected since a long time. I didn't do a full piglit run to check
if it fixes some other weird issues.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit efb36271a92b44ee0e35c4f833610dbea776badd
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Jul 8 01:57:00 2015 -0700
nir: Fix comment above nir_convert_from_ssa() prototype.
Connor renamed the parameter, inverting the sense.
Update the comment accordingly.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit e27ea996444743b8cbdca096a4aab47dd405ebf9
Author: Julien Isorce <julien.isorce at gmail.com>
Date: Thu Jun 18 06:53:52 2015 +0100
egl/dri2: load libglapi.0.dylib on osx
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90903
Signed-off-by: Julien Isorce <j.isorce at samsung.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 7d642442d9339e5b65c30802c44091816cdf18be
Author: Julien Isorce <j.isorce at samsung.com>
Date: Thu Jul 2 23:10:38 2015 +0100
egl: use unix defines on osx with clang
I also created an bug in Khronos 's bugzilla as you suggested:
https://www.khronos.org/bugzilla/show_bug.cgi?id=1356
I'll let you know if I get feedback from this bug or else where.
Patch with updated error messages:
[PATCH] eglplatform: treat __APPLE__ the same way as __unix__ to handle X11 types
CC eglapi.lo
./egldisplay.h:258:19: error: unknown type name 'Display'
_eglGetX11Display(Display *native_display, const EGLint *attrib_list);
eglapi.c:290:4: error: array size is negative
STATIC_ASSERT(sizeof(void*) == sizeof(nativeDisplay));
eglapi.c:291:25: warning: cast to 'void *' from smaller integer type
'EGLNativeDisplayType' (aka 'int') [-Wint-to-void-pointer-cast]
native_display_ptr = (void*) nativeDisplay;
eglapi.c:307:32: error: use of undeclared identifier 'Display'
dpy = _eglGetX11Display((Display*) native_display, attrib_list);
eglapi.c:776:35: error: use of undeclared identifier 'Window'
native_window = (void*) (* (Window*) native_window);
eglapi.c:847:35: error: use of undeclared identifier 'Pixmap'
native_pixmap = (void*) (* (Pixmap*) native_pixmap);
Bugzilla Mesa: https://bugs.freedesktop.org/show_bug.cgi?id=90249
Bugzilla Khronos: https://www.khronos.org/bugzilla/show_bug.cgi?id=1356
Signed-off-by: Julien Isorce <j.isorce at samsung.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit c7f3657450683827446072ad6b1e8fce04078162
Author: Julien Isorce <julien.isorce at gmail.com>
Date: Wed Jul 1 00:33:14 2015 +0100
darwin: Suppress type conversion warnings for GLhandleARB
This patch and its description are inspired from Jose Fonseca
explanations and suggestions.
With this patch the following logic applies and only if __APPLE__:
When building mesa, GLhandleARB is defined as unsigned long and
at some point casted to GLuint in gl fuction implementations.
These exact points are where these errors and warnings appear.
When building an application GLhandleARB is defined as void*.
Later when calling a gl function, for example glBindAttribLocationARB,
it will be dispatched to _mesa_BindAttribLocation. So internally
void* will be treated as unsigned long which has the same size.
So the same truncation happens when casting it to GLuint.
Same when GLhandleARB appears as return value.
For mesa it will be GLuint -> unsigned long.
For an application it will be GLuint -> unsigned long -> void*.
Note that the value will be preserved when casting back to GLuint.
When GLhandleARB appears as a pointer there are also separate
entry-points, i.e. _mesa_FuncNameARB. So the same logic can
be applied.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=66346
Signed-off-by: Julien Isorce <julien.isorce at gmail.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 64cb014037551c4b7bbed1cf2ca8f1126c970146
Author: Varad Gautam <varadgautam at gmail.com>
Date: Sat Jun 27 11:32:26 2015 +0530
android: freedreno: add missing components to the build
Freedreno requires {a4xx,ir3}_SOURCES and NIR to build.
Signed-off-by: Varad Gautam <varadgautam at gmail.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit f1d08c4f75794add30d1714a4cd9ce2bf335148d
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Fri May 1 11:25:20 2015 +0100
i965: Move pipecontrol workaround bo to brw_pipe_control
With the exception of gen8, the sole user of the workaround bo are for
emitting pipe controls. Move it out of the purview of the batchbuffer
and into the pipecontrol.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
commit f2413457937f8f4a92e11379569be69e508d7477
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Wed Jun 10 08:28:13 2015 +0100
loader: Look for any version of currently linked libudev.so
Since there was an ABI break and linking twice against libudev.so.0 and
libudev.so.1 causes the application to quickly crash, we first check if
the application is currently linked against libudev before dlopening a
local handle. However for backwards/forwards compatability, we need to
inspect the application for current linkage against all known versions
first. Not doing so causes a crash when both libraries are present and
so mesa chooses libudev.so.1 but the application was linked against
libudev.so.0.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Emil Velikov:
I'm ever so slightly conserned that RTLD_NOLOAD is not part of the POSIX
standard, thus it's missing on some platforms (*BSD seems ok, while
Solaris, MacOS are not).
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Cc: mesa-stable at lists.freedesktop.org
commit c8d3ebaffc0d7d915c1c19d54dba61fd1e57b338
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Wed Apr 29 13:32:38 2015 +0100
i965: Query whether we have kernel support for the TIMESTAMP register once
Move the query for the TIMESTAMP register from context init to the
screen, so that it is only queried once for all contexts.
On 32bit systems, some old kernels trigger a hw bug resulting in the
TIMESTAMP register being shifted and the low 32bits always zero. Detect
this by repeating the read a few times and check the register is
incrementing every 80ns as expected and not stuck on zero (as would be
the case with the buggy kernel/hw.).
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Martin Peres <martin.peres at linux.intel.com>
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 38c2ec5ff0bf626578db7b84387279342aa48844
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Tue Jul 7 23:05:45 2015 -0400
nvc0: turn sample counts off during blit
Fixes the following piglits:
occlusion_query_meta_fragments
occlusion_query_meta_no_fragments
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org
commit 87d2e15b1aa6f438983405aa25bf067034c898b0
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Wed Jul 8 09:20:40 2015 +1000
mesa: use implementation specified MAX_VERTEX_ATTRIBS rather than hardcoded value
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 73d0e7f3451eaeb62ac039d2dcee1e1c6787e3db
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Jul 1 20:13:00 2015 -0700
i965/vs: Fix matNxM vertex attributes where M != 4.
Matrix vertex attributes have their columns padded out to vec4s, which
I was failing to account for. Scalar NIR expects them to be packed,
however.
Fixes 1256 dEQP tests on Broadwell.
Cc: mesa-stable at lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Tested-by: Mark Janes <mark.a.janes at intel.com>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit 6611f65047575054a38ce83ebfe0331e39e1774f
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Jul 7 18:28:31 2015 +0200
st/dri: don't set PIPE_BIND_SCANOUT for MSAA surfaces
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91231
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 10cff5e1ae55406799f4b0ad6b327d4c45dbca11
Author: Brian Paul <brianp at vmware.com>
Date: Tue Jul 7 13:17:01 2015 -0600
gallium/hud: display percentages with % suffix
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit a804f5824352e4f714779bd9445c09b66d54bc4a
Author: Brian Paul <brianp at vmware.com>
Date: Tue Jul 7 09:15:59 2015 -0600
gallium/hud: add PIPE_DRIVER_QUERY_TYPE_MICROSECONDS for HUD
This allows drivers to report queries in units of microseconds and
have the HUD display "us" (microseconds), "ms" (milliseconds) or "s"
(seconds) on the graph.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 86ebd31c672f389f354e11b7aef4513dc8b76f13
Author: Brian Paul <brianp at vmware.com>
Date: Tue Jul 7 09:13:02 2015 -0600
gallium/hud: replace byte units flag with pipe_driver_query_type
Instead of using a boolean 'is bytes' value, use the pipe_driver_query_type
enum type. This will let is add support for time values in the next patch.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit f025aec906fce0f2918b6f4acb15548dc957ba67
Author: Brian Paul <brianp at vmware.com>
Date: Mon Jul 6 15:28:59 2015 -0600
gallium/os: minor whitespace fixes in os_time.h
Trivial.
commit 7009e2683ebb917393d87639f549588f22c03a32
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 6 18:55:26 2015 +0300
i965/gen4-5: Enable 16-wide dispatch on shaders with control flow.
This was probably disabled due to a combination of several bugs in the
generator code (fixed earlier in this series) and a misunderstanding
of the hardware spec. The documentation for most control flow
instructions mentions among other restrictions:
"Instruction compression is not allowed."
This however doesn't have any implications on 16 wide not being
supported, because none of the control flow instructions have
multi-register operands (control flow instructions are not compressed
on more recent hardware either, except maybe SNB's IF with inline
compare). In fact Gen4-5 had 16-wide control flow masks and stacks,
and the spec mentions in several places that control flow instructions
push and pop 16 channels worth of data -- Otherwise there doesn't seem
to be any indication that it shouldn't work.
Causes no piglit regressions, and gives the following shader-db
results on ILK:
total instructions in shared programs: 4711384 -> 4711384 (0.00%)
instructions in affected programs: 0 -> 0
helped: 0
HURT: 0
GAINED: 1215
LOST: 0
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 24842e18aabdaeff41668b0e71e52d32975d2ccd
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 6 19:11:54 2015 +0300
i965/gen4-5: Program the execution size correctly for DO/WHILE instructions.
From the hardware docs for the DO instruction:
"Execution size is ignored for this instruction."
My observation on ILK hardware contradicts the spec though, channels
over the execution size of a DO instruction won't enter the loop, and
channels over the execution size of a WHILE instruction will exit the
loop after the first iteration -- The latter is consistent with the
spec though, there's no claim about the execution size being ignored
for the WHILE instruction so it's not completely unexpected that it
has an influence on the evaluation of EMask.
The execute_size argument of brw_DO() shouldn't have any effect on
Gen6 and newer hardware. On Gen4-5 WHILE instructions inherit the
execution size from the matching DO, so this patch should fix them
too. The execution size of BREAK and CONT instructions was already
being set correctly.
Fixes some 50 piglit tests on Gen4-5 when forced to run shaders with
conditional and loop instructions 16-wide,
e.g. shaders/glsl-fs-continue-inside-do-while.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 40e2102e528498dd4c03c4567d3522241f4d1f22
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jul 6 18:23:57 2015 +0300
i965/gen4-5: Set ENDIF dst and src0 fields to the null register.
The hardware docs don't mention explicitly what these fields should
be, but I've verified experimentally on ILK that using a GRF as
destination causes the register to be corrupted when the execution
size of an ENDIF instruction is higher than 8 -- and because the
destination we were using was g0, eventually a hang.
Fixes some 150 piglit tests on Gen4-5 when forced to run shaders with
if conditionals 16-wide, e.g. shaders/glsl-fs-sampler-numbering-3.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 248b26429f52d0f19949a083aa3e0aeebcbe2138
Author: Michel Dänzer <michel.daenzer at amd.com>
Date: Mon Jul 6 17:23:07 2015 +0900
radeonsi: Use param export count from si_llvm_export_vs in si_shader_vs
This eliminates the error prone logic in si_shader_vs recalculating this
value.
It also fixes TGSI_SEMANTIC_CLIPDIST outputs incorrectly not being
counted for VS exports. They need to be counted because they are passed
to the pixel shader as parameters as well.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91193
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit b0334a9aeb9369fd20854ab2ef4b2ee0087492ab
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu Jun 25 16:57:20 2015 -0700
mesa: Convert some asserts into STATIC_ASSERT.
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit 7b06af9d3ca7310197d39d55fc52c265da4bc59e
Author: Roland Scheidegger <sroland at vmware.com>
Date: Sat Jul 4 03:03:33 2015 +0200
gallivm: fix lp_build_compare_ext
The expansion should always be to the same width as the input arguments
no matter what, since these functions should work with any bit width of
the arguments (the sext is a no-op on any sane simd architecture).
Thus, fix the caller expecting differently.
This fixes https://bugs.freedesktop.org/show_bug.cgi?id=91222
Tested-by: Vinson Lee <vlee at freedesktop.org>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 128de6f6d7cd0eb5386dcc622afc6e28a8512e7f
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Jul 6 11:04:19 2015 -0700
mesa: Add a MUST_CHECK macro for __attribute__((warn_unused_result)).
In the kernel, this is called __must_check; all our attribute macros in
Mesa appear to be uppercase, so I went with that.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 86a3557d7c95ac945eedf42ab095639b255c1bed
Author: Neil Roberts <neil at linux.intel.com>
Date: Sat Jul 4 22:40:59 2015 +0100
glsl: Make sure not to dereference NULL
In this bit of code point_five can be NULL if the expression is not a
constant. This fixes it to match the pattern of the rest of the chunk
of code so that it checks for NULLs.
Cc: Matt Turner <mattst88 at gmail.com>
Cc: "10.6" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 18039078e0254c7cb5e15b7186be05e2e4c10f38
Author: Neil Roberts <neil at linux.intel.com>
Date: Sat Jul 4 22:40:58 2015 +0100
glsl: Add missing check for whether an expression is an add operation
There is a piece of code that is trying to match expressions of the
form (mul (floor (add (abs x) 0.5) (sign x))). However the check for
the add expression wasn't checking whether it had the expected
operation. It looks like this was just an oversight because it doesn't
match the pattern for the rest of the code snippet. The existing line
to check whether add_expr!=NULL was added as part of a coverity fix in
3384179f.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91226
Cc: Matt Turner <mattst88 at gmail.com>
Cc: "10.6" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit d9ab95b365f058a46bc43a8cb96b6fff10a13faf
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Mar 4 15:46:57 2015 -0800
i965: Reserve more batch space to accomodate Gen6 perfmonitors.
Ben noticed that I said each PIPE_CONTROL was 4 DWords, but it's
actually 5 DWords on Gen6-7. We've been reserving insufficient space
for performance monitoring on Sandybridge, which means it would likely
break if you used that functionality. (Thankfully, no one does...)
Also, the existing number of 146 was the result of me flubbing up the
arithmetic: it should have actually been 140.
Cc: mesa-stable at lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit 493af150fb3b1c007d791b24dcd5ea8a92ad763c
Author: Neil Roberts <neil at linux.intel.com>
Date: Fri Jul 3 13:15:21 2015 +0100
i965/skl: Set the pulls bary bit in 3DSTATE_PS_EXTRA
On Gen9+ there is a new bit in 3DSTATE_PS_EXTRA that must be set if
the shader sends a message to the pixel interpolator. This fixes the
interpolateAt* tests on SKL, apart from interpolateatsample-nonconst
but that is not implemented anywhere so it's not a regression.
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Cc: "10.6 10.5" <mesa-stable at lists.freedesktop.org>
commit fc2726e4afa6dfb691affed576a38d2b0573465b
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Jun 26 19:01:04 2015 +0200
winsys/radeon: use os_wait_until_zero in radeon_bo_set_tiling
commit f1be3d8cdde17a9b9ae283e1bab2f46b992d3bf3
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jun 27 14:03:46 2015 +0200
radeonsi: don't flush an empty IB if the only thing we need is a fence
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
commit 7316cc92f3810c9e53a22c35343190d8fb7980be
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jun 27 00:05:26 2015 +0200
gallium/os: add conversion and wait functions for absolute timeouts
Absolute timeouts are used with the amdgpu kernel driver.
It also makes waiting for several variables and fences at the same time
easier (the timeout doesn't have to be recalculated after every wait call).
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
commit 3836857a777a248dd212ce7a1d7307d2984fda7d
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Jun 25 20:39:34 2015 +0200
gallium/os: add os_wait_until_zero (v2)
This will be used by radeon and amdgpu winsyses.
Copied from the amdgpu winsys.
v2: use volatile and p_atomic_read
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
commit 245b464d5caa21680373ae5929dccd294078cc50
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Jun 26 19:01:23 2015 +0200
gallium/radeon: mark the gpu load thread stop trigger as volatile
commit 872ede6fd136c7f9701cc60268ab195a48e75e67
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jun 27 13:57:06 2015 +0200
st/mesa: if a fence isn't returned, assume it's signalled
The reason might be that no commands have been submitted before the flush
and the GPU is idle.
commit 5a69929683b15d48e4f2fd47e2c816e716ab60ef
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Jun 26 16:34:31 2015 +0200
gallium: remove redundant pipe_context::fence_signalled
fence_finish(timeout=0) does the same thing
Reviewed-by: Brian Paul <brianp at vmware.com>
commit bd214f030f1cb102a7fe41f40f140d4de2b304c0
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Jun 26 16:28:53 2015 +0200
gallium: use fence_finish instead of fence_signalled in state trackers
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 3da1c7919d0dffee3887f390fcf29893016e3043
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Jun 26 13:13:16 2015 +0200
gallium: handle fence_finish timeout in various drivers
I copied what fence_signalled does.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit d50598fbad16bfb2b46800b664d382f42af64db0
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Jun 26 13:19:45 2015 +0200
gallium/docs: remove out-of-date document about D3D11 features
Reviewed-by: Brian Paul <brianp at vmware.com>
commit d3f4f6b2e9380a91ab61b93c55ab36106345e7b2
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Jun 24 11:58:50 2015 +0200
radeonsi: fix a hang with DrawTransformFeedback on 4 SE chips
Cc: 10.6 10.5 <mesa-stable at lists.freedesktop.org>
Acked-by: Christian König <christain.koenig at amd.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
commit ff0a41b5d524d7f10494e0c9006389d184ed6330
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Jul 4 12:53:22 2015 +0100
docs: add news item and link release notes for mesa 10.5.9
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit c427daa23ef4879550ed3b756d6a901475432c32
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Jul 4 12:48:39 2015 +0100
docs: Add sha256sums for the 10.5.9 release
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit 4a0bd3dcff3c07965828e648e14d89314d262169)
commit 24bf11e9c7846a2ad9624e421c85aaa1d4411cd9
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Jul 4 12:09:10 2015 +0100
Add release notes for the 10.5.9 release
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit 7f40d083748f3a8276e08a2fa0ae7149269ea379)
commit 939dc2850645786b4ff76aa162e44eb9f77be805
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Sat Mar 14 12:40:20 2015 +1100
glsl: update types for unsized arrays of members
Assigns a new array type based on the max access of
unsized array members. This is to support arrays of arrays.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 7ecb11c81c1e2fc816b36c82657ab139eb1d84b6
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Sun Feb 22 23:35:43 2015 +1100
glsl: update assert to support arrays of arrays
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 9565e345285c71af064e2bb5e0ee762655310802
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Wed May 27 12:02:40 2015 +1000
glsl: allow precision qualifiers for AoA
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit f70719cc4b64e12310dfe8825a8e2d4bce970673
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Jul 3 19:09:09 2015 -0400
nv50/ir: UCMP arguments are float, so make sure modifiers are applied
The first argument to UCMP needs to be compared against 0, but the
latter arguments are treated as float and need to be able to properly
apply neg/abs arguments. Adjust the inferSrcType function accordingly.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
commit 83984f134b4a1e2829cb238c404bc82c98be6082
Author: Erik Faye-Lund <kusmabite at gmail.com>
Date: Fri Jul 3 09:46:01 2015 +0200
glsl: add a missing call to _mesa_locale_init
After c61bc6e ("util: port _mesa_strto[df] to C"), "make check"
fails due to a missing _mesa_locale_init. Fixup this oversight,
by moving the stand-alone compiler initializer inside
initialize_context_to_defaults().
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Signed-off-by: Erik Faye-Lund <kusmabite at gmail.com>
commit 28dda47ae4d974e3e032d60e8e0965c8c068c6d8
Author: Mario Kleiner <mario.kleiner.de at gmail.com>
Date: Sun Jun 28 03:02:31 2015 +0200
winsys/radeon: Use dup fd as key in drm-winsys hash table to fix ZaphodHeads.
Same problem and fix as for nouveau's ZaphodHeads trouble.
See patch ...
"nouveau: Use dup fd as key in drm-winsys hash table to fix ZaphodHeads."
... for reference.
Cc: "10.3 10.4 10.5 10.6" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Mario Kleiner <mario.kleiner.de at gmail.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 97ec2c694fe568e375ec7a2b85c1acb1e4666b54
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Jul 3 16:20:32 2015 +0200
r600g: disable single-sample fast color clear due to hangs
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=73528
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82186
Cc: 10.4 10.5 10.6 <mesa-stable at lists.freedesktop.org>
commit 7744687ddb7f1b223da6a862c282173123921023
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Apr 29 17:57:46 2015 +0200
docs/relnotes: document create_context_robustness extensions
commit 914365c0eb039f66370cff166428c703e02ad510
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Apr 29 15:27:50 2015 +0200
r600g,radeonsi: implement get_device_reset_status
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit a34e8714491022a2efde8a44972ac582f098b7ad
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Jun 10 02:50:42 2015 +0200
dri/common: allow BGRX sRGB visuals
commit 9e127325ef461a11345df7ba6884e77c7168ab37
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Jun 10 02:53:33 2015 +0200
mesa: fix sRGB rendering for GLES1
commit 32aa1d769de070c4e8756922571c35deaf12a40a
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Jun 9 23:08:57 2015 +0200
egl: sort extension lists alphabetically
and add the missing KHR_gl_colorspace case.
commit b193f2b9b6ae4d071e2cdef62d4398fec5d9aad8
Author: Anatoli Antonovitch <anatoli.antonovitch at amd.com>
Date: Wed Jun 10 14:42:31 2015 +0200
egl: implement EGL_KHR_gl_texture_3D_image
Most of the code has been in place already.
commit a84505c71920f2c70bc8d83cee3e223cd2d976ad
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Jul 2 15:38:34 2015 -0400
freedreno/ir3: don't be confused by eliminated indirects
If an instruction using address register value gets eliminated, we need
to remove it from the indirects list, otherwise it causes mayhem in
sched for scheduling address register usage.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 2215ff2a5d5f1df5791399e1ff78b56bf06e9102
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Jul 2 14:59:08 2015 -0400
freedreno/ir3: sched fixes for addr register usage
A handful of fixes and cleanups:
1) If we split addr/pred, we need the newly created instruction to
end up in the unscheduled_list
2) Avoid scheduling a write to the address register if there is no
instruction using the address register that is otherwise ready
to schedule. Note that I currently don't bother with the same
logic for predicate register, since the only instructions using
predicate (br/kill) don't take any other src registers, so this
situation should not arise.
3) few other cosmetic cleanups
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 6b9f5cd5f7b25e9e03104fe279df74817f69fe87
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Jul 2 13:52:38 2015 -0400
freedreno/ir3: fix indirects tracking
cp would update instr->address but not update the indirects array
resulting in sched getting confused when it had to 'spill' the address
register. Add an ir3_instr_set_address() helper to set instr->address
and also update ir->indirects, and update all places that were writing
instr->address to use helper instead.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 0a155538eb7e7870b99fb8b3fd8e2a268361d2c8
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Jun 27 17:38:57 2015 -0400
gallium/ttn: mark location specially in nir for color0-writes-all
We need to distinguish a shader that has separate writes to each MRT
from one which is supposed to write the data from MRT 0 to all the MRTs.
In TGSI this is done with a property. NIR doesn't have that, so encode
it as a funny location and decode on the other end.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 959b47262b339ad6d1a072c17a1abe9735ead41d
Author: Rob Clark <robclark at freedesktop.org>
Date: Fri Jun 26 15:05:32 2015 -0400
nir/lower_phis_to_scalar: undef is trivially scalarizable
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 29addf50e038d7323a7ac8093d93422c28ad8635
Author: Rob Clark <robclark at freedesktop.org>
Date: Fri Jun 26 19:11:53 2015 -0400
gallium/ttn: IN/OUT are only array if ArrayID != 0
Fixes issue with gallium HUD. See this thread for details:
http://lists.freedesktop.org/archives/mesa-dev/2015-June/087140.html
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit fc73f8ab8cd3975993546b5e0312d595b76d03be
Author: Rob Clark <robclark at freedesktop.org>
Date: Fri Jun 26 19:04:39 2015 -0400
tgsi: update docs for ArrayID usage
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 7abc1e3286bc4729e144d3a247c2a275e46aaf53
Author: Neil Roberts <neil at linux.intel.com>
Date: Thu Jul 2 17:49:19 2015 +0100
i965/fs: Don't disable SIMD16 when using the pixel interpolator
There was a comment saying that in SIMD16 mode the pixel interpolator
returns coords interleaved 8 channels at a time and that this requires
extra work to support. However, this interleaved format is exactly
what the PLN instruction requires so I don't think anything needs to
be done to support it apart from removing the line to disable it and
to ensure that the message lengths for the send message are correct.
I am more convinced that this is correct because as it says in the
comment this interleaved output is identical to what is given in the
thread payload. The code generated to apply the plane equation to
these coordinates is identical on SIMD16 and SIMD8 except that the
dispatch width is larger which implies no special unmangling is
needed.
Perhaps the confusion stems from the fact that the description of the
PLN instruction in the IVB PRM seems to imply that the src1 inputs are
not interleaved so it wouldn't work. However, in the HSW and BDW PRMs,
the pseudo-code is different and looks like it expects the interleaved
format. Mesa doesn't seem to generate different code on IVB to
uninterleave the payload registers and everything is working so I can
only assume that the PRM is wrong.
I tested the interpolateAt tests on HSW and did a full Piglit run on
IVB on there were no regressions.
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit 89bd5ee64c5aa1b977f4ba832cf7772e81ee286d
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Jul 1 16:00:08 2015 -0700
nir: Don't allow copying SSA destinations
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 197a19f9ed0ba12cc431542ac09f2af0a8bd0bce
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Jul 1 18:22:23 2015 -0400
mesa/prog: relative offsets into constbufs are not constant
The optimization logic relies on being able to read out constbuf values
from program parameters. However that only works if there's no relative
addressing involved.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91173
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit fe2b748a39ff676949fcefccf739aff967fc38c5
Author: Mike Stroyan <mike at lunarg.com>
Date: Wed Jul 1 10:16:28 2015 -0600
i965: allocate at least 1 BLEND_STATE element
When there are no color buffer render targets, gen6 and gen7 still
use the first BLEND_STATE element to determine alpha test.
gen6_upload_blend_state was allocating zero elements when
ctx->Color.AlphaEnabled was false.
That left _3DSTATE_CC_STATE_POINTERS or _3DSTATE_BLEND_STATE_POINTERS
pointing to random data from some previous brw_state_batch().
That sometimes suppressed depth rendering when those bits
happened to mean COMPAREFUNC_NEVER.
This produced flickering shadows for dota2 reborn.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80500
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 9d408a41a3ab2fe456ebf2f7af7bad8f6c4bca17
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Mon Jun 29 10:44:52 2015 +0200
mesa/st: Add checks for signed/unsigned integer conversions in ReadPixels
These checks were in Mesa prior to commit fbba25bba, but they were
not necessary for the purpose that Mesa intended (check if we could
resolve ReadPixels via memcpy), so that commit took them away.
Unfortunately, it seems that some Gallium drivers rely on these
checks to make the decision of whether they should fallback to Mesa's
implementation of ReadPixels correctly. Michel Dänzer reported that
the following piglit test would fail on radeonsi after commit
fbba25bba:
spec at ext_texture_integer@fbo_integer_readpixels_sint_uint
This patch puts the checks back in Gallium, where they are needed.
Tested-by: Michel Dänzer <michel.daenzer at amd.com>
commit c3215ef204c0fdfc44230adbd423720169d44dcb
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Jul 2 00:13:36 2015 -0400
nv50/ir: don't emit src2 in immediate form
In the immediate form, src2 == dst, so it does not need to be emitted.
Otherwise it overlaps with the immediate value's low bits.
Fixes: 09ee907266 (nv50/ir: Fold IMM into MAD)
Cc: "10.6" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 1087c566e3496d08fe70bc0725073e3022716dc5
Author: Alexandre Courbot <acourbot at nvidia.com>
Date: Thu Jul 2 11:36:55 2015 +0900
nvc0: tune PREFER_BLIT_BASED_TEXTURE_TRANSFER capability
Prefer blit-based texture transfers only if the chip has dedicated VRAM
since it would translate to a copy into the same memory on shared-memory
chips.
Signed-off-by: Alexandre Courbot <acourbot at nvidia.com>
Reported-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 4f57cdba2767b56eb4752f14ba9853ba6bc06d0e
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Jul 1 15:18:47 2015 -0400
mesa: reset the source packing when creating temp transfer image
Commit 4b249d2ee (mesa: Handle transferOps in texstore_rgba) introduced
proper transferops handling, but in updating the source to the newly
allocated temporary image neglected to reset the source packing. Set it
to the default which should be appropriate for the floats used.
Fixes: 4b249d2ee (mesa: Handle transferOps in texstore_rgba)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91173
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit e212a80db37b0fc9d57beb91dbca1c43ae4476a0
Author: Alexandre Courbot <acourbot at nvidia.com>
Date: Tue Jun 30 22:37:40 2015 +0900
nvc0: create screen fence objects with coherent attribute
This is required on non-coherent architectures to ensure the value of
the fence is correct at all times. Failure to do this results in the
display freezing for a few seconds every now and then on Tegra.
The NOUVEAU_BO_COHERENT is a no-op for coherent architectures, so behavior
on x86 should not be affected by this patch.
Also bump the required libdrm version to 2.4.62, which introduced this
flag.
Signed-off-by: Alexandre Courbot <acourbot at nvidia.com>
Reviewed-by: Martin Peres <martin.peres at free.fr>
commit 2c8f251369072ce382f651ba73ca280517d26e7f
Author: Nanley Chery <nanley.g.chery at intel.com>
Date: Wed Jun 24 10:59:13 2015 -0700
i965/gen9: use an unreserved surface alignment value
Although the horizontal and vertical alignment fields are ignored here,
0 is a reserved value for them and may cause undefined behavior. Change
the default value to an abitrary valid one.
v2: add comment about chosen value (Topi).
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
commit 80fc9c01dfe4cbbcf1c6b101fcdfdecbda63131e
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Jun 30 17:04:52 2015 -0700
i965/fs: Use the builder directly for the gen6 interpolation add(32)
Now that we can create builders with a bigger width than their parent as
long as it's exec_all, we don't need to create the instruction manually.
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit dabec9c293ee29335f5a6d5d1d3c2b7a715605c1
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue Jun 30 15:15:44 2015 +0300
i965/fs: Relax fs_builder channel group assertion when force_writemask_all is on.
This assertion was meant to catch code inadvertently escaping the
control flow jail determined by the group of channel enable signals
selected by some caller, however it seems useful to be able to
increase the default execution size as long as force_writemask_all is
enabled, because force_writemask_all is an explicit indication that
there is no longer a one-to-one correspondence between channels and
SIMD components so the restriction doesn't apply.
In addition reorder the calls to fs_builder::group and ::exec_all in a
couple of places to make sure that we don't temporarily break this
invariant in the future for instructions with exec_size higher than
the dispatch width.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 8276ba260e5500664b8d8748f3224f73ef221887
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Jul 1 03:47:41 2015 -0400
nouveau: rename var name for nouveau_vieux to avoid conflict with nouveau
We want to require different versions for nouveau and nouveau_vieux.
autoconf will only check for NOUVEAU once if both drivers are enabled,
meaning both version checks don't get executed. Rename the nouveau_vieux
one to NVVIEUX to avoid the issue.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Tested-by: Alexandre Courbot <acourbot at nvidia.com>
Tested-by: Martin Peres <martin.peres at free.fr>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit f045b8b2ff5ac75da3e092f482fd1717571d8462
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Mon Jun 29 15:23:45 2015 +0300
glsl: create program resource list after LinkShader
Resource list can be created properly only after LinkShader hook
has been called to make sure all dead variables have been removed.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90925
commit 73afa31f07fe4af605088f6590edc4227652c482
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Mon Jun 29 14:39:05 2015 +0300
glsl: expose build_program_resource_list function
This is required so that we can move resource list creation
to happen later.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
commit ccaf37f4496eb836866c9daacf21f1f5ac8c6d66
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Mon Jun 29 14:19:00 2015 +0300
glsl: build stageref mask using IR, not symbol table
Instead of using symbol table, build mask by inspecting IR. This
change is required by further patches to move resource list creation
to happen later when symbol table does not exist anymore.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
commit 19ea623586aacc995b3f4a1a3ea321ead12dc43c
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Jun 29 16:58:17 2015 +0800
ilo: remove ilo_image_params
It suffices to use ilo_image_layout directly.
commit b4c66e4d3eadc04bdffbf4821636299bc49c89a4
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Jun 29 16:51:46 2015 +0800
ilo: add image_init_gen6_transfer_layout()
It replaces img_init_for_transfer().
commit 3c6af396f9526bdc8351ff61bcc6c42a3892e6b8
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Jun 29 16:46:34 2015 +0800
ilo: add image_set_gen6_bo_size()
It replaces img_calculate_bo_size().
commit 0896d629fded96178daa79c393ba4dae0d56f2ff
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Jun 29 16:42:04 2015 +0800
ilo: add image_set_gen6_{hiz,mcs}
They replace img_calculate_{hiz,mcs}_size().
commit 0da3b732ad156f63e32e7520bc1af97e1b733be7
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Jun 29 16:38:49 2015 +0800
ilo: add image_get_gen6_monolithic_size()
It replaces img_align().
commit 0faeb21dc0c029b345eaf5545b17b97d5fb8d8da
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Jun 29 16:25:32 2015 +0800
ilo: add image_get_gen6_lods()
It replaces img_init_lods() and img_init_layer_height().
commit f1946546c7d4ac22799a8b4944d6c36b77e22626
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Jun 29 16:16:11 2015 +0800
ilo: add image_get_gen{6,7}_alignment()
They replace img_init_alignments().
commit c88e6cdfbfd7a7727dbae6b47a803b18aca5d9f4
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Jun 29 16:14:36 2015 +0800
ilo: add image_get_gen6_{hiz,mcs}_enable()
They replace img_init_aux().
commit c3b205dbeba9534e0cf707ddd9c075170ccad1bf
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Jun 29 16:11:09 2015 +0800
ilo: add image_get_gen6_tiling()
It replaces img_init_tiling().
commit 9e13f5c85f23ff67e685b41a4d439fc443de2dd0
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Jun 29 16:02:52 2015 +0800
ilo: add image_get_gen6_layout()
It replaces only img_init_walk() right now. It will replace all img_init_*().
commit 5dcb28c3d26828ed1b0e2bd5a0589c5baab04b85
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Jul 1 02:11:39 2015 -0400
nv50/ir: copy joinAt when splitting both before and after
The current implementation only moves the joinAt when splitting after
the given instruction, not before it. So if you have a BB with
foo
instr
bar
joinat
and thus with joinAt set, we end up first splitting before instr, at
which point the instr's bb is updated to the new bb. Since that bb
doesn't have a joinAt set (despite containing one), when splitting after
the instr, there is nothing to copy over. Since the joinat will be in
the "split" bb irrespective of whether we're splitting before or after
the instruction, move it over in either case.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91124
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
commit 4caaa2681e727fa6405ff6de6d1f6c6a356ede34
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Jun 29 17:11:59 2015 +1000
docs: update for llvmpipe fp64 support
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit e35c5717837d9ac6d9722b011852bdf187f29776
Author: Dave Airlie <airlied at gmail.com>
Date: Sat Jun 27 14:21:54 2015 +1000
gallivm: add fp64 support. (v2.1)
This adds support for ARB_gpu_shader_fp64 and ARB_vertex_attrib_64bit to
llvmpipe.
Two things that don't mix well are SoA and doubles, see
emit_fetch_double, and emit_store_double_chan in this.
I've also had to split emit_data.chan, to add src_chan,
which can be different for doubles.
It handles indirect double fetches from temps, inputs, constants
and immediates. It doesn't handle double stores to indirects,
however it appears the mesa/st doesn't currently emit these,
it always does UARL/MOV combos, which will work fine.
tested with piglit, no regressions, all the fp64 tests seem to pass.
v2:
switch to using shuffles for fetch/store (Roland)
assert on indirect double stores - mesa/st never emits these (it uses MOV)
fix indirect temp/input/constant/immediates (Roland)
typos/formatting fixes (Roland)
v2.1:
cleanup some long lines, emit_store_double_chan cleanups.
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 5ccd61217d873567b8d9a7a0fa8f678522ec78cb
Author: Dave Airlie <airlied at gmail.com>
Date: Sat Jun 27 14:21:27 2015 +1000
tgsi: add infer support for double opcodes.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 1de93f94991c41081c3d9e01c2097401970f4095
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Tue Jun 23 07:53:24 2015 +1000
freedreno: use consistent version string format
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit 5afed936fea56a60300c6ed1228eaccf60c8cbd6
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Tue Jun 23 07:47:58 2015 +1000
glsl: use consistent version string format
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit ebe3043eeacb073c7dbb6162d8f0aee3bc66eeb1
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Jun 30 17:47:53 2015 -0700
i965/fs: Fix PIXEL_X/Y in regs_read()
PIXEL_X/Y takes a vec2 in the first argument
commit 830f67046ace3c0b95a7f093fe373eeb417a1aad
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Jun 18 12:44:35 2015 -0700
i965/fs: Remove the width field from fs_reg
As of now, the width field is no longer used for anything. The width field
"seemed like a good idea at the time" but is actually entirely redundant
with the instruction's execution size. Initially, it gave us the ability
to easily set the instructions execution size based entirely on register
widths. With the builder, we can easiliy set the sizes explicitly and the
width field doesn't have as much purpose. At this point, it's just
redundant information that can get out of sync so it really needs to go.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Acked-by: Francisco Jerez <currojerez at riseup.net>
commit 7f77abc9edf1348b8c6b82dfff102896cd4a2a58
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Jun 18 13:57:37 2015 -0700
i965/fs_generator: Use inst->exec_size for determining hardware reg widths
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Acked-by: Francisco Jerez <currojerez at riseup.net>
commit 83458e7c53cfc1f344280da6eb9a3b4e2dfdbc00
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Jun 18 13:49:22 2015 -0700
i965/fs: Use exec_size instead of dst.width for computing component size
There are a variety of places where we use dst.width / 8 to compute the
size of a single logical channel. Instead, we should be using exec_size.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Acked-by: Francisco Jerez <currojerez at riseup.net>
commit 9a0c883292cf48910a32634f7cc8b855e08c09d5
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Jun 25 11:00:01 2015 -0700
i965/fs: Use the builder dispatch_width for computing register offsets
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 21803b7b3304f053a48e313951ffddf1d2cd0bd9
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Jun 18 13:41:38 2015 -0700
i965/fs: Use the builder dispatch width instead of dst.width for pull constants
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Acked-by: Francisco Jerez <currojerez at riseup.net>
commit c9676329dd6c69b2e0b12405c3b4078f7d216f2f
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Jun 18 12:34:52 2015 -0700
i965/fs: Remove exec_size guessing from fs_inst::init()
Now that all of the non-explicit constructors are gone, we don't need to
guess anymore.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Acked-by: Francisco Jerez <currojerez at riseup.net>
commit b624ccc206cbf19989c6562416d7c21b66270577
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Jun 18 12:51:51 2015 -0700
i965/fs_builder: Use the dispatch width for setting exec sizes
Previously we used dst.width but the two *should* be the same.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Acked-by: Francisco Jerez <currojerez at riseup.net>
commit 500525e96019aff551afa8fee841d00ca9ec4c4f
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Jun 18 12:50:09 2015 -0700
i965/fs: Use exec_size for determining regs read/written and partial writes
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Acked-by: Francisco Jerez <currojerez at riseup.net>
commit 89bc4c78c394e50ddb16cc089bd3ec90681342d7
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Jun 18 12:30:43 2015 -0700
i965/fs: Remove fs_inst constructors that don't take an explicit exec_size
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Acked-by: Francisco Jerez <currojerez at riseup.net>
commit 67c4c9e1a709508b88d6d31eb1f7cb61d187189e
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Jun 18 12:24:27 2015 -0700
i965/fs: Make better use of the builder in shader_time
Previously, we were just depending on register widths to ensure that
various things were exec_size of 1 etc. Now, we do so explicitly using the
builder.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Acked-by: Francisco Jerez <currojerez at riseup.net>
commit f7dcc1160331462a071c54ca1067f9e2f57b55be
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Jun 18 12:07:27 2015 -0700
i965/fs: Add a builder argument to offset()
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Acked-by: Francisco Jerez <currojerez at riseup.net>
commit 7fcbe141076d18bf0245de1fd589c82f7c543fdf
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Jun 25 10:55:51 2015 -0700
i965/fs: Move offset(fs_reg, unsigned) to brw_fs.h
Shortly, offset() will depend on the builder so we need it moved to some
place where it has access to that.
Reviewed-by: Iago Toral Quiroga <itoral at igali.com>
Acked-by: Francisco Jerez <currojerez at riseup.net>
commit b535ba55ed6023f402374aeff79f9f37dbb21df0
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Jun 18 12:00:54 2015 -0700
i965/blorp: Explicitly set execution sizes for new'd instructions
This doesn't affect instructions allocated using the builder.
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Acked-by: Francisco Jerez <currojerez at riseup.net>
commit 362eff7741f9ca6e49074509120a2e6c03ef7ae6
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Jun 18 15:58:59 2015 -0700
i965/fs: Set the builder group for emitting FB-write stencil/AA alpha
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Acked-by: Francisco Jerez <currojerez at riseup.net>
commit 438e9c8b88c8faf7cbc2a20b03c077342be214e3
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Jun 17 17:32:24 2015 -0700
i965/fs: Explicitly set the exec_size on the add(32) in interpolation setup
Soon we will start using the builder to explicitly set all the execution
sizes. We could make a 32-wide builder, but the builder asserts that we
never grow it which is usually a reasonable assumption. Since this one
instruction is a bit of an odd-ball, we just set the exec_size explicitly.
v2: Explicitly new the fs_inst instead of using the builder and setting
exec_size after the fact.
v3: Set force_writemask_all with the builder instead of directly. The
builder over-writes it if we set it manually. Also, if we don't have
force_writemask_all in the builder it will assert-fail on SIMD32.
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
Acked-by: Francisco Jerez <currojerez at riseup.net>
commit c5a8da5f24eae4479b4ebe6301d780f781e24ed2
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Jun 30 15:51:13 2015 -0700
i965/fs: Properly handle LOAD_PAYLOAD in fs_inst::regs_read
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 12bc22ef58377191508af91a918efd18e2da7500
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Jun 18 17:48:27 2015 -0700
i965/fs: Report the right value in fs_inst::regs_read() for PIXEL_X/Y
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Acked-by: Francisco Jerez <currojerez at riseup.net>
commit aca5228011e7b9e96f3bd3a621c88e63ba47a4f3
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Jun 17 18:02:11 2015 -0700
i965/fs: Fix fs_inst::regs_read() for uniform pull constant loads
Previously, fs_inst::regs_read() fell back to depending on the register
width for the second source. This isn't really correct since it isn't a
SIMD8 value at all, but a SIMD4x2 value. This commit changes it to
explicitly be always one register.
v2: Use mlen for determining the number of registers read
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
Acked-by: Francisco Jerez <currojerez at riseup.net>
commit 241317d59ab440bdcda25bacaadacfb3b4c2dd93
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Jun 19 12:58:37 2015 -0700
i965/fs: Actually set/use the mlen for gen7 uniform pull constant loads
Previously, we were allocating the payload with different sizes per gen and
then figuring out the mlen in the generator based on gen. This meant,
among other things, that the higher level passes knew nothing about it.
Acked-by: Francisco Jerez <currojerez at riseup.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 3258e1b80d66ec26f14a24a5eae0629a2d23a444
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Jun 18 11:53:08 2015 -0700
i965/fs: Use a switch statement in fs_inst::regs_read()
This makes things a little simpler, more efficient, and quite a bit more
readable.
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit aa7d4cecec1a1236d237b83ebf035285f438ee67
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Wed Jun 24 12:55:41 2015 -0700
nir: remove parent_instr from nir_register
It's no longer used.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit f49e51ef44ac6400967731b75db871129b6c45f5
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Wed Jun 24 12:43:15 2015 -0700
nir: remove nir_src_get_parent_instr()
It's now unused.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 0ecdf04060518149e99a098caf4f6025fd6482a4
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Thu Jun 25 16:22:26 2015 -0700
i965/fs: emit constants only once
Before, we would lazily emit a MOV whenever we encountered a use of a
constant. Now that we have a dedicated file for SSA values, we can
instead only emit the MOV's once, which is more consistent and prevents
us from relying on CSE to re-combine the constants when they aren't
absorbed into the instruction.
total instructions in shared programs: 6078991 -> 6073118 (-0.10%)
instructions in affected programs: 402221 -> 396348 (-1.46%)
helped: 1527
HURT: 0
GAINED: 8
LOST: 2
v2: split this out from the previous commit (Jason)
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 864907e2f14523c130e6ff24c081789bb079bae1
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Wed Jun 24 12:28:47 2015 -0700
i965/fs: use SSA values directly
Before, we would use registers, but set a magical "parent_instr" field
to indicate that it was actually purely an SSA value (i.e., it wasn't
involved in any phi nodes). Instead, just use SSA values directly, which
lets us get rid of the hack and reduces memory usage since we're not
allocating a nir_register for every value. It also makes our handling of
load_const more consistent compared to the other instructions.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 2b1a1d8b1294f91b7ac563da1f395deba4384765
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Wed Jun 24 05:28:34 2015 -0700
nir/from_ssa: add a flag to not convert everything from SSA
We already don't convert constants out of SSA, and in our backend we'd
like to have only one way of saying something is still in SSA.
The one tricky part about this is that we may now leave some undef
instructions around if they aren't part of a phi-web, so we have to be
more careful about deleting them.
v2: rename and flip meaning of flag (Jason)
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit af2aea40d29dffd5e584432e0652db114113469b
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Jun 18 20:39:28 2015 +0100
egl/x11: handle when invalid drawable is passed in create_surface
0 is not used as a valid drawable id, as such there is no point in
attempting to query its geometry. Just bail out early and provide the
more meaningful EGL_BAD_NATIVE_WINDOW to the user.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 4ea5223a95436b76a3f808732c565e9833f84551
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Jun 18 20:22:54 2015 +0100
egl/wayland: cleanup dri2_wl_create_surface error path
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 0afa6335079093627b47ff08da38bed00972c217
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Jun 18 20:19:32 2015 +0100
egl/wayland: handle NULL native_window in create_surface
Raise EGL_BAD_NATIVE_WINDOW instead of crashing.
v2: s/Rise/Raise/ (spotted by Michel)
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 6098ef824467f685fb34914eb3fef73b3ba18c6f
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Jun 18 20:16:46 2015 +0100
egl/drm: plug memory leak
Free the memory for dri2_surf in the unlikely case that one provides
NULL for native_window. Also set the relevant EGL_ERROR to provide
feedback to the user.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 879dcf07f6a3ab56f23d540b0df94c57e0706094
Author: Rob Clark <robclark at freedesktop.org>
Date: Fri Jun 26 14:24:08 2015 -0400
gallium/ttn: don't upset nir_validate w/ BRK's
Previously we were unconditionally doing ttn_get_src() even for
instructions with no src's. Which created a lot of unnecessary
load_const instructions. These were mostly harmless since NIR opt
passes would strip them back out. But for an ENDIF following a
BRK, it would result in load_const instructions created after the
NIR break instruction. Which nir_validate dislikes.
But we can actually just dtrt by using NumSrcRegs instead.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit d1f0e019797863b23388bfef53a77f659f749d3c
Author: Rob Clark <robclark at freedesktop.org>
Date: Fri Jun 26 13:48:29 2015 -0400
gallium/ttn: add TXB2
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 6082515de7c7b4885bd685d88aee32fc9e5103a1
Author: Rob Clark <robclark at freedesktop.org>
Date: Sat Jun 27 09:58:28 2015 -0400
gallium/ttn: partial fix for output arrays
It isn't quite yet practical to enable TGSI_ANY_INOUT_DECL_RANGE shader
cap yet, at least not in drivers that need lower_to_scalar pass (which
right now is all of the ttn users), since the register arrays do not get
converted to SSA, which angers nir_lower_alu_to_scalar.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit dc7e6463d3ec6980f1517ff10048e0dbf5bb38ad
Author: Rob Clark <robclark at freedesktop.org>
Date: Sat Jun 27 10:07:18 2015 -0400
nir: cleanup open-coded instruction casts
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
commit 00b6b41482985ba4a81fbb479a47c06ec83f3797
Author: Rob Clark <robclark at freedesktop.org>
Date: Mon Jun 29 14:49:08 2015 -0400
freedreno/ir3: cache defining instruction
It is silly to traverse back to find first instruction that writes part
of a larger "virtual" register many times per instruction (plus per use
as a src to later instructions). Cache this information so we only
figure it out once.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 906da495272b1be4c278f5f7402594e3c52521c1
Author: Rob Clark <robclark at freedesktop.org>
Date: Sun Jun 28 11:13:58 2015 -0400
freedreno/ir3: fix RA issue with fanin
The fanin source could be grouped, for example with shaders like:
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[9]
DCL SAMP[0]
DCL SVIEW[0], 2D, FLOAT
DCL TEMP[0], LOCAL
0: MOV TEMP[0].xy, IN[1].xyyy
1: MOV TEMP[0].w, IN[1].wwww
2: TXF TEMP[0], TEMP[0], SAMP[0], 2D
3: MOV OUT[1], TEMP[0]
4: MOV OUT[0], IN[0]
5: END
The second arg to the isaml is IN[1].w, so we need to look at the fanin
source to get the correct offset.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit db5105b4b35e064f3934154b45de15422a1bdb0a
Author: Rob Clark <robclark at freedesktop.org>
Date: Mon Jun 29 10:21:08 2015 -0400
freedreno/ir3: add ir3_shader_disasm()
Split out most of dump_info() from ir3_cmdline compiler into a function
that can be used both by cmdline compiler and also for the disasm debug
option. This way, for FD_MESA_DEBUG=disasm we also get to see intput/
output registers, etc.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 3244195f48affec1d3c2eb5d0e267c75b046db9f
Author: Rob Clark <robclark at freedesktop.org>
Date: Fri Jun 26 13:55:49 2015 -0400
freedreno/a4xx: fix for sparse-samplers
Some piglit tests, like arb_fragment_program-sparse-samplers, result in
having a null samp#0 but valid samp#1.
TODO: a3xx probably needs similar fix
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 0a8c8fa770db4cc4ef3db89a5dae1d136361495d
Author: Rob Clark <robclark at freedesktop.org>
Date: Fri Jun 26 13:38:03 2015 -0400
freedreno/ir3: fix crash in fail path
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 1370fde8af1b0b5c5e6204c0dea6ebffb85dce0a
Author: Rob Clark <robclark at freedesktop.org>
Date: Fri Jun 26 14:32:08 2015 -0400
freedreno/ir3: fix crash in RA
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit bb2c4b68f78f0105088c11408f8902fb22802125
Author: Rob Clark <robclark at freedesktop.org>
Date: Fri Jun 26 10:52:34 2015 -0400
freedreno/ir3: fixes for indirect writes
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 01b5f1336330f1c0f937fb08a444efc593b43435
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Jun 24 18:57:22 2015 -0400
freedreno/ir3: fix constlen in case of load_uniform_indirect
We can't rely on what we get from the assembler if we have indirect
addressing of constant file, since the assembler doesn't know the array
index. This got lost in the transition to NIR.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 9350ea6979c48772e1fb55d4f1c7c5a3cfa987b0
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Tue May 19 15:01:49 2015 +0300
glsl: validate sampler array indexing for 'constant-index-expression'
Desktop GLSL < 130 and GLSL ES < 300 allow sampler array indexing where
index can contain a loop induction variable. This extra check will warn
during linking if some of the indexes could not be turned in to constant
expressions.
v2: warning instead of error for backends that did not enable
EmitNoIndirectSampler option (have dynamic indexing)
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
Cc: "10.5" and "10.6" <mesa-stable at lists.freedesktop.org>
commit f17c8c287f3581fccb52714fbd4b2ea09a58e3d3
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Mon Jun 29 09:48:52 2015 +0300
mesa/st: use EmitNoIndirectSampler if !ARB_gpu_shader5
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Cc: "10.5" and "10.6" <mesa-stable at lists.freedesktop.org>
commit 2dc2b12ed15abb84c7e2b3c2726dcc1b735abcda
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Mon Jun 29 09:53:45 2015 +0300
i915: use EmitNoIndirectSampler
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
Cc: "10.5" and "10.6" <mesa-stable at lists.freedesktop.org>
commit 8852e26e93af1fc4b72bf9d57e847f53e1a1371b
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Wed Jun 24 13:22:43 2015 +0300
i965: use EmitNoIndirectSampler for gen < 7
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
Cc: "10.5" and "10.6" <mesa-stable at lists.freedesktop.org>
commit e4512e1581cf90f56d13cfa6a809832ef3517283
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Tue Jun 9 13:33:39 2015 +0300
mesa/glsl: new compiler option EmitNoIndirectSampler
Patch provides new compiler option for backend to force unroll loops
that have non-constant expression indexing on sampler arrays.
This makes sure that we can never end up with a shader that uses loop
induction variable as sampler array index but does not unroll because
of having too much instructions. This would not work without dynamic
indexing support.
v2: change option name as EmitNoIndirectSampler
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
Cc: "10.5" and "10.6" <mesa-stable at lists.freedesktop.org>
commit edb8383c98ee23385731d0fc23a6b6673528a8ec
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Tue Jun 9 13:28:44 2015 +0300
glsl: Allow dynamic sampler array indexing with GLSL ES < 3.00
Dynamic indexing of sampler arrays is prohibited by GLSL ES 3.00.
Earlier versions allow 'constant-index-expression' indexing, where
index can contain a loop induction variable.
Patch allows dynamic indexing for sampler arrays when GLSL ES < 3.00.
This change makes 'sampler-array-index.frag' parser test in Piglit
pass + fishgl.com works when running Chrome on OpenGL ES 2.0 backend
v2: small change and some more commit message (Tapani)
v3: refactor checks to make it more readable (Ian Romanick)
v4: change warning comment in GLSL ES case (Curro)
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Signed-off-by: Kalyan Kondapally <kalyan.kondapally at intel.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
Cc: "10.5" and "10.6" <mesa-stable at lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84225
commit d5f1253b0c4637ad996fd0da45095165006d61d3
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Tue Jun 30 02:46:26 2015 -0400
nv50/ir: fix emission of address reg in 3rd source
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91056
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
commit 21b7c58b8a0cbf18c9ed90c260f01d00fefe0db2
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Jun 23 23:57:31 2015 -0700
i965: Don't use GCC extension for ?: with only two operands.
From the "apparently I don't know C" files...GCC apparently supports:
x ?: y
which is equivalent to
x ? x : y
except that it doesn't cause side-effects to occur twice. See:
https://gcc.gnu.org/onlinedocs/gcc/Conditionals.html#Conditionals
This was confusing and looked like a typo. It doesn't really buy us
anything, so just write the obvious code in normal C.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit e22e0de0d7c3a412bdd53c6d53825b7646624e3d
Author: Alexander von Gluck IV <kallisti5 at unixzen.com>
Date: Mon Jun 29 23:29:44 2015 -0500
egl/haiku: fix Mesa build under Haiku
Performing a goto crosses the initialization of 'BWindow* win'
breaking the build. We also fix a missing semicolon.
commit 089e7c378838e7972d2c0588bb84a316fb929a59
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Jun 29 21:58:54 2015 -0400
nv30: align transfer stride to 64, required by blit, sifm transfer impls
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit dacf9efd6326bed1166750680bfaa4e173315eba
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Jun 29 21:58:11 2015 -0400
nv30: allow vertex state creation with 0 elements
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit bad107f2ec24b16118f4d99c54b853277b1a966d
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Jun 29 02:38:38 2015 -0400
nv30: reset fragprog bufctx at bind time
A clear will do a partial validate, which will in turn reference all the
buffers in the bufctx again. However the fragprog last validated might
have already been deleted. So reset the bufctx when updating state.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit b875198f1f0b7c90bcb22511c0050b06d8a33ac4
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Jun 29 02:16:23 2015 -0400
nv30: modernize fp upload logic
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 54afb10f0e0a3b72a977c239c0aee04ea5dec967
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Jun 29 22:04:50 2015 -0400
nv30: provide a minimum map buffer alignment
Otherwise we return 0, which is out of spec. Return 64 like all the
other nouveau drivers.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 3df5aaaa158bfb878e9e5ce467dd654466942880
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Wed May 27 19:28:34 2015 -0700
i965/skl: Extract the blit command setup in to a helper
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit 412c8c8e7eaeec2763bb21a30626544b5a711cb2
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Tue Apr 14 22:06:49 2015 -0700
i965/gen9: Add XY_FAST_COPY_BLT support to intelEmitCopyBlit()
This patch enables using XY_FAST_COPY_BLT only for Yf/Ys tiled buffers.
It can be later turned on for other tiling patterns (X,Y) too.
V3: Flush in between sequential fast copy blits.
Fix src/dst alignment requirements.
Make can_fast_copy_blit() helper.
Use ffs(), is_power_of_two()
Move overlap computation inside intel_miptree_blit().
V4: Use _mesa_regions_overlap() function.
Add check for src_buffer == dst_buffer.
Simplify horizontal and vertical alignment computations.
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit ca21c9ab28df24ef015ead28df1dcccd90387df6
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Tue Jun 9 15:18:13 2015 -0700
mesa/swrast: Use global function _mesa_regions_overlap()
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 2a397c7958089f766aa0d3c66016742fdf7494dd
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Fri Jun 5 19:23:46 2015 -0700
mesa/st: Use global function _mesa_regions_overlap()
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 7f282d05a11e0c29bddc1fac8c7028c7e823234f
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Fri Jun 5 19:18:19 2015 -0700
mesa: Add a new helper function _mesa_regions_overlap()
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 69ee316c1daf93b4a53b1c02301ffe9df9598d28
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Tue Apr 14 22:06:48 2015 -0700
i965/gen9: Allocate YF/YS tiled buffer objects
In case of I915_TILING_{X,Y} we need to pass tiling format to libdrm
using drm_intel_bo_alloc_tiled(). But, In case of YF/YS tiled buffers
libdrm need not know about the tiling format because these buffers
don't have hardware support to be tiled or detiled through a fenced
region. libdrm still need to know buffer alignment value for its use
in kernel when resolving the relocation.
Using drm_intel_bo_alloc_for_render() for YF/YS tiled buffers
satisfy both the above conditions.
V2: Delete min/max buffer size restrictions not valid for i965+.
Remove redundant align to tile size statements.
Remove some redundant code now when there are no min/max buffer size.
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit a1afd59662449803fa4a40a79bdf0db16ffcbcf5
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Fri Jun 5 10:56:40 2015 -0700
i965: Make a helper function intel_miptree_can_use_tr_mode()
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit 385cd3e0bed8113659f2db8976b677b090acc9d8
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Fri Jun 5 10:41:24 2015 -0700
i965: Make a helper function intel_miptree_release_levels()
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit c9dbdc08b9de016ab3b076feac3df4c81009996e
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Tue Apr 14 22:06:49 2015 -0700
i965/gen9: Plugin the code for selecting YF/YS tiling on skl+
Buffers with Yf/Ys tiling end up using meta upload / download
paths or the blitter for cases where they used tiled_memcpy paths
in case of Y tiling. This has exposed some bugs in meta path. To
avoid any piglit regressions on SKL this patch keeps the Yf/Ys
tiling disabled at the moment.
V3: Make brw_miptree_choose_tr_mode() actually choose TRMODE. (Ben)
Few cosmetic changes.
V4: Get rid of brw_miptree_choose_tr_mode().
Take care of all tile resource modes {Yf, Ys, none} for all
generations at one place.
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit 06f76b7fa68db1ac74ecca015412f71b3a5e9f9c
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Thu Jun 4 16:57:02 2015 -0700
i965: Make a helper function intel_miptree_set_alignment()
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit e566e5203aaba98109a67766cf28991de3358490
Author: Erik Faye-Lund <kusmabite at gmail.com>
Date: Sun Jun 28 14:51:09 2015 +0200
mesa/main: free locale at exit
In order to save a small leak if mesa is continously loaded and
unloaded, let's free the locale when the shared object is unloaded.
Signed-off-by: Erik Faye-Lund <kusmabite at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit c61bc6ed844b39e600cc64e3e552c7bf1894d7ba
Author: Erik Faye-Lund <kusmabite at gmail.com>
Date: Sun Jun 28 14:51:08 2015 +0200
util: port _mesa_strto[df] to C
_mesa_strtod and _mesa_strtof are only used from the GLSL compiler and
the ARB_[vertex|fragment]_program code, meaning that the locale doesn't
need to be initialized before the first OpenGL context gets initialized.
So let's use explicit initialization from the one-time init code instead
of depending on a C++ compiler to initialize at image-load time.
Signed-off-by: Erik Faye-Lund <kusmabite at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit de3e323be1bdc40a2a7d724d0f3db7a81a93bbbb
Author: Erik Faye-Lund <kusmabite at gmail.com>
Date: Sun Jun 28 14:51:07 2015 +0200
glsl: No need to lock in _mesa_glsl_release_types
This function only gets called while mesa is unloading, so there's
no potential of racing or multiple calls at the same time. So let's
just get rid of the locking.
Signed-off-by: Erik Faye-Lund <kusmabite at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 195ab79ddecbdbf1f1714c233df278bff46c13e8
Author: Erik Faye-Lund <kusmabite at gmail.com>
Date: Sun Jun 28 14:51:06 2015 +0200
mesa/main: only call _mesa_destroy_shader_compiler once on exit
There's no point in calling _mesa_destroy_shader_compiler multiple
times on exit; the resources will only be released once anyway.
So let's move the atexit-call into the part that is only called
once.
Signed-off-by: Erik Faye-Lund <kusmabite at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit ba5e1612c892282b930e278b5b98f1578cbe7dbb
Author: Erik Faye-Lund <kusmabite at gmail.com>
Date: Sun Jun 28 14:51:05 2015 +0200
dri: don't touch the shader compiler
This function is for deleting per-screen resources, and the shader
compiler resources are not of such nature. Besides, dri shouldn't
need to even know about the presence of a shader compiler.
These resources will already be released when mesa gets unloaded,
and that should be sufficient.
Signed-off-by: Erik Faye-Lund <kusmabite at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 73d2b5af526676fd3f34243cdc155b3e1341b988
Author: Erik Faye-Lund <kusmabite at gmail.com>
Date: Sun Jun 28 14:51:04 2015 +0200
mesa/main: Get rid of outdated GDB-hack
All of these enums are now in use around in the code, so there's no need
to explicitly use them here any more.
Signed-off-by: Erik Faye-Lund <kusmabite at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit d15b32ebded278243eb648bb9ecd4c5f5d6d0569
Author: Grigori Goronzy <greg at chown.ath.cx>
Date: Thu May 28 13:01:51 2015 +0200
clover: implement CL_KERNEL_PREFERRED_WORK_GROUP_SIZE_MULTIPLE
Work-group size should always be aligned to subgroup size; this is a
basic requirement, otherwise some work-items will be no-operation.
It might make sense to refine the value according to a kernel's
resource usage, but that's a possible optimization for the future.
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 249a9df7fce0a6bebc70852ab583c5324208bf06
Author: Grigori Goronzy <greg at chown.ath.cx>
Date: Thu May 28 12:40:29 2015 +0200
gallium: add PIPE_COMPUTE_CAP_SUBGROUP_SIZE
We need this to implement OpenCL's
CL_KERNEL_PREFERRED_WORK_GROUP_SIZE_MULTIPLE.
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit c0ca6c30eaf7f488f154c462a01a8945cb4a3103
Author: Neil Roberts <neil at linux.intel.com>
Date: Fri Jun 26 17:54:15 2015 +0100
i965: Don't try to print the GLSL IR if it has been freed
Since commit 104c8fc2c2aa5621261f8 the GLSL IR will be freed if NIR is
being used. This was causing it to segfault if INTEL_DEBUG=wm is set.
This patch just makes it avoid dumping the GLSL IR in that case.
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit dd9ceb0219f6ca7864940ee1961f1b1890d27cea
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Jun 29 09:03:19 2015 +0100
docs: add news item and link release notes for mesa 10.6.1
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 24df6cd0f7723e163d75ed3eb0b7e22adc3ffd7f
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Jun 29 09:00:24 2015 +0100
docs: Add sha256 checksums for the 10.6.1 release
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit 6ff3ae8deb1d99037f2f8e5890b09bd984059cf0)
commit 07158c508ac9b933d60dd3e2cd1e748601c44b68
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Jun 29 08:23:14 2015 +0100
Add release notes for the 10.6.1 release
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit a871e80fc6237fa029d6970f7e9b414fd097bd98)
commit 6218c68bece0cea671f2940a651119a87ab8b24e
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sun Jun 28 22:17:16 2015 -0700
Revert "glsl: clone inputs and outputs during linking"
This reverts commit c2ff3485b3d48749ea9dcad07bc1a691627dc3e5.
Ilia and I noticed a memory leak caused by this patch: at least with
fixed-function programs, we clone things using ProgramResourceList as
the context before reralloc makes it non-NULL.
I believe Tapani found other bugs with these patches, so I'm just going
to revert them for now and let him pursue them further.
commit cae701fc8ed0faeaaaafd1cf57f6143031edcab2
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sun Jun 28 22:17:09 2015 -0700
Revert "i965: Delete linked GLSL IR when using NIR."
This reverts commit 104c8fc2c2aa5621261f80aa6b4f76c3163078f1.
commit 61912036d1cb67e52b1cc191bdff8ebded439e8c
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Jun 29 00:23:55 2015 -0400
nv30: avoid leaking blit fp/vp
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit b5622313ea2e070cc0c20c7cdccd844d383713d0
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Jun 28 22:30:27 2015 -0400
nv40: enable base vertex
Still appears to have issues with negative indices less than -1M, but
that's a corner case of a corner case.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 19a0ba130fd0d0f3b86181a8d05cf5391420360d
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Jun 26 15:05:13 2015 -0700
i965/vs: Move compute_clip_distance() out of emit_urb_writes().
Legacy user clipping (using gl_Position or gl_ClipVertex) is handled by
turning those into the modern gl_ClipDistance equivalents.
This is unnecessary in Core Profile: if user clipping is enabled, but
the shader doesn't write the corresponding gl_ClipDistance entry,
results are undefined. Hence, it is also unnecessary for geometry
shaders.
This patch moves the call up to run_vs(). This is equivalent for VS,
but removes the need to pass clip distances into emit_urb_writes().
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit 17e8fca626c908dcbedabf57ce175113840e65c2
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri May 29 22:40:07 2015 -0700
i965: Write at least some data in SIMD8 URB write messages.
According to the "URB SIMD8 Write > Write Data Payload" documentation,
"The write data payload can be between 1 and 8 message phases long."
Apparently, the simulator considers it an error if you issue an URB
SIMD8 message with only a header and no actual data to write.
v2: Try to put in a better PRM citation, now that the Broadwell docs
actually exist (requested by Jordan).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit b4b4406e1e8dcf577551087cc6eb068e5303efdf
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Wed Jun 24 21:11:27 2015 +0200
gallium/hud: prevent NULL pointer dereference with pipe_query functions
The HUD doesn't check if query_create() fails and it calls other
pipe_query functions with NULL pointer instead of a valid query object.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit a98600b0ebdfc8481c168aae6c5670071e22fc29
Author: Mario Kleiner <mario.kleiner.de at gmail.com>
Date: Fri Jun 5 15:36:52 2015 +0200
nouveau: Use dup fd as key in drm-winsys hash table to fix ZaphodHeads.
The dup'ed fd owned by the nouveau_screen for a device node
must also be used as key for the winsys hash table, instead
of using the original fd passed in for a screen, to make
multi-x-screen ZaphodHeads configurations work on nouveau.
The original fd's lifetime differs from that of the nouveau_screen stored
in the hash. The hash key is the fd, and in order to compare hash entries
we fstat them, so the fd must be around for as long as the screen is.
This is an extension of the fix in commit a59f2bb1 (nouveau: dup fd
before passing it to device).
Cc: "10.3 10.4 10.5 10.6" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Mario Kleiner <mario.kleiner.de at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 2a210b797eacd27a556af9c5e0edca940f9486c5
Author: Mike Stroyan <mike at lunarg.com>
Date: Fri Jun 26 15:15:46 2015 -0600
meta: Only change and restore viewport 0 in mesa meta mode
The meta code was setting a default depth range for all viewports
and 'restoring' all viewports to depth range values saved from viewport 0.
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 556dd4af76ca0be9b0698139c06e6d12d52e8ff3
Author: Dave Airlie <airlied at redhat.com>
Date: Thu Jun 25 03:55:54 2015 +0100
radeonsi: add support for geometry shader invocations.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 7e5064360c03b8dbdd60298b46e1595418c6cea3
Author: Dave Airlie <airlied at redhat.com>
Date: Thu Jun 25 03:36:23 2015 +0100
radeonsi: add support for viewport array (v3)
This isn't pretty and I'd suggest it the pm4 interface builder
could be tweaked to do this more efficently, but I'd need
guidance on how that would look.
This seems to pass the few piglit tests I threw at it.
v2: handle passing layer/viewport index to fragment shader.
fix crash in blit changes,
add support to io_get_unique_index for layer/viewport index
update docs.
v3: avoid looking up viewport index and layer in es (Marek).
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 35d83793047b3de31a706fa2a62a233090ea7cfc
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Jun 18 13:55:52 2015 -0700
i965/fs: Fix ir_txs in emit_texture_gen4_simd16().
We were not emitting the LOD, which led to message lengths of 1 instead
of 3. Setting has_lod makes us emit the LOD, but I had to make changes
to avoid emitting the non-existent coordinate as well.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91022
Cc: mesa-stable at lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit ad62ec8316a926682958e7ab52639992867c3755
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Jun 26 15:01:22 2015 -0400
nv50/ir: propagate modifier to right arg when const-folding mad
An immediate has to be the second arg of an ADD operation. However we
were mistakenly propagating the modifier of the non-folded value to the
folded immediate argument.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91117
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
commit 052b3d4e2f159038137504f01e9ff2380a67af8b
Author: Boyan Ding <boyan.j.ding at gmail.com>
Date: Sat Jun 13 15:36:27 2015 +0800
egl_dri2: Remove trailing whitespaces
Signed-off-by: Boyan Ding <boyan.j.ding at gmail.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 3cf90bb183c7f403ded4c069a78eae1fd71f8eab
Author: Neil Roberts <neil at linux.intel.com>
Date: Tue Jun 16 13:53:40 2015 +0100
i965/skl: Fix aligning mt->total_width to the block size
brw_miptree_layout_2d tries to ensure that mt->total_width is a
multiple of the compressed block size, presumably because it wouldn't
be possible to make an image that has a fraction of a block. However
it was doing this by aligning mt->total_width to align_w. Previously
align_w has been used as a shortcut for getting the block width
because before Gen9 the block width was always equal to the alignment.
Commit 4ab8d59a2 tried to fix these cases to use the block width
instead of the alignment but it missed this case.
I think in practice this probably won't make any difference because
the buffer for the texture will be allocated to be large enough to
contain the entire pitch and libdrm aligns the pitch to the tile width
anyway. However I think the patch is worth having to make the
intention clearer.
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit 404a90b82786080564fe32716f83ce055b9a934f
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Jun 10 16:30:56 2015 -0700
mesa: Enable subdir-objects globally.
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 229450520a23ba211fd9f7b3c9bc80f291229ec1
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Jun 24 14:06:33 2015 +0100
mesa: fold duplicated GL/GL_CORE/GLES3 entry in get_hash_params.py
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 7de85694fa606b112b8badd4f07969aef782efb8
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Jun 26 11:38:46 2015 +0800
ilo: define ILO_IMAGE_MAX_LEVEL_COUNT
Define ILO_IMAGE_MAX_LEVEL_COUNT for ilo_image and remove unnecessary header
includes.
commit cbdc26aa3f76dc20285caa7e62ca8809cb2fe638
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Thu Jun 25 22:27:04 2015 +0800
ilo: replace pipe_format by gen_surface_format
Replace pipe_format by gen_surface_format in ilo_image. Change how depth
format is specified in ilo_state_zs.
commit 2ee95f6d64aca9e9490c1ac293dd711b5f60a16b
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Thu Jun 25 07:43:47 2015 +0800
ilo: always use the specified image format
Move silent promotion of PIPE_FORMAT_ETC1_RGB8 or combined depth/stencil out
of core.
commit dc2e92b2d3d216fc9657f2ef594d7c5d0b03370e
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Wed Jun 24 22:47:30 2015 +0800
ilo: replace pipe_texture_target by gen_surface_type
Replace pipe_texture_target by gen_surface_type in ilo_image. Change how
GEN6_SURFTYPE_CUBE is specified in ilo_state_surface and ilo_state_zs.
commit 934e4a469fd37dac03b8280cce41df4d9f4ed123
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Wed Jun 24 22:46:36 2015 +0800
ilo: initialize ilo_image from ilo_image_info
Convert pipe_resource to ilo_image_info for image initialization.
commit f825fe8e13adfec4cd488bac3663b7e9c90a8c06
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Thu Jun 25 07:18:31 2015 +0800
ilo: remove ilo_image_disable_aux()
Fail resource creation when aux bo allocation fails.
commit 07acf9cb167d4e1f7aebd6837d22e3523ad63109
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Wed Jun 24 12:57:57 2015 +0800
ilo: improve SURFTYPE_BUFFER validations
Reorganize the validations to make them more systematic.
commit 9871646c132ba137709b0bfebfe285985dc351e6
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Jun 26 13:08:32 2015 +0800
ilo: remove ilo_buffer
Since the addition of ilo_vma, it was used only to pad a bo for sampling
engine surfaces. Replace it entirely with these functions
ilo_state_surface_buffer_size()
ilo_state_vertex_buffer_size()
ilo_state_index_buffer_size()
ilo_state_sol_buffer_size()
commit 36d107e92cc4c1d2b60e0017dbe998af3a2e8b75
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Tue Jun 23 23:59:31 2015 -0600
ilo: introduce ilo_vma
This cleans up the code a bit and makes ilo_state_vector_resource_renamed()
simpler and more robust. It also allows a single bo to back mulitple VMAs.
commit fbba25bba017b3dde5f6613698004b0086bdea00
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Tue Jun 23 08:42:14 2015 +0200
mesa: remove unnecessary checks in _mesa_readpixels_needs_slow_path
readpixels_can_use_memcpy will later call _mesa_format_matches_format_and_type
which does much tighter checks than these to decide if we can use
memcpy for readpixels.
Also, the checks do not seem to be extensive enough anyway, since we are
checking for signed/unsigned conversion only when the framebuffer has integers,
but the same checks could be done for other types anyway, since as long as
there is a signed/unsigned conversion we can't memcpy.
No regressions observed on i965/llvmpipe.
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 316206ee9ea06419c9a2ea6fe48d66a0b805319d
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Jun 25 08:08:27 2015 -0700
i965/vec4_live_variables: Do liveness analysis bottom-to-top
From Muchnick's Advanced Compiler Design and Implementation:
"To determine which variables are live at each point in a flowgraph, we
perform a backward data-flow analysis"
Previously, we were walking the blocks forwards and updating the livein and
then the liveout. However, the livein calculation depends on the liveout
and the liveout depends on the successor blocks. The net result is that it
takes one full iteration to go from liveout to livein and then another
full iteration to propagate to the predecessors. This works out to an
O(n^2) computation where n is the number of blocks. If we run things in
the other order, it's O(nl) where l is the maximum loop depth which is
practically bounded by 3.
In b2c6ba0c4b21391dc35018e1c8c4f7f7d8952bea, we made this same change in
the FS backend to great effect. Might as well keep it consistent and make
the same change for vec4. Also, this took the time to run the test:
ES31-CTS.arrays_of_arrays.InteractionFunctionCalls1
from 6:49.62 to 3:31.40 on Timothy Arceri's machine.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit c1151b18f2dce7c6f238f057e9c4fa8d912ce6b5
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Wed Jun 24 20:07:54 2015 -0700
i965/skl: Use more compact hiz dimensions
gen8 had some special restrictions which don't seem to carry over to gen9.
Quoting the spec for SKL:
"The Z_Height and Z_Width values must equal those present in
3DSTATE_DEPTH_BUFFER incremented by one."
This fixes nothing in piglit (and regresses nothing).
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 101a73846b48ebac8e2386a25b24659f013c66a4
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Jun 25 14:58:37 2015 +0200
radeonsi: don't fail in si_shader_io_get_unique_index
Trivial. Picked from my tessellation branch.
commit c97105ee12e54ab893351ebbda8c2348c899adde
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Jun 24 00:04:11 2015 -0700
i965: Drop brw->depthstencil.stencil_offset from gen8_depth_state.c.
This is always 0 - only brw_workaround_depthstencil_alignment ever sets
it, and that doesn't run on Gen6+. My initial Broadwell depth state
commit had this mistake.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 6026f7e8fb993a34f3e2ad1638d7a842a5cefd80
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Jun 11 01:59:44 2015 -0700
nir: Recognize max(min(a, 1.0), 0.0) as fsat(a).
We already recognize min(max(a, 0.0), 1.0) as a saturate, but neglected
this variant (which is also handled by the GLSL IR pass).
shader-db results on Broadwell:
total instructions in shared programs: 7363046 -> 7362788 (-0.00%)
instructions in affected programs: 11928 -> 11670 (-2.16%)
helped: 64
HURT: 0
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 77a78c65f80323059d892c501ca551ccf324b17d
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Jun 25 00:56:32 2015 +0200
softpipe,llvmpipe: fix PIPE_SHADER_CAP_MAX_INPUTS value
PIPE_MAX_SHADER_INPUTS was recently bumped to 80 because of tessellation.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91099
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91101
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit d1663ccb4c664b0f544ed5d6f0761f3ae2435199
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Wed Jun 17 15:50:11 2015 -0700
i965/bxt: Add basic Broxton infrastructure
The thread counts and URB information are all speculative numbers that were
based on some CHV numbers at the time.
v2:
Originally this patch had PCI IDs. I've moved that to a new patch at the end of
the series.
Remove is_cherryview hack.
Add PCI ids. These match the ones defined in the kernel. The only one tested by
us is 0x0a84.
Capitalize the hex string (Mark)
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Tested-by: "Lecluse, Philippe" <Philippe.Lecluse at intel.com>
Reviewed-by: Mark Janes <mark.a.janes at intel.com>
commit 9f261dc18dba0aa4dc43fc560d343ba9ffd486e9
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Jun 22 11:09:27 2015 -0700
radeon: Advertise correct GL_QUERY_COUNTER_BITS/GL_SAMPLES_PASSED value
Commit b765119c changed the default value of all the counter bits to
64. However, older hardware only has 32 counter bits.
This has only been build-tested. We don't have any tests that verify
the advertised value against implementation behavior, so I don't know
what additional testing could be done.
NOTE: It appears that many Gallium drivers (at least r300 and i915g)
have the same problem, but I don't see a way for the state-tracker to
determine the counter size. Marek says, "For Gallium, a new PIPE_CAP or
new get_xxx_param function will be needed."
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Cc: Alex Deucher <alexander.deucher at amd.com>
commit b2c6ba0c4b21391dc35018e1c8c4f7f7d8952bea
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Jun 8 16:03:19 2015 -0700
i965/fs_live_variables: Do liveness analysis bottom-to-top
From Muchnick's Advanced Compiler Design and Implementation:
"To determine which variables are live at each point in a flowgraph, we
perform a backward data-flow analysis"
Previously, we were walking the blocks forwards and updating the livein and
then the liveout. However, the livein calculation depends on the liveout
and the liveout depends on the successor blocks. The net result is that it
takes one full iteration to go from liveout to livein and then another
full iteration to propagate to the predecessors. This works out to an
O(n^2) computation where n is the number of blocks. If we run things in
the other order, it's O(nl) where l is the maximum loop depth which is
practically bounded by 3.
On my HSW desktop, one particular shadertoy test gets a 20% improvement in
compile times:
N Min Max Median Avg Stddev
x 10 15.965 16.884 16.026 16.1822 0.34736846
+ 10 12.813 13.052 12.876 12.8891 0.06913666
Difference at 95.0% confidence
-3.2931 +/- 0.235316
-20.3501% +/- 1.45417%
(Student's t, pooled s = 0.250444)
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 104c8fc2c2aa5621261f80aa6b4f76c3163078f1
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Thu Jun 11 10:41:53 2015 +0300
i965: Delete linked GLSL IR when using NIR.
This is based on Kenneth's patch to delete 'most of the IR'. Due to
linker changes to clone variables, we can now free all of IR.
Saves 58MB of memory when replaying a Dota 2 trace on Broadwell.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Cc: mesa-stable at lists.freedesktop.org
commit c2ff3485b3d48749ea9dcad07bc1a691627dc3e5
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Thu Jun 11 10:41:52 2015 +0300
glsl: clone inputs and outputs during linking
This increases memory pressure during linking but makes it easier
for backend to free IR after it is not needed anymore.
v2: use resource list as ralloc context in case of relink (Kenneth)
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Cc: mesa-stable at lists.freedesktop.org
commit 4b35ab9bdb4e663f41ff5c9ae5bbcc650b6093f9
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Thu Apr 30 17:04:51 2015 +0100
i965: Rename intel_emit* to reflect their new location in brw_pipe_control
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 9d4b9f1e0c661e5ed8ce2e71c76ce8cc1adf90dd
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Thu Apr 30 16:53:12 2015 +0100
i965: Transplant PIPE_CONTROL routines to brw_pipe_control
Start trimming the fat from intel_batchbuffer.c. First by moving the set
of routines for emitting PIPE_CONTROLS (along with the lore concerning
hardware workarounds) to a separate brw_pipe_control.c
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 147cdb53ecd225ea21d8d552607d384217346ecb
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Jun 23 23:17:53 2015 -0700
nir: Use a switch statement for detecting move-like operations.
Suggested by Jason Ekstrand.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit e31bce4041122cd00712b60b4dc1eae6486f6579
Author: Brian Paul <brianp at vmware.com>
Date: Wed Jun 24 10:41:52 2015 -0600
svga: silence warnings about unexpected shader type
Trivial.
commit c1de7df6d4086070e63369ab0af3950f53a03592
Author: Brian Paul <brianp at vmware.com>
Date: Mon Jun 22 14:04:09 2015 -0600
st/mesa: remove unneeded pipe_surface_release() in st_render_texture()
This caused us to always free the pipe_surface for the renderbuffer.
The subsequent call to st_update_renderbuffer_surface() would typically
just recreate it. Remove the call to pipe_surface_release() and let
st_update_renderbuffer_surface() take care of freeing the old surface
if it needs to be replaced (because of change to mipmap level, etc).
This can save quite a few calls to pipe_context::create_surface() and
surface_destroy().
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit a552c897caea31bbff3f16d2af8f5028a58bd344
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Jun 24 12:59:55 2015 +0100
st/wgl: add stw_nopfuncs.h to the sources lists
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 30d67d38246410274713380664be87cd1df9486a
Author: Julien Isorce <julien.isorce at gmail.com>
Date: Tue Jun 23 22:47:05 2015 +0100
loader: move loader_open_device out of HAVE_LIBUDEV block
Fixes the following build issue, when building without libudev.
CCLD libGL.la
./.libs/libglx.a(dri2_glx.o): In function `dri2CreateScreen':
src/glx/dri2_glx.c:1186: undefined reference to `loader_open_device'
collect2: ld returned 1 exit status
CCLD libEGL.la
Undefined symbols for architecture x86_64:
"_loader_open_device", referenced from:
_dri2_initialize_x11_dri2 in libegl_dri2.a(platform_x11.o)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91077
Signed-off-by: Julien Isorce <j.isorce at samsung.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 390f94e3581384838595185a06d5943089d3f9ab
Author: Grigori Goronzy <greg at chown.ath.cx>
Date: Wed Jun 24 03:40:38 2015 +0200
winsys/radeon: reduce BO cache timeout
1000 ms is an extreme value for typical interactive loads. A large
cache has some disadvantages. Search for reusable BOs can take a long
time and memory might get exhausted.
Let's be rather conservative and use half of the old value,
500ms. This is beneficial to some loads on my test system and there
are no regressions.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 29aaab2b5f55cc6d9a84f58ce2bb8607e76a9dde
Author: Grigori Goronzy <greg at chown.ath.cx>
Date: Wed Jun 24 03:38:02 2015 +0200
winsys/radeon: align BO size to page size
This is the basic granularity for BO allocations. The alignment also
helps with BO reuse by the cached bufmgr.
This results in a huge 45% speedup in Metro 2033 Redux on my test
system. The game relies on buffer orphaning with very small buffers
(hundreds of bytes in size) and that did not work efficiently
before. This change may also affect other applications and games.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 32a220f1f60980de50ecefb3b9ab1f754ade8c83
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Tue Jun 9 11:06:56 2015 +0300
glsl: remove cross validation of interpolation qualifier with GLSL 4.40
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
commit 23132cd13baa7b3e9688a118466261a282594b8e
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Jun 23 23:15:22 2015 -0700
i965: Fix whitespace error in gen8_depth_state.c
Trivial.
commit c8b8e8b29b755cd3d80fc5e470f441cb3716152a
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Jun 22 14:20:20 2015 -0700
i965: Don't count NIR instructions for shader-db.
Matt, Jason, and I haven't found this useful in a long time.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 7796e8889a9a2cc1b454dc32d8da3d756404339a
Author: Michel Dänzer <michel.daenzer at amd.com>
Date: Thu May 21 10:49:05 2015 +0900
winsys/radeon: Unmap GPU VM address range when destroying BO
But only when doing so is safe according to the
RADEON_INFO_VA_UNMAP_WORKING kernel query.
This avoids kernel GPU VM address range conflicts when the BO has other
references than the GEM handle being closed, e.g. when the BO is shared.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90537
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90873
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Christian König <christian.koenig at amd.com>
commit 3fd4c80b32e3080d761e176d129a1e46c618584a
Author: Eric Anholt <eric at anholt.net>
Date: Mon Jun 22 17:38:14 2015 -0700
vc4: Also dump VC4_PACKET_LOAD_TILE_BUFFER_GENERAL.
commit 5458ac01ae046010f3f7e4ddbf8ef18cca04d96c
Author: Eric Anholt <eric at anholt.net>
Date: Mon Jun 22 17:34:24 2015 -0700
vc4: Add dumping for VC4_PACKET_LOAD/STORE_FULL_RES_TILE_BUFFER.
commit 997f6778414a352457162b73ff5295e51e09ad63
Author: Eric Anholt <eric at anholt.net>
Date: Tue Jun 23 18:08:49 2015 -0700
vc4: Don't try to CSE color reads.
It returns a new value for each sample in the TLB. We've already avoided
trying to get the same index's color multiple times at the vc4_program.c
level, so we're not losing anything by doing this.
commit 0f69d59b1c8f5314c1abe18659b96adcfc51a0e5
Author: Eric Anholt <eric at anholt.net>
Date: Tue Jun 23 18:04:00 2015 -0700
vc4: Make a helper for TLB color writes, too.
We've done so for all the other QIR instruction generation in this file.
commit af83eb25812fbda89de62b58f9e59a5408ad4654
Author: Eric Anholt <eric at anholt.net>
Date: Tue Jun 23 17:53:07 2015 -0700
vc4: Pull the blending operation out to a separate function.
It's fairly separate from the rest of the TLB operations at frag end time,
and we'll need to run it multiple times to support MSAA blending.
commit 76851f49a5beac01b4eee7892ca95f44b5e18e29
Author: Eric Anholt <eric at anholt.net>
Date: Mon Jun 22 11:45:27 2015 -0700
vc4: Clarify size calculation for Z/S writes.
It's the same value for loads and stores, because they're basically the
same packet.
commit 8fbcabc41a4b2c7d7571585bde2e009e57982da4
Author: Eric Anholt <eric at anholt.net>
Date: Mon Jun 22 13:14:57 2015 -0700
vc4: Add an "args" temporary for RCL setup.
commit 19056d04296444afefe71ad8094d327ed38967bf
Author: Eric Anholt <eric at anholt.net>
Date: Mon Jun 22 17:31:24 2015 -0700
vc4: Reuse (and extend) the packet.h sizes for dumping.
commit fc0da629b502bb072b945932bae0477eb9b62bd5
Author: Eric Anholt <eric at anholt.net>
Date: Sat Jun 20 15:30:19 2015 -0700
vc4: Fix printfs for blit fallbacks.
commit e70f5617f1125e1f39a75d7a8c92ddda86a8056d
Author: Eric Anholt <eric at anholt.net>
Date: Tue Jun 23 11:02:12 2015 -0700
tgsi_to_nir: Fix translation of TXF on MSAA targets.
Noticed while trying to add GL_ARB_texture_multisample support to vc4.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 6844d6b7f8398a25eff511541b187afeb1199ce0
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Jun 23 15:39:42 2015 -0700
i965/fs: Get rid of an unused variable in emit_barrier()
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 40801295d5a3d747661abb1e2ca64d44c0e3dc05
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Jun 22 17:17:56 2015 -0700
i965: Remove the brw_context from the visitors
As of this commit, nothing actually needs the brw_context.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit bcaf4a3f077e3e3fbc66f264fe9124fa920ee70c
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Jun 22 17:30:23 2015 -0700
i965/vec4_vs: Add an explicit use_legacy_snorm_formula flag
This way we can stop doing is_gles3 checks inside of the compiler.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit 924b15d7de2a4ae9057cdf6d5d589c9b677d3325
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Jun 22 17:17:51 2015 -0700
i965/vec4: Turn some _mesa_problem calls into asserts
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit 663f8d121d792edee5c012461bfd0b650011ff4a
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Jun 19 17:29:42 2015 -0700
i965/vs: Pass the current set of clip planes through run() and run_vs()
Previously, these were pulled out of the GL context conditionally based on
whether we were running ff/ARB or a GLSL program. Now, we just pass them
in so that the visitor doesn't have to grab them itself.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit 4af62c0f5cbadc762abb1bd2e59f44ca220e3f0a
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Jun 19 17:25:28 2015 -0700
i965/fs: Add a do_rep_send flag to run_fs
Previously, we were pulling it from brw->do_rep_send
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit 1b0f6ffa15b25e8601d60fe1ea74e893f7d33cf5
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Jun 19 15:40:09 2015 -0700
i965: Pull calls to get_shader_time_index out of the visitor
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit c7893dc3c590b86787d8118e3920debaea3f16da
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Jun 19 14:46:03 2015 -0700
i965: Use a single index per shader for shader_time.
Previously, each shader took 3 shader time indices which were potentially
at arbirary points in the shader time buffer. Now, each shader gets a
single index which refers to 3 consecutive locations in the buffer. This
simplifies some of the logic at the cost of having a magic 3 a few places.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit 6e255a3299c9ec5208cb5519b5da2edb0ce2972b
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Apr 16 15:28:17 2015 -0700
i965: Add compiler options to brw_compiler
This creates the options at screen cration time and then we just copy them
into the context at context creation time. We also move is_scalar to the
brw_compiler structure.
We also end up manually setting some values that the core would have set by
default for us. Fortunately, there are only two non-zero shader compiler
option defaults that we aren't overriding anyway so this isn't a big deal.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit 073294d3ef20d0dbeffcc38aff3d69eda624ee75
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Jun 22 17:01:22 2015 -0700
i965/fs: Plumb compiler debug logging through brw_compiler
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit 3fd457c9ddd4b9f730e70bfd19b2f9eeeeaef089
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Jun 22 16:32:06 2015 -0700
i965/fs: Do the no16 perf logging directly in fs_visitor::no16()
While we're at it, we'll drop the note about 10-20% performance loss.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit f45bf97f30f2feacf8f976271a43feea70e5c382
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Jun 22 16:30:04 2015 -0700
i965/fs: Make no16 non-variadic
We never used the fact that it was variadic anyway.
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 1bc3b62d4aad22b94b8031c29c654a8f90ccc24d
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Apr 16 17:39:13 2015 -0700
i965: Move INTEL_DEBUG variable parsing to screen creation time
v2: Do bufmgr set_debug and set_aub_dump at screen time as well.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit d7565b7d65f8203c20735a61b86e9158b8ec4447
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Apr 16 14:34:04 2015 -0700
i965: Remove the dependance on brw_context from the generators
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit e639a6f68e701f23b977a49c45d646c164991d36
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Apr 16 14:13:52 2015 -0700
i965: Plumb compiler debug logging through a function pointer in brw_compiler
v2 (Ken): Make shader_debug_log a printf-like function.
v3 (Jason): Add a void * to pass the brw_context through
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit b0ad3ce4e7b9a23ab8fad4823e3c1094d6cf42a6
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Apr 18 12:23:33 2015 -0700
mesa: Add a va_args variant of _mesa_gl_debug().
This will be useful for wrapper functions.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit 630764407aeba4acf9364739bafb0e3516f72e31
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Jun 19 17:19:38 2015 -0700
i965: Replace some instances of brw->gen with devinfo->gen
commit ae097580ac49fbfaf184c89c68cb42b755f62939
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Jun 22 11:42:15 2015 -0700
i965: Initialize backend_shader::mem_ctx in its constructor.
We were initializing it in each subclasses' constructors for some
reason.
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit d8eeb4917ca39a0698731f64933c85a7c44e9247
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Jun 22 11:20:32 2015 -0700
i965: Assert that the GL primitive isn't out of range.
Coverity sees the if (mode >= BRW_PRIM_OFFSET (128)) test and assumes
that the else-branch might execute for mode to up 127, which out be out
of bounds.
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 4d93a07c45c8aa4cb3adbfcb9d61dcb54d8c404f
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Jun 22 11:09:49 2015 -0700
i965/cfg: Assert that cur_do/while/if pointers are non-NULL.
Coverity sees that the functions immediately below the new assertions
dereference these pointers, but is unaware that an ENDIF always follows
an IF, etc.
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 04758d25b4240129d4fa8784608a54c40bff3568
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Jun 19 20:40:15 2015 -0700
mesa: Delete unused ICEIL().
Can't find any uses of it in git history.
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit a49328d58d1e3e143f9434976d9f3574acefc4ea
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Jun 22 10:59:33 2015 -0700
i965/fs: Don't mess up stride for uniform integer multiplication.
If the stride is 0, the source is a uniform and we should not modify the
stride.
Cc: "10.6" <mesa-stable at lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91047
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 3fa9bb81ec8b21f472de32e08d0caf917239da08
Author: Boyan Ding <boyan.j.ding at gmail.com>
Date: Sat Jun 13 15:33:20 2015 +0800
egl/x11: Remove duplicate call to dri2_x11_add_configs_for_visuals
The call to dri2_x11_add_configs_for_visuals (previously
dri2_add_configs_for_visuals) was moved downwards in commit f8c5b8a1,
but appeared again in its original position after its rename in
d019cd81. Remove it.
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Boyan Ding <boyan.j.ding at gmail.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit 20dca37a20f90762df13efd0e0ec97002b6a89f2
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Wed Jun 17 15:50:13 2015 -0700
i965/gen9: Don't use encrypted MOCS
On gen9+ MOCS is an index into a table. It is 7 bits, and AFAICT, bit 0 is for
doing encrypted reads.
I don't recall how I decided to do this for BXT. I don't know this patch was
ever needed, since it seems nothing is broken today on SKL. Furthermore, this
patch may no longer be needed because of the ongoing changes with MOCS setup. It
is what is being used/tested, so it's included in the series.
The chosen values are the old values left shifted. That was also an arbitrary
choice.
v2: Use shift in MOCS to make it clear what we're doing. (Ken)
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 78d58e642549fbf340fdb4fca06720d2891216a8
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Jun 21 19:03:35 2015 -0400
nv50,nvc0: make sure to pushbuf_refn before putting bo into pushbuf_data
Without first running the bo through pushbuf_refn, the nouveau drm
library will have uninitialized structures regarding this bo, and will
insert incorrect data.
This fixes supertuxkart 0.9 crash on start (where it ends up doing a lot
of indirect draws).
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
commit 9fcbf515b431a92e0289f234ab77a796cf2a5612
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Jun 21 15:00:16 2015 -0400
nvc0: always put all tfb bufs into bufctx
Since we clear the TFB bufctx binding point above, we need to put all of
the active tfb's back in, even if they haven't changed since last time.
Otherwise the tfb may get moved into sysmem and the underlying mapping
will generate write errors.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
commit fccf012adc0d3aad877de095244324aa1d2d046a
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Tue Jun 23 00:16:59 2015 -0400
glsl: binding point is a texture unit, which is a combined space
This fixes compilation failures in Dota 2 Reborn where a texture unit
binding point was used that was numerically higher than the max
per stage.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
Tested-by: Nick Sarnie <commendsarnex at gmail.com>
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
commit 59f8d4ee793a1b620fb385f53b4dfe10e4b70f19
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Jun 19 19:35:19 2015 +0100
android: egl: do not link against libglapi
The only reason we touch glapi is to dlopen it in order to:
- make sure that the unresolved _glapi* symbols in the dri modules are
provided.
- fetch glFlush() and use it at various stages in the dri2 driver.
Cc: Chih-Wei Huang <cwhuang at linux.org.tw>
Cc: Eric Anholt <eric at anholt.net>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit a0dc6b7824d3b9095919e29393a379ea7f9c1318
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Jun 19 19:22:38 2015 +0100
gbm: do not (over)link against libglapi.so
The whole of GBM does not rely on even a single symbol from the GL
dispatch library, unsuprisingly. The only need for it comes from the
unresolved symbols in the DRI modules, which are now correctly handled
with Frank's commit.
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 828f13330c9384f2b55c8b0f962d93a74ecd0601
Author: Frank Henigman <fjhenigman at chromium.org>
Date: Thu Nov 6 16:29:26 2014 -0500
gbm: dlopen libglapi so gbm_create_device works
Dri driver libs are not linked to pull in libglapi so gbm_create_device()
fails when it tries to dlopen them (unless the application is linked
with something that does pull in libglapi, like libGL).
Until dri drivers can be fixed properly, dlopen libglapi before trying
to dlopen them.
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Frank Henigman <fjhenigman at google.com>
[Emil Velikov: Drop misleading bugzilla link, mention that libname differs]
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 6ed52f78a05a2b56eb521c50767b7a991df51564
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Jun 19 17:48:30 2015 +0100
configure: drop unused variable GBM_BACKEND_DIRS
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 994be5143a097ae2cf504ba344362edfee388ac3
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Jun 19 17:46:41 2015 +0100
configure: error out when building libEGL without shared-glapi
The latter is a hard requirement and without it we'll error out later
on in the build.
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit ddc886b5bfe5976fa2e5f49eeefa918736f1aa97
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Jun 19 17:44:02 2015 +0100
configure: error out when building backend-less libEGL
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 2752e629e71a8b4345b61f55b09d5ed04fc5e4b8
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Jun 19 17:37:18 2015 +0100
drivers/x11: drop unneeded HAVE_X11_DRIVER check
Already handled in the Makefile which includes the drivers/x11 subdir.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 92dc50786224411dc0aeff18b80a1995fcb04dc1
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Jun 19 19:43:23 2015 +0100
configure: allow building shared-glapi powered libgl-xlib
Cc: Brian Paul <brianp at vmware.com>
Cc: Adam Jackson <ajax at redhat.com>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
Acked-by: Jose Fonseca <jfonseca at vmware.com>
commit 5c37ababae6069ed73522bee35bca6228a80be77
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Jun 19 17:30:13 2015 +0100
targets/libgl-xlib: fix the build against shared_glapi
Cc: Brian Paul <brianp at vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
Acked-by: Jose Fonseca <jfonseca at vmware.com>
commit b92233f2a57ec09e9266ba4ed7f200904b784b9a
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Jun 19 17:28:25 2015 +0100
drivers/x11: fix the build against shared_glapi
Cc: Brian Paul <brianp at vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
Acked-by: Jose Fonseca <jfonseca at vmware.com>
commit 6d744aaf4e427b6b0b3d8d35d756592a50abbb97
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Jun 19 17:19:46 2015 +0100
configure: warn about shared_glapi & xlib-glx only when both are set
Printing out the message when shared_glapi is disabled only leads to
confusion.
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 06109db47b69867da0c7537f97b1aa8650598a08
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Jun 18 23:30:34 2015 +0100
glapi: remap_helper.py: remove unused argument 'es'
Identical to the previous commit - unused by neither the Autotools,
Android or SCons build.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Dylan Baker <baker.dylan.c at gmail.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit ec16bb62acfdfe6023d1ba6456ae8a19f14c5d80
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Jun 18 23:28:05 2015 +0100
glapi: gl_table.py: remove unused variable 'es'
None of the three build systems ever set it, as such we can clear things
up a bit.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Dylan Baker <baker.dylan.c at gmail.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 4f8f790525f1adcb5259cb72b7c9dbfd121867c6
Author: Derek Foreman <derekf at osg.samsung.com>
Date: Wed Jun 17 11:28:51 2015 -0500
egl: Use the loader_open_device() helper to do open with CLOEXEC
We've moved the open with CLOEXEC idiom into a helper function, so
call it instead of duplicating the code.
This also replaces a couple of opens that didn't properly do CLOEXEC.
Signed-off-by: Derek Foreman <derekf at osg.samsung.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 324ee9b391ea2db4b74709d30a131e79055bf071
Author: Derek Foreman <derekf at osg.samsung.com>
Date: Wed Jun 17 11:28:50 2015 -0500
glx: Use loader_open_device() helper
We've moved the open with CLOEXEC idiom into a helper function, so
call it instead of duplicating the code here.
Signed-off-by: Derek Foreman <derekf at osg.samsung.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 9c927463492dea14d82ebdd77f711f86b0e6fc5e
Author: Derek Foreman <derekf at osg.samsung.com>
Date: Wed Jun 17 11:28:49 2015 -0500
loader: Rename drm_open_device() to loader_open_device() and share it
This is already our common idiom for opening files with CLOEXEC and
it's a little ugly, so let's share this one implementation.
Signed-off-by: Derek Foreman <derekf at osg.samsung.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit aaac913e901229d11a1894f6aaf646de6b1a542c
Author: Derek Foreman <derekf at osg.samsung.com>
Date: Wed Jun 17 11:28:48 2015 -0500
egl/drm: Duplicate fd with F_DUPFD_CLOEXEC to prevent leak
Replacing dup() with fcntl F_DUPFD_CLOEXEC creates the duplicate
file descriptor with CLOEXEC so it won't be leaked to child
processes if the process fork()s later.
Signed-off-by: Derek Foreman <derekf at osg.samsung.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit be5f71d4a52c9ef72f63bb6c339fe0110f2027af
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Tue Jun 23 12:18:06 2015 +0100
draw,tgsi: Assume TGSI_PROPERTY_GS_INVOCATIONS default of 1.
If the shader doesn't specify number of invocations, assume one.
This fixes geometry shaders on state trackers other than Mesa (and
probably graw tests too.)
Trivial.
commit 634cfb9a458bcc1051b60ab13bd12e17bba0f71b
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Fri Jun 19 13:53:46 2015 +0100
glsl: Specify the shader stage in linker errors due to too many in/outputs.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 4731be701f3094666c24c143d9d6ddf53c456c39
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Jun 23 15:55:30 2015 +1000
docs: update GL3 with softpipe/llvmpipe gpu_shader5 pieces.
This just updates the bits I've added in the previous few patches.
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 1a71fbe28ca0525b618f6fb9d7354f3a6589af2f
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Jun 22 13:59:25 2015 +1000
draw/gallivm: add invocation ID support for llvmpipe.
This extends the draw code to add support for invocations.
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 40d225803ecfa805b4dea4ee0ebd04df00ca8827
Author: Dave Airlie <airlied at redhat.com>
Date: Wed May 20 10:32:32 2015 +1000
draw/tgsi: implement geom shader invocation support.
This is just for softpipe, llvmpipe won't work without
some changes.
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 24e77cb09fda9a57d4a8288ced3e01df4c8ac280
Author: Dave Airlie <airlied at gmail.com>
Date: Wed May 27 18:37:17 2015 +1000
tgsi: handle indirect sampler arrays. (v2)
This is required for ARB_gpu_shader5 support in softpipe.
v2: add support to txd/txf/txq paths.
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 1762568fd39b9be42d963d335e36daea25df7044
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Jun 10 00:52:07 2015 -0700
nir: Allow vec2/vec3/vec4 instructions in the select peephole pass.
These are basically just moves, so they should be safe as well.
When disabling i965's GLSL IR level scalarizer (channel expressions)
pass, I started seeing NIR code like this:
if ssa_21 {
block block_1:
/* preds: block_0 */
vec4 ssa_120 = vec4 ssa_82, ssa_83, ssa_84, ssa_30
/* succs: block_3 */
} else {
block block_2:
/* preds: block_0 */
/* succs: block_3 */
}
block block_3:
/* preds: block_1 block_2 */
vec4 ssa_33 = phi block_1: ssa_120, block_2: ssa_2
Previously, the GLSL IR scalarizer pass would break the vec4 into a
series of fmovs, which were allowed by the peephole pass. But with
the vec4 operation, they were not. We want to keep getting selects.
Normal i965 on Broadwell:
instructions in affected programs: 200 -> 176 (-12.00%)
helped: 4
With brw_fs_channel_expressions() disabled:
instructions in affected programs: 1832 -> 1646 (-10.15%)
helped: 30
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 94e3864707e48d4b1d5fb5f88a01370a73ddb0cb
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri May 15 09:58:42 2015 -0700
i965: Add and fix comments in brw_vue_map.c.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 38eb9015e3be9b93248e64b6befce16872107a7c
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri May 15 09:54:23 2015 -0700
i965: Split VUE map handling out of brw_vs.c into brw_vue_map.c.
This was originally only used by the vertex shader, but it's now used by
the geometry shader as well, and will also eventually be used for
tessellation control and evaluation shaders.
I suspect it will be easier to find in a file named after the concept.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 90754d2df05eafe1a3ee3cd9bb1611a19099fc49
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Wed Jun 3 21:35:51 2015 -0700
i965/gen9: Implement Push Constant Buffer workaround
This implements a workaround (exact excerpt as a comment in the code). The docs
specify [clearly, after you struggle for a while] that the offset isn't relative
to state base. This actually makes sense. This fixes hangs on SKL.
Buffer #0 is meant to be used for normal uniforms.
Buffer #1 is typically used for gather constants when using RS.
Buffer #1-#3 could be used to push a bunch of UBO data which would just be
somewhere in memory, and not relative to the dynamic state.
NOTE: I've moved away from the ternary operator for the new gen9 conditions.
Admittedly it's probably not great to do this, but I really want to fix this all
up in the subsequent patch and doing it here makes that diff a lot nicer. I want
to split out the gen8/9 code to make the function a bit more readable, but to
keep this easily cherry-pickable I am doing this fix first. If we decide not to
merge the cleanup patch then I can revisit this.
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Tested-by: Valtteri Rantala <Valtteri.rantala at intel.com>
commit 2b07b8d104a93c26ac92edb3ba72328cdc2dcb52
Author: Brian Paul <brianp at vmware.com>
Date: Mon Jun 22 08:29:49 2015 -0600
mesa: use _mesa_lookup_enum_by_nr() in print_array()
Print GL_FLOAT, etc. instead of hex value.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 878714142999ca6a6aa03d962e01da94d44c8574
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Jun 22 14:27:19 2015 +0800
ilo: emit 3DPRIMITIVE from gen6_3dprimitive_info
It allows us to remove ilo_ib_state::draw_start_offset and
ILO_PRIM_RECTANGLES. gen6_3d_translate_pipe_prim() is also replaced by
ilo_translate_draw_mode().
commit 58f95b332d0cbad226f5bb2e96cd0cad8864fe79
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Jun 22 14:15:52 2015 +0800
ilo: align vertex buffer size in buf_create()
With ilo_format.[ch] moved out of core, the aligning of vertex buffers does
not belong to core anymore.
commit 513bc5d90b8e9237bd6a04da5d0dee175ff134f6
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Jun 22 14:06:13 2015 +0800
ilo: move ilo_format.[ch] out of core
They provide PIPE_FORMAT_x to GEN6_FORMAT_x translation as well as some
convenient helpers. Move them out of core.
commit 3547bb078307995e92d509037bc86af7fd60c8c3
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Jun 22 13:37:05 2015 +0800
ilo: add ilo_state_surface_valid_format()
Check if a surface format can be used for the specified access type.
commit aa3e5e0dded4d732ea46083201940bd23214785c
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Jun 22 13:15:24 2015 +0800
ilo: add ilo_state_vf_valid_element_format()
Check if a surface format can be used as a VE format.
commit da8300cb03e8cf1f37b5573a2db026fd28e0a3c5
Author: Alexandre Courbot <acourbot at nvidia.com>
Date: Fri Oct 17 15:05:32 2014 +0900
nvc0: use NV_VRAM_DOMAIN() macro
Use the newly-introduced NV_VRAM_DOMAIN() macro to support alternative
VRAM domains for chips that do not have dedicated video memory.
Signed-off-by: Alexandre Courbot <acourbot at nvidia.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Martin Peres <martin.peres at free.fr>
commit f22406837ff5dc881d8496d05ab001204b14eaf5
Author: Alexandre Courbot <acourbot at nvidia.com>
Date: Fri Oct 17 14:58:11 2014 +0900
nouveau: support for custom VRAM domains
Some GPUs (e.g. GK20A, GM20B) do not embed VRAM of their own and use
the system memory as a backend instead. For such systems, allocating
objects in VRAM results in errors since the kernel will not allow
VRAM objects allocations.
This patch adds a vram_domain member to struct nouveau_screen that can
optionally be initialized to an alternative domain to use for VRAM
allocations. If left untouched, NOUVEAU_BO_VRAM will be used for
systems that embed VRAM, and NOUVEAU_BO_GART will be used for VRAM-less
systems.
Code that uses GPU objects is then expected to use the NV_VRAM_DOMAIN()
macro in place of NOUVEAU_BO_VRAM to ensure correct behavior on
VRAM-less chips.
Signed-off-by: Alexandre Courbot <acourbot at nvidia.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Martin Peres <martin.peres at free.fr>
commit 57bdcae9e0fbf639014cd375543a8dd356406ac0
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Sat Jun 20 23:27:08 2015 +0800
ilo: add ilo_state_compute
Replace gen6_idrt_data with ilo_state_compute, which has a bunch of
validations and is now preferred.
commit 2bf5a4211ef305d90ca6133ca09c3b79e6088d50
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Jun 22 13:36:41 2015 +1000
r600g: ignore sampler views for now.
This fixes a regression in that r600 stopped working when
sampler views were pushed.
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 66a93a0ff9aa402c37aa9d00b4489715d611b496
Author: Rob Clark <robclark at freedesktop.org>
Date: Sat Jun 13 09:14:31 2015 -0400
freedreno/ir3: pass sz to split_dest()
For query_levels, we generate a getinfo with writemask of (z), which RA
will consider as size==3. But we were still generating four fanouts.
Which meant that RA would see it as two different register classes,
depending on the path to definer. Ie. on the getinfo instruction itself
it would see size==3, but when chasing back through the fanouts it would
see size==4.
Easiest way to solve that is to just generate the chain of neighboring
fanouts to have the correct size in the first place.
Note: we may eventually want split_dest() to take start/end or wrmask
instead, since really we only need size==1. But RA is not clever enough
for that, query_levels is not that common, and the other two registers
that get allocated are never used so those register slots can be
immediately re-used. So bunch of work for probably no real gain.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 1ee4d51e7a68f8f2dcb52a0e2f9af81fdbe078a2
Author: Rob Clark <robclark at freedesktop.org>
Date: Fri Jun 12 14:27:44 2015 -0400
freedreno/ir3/nir: add more opcodes
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 43048c7093c367897fbcbb3ca8580e9c122cd6f6
Author: Rob Clark <robclark at freedesktop.org>
Date: Mon Jun 8 14:45:47 2015 -0400
freedreno/ir3: only unminify txf coords on a3xx
Seems like a4xx gets this right.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 0f008082b184072159e5aedc7fc103efba8740ed
Author: Rob Clark <robclark at freedesktop.org>
Date: Mon Jun 8 14:23:49 2015 -0400
freedreno: remove int sampler shader variants
We get this information from NIR (which gets it from sview decl in tgsi
when translating from tgsi), so no need to maintain shader variants for
this.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 457f7c2a2a93b45396ac66e0d4b3896d2db8fdf3
Author: Rob Clark <robdclark at gmail.com>
Date: Tue Jun 9 17:17:06 2015 -0400
freedreno/ir3: block reshuffling and loops!
This shuffles things around to allow the shader to have multiple basic
blocks. We drop the entire CFG structure from nir and just preserve the
blocks. At scheduling we know whether to schedule conditional branches
or unconditional jumps at the end of the block based on the # of block
successors. (Dropping jumps to the following instruction, etc.)
One slight complication is that variables (load_var/store_var, ie.
arrays) are not in SSA form, so we have to figure out where to put the
phi's ourself. For this, we use the predecessor set information from
nir_block. (We could perhaps use NIR's dominance frontier information
to help with this?)
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 660d5c1646f5d63f9626b24beabc9cfc318849d4
Author: Rob Clark <robclark at freedesktop.org>
Date: Mon Jun 1 12:35:19 2015 -0400
freedreno/ir3: a4xx encodes larger immed offset
Without this, negative branch/jump offsets look like very large positive
offsets.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit d646d3ae9d221104db0e9daec33ef470b1bdd957
Author: Rob Clark <robclark at freedesktop.org>
Date: Mon May 25 10:59:21 2015 -0400
freedreno/ir3: simplify find_neighbors stop condition
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit c8fb5f8a011e1db78af3ceaf91c5cb3b1acaee14
Author: Rob Clark <robclark at freedesktop.org>
Date: Mon May 25 10:30:54 2015 -0400
freedreno/ir3: move inputs/outputs to shader
These belong in the shader, rather than the block. Mostly a lot of
churn and nothing too interesting. But splitting this out from the
rest of ir3_block reshuffling to cut down the noise in the later
patch.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit d52fb2f5ad828f879286b9068023b82b9897bc17
Author: Rob Clark <robclark at freedesktop.org>
Date: Fri May 1 12:21:12 2015 -0400
freedreno/ir3/ra: use register_allocate
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 694beb8b830c993e9bfb744655be3dbd558ab3a8
Author: Rob Clark <robclark at freedesktop.org>
Date: Sat May 23 13:37:41 2015 -0400
freedreno/ir3: introduce ir3_compiler object
Right now, just provides a cleaner way to get at the gpu-id, given the
separation between compiler and context. But we will need this also to
hold the reg-set for new register allocation.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 5c1e153467a50dec91df49239654017e9ed86d69
Author: Rob Clark <robclark at freedesktop.org>
Date: Sat Apr 25 16:30:55 2015 -0400
freedreno/ir3: dump nocp option
No longer used, or even possible, with NIR frontend.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 7674ab12e826d2ea33f13fb2e6ca8ae2a62fe460
Author: Rob Clark <robdclark at gmail.com>
Date: Tue Jun 9 17:42:16 2015 -0400
freedreno/ir3: silence warnings
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 0f6faa8ff317634ffb75e6040f2de2019dd80d13
Author: Rob Clark <robclark at freedesktop.org>
Date: Sat Apr 25 10:22:49 2015 -0400
freedreno/ir3: remove tgsi f/e
Also remove ir3_flatten which was only used by tgsi f/e.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 7273cb4e933f8be65fc73b9d8c69c76d1078cb14
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Apr 30 13:57:15 2015 -0400
freedreno/ir3/sched: convert to priority queue
Use a more standard priority-queue based scheduling algo. It is simpler
and will make things easier once we have multiple basic blocks and flow
control.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit adf1659ff5f07d907eca552be3b566e408c8601e
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Apr 30 11:38:43 2015 -0400
freedreno/ir3: use standard list implementation
Use standard list_head double-linked list and related iterators,
helpers, etc, rather than weird combo of instruction array and next
pointers depending on stage. Now block has an instrs_list. In
certain stages where we want to remove and re-add to the blocks list
we just use list_replace() to copy the list to a new list_head.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 67d994c6761e09205dbc9a0515c510fc9dde02c7
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Apr 30 10:10:14 2015 -0400
freedreno/ir3: drop dot graph dumping
At least for now.. right now the instruction and instruction list
printing should suffice, and the re-working of ir3_block would require
a lot of changes in that code.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 5c8c2e2f97394436effbdd3e0f61eec4590accb2
Author: Rob Clark <robclark at freedesktop.org>
Date: Sat Apr 25 11:05:27 2015 -0400
freedreno/ir3: more builder helpers
Use ir3_MOV() builder in a couple of spots, rather than open-coding the
instruction construction. Also add ir3_NOP() builder and use that
instead of open coding.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit b33015f8895a37fcae1da2984796cb1ef30f8b13
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Apr 30 15:20:03 2015 -0400
gallium/ttn: add missing SNE
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit c79b2e626c60a29f684bc389f07a712b59fa99cc
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Apr 29 08:38:45 2015 -0400
util/list: add list_first/last_entry
I need an easier way to get at head/tail in ir3.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit b3d2e367167b675c0b402c90220f40f8cd567d7c
Author: Rob Clark <robclark at freedesktop.org>
Date: Mon Jun 8 14:09:09 2015 -0400
gallium/ttn: add texture-type support
v2: rebased on using SVIEW to hold type information
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit cb258c1dec1ff348d508a6b02fbc9aa11eb9f829
Author: Rob Clark <robclark at freedesktop.org>
Date: Mon Jun 8 13:20:30 2015 -0400
glsl_to_tgsi: add SVIEW decl support
Freedreno needs sampler type information to deal with int/uint textures.
To accomplish this, start creating sampler-view declarations, as
suggested here:
http://lists.freedesktop.org/archives/mesa-dev/2014-November/071583.html
create a sampler-view with index matching the sampler, to encode the
texture type (ie. SINT/UINT/FLOAT). Ie:
DCL SVIEW[n], 2D, UINT
DCL SAMP[n]
TEX OUT[1], IN[1], SAMP[n]
For tgsi texture instructions which do not take an explicit SVIEW
argument, the SVIEW index is implied by the SAMP index.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 93379748f7e4f5ab22040cdb7a4cccdcfb7954c1
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Jun 10 20:02:55 2015 -0400
util/blitter (and friends): generate appropriate SVIEW decls
Some hardware needs to know the sampler type. Update the blit related
shaders to include SVIEW decl.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit e53699298640df7d7659a8ce88b68e43918b600c
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Jun 10 20:01:11 2015 -0400
util/pstipple: updates for SVIEW decls
To allow for shaders which use SVIEW decls for TEX* instructions, we
need to preserve the constraint that the shader either has no SVIEW's or
it has one matching SVIEW for each SAMP.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit b516e68afb548894eff6b1f375c01f6dfafb6aed
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Jun 10 19:59:20 2015 -0400
draw: updates to support SVIEW decls
To allow for shaders which use SVIEW decls for TEX* instructions, we
need to preserve the constraint that the shader either has no SVIEW's or
it has one matching SVIEW for each SAMP.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit f481af110e6ab42b2d184f225bfe7eb1e66df393
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Jun 10 19:51:32 2015 -0400
tgsi/transform: add support for SVIEW decls
TODO single return_type (use enum)
v2: single return_type arg, and use enum
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit b13135e06671468d296a33abf4150060f2b2a061
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Jun 10 19:49:55 2015 -0400
tgsi: update docs for SVIEW usage with TEX* instructions
Based on mailing list discussion here:
http://lists.freedesktop.org/archives/mesa-dev/2014-November/071583.html
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 717376155d2082d7bf94122a1e1d383b39e0b070
Author: Eric Anholt <eric at anholt.net>
Date: Sat Jun 20 15:02:50 2015 -0700
mesa: Back out an accidental change I had in a VC4 commit.
This was a hack as part of debugging some glamor-on-GLES2 behavior that
ended up being an xserver bug. I suspect we can just flip this extension
on for GLES2, but the spec says it requires 3.1.
commit 104bff037665075aa2b92964ad2895f45d9a5866
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Jun 20 16:40:56 2015 +0100
docs: add news item and link release notes for mesa 10.5.8
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit aa28423bcc7cd6b5f2c5f9c8f1a385a79469a439
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Jun 20 16:37:16 2015 +0100
docs: Add sha256sums for the 10.5.8 release
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit a81b1d5512f64ffca1c13a5937e7eb0de24713ae)
commit 97caf2054f6ebd3106ed22ef73622483ef193bf7
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Jun 20 15:14:45 2015 +0100
Add release notes for the 10.5.8 release
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit 24b043aab73ce066ded6e4bc93f589008dfc8484)
commit c00903867417f1522047b7c50ea9248e1aa2f50c
Author: Eric Anholt <eric at anholt.net>
Date: Fri Jun 19 19:47:44 2015 -0700
vc4: Use a defined t value for 1D textures.
This doesn't fix the broken 1D cases of texsubimage, but it does prevent
segfaulting when dumping the QIR code generated in fbo-1d.
commit bb107110a4d97191841985076dd9f2fbd0937dfc
Author: Eric Anholt <eric at anholt.net>
Date: Fri Jun 19 19:41:25 2015 -0700
vc4: Fix write-only texsubimage when we had to align.
We need to make sure that when we store the aligned box, we've got
initialized contents in the border. We could potentially just load the
border area, but for now let's get text rendering working in X (and fix
the GL_TEXTURE_2D errors in piglit's texsubimage test and
gl-2.1-pbo/test_tex_image)
commit 028590cbc758e877b963ba430f0a0cb49e882a6b
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Thu Jun 18 22:48:14 2015 +0800
ilo: clean up header includes
Core is more self-contained now.
commit 244caba2502402b93876cb89952ac05e6d87c5b2
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Sat Jun 20 00:34:29 2015 +0800
ilo: avoid ilo_ib_state in genX_3DPRIMITIVE()
ilo_ib_state is not in core.
commit dcb5bad3a3a8ff116c32ecb01827ea8461fa2baa
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Thu Jun 18 22:47:20 2015 +0800
ilo: move gen6_so_SURFACE_STATE() out of core
It does not belong to core.
commit e3372c4bfb8d5960714651ca7d3f1acc0018a8fa
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Jun 15 15:17:45 2015 +0800
ilo: add ilo_state_sol_buffer
It serves the same purpose as ilo_state_vertex_buffer does.
commit 9904e647cca0a15c80557ed7bcc6893faf147436
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Jun 19 15:10:02 2015 +0800
ilo: add ilo_state_index_buffer
It serves the same purpose as ilo_state_vertex_buffer does.
commit da4878cb807f46e6053731a177c3c75497aaf4fb
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Jun 19 15:06:50 2015 +0800
ilo: add ilo_state_vertex_buffer
Being a parameter-like state, we may want to get rid of
ilo_state_vertex_buffer_info or ilo_state_vertex_buffer eventually. But we
want them now as they are how we do cross-validation right now.
commit 4555211028394673f8ad68f3de9c12e9a1f93160
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Thu Jun 18 14:26:29 2015 +0800
ilo: add 3DSTATE_VF_INSTANCING to ilo_state_vf
3DSTATE_VF_INSTANCING specifies instancing enable and step rate. They are
specified along with 3DSTATE_VERTEX_BUFFERS instead prior to Gen8. Both
commands are added.
commit e8d297b7a108fcf1cb688fe1db89e83b8f85e091
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Tue Jun 16 23:11:06 2015 +0800
ilo: add 3DSTATE_VF to ilo_state_vf
3DSTATE_VF specifies cut index enable and cut index. Cut index enable is
specified in 3DSTATE_INDEX_BUFFER instead prior to Gen7.5. Both commands are
added.
commit 7b3432b62d25494b3662d12634e34d75e29ec865
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Thu Jun 18 13:55:32 2015 +0800
ilo: embed pipe_index_buffer in ilo_ib_state
Make it obvious that we save a copy of pipe_index_buffer.
commit 73f0d6d22db21f1fa553d8a26687edc5083e3c23
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Jun 19 23:29:32 2015 +0800
ilo: fix a buffer overrun
Add missing parentheses in SURFTYPE_NULL initialization.
commit aa3ec8bc465f8c82cb38e0ed067dbdd9122dbd44
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Jun 19 23:24:17 2015 +0800
ilo: fix a -Wmaybe-uninitialized warning
ilo_shader.c: In function ‘ilo_shader_select_kernel_sbe’:
ilo_shader.c:1140:27: warning: ‘src_skip’ may be used uninitialized in this
function [-Wmaybe-uninitialized]
commit a1f84453a2f104a92f9efd353c629177e00e4b5e
Author: Brian Paul <brianp at vmware.com>
Date: Fri Jun 19 16:45:44 2015 -0600
glsl: fix formatting glitch in _mesa_print_ir()
Print the closing ) before the newline. Trivial.
commit 7c3da3592e8799059abca9cd7c92d61ebfd09f29
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Thu Jun 18 18:45:47 2015 -0700
i965/gen8: Use HALIGN_16 for single sample mcs buffers
The original code meant to do this, but was only checking num_samples == 1 to
figure out if a surface was fast clear capable. However, we can allocate single
sample miptrees with num_samples == 0 (when it's an internally created buffer).
This fixes a bunch of the piglit tests on gen8. Other gens should have been
fine.
Here is the order of events that allowed this to slip through:
t0: I wrote halign patches and tested them. These alignment assertions are for
gen8 fast clear surfaces, basically.
t1: I pushed bogus perf patch which made fast clears never happen
t2: Reworked halign patches based on Chad's feedback and introduced the bug this
patch fixes.
t2.5: I tested reworked patches, but assertion wasn't hit because of t1.
t3. Matt fixed issue in t1 which made fast clears happen here:
commit 22af95af8316f2888a3935cdf774ff0997b3dd42
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu Jun 18 16:14:50 2015 -0700
i965: Add missing braces around if-statement.
This logic should match that of the v1 of my halign patch series.
Cc: Kenneth Graunke <kenneth at whitecape.org>
Cc: Matt Turner <mattst88 at gmail.com>
Reported-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Tested-by: Mark Janes <mark.a.janes at intel.com>
commit 539cb2b76efd02f14798cad0a5462ee9ed27aa83
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Jun 19 12:08:24 2015 -0400
mesa: move ARB_gs5 enums to core, EXT_polygon_offset_clamp to desktop
When adding EXT_polygon_offset_clamp, I first made it core-only, and
never moved the enum getter back to the GL/GL_CORE section. Similarly,
ARB_gs5 is a core-only extension, so move its getters to the GL_CORE
section.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 6ec4e9c28d54877fbaca04b080c249048c6e7634
Author: Brian Paul <brianp at vmware.com>
Date: Thu Jun 18 18:03:29 2015 -0600
u_vbuf: fix src_offset alignment in u_vbuf_create_vertex_elements()
If the driver says PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY=1,
the driver should never receive a pipe_vertex_element::src_offset value
that's not a multiple of four. But the vbuf code wasn't actually adjusting
the src_offset value when creating the vertex element state object.
We just need to align the src_offset values put in the driver_attribs[]
array.
See the piglit gl-1.5-vertex-buffer-offsets test.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit c40f44cc991d9499243063cba95fbdc947c53371
Author: Brian Paul <brianp at vmware.com>
Date: Thu Jun 18 17:53:42 2015 -0600
gallium: whitespace, formatting clean-up in p_state.h
Remove trailing whitespace, move some braces, 78-column wrapping.
Trivial.
commit 4c11008eba9f58621bbbae430f8717176045b0ce
Author: Brian Paul <brianp at vmware.com>
Date: Tue Jun 16 15:32:46 2015 -0600
st/wgl: fix WGL_SWAP_METHOD_ARB query
There are three possible return values (not two): WGL_SWAP_COPY_ARB,
WGL_SWAP_EXCHANGE_EXT and WGL_SWAP_UNDEFINED_ARB.
VMware bug 1431184
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
commit 73bdf4ba86751983dff011ac488ac60321d70a7f
Author: Brian Paul <brianp at vmware.com>
Date: Tue Jun 16 15:32:46 2015 -0600
stw: use new stw_get_nop_function() function to avoid Viewperf 12 crashes
Also, print a warning if we do return NULL from wglGetProcAddress() to
help spot this sort of problem in the future.
Reviewed-by: José Fonseca <jfonseca at vmware.com>
commit 8d005a643ed94c1871ec854bc069366cdda6581f
Author: Brian Paul <brianp at vmware.com>
Date: Tue Jun 16 15:32:46 2015 -0600
stw: add some no-op functions for GL_EXT_dsa, GL_NV_half_float
Viewperf 12 calls wglGetProcAddress() to get pointers to some unsupported
DSA and half-float functions. We return NULL but Viewperf doesn't check
for null before trying to jump through the pointer. That causes a crash.
This patch adds no-op functions to call instead (used by the next patch).
This avoids the crash but the rendering is incorrect.
Some DSA functions are being added to Mesa at this time so we may be
able to remove some of these no-ops in the future.
More no-op functions may be added as needed.
VMware PR1383421
Reviewed-by: José Fonseca <jfonseca at vmware.com>
commit eee9247018d710659f14678715a85e4ad6f54366
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Tue Jun 16 15:32:46 2015 -0600
st/wgl: Don't return core profile for 3.1 contexts.
WGL_CONTEXT_PROFILE_MASK_ARB doesn't apply to desktop OpenGL versions
less than 3.2 -- applications can't specify whether they want a core or
a compat 3.1 context -- instead they are supposed the check whether the
returned context advertises GL_ARB_compatibility extension.
Mesa doesn't support compatability contexts for version higher than 3.1,
so we used to return core profile context, but this makes several Windows
applications unhappy, because they just assume they got a compatability
context without checking.
So it seems safer to on Windows to never return core profile for 3.1,
ie, just fail the context creation.
VMware PR1365920.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 528bd94432b20becc1f436da75f7a102416dabeb
Author: Brian Paul <brianp at vmware.com>
Date: Tue Jun 16 15:32:46 2015 -0600
st/wgl: set PIPE_BIND_SAMPLER_VIEW for window color buffers
To allow sampling from the surface for things like glCopyPixels
or glCopyTexSubImage.
Reviewed-by: Charmaine Lee <charmainel at vmware.com>
commit 9405c1b3b0b207409931166a608276198a068cb8
Author: Brian Paul <brianp at vmware.com>
Date: Tue Jun 16 15:32:45 2015 -0600
st/wgl: add support for multisample pixel formats
Create pixel formats with 0, 4, 8 and 16 samples per pixel.
Add a SVGA_FORCE_MSAA env var to force creating all pixel formats
with a particular sample count. This is useful for testing Mesa/GLUT/
etc. programs which don't ordinarily use multisample.
Reviewed-by: Matthew McClure <mcclurem at vmware.com>
commit 0925e5f5bc843237e534313dd5b99095ecbdd987
Author: Brian Paul <brianp at vmware.com>
Date: Tue Jun 16 15:32:45 2015 -0600
st/wgl: respect sample count when creating framebuffer surfaces
Use the visual/pixel format's sample count instead of zero.
Reviewed-by: Matthew McClure <mcclurem at vmware.com>
commit b8249de646e75f8af0c84d7f06b7805fe555e13e
Author: Brian Paul <brianp at vmware.com>
Date: Tue Jun 16 15:32:45 2015 -0600
st/wgl: fix WGL_SAMPLE_BUFFERS_ARB query
Only report 1 for WGL_SAMPLE_BUFFERS_ARB if the number of samples
per pixel > 1.
Reviewed-by: Matthew McClure <mcclurem at vmware.com>
commit 5ad5d44af57a815c6eb16d4d61070135acb55f37
Author: Brian Paul <brianp at vmware.com>
Date: Sat Jun 13 08:07:08 2015 -0600
tgsi: add comments for ureg_emit_label()
commit 12c1c0706d4356819cfbaa15c3d71402a42e3539
Author: Brian Paul <brianp at vmware.com>
Date: Sat Jun 13 07:58:53 2015 -0600
tgsi: new comments, assertion for executing TGSI_OPCODE_CAL
commit 2ce2b80c6fd7ba5effbdf86ca3affe10a9c70492
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Fri Jun 19 13:03:36 2015 +1000
docs: update developer info
Update piglit link to the current Piglit website.
Add note about updating patchwork when sending patch revisions.
Acked-by: Matt Turner <mattst88 at gmail.com>
commit afeb92220690c8f27cdc56c30e109ca175d51d83
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Thu Jun 18 15:47:00 2015 +0100
llvmpipe: Truncate the binned constants to max const buffer size.
Tested with Ilia Mirkin's gzdoom.trace and
"arb_uniform_buffer_object-maxuniformblocksize fsexceed" piglit test
without my earlier fix to fail linkage when UBO exceeds
GL_MAX_UNIFORM_BLOCK_SIZE.
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit f734d2556013e9239e91f43b563b5b1d8f03ada4
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Mon Jun 15 18:29:02 2015 +0100
glsl: Fail linkage when UBO exceeds GL_MAX_UNIFORM_BLOCK_SIZE.
It's not totally clear whether other Mesa drivers can safely cope with
over-sized UBOs, but at least for llvmpipe receiving a UBO larger than
its limit causes problems, as it won't fit into its internal display
lists.
This fixes piglit "arb_uniform_buffer_object-maxuniformblocksize
fsexceed" without regressions for llvmpipe.
NVIDIA driver also fails to link the shader from
"arb_uniform_buffer_object-maxuniformblocksize fsexceed".
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=65525
PS: I don't recommend cherry-picking this for Mesa stable, as some app
might inadvertently been relying on UBOs larger than
GL_MAX_UNIFORM_BLOCK_SIZE to work on other drivers, so even if this
commit is universally accepted it's probably best to let it mature in
master for a while.
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit 5974841fd0be7e2c336f63bd9ef416723e1923dc
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Jun 18 19:08:24 2015 -0400
glsl: guard gl_NumSamples enablement on ARB_sample_shading
gl_NumSamples should only be enabled when ARB_sample_shading is enabled.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 22af95af8316f2888a3935cdf774ff0997b3dd42
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu Jun 18 16:14:50 2015 -0700
i965: Add missing braces around if-statement.
Fixes a performance problem caused by commit b639ed2f.
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90895
commit 2310a65c28f809442c24fc8893c65ce7c7a4dca3
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Tue Jun 16 14:27:15 2015 -0700
i965/compute: Fix undefined code with right_mask for SIMD32
Although we don't support SIMD32, krh pointed out that the left shift
by 32 is undefined by C/C++ for 32-bit integers.
Suggested-by: Kristian Høgsberg <krh at bitplanet.net>
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 770f141866654dab969302f720228497f0fb35fd
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Jun 17 23:00:44 2015 -0400
mesa: add GL_PROGRAM_PIPELINE support in KHR_debug calls
This was apparently missed when ARB_sso support was added.
Add label support to pipeline objects just like all the other
debug-related objects.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
commit b6e238023c4f8af2328dc3bcab1d73a3e19f4fbb
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Jun 17 15:09:26 2015 -0400
glsl: add version checks to conditionals for builtin variable enablement
A number of builtin variables have checks based on the extension being
enabled, but were missing enablement via a higher GLSL version.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
commit c40e7ee7c47cb24264fd77ef37fab99dea4c299a
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Jun 17 15:07:14 2015 -0400
glsl: handle conversions to double when comparing param matches
This allows mod(int, int) to become selected as float mod when doubles
are supported.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
Cc: "10.6" <mesa-stable at lists.freedesktop.org>
commit 6b0378e483ba53359545ac8b774dbdd81c2fab3f
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Jun 18 12:59:28 2015 +0100
ilo: remove missing ilo_fence.h from the sources list
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 997fc807b2f71ef65b4601d6db33d0f912c18d3f
Author: Boyan Ding <boyan.j.ding at gmail.com>
Date: Tue Jun 16 11:08:33 2015 +0800
egl/x11: Set version of swrastLoader to 2
which it actually implements instead of the newest version defined in
dri_interface.h
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Boyan Ding <boyan.j.ding at gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 1d45e44b2f9e52d6eebe84ab08da6b7393011f95
Author: Eric Anholt <eric at anholt.net>
Date: Wed Jun 17 13:24:06 2015 -0700
vc4: Move tile state/alloc allocation into the kernel.
This avoids a security issue where userspace could have written the tile
state/tile alloc behind the GPU's back, and will apparently be necessary
for fixing stability bugs (tile state buffers are missing some top bits
for the tile alloc's address).
commit 9adcd2d80aceec90b9c3712b53d8e7839dc5634b
Author: Eric Anholt <eric at anholt.net>
Date: Wed Jun 10 12:36:47 2015 -0700
vc4: Move RCL generation into the kernel.
There weren't that many variations of RCL generation, and this lets us
skip all the in-kernel validation for what we generated.
commit 91c73a9a280b749a781cd3f071fc377fcb9758e1
Author: Eric Anholt <eric at anholt.net>
Date: Wed Jun 17 13:51:55 2015 -0700
vc4: Add dumping of VC4_PACKET_TILE_BINNING_MODE_CONFIG.
commit dc1fbad2eb5454ed36a066d2a69b575cd5a8abaf
Author: Eric Anholt <eric at anholt.net>
Date: Wed Jun 17 23:49:19 2015 -0700
vc4: Fix memory leak from simple_list conversion.
I accidentally shadowed the outside declaration, so we always returned
NULL even when we'd found something in the cache.
commit 62d153ea37b1bf572c39aab8ec46099fc903362d
Author: Eric Anholt <eric at anholt.net>
Date: Wed Jun 17 22:56:15 2015 -0700
vc4: Track the number of BOs allocated and their size.
This is useful for BO leak debugging.
commit 2b1cdb0eddb73f62e4848d4b64840067f1f70865
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Tue Feb 24 19:02:50 2015 +0100
i965: Fix textureGrad with cube samplers
We can't use sampler messages with gradient information (like
sample_g or sample_d) to deal with this scenario because according
to the PRM:
"The r coordinate and its gradients are required only for surface
types that use the third coordinate. Usage of this message type on
cube surfaces assumes that the u, v, and gradients have already been
transformed onto the appropriate face, but still in [-1,+1] range.
The r coordinate contains the faceid, and the r gradients are ignored
by hardware."
Instead, we should lower this to compute the LOD manually based on the
gradients and use a different sample message that takes the computed
LOD instead of the gradients. This is already being done in
brw_lower_texture_gradients.cpp, but it is restricted to shadow
samplers only, although there is a comment stating that we should
probably do this also for samplerCube and samplerCubeArray.
Because of this, both dEQP and Piglit test cases for textureGrad with
cube maps currently fail.
This patch does two things:
1) Activates the texturegrad lowering pass for all cube samplers.
2) Corrects the computation of the LOD value for cube samplers.
I had to do 2) because for cube maps the calculations implemented
in the lowering pass always compute a value of rho that is twice
the value we want (so we get a LOD value one unit larger than we
want). This only happens for cube map samplers (all kinds). I am
not sure about why we need to do this, but I suspect that it is
related to the fact that cube map coordinates, when transported
to a specific face in the cube, are in the range [-1, 1] instead of
[0, 1] so we probably need to divide the derivatives by 2 when
we compute the LOD. Doing that would produce the same result as
dividing the final rho computation by 2 (or removing a unit
from the computed LOD, which is what we are doing here).
Fixes the following piglit tests:
bin/tex-miplevel-selection textureGrad Cube -auto -fbo
bin/tex-miplevel-selection textureGrad CubeArray -auto -fbo
bin/tex-miplevel-selection textureGrad CubeShadow -auto -fbo
Fixes 10 dEQP tests in the following category:
dEQP-GLES3.functional.shaders.texture_functions.texturegrad.*cube*
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit 36e3eb6a957f8f20ed187ec88a067fc65cb81432
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Jun 17 22:18:09 2015 -0400
nvc0/ir: can't have a join on a load with an indirect source
Triggers an INVALID_OPCODE warning on GK208. Seems rare enough to not
warrant verification on other chips. Fixes the new piglits:
ubo_array_indexing/fs-nonuniform-control-flow.shader_test
ubo_array_indexing/vs-nonuniform-control-flow.shader_test
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
commit ff06901082b84c91ee64d3a54bf372f0c809f4bf
Author: Kevin Rogovin <kevin.rogovin at intel.com>
Date: Wed Jun 17 13:29:59 2015 +0300
docs: mark GL_ARB_framebuffer_no_attachments done for i965
Mark GL_ARB_framebuffer_no_attachments as done for i965.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogovin at intel.com>
commit 83199998310591b9162ab12e922ed79ee235b5c8
Author: Kevin Rogovin <kevin.rogovin at intel.com>
Date: Wed Jun 17 13:29:58 2015 +0300
i965: enable ARB_framebuffer_no_attachments for Gen7+
Enable GL_ARB_framebuffer_no_attachments in i965 for Gen7 and higher.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogovin at intel.com>
commit 9ded6369754910f7f58f896c1627ba0bbfb0f864
Author: Kevin Rogovin <kevin.rogovin at intel.com>
Date: Wed Jun 17 13:29:57 2015 +0300
i965: execution of frag-shader when it has atomic buffer
Ensure that the GPU spawns the fragment shader thread for those
fragment shaders with atomic buffer access.
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogovin at intel.com>
commit bbb700967e9991a03ed6e8073c9bdc2ca0d1381d
Author: Kevin Rogovin <kevin.rogovin at intel.com>
Date: Wed Jun 17 13:29:56 2015 +0300
mesa: function for testing if current frag-shader has atomics
Add helper function that checks if current fragment shader active
of gl_context has atomic buffer access.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogovin at intel.com>
commit 41b6db225f42a5d81beec1b4455ec7b504e2416d
Author: Kevin Rogovin <kevin.rogovin at intel.com>
Date: Wed Jun 17 13:29:55 2015 +0300
i965: Use _mesa_geometric_ functions appropriately
Change references to gl_framebuffer::Width, Height, MaxNumLayers
and Visual::samples to use the _mesa_geometry_ convenience functions
for those places where the geometry of the gl_framebuffer is needed
(in contrast to the geometry of the intersection of the attachments
of the gl_framebuffer).
This patch is to pave the way to enable GL_ARB_framebuffer_no_attachments
on Gen7 and higher in i965.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogovin at intel.com>
commit 51f4b51151cb08988b5de466f3c2348876784cc5
Author: Kevin Rogovin <kevin.rogovin at intel.com>
Date: Wed Jun 17 13:29:54 2015 +0300
mesa: helper function for scissor box of gl_framebuffer
Add helper convenience function that intersects the scissor values
against a passed bounding box. In addition, to avoid replicated code,
make the function _mesa_scissor_bounding_box() use this new function.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogovin at intel.com>
commit 74987977a36a7111281e8fb53568dc05dbd3a8b4
Author: Kevin Rogovin <kevin.rogovin at intel.com>
Date: Wed Jun 17 13:29:53 2015 +0300
mesa: add helper functions for geometry of gl_framebuffer
Add convenience helper functions for fetching geometry of gl_framebuffer
that return the geometry of the gl_framebuffer instead of the geometry of
the buffers of the gl_framebuffer when then the gl_framebuffer has no
attachments.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogovin at intel.com>
commit 6aa12994bdf0068a9804204a8f1b197cc0f46ec6
Author: Kevin Rogovin <kevin.rogovin at intel.com>
Date: Wed Jun 17 13:29:52 2015 +0300
PATCH 03/10] mesa: Complete ARB_framebuffer_no_attachments in Mesa core
Implement GL_ARB_framebuffer_no_attachments in Mesa core
- changes to conditions for framebuffer completenss
- implement set/get functions for framebuffers for
new functions in GL_ARB_framebuffer_no_attachments
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogovin at intel.com>
commit c9d26f201aca58c72629d1ba1bb13c32c158d9dd
Author: Kevin Rogovin <kevin.rogovin at intel.com>
Date: Wed Jun 17 13:29:51 2015 +0300
mesa: Constants and functions for ARB_framebuffer_no_attachments
Define the enumeration constants, function entry points and
glGet for the GL_ARB_framebuffer_no_attachments.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogovin at intel.com>
commit da81999bee7b1f1bc0bb296e903deb03617ae22c
Author: Kevin Rogovin <kevin.rogovin at intel.com>
Date: Wed Jun 17 13:29:50 2015 +0300
mesa: Define infrastructure for ARB_framebuffer_no_attachments
Define the infrastructure for the extension GL_ARB_framebuffer_no_attachments:
- extension table
- additions to gl_framebuffer
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogovin at intel.com>
commit a0cd1a4060fdb55a57609b460629c7059bbe7047
Author: Eric Anholt <eric at anholt.net>
Date: Mon Jun 15 15:05:36 2015 -0700
vc4: Make sure that direct texture clamps have a minimum value of 0.
I was thinking of the MIN opcode in terms of unsigned math, but it's
signed, so if you used a negative array index, you could read before the
UBO. Fixes segfaults under simulation in piglit array indexing tests with
mprotect-based guard pages.
commit d4d27361499cac73da4716b571519ecb71cef551
Author: Eric Anholt <eric at anholt.net>
Date: Mon Jun 15 17:47:12 2015 -0700
vc4: Swap around which src we spill to ra31/rb31.
I wanted to assert that src1 came from a non-unspilled register in shader
validation, and this easily gets us that. And, as a bonus:
total instructions in shared programs: 93347 -> 92723 (-0.67%)
instructions in affected programs: 60524 -> 59900 (-1.03%)
commit 507f3e708cbd10a4272aeffa0f066f1a80b48239
Author: Eric Anholt <eric at anholt.net>
Date: Tue Jun 16 12:03:10 2015 -0700
vc4: R4 is not a valid register for clamped direct texturing.
Our array only goes to R3, and R4 is a special case that shouldn't be
used.
commit 2eac356467cef898ed05d0699077d9a9f4fa9156
Author: Eric Anholt <eric at anholt.net>
Date: Mon Jun 15 14:54:26 2015 -0700
vc4: Factor out the live clamp register getter.
commit 596532cc7d477671f87116e0788b4214ae1d0559
Author: Eric Anholt <eric at anholt.net>
Date: Mon Jun 15 11:41:06 2015 -0700
vc4: Drop the unused "stride" field of surfaces.
We're always looking at the slice anyway, when we would have needed it.
commit 6dd55b49090da22d3a8e9226507a95e914eaf10f
Author: Eric Anholt <eric at anholt.net>
Date: Fri Jun 12 12:47:47 2015 -0700
vc4: Handle refcounting the exec BO like we do in the kernel.
This reduces the diff to the kernel, and will be useful when I make the
kernel allocate more BOs as part of validation.
commit 731ac05cc4e444175288032a76a29c95059af038
Author: Eric Anholt <eric at anholt.net>
Date: Thu Jun 11 16:08:11 2015 -0700
vc4: Use VC4_SET/GET_FIELD for some RCL packets.
commit e22a1927844cdda499ea15f539028c16e47394ea
Author: Eric Anholt <eric at anholt.net>
Date: Wed Jun 10 13:20:25 2015 -0700
vc4: Make symbolic values for packet sizes.
commit c2f82876014c9acb0518cf31a6f675fcc73c955a
Author: Eric Anholt <eric at anholt.net>
Date: Wed Jun 10 12:58:47 2015 -0700
vc4: Use symbolic values in texture ptype validation.
commit 5fbbec9aae8185b96aa4cf6d778901dea44fefa4
Author: Eric Anholt <eric at anholt.net>
Date: Wed Jun 10 12:47:56 2015 -0700
vc4: Move vc4_packet.h to the kernel/ directory, since it's also shared.
I want to notice discrepancies when I diff -u between Mesa and the kernel.
commit e20345204d8fe8864240be2428ac0f225b92b7cc
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Tue Apr 14 22:06:50 2015 -0700
i965/gen9: Disable Mip Tail for YF/YS tiled surfaces
Disabling miptails fixed the buffer corruption happening in FBO
which use YF/YS tiled renderbuffer or texture as color attachment.
Spec recommends disabling mip tails only for non-mip-mapped surfaces.
But, without disabling miptails I couldn't get correct data out of
mipmapped YF/YS tiled surface.
We need better understanding of miptails before start using them.
For now this patch helps move things forward.
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit 54591bb67f189820ef0d61b040179abbd5ecf78a
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Tue Apr 14 22:06:48 2015 -0700
i965/gen9: Set vertical and horizontal surface alignments
Patch sets the alignments for texture and renderbuffer surfaces.
V3: Make changes inside horizontal_alignment() and
vertical_alignment() (Topi)
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 6c380d42b161da977d164ccf75ccc25a2e056bb1
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Tue Apr 14 22:06:48 2015 -0700
i965: Use BRW_SURFACE_* in place of GL_TEXTURE_*
Makes no functional changes in the code.
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit af0853033296a4db3c48352e8cb60f8209424f79
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Tue Apr 14 22:06:48 2015 -0700
i965: Rename use_linear_1d_layout() and make it global
This function will be utilised in later patches.
V2: Make both pointers constants (Topi)
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 06687564479be1a2eed5842cfe4ad85dd099261b
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Tue Apr 14 22:06:48 2015 -0700
i965/gen9: Set tiled resource mode in surface state
This patch sets the tiled resource mode for texture and renderbuffer
surfaces.
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 6b8accb36b541f77774109ea42533c02bb90bc68
Author: Haixia Shi <hshi at chromium.org>
Date: Fri Jun 12 10:10:58 2015 -0700
egl/dri2: implement platform_surfaceless
The surfaceless platform is for off-screen rendering only. Render node support
is required.
Only consider the render nodes. Do not use normal nodes as they require
auth hooks.
v3: change platform_null to platform_surfaceless
v4: make libdrm required for surfaceless
v5: remove modified include guards with defined(HAVE_SURFACELESS_PLATFORM)
v6: use O_CLOEXEC for drm fd
Signed-off-by: Haixia Shi <hshi at chromium.org>
Signed-off-by: Zach Reizner <zachr at google.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit c753866cc4ae15313430f9b6edba1b82e44b003a
Author: Neil Roberts <neil at linux.intel.com>
Date: Thu May 28 19:35:44 2015 +0100
i965/vec4: Fix the source register for indexed samplers
Previously when setting up the sample instruction for an indirect
sampler the vec4 backend was directly passing the pseudo opcode's
src0. However vec4_visitor::visit(ir_texture *) doesn't set the
texture operation's src0 -- it's left as BAD_FILE, which when
translated into a brw_reg gives the null register. In brw_SAMPLE,
gen6_resolve_implied_move() inserts a MOV from the inst->base_mrf and
sets the src0 appropriately. The indirect sampler case did not have a
call to gen6_resolve_implied_move().
The fs backend avoids this because the platforms that support dynamic
indexing of samplers (IVB+) have been converted to not use the
fake-MRF hack, and instead send from proper GRFs.
This patch makes it call gen6_resolve_implied_move before setting up
the indirect message. This is similar to what is done for constant
sampler numbers in brw_SAMPLE.
The Piglit tests for sampler array indexing didn't pick this up
because they were using a texture with a solid colour so it didn't
matter what texture coordinates were actually used. The tests have now
been changed to be more thorough in this commit:
http://cgit.freedesktop.org/piglit/commit/?id=4f9caf084eda7
With that patch the tests for gs and vs are currently failing on
Ivybridge, but this patch fixes them. There are no other changes to a
Piglit run on Ivybridge.
On Skylake the gs tests were failing even without the Piglit patch
because Skylake needs the source registers to work correctly in order
to send a message header to select SIMD4x2 mode.
(The explanation in the commit message is partially written by Matt
Turner)
Tested-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit aab55b0bc6086a032f44c99ad6569ea2eac128ca
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Apr 7 01:10:17 2015 +0200
st/mesa: improve assertions in vp/fp translation
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 42a3c1ec8471fc76eb6d3d6f1bd1739e24a5f33a
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Jun 14 16:37:02 2015 +0200
mesa: don't rebind constant buffers after every state change if GS is active
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 358b6bb7a71663ab5e1c62f2b7767c20acebc2fa
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Sun Sep 21 12:07:55 2014 +1200
mesa: generalize sso stage interleaving check
For tessellation.
v2: cleanup by Marek Olšák
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 8af11afc38532c65a242f7d45c31cf098ce2fa2f
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jun 13 13:02:20 2015 +0200
mesa: remove unused variables from gl_program
Reviewed-by: Brian Paul <brianp at vmware.com>
commit fa49536ab10748f6ab05e930d4b01fe714ea6b59
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Sun Sep 7 19:24:15 2014 +1200
glsl: add ir reader support for ir_barrier
Picked from the tessellation branch.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 2f86c22e75a3273a7541f88ffedd2edefaf6f482
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Mar 19 23:28:25 2015 +0100
glsl: print locations of variables
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 797f4eacea8a6b08b7c9143a74c7f2b422d1535d
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jun 6 13:24:11 2015 +0200
configure.ac: rename LLVM_VERSION_PATCH to avoid conflict with llvm-config.h
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
commit da6996485f2ca636218e3d83b53cf6a450bb9b38
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Mon Jun 15 21:00:47 2015 +1000
Revert "glsl: remove restriction on unsized arrays in GLSL ES 3.10"
This reverts commit adee54f8269c5e9f4fde91d19f0e465afc8f14d8.
Further down in the GLSL ES 3.10 spec it say:
"If an array is declared as the last member of a shader storage block
and the size is not specified at compile-time, it is sized at run-time.
In all other cases, arrays are sized only at compile-time."
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit 7d88ab42b9dda825feddbae774a2a48ddf3cbec2
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Tue Jun 16 13:46:47 2015 +0300
mesa: set override_version per api version override
Before 9b5e92f get_gl_override was called only once, but now it is
called for multiple APIs (GLES2, GL), version needs to be set always.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90797
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
Tested-by: Martin Peres <martin.peres at linux.intel.com>
commit 1a6220b416f02e56575894efbbd1717c9427c763
Author: Neil Roberts <neil at linux.intel.com>
Date: Thu Jun 11 16:59:07 2015 +0100
i965: Fix aligning to the block size in intel_miptree_copy_slice
This function was trying to align the width and height to a multiple
of the block size for compressed textures. It was using align_w/h as a
shortcut to get the block size as up until Gen9 this always happens to
match. However in Gen9+ the alignment values are expressed as
multiples of the block size so in effect the alignment values are
always 4 for compressed textures as that is the minimum value we can
pick. This happened to work for most compressed formats because the
block size is also 4, but for FXT1 this was breaking because it has a
block width of 8.
This fixes some Piglit tests testing FXT1 such as
spec at 3dfx_texture_compression_fxt1@fbo-generatemipmap-formats
Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>
commit 8b24388647f626a5cad10fd48e61335ed26a8560
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Jun 15 15:48:58 2015 -0400
nv50,nvc0: clamp uniform size to 64k
The state tracker will pass through requests from buggy applications
which will have the buffer size larger than the max allowed (64k). Clamp
the size to 64k so that we don't get errors when uploading the constbuf
data.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
commit a2af42c1d2dc91f4c31e25ff9fff15a89a9b6ead
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Jun 12 16:09:05 2015 +0200
nvc0/ir: fix collection of first uses for texture barrier insertion
One of the places we have to insert texbars is in situations where the
result of the tex gets overwritten by a different instruction (e.g. in a
conditional statement). However in some situations it can actually
appear as though the original tex itself is an overwriting instruction.
This can naturally never really happen, so just ignore the tex
instruction when it comes up.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90347
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
commit 932d1613d1e15ec22555e5ec09105c49eb850e36
Author: Eric Anholt <eric at anholt.net>
Date: Tue Jun 9 12:16:19 2015 -0700
egl: Drop check for driver != NULL.
Back in 2013, a patch was added (with 2 reviewers!) at the end of the
block to early exit the loop in this case, without noticing that the loop
already did. I added another early exit case, again without noticing, but
Rob caught me. Just drop the loop condition that apparently surprises
most of us, instead of leaving the end of the loop conspicuously not
exiting on success.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Rob Clark <robdclark at gmail.com>
commit bcd8a64f32f6387cbd8ed8d0bda0f49bd7dd4251
Author: Eric Anholt <eric at anholt.net>
Date: Tue Jun 9 11:45:05 2015 -0700
gallium: Drop the gallium-specific Android sw winsys.
This was part of gallium_egl, and we now have the normal libEGL Android
winsys support to handle it.
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 6ce0b0e31754d88a542d4e3c90062e3f6a67f7b9
Author: Eric Anholt <eric at anholt.net>
Date: Wed Jun 3 10:15:31 2015 -0700
vc4: Add support for building on Android.
v2: Add a comment explaining why we link libmesa_glsl. Drop warning
option from freedreno. Add vc4 to the documentation for
BOARD_GPU_DRIVERS.
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit fd3234891f7203d6b2b0992c34e880df325f75ea
Author: Eric Anholt <eric at anholt.net>
Date: Sun Jun 7 11:57:46 2015 -0700
gallium: Enable build of NIR support on Android.
v2: Add a comment explaining why we link libmesa_glsl.
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 71aaf62fca3ed8b18fc2dcd69be0fd6bb7e58a91
Author: Eric Anholt <eric at anholt.net>
Date: Sun Jun 7 16:47:25 2015 -0700
egl/dri2: Fix Android Lollipop build on ARM.
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 8e9eec5cbf73bf977bc7e808a4e653737ee94c38
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Fri May 15 06:01:15 2015 -0700
meta: Abort texture upload if pixels == null and no pixel unpack buffer set
in case of glTexImage{1,2,3}D(). Texture has already been allocated
at this point and we have no data to upload. With out this patch,
with create_pbo = true, we end up creating a temporary pbo and then
uploading uninitialzed texture data.
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Neil Roberts <neil at linux.intel.com>
commit a4ff47ade9d95a27c9c55afbf6dd77d3f3b10562
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Tue May 12 04:17:04 2015 -0700
meta: Abort meta path if ReadPixels need rgb to luminance conversion
After recent addition of pbo testing in piglit test getteximage-luminance,
it fails on i965. This patch makes a sub test pass.
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Cc: <mesa-stable at lists.freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit ba2b1f8668811eade97a4f134f6df900ff36c8aa
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Fri May 1 00:05:18 2015 -0700
mesa: Turn need_rgb_to_luminance_conversion() in to a global function
This will be used by _mesa_meta_pbo_GetTexSubImage() in a later patch.
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Cc: <mesa-stable at lists.freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 0b13adcd0802d1ad60f625e7e557d2090a7c143e
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Thu Apr 30 23:36:18 2015 -0700
mesa: Use helper function need_rgb_to_luminance_conversion()
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Cc: <mesa-stable at lists.freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 82abdf209a2fb5b95b2bae80045aecc61202b13c
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Thu Apr 30 23:35:20 2015 -0700
mesa: Handle integer formats in need_rgb_to_luminance_conversion()
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Cc: <mesa-stable at lists.freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 6c14b66e40d34104c841ee6dfaeb65617e47be80
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Mon Jun 1 09:32:55 2015 -0700
meta: Use is_power_of_two() helper function
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 278460279b4e089d51a24fb01dc56dc1e88dcb72
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Mon May 4 23:10:28 2015 -0700
i965: Check for miptree pitch alignment before using intel_miptree_map_movntdqa()
We have an assert() in intel_miptree_map_movntdqa() which expects
the pitch to be 16 byte aligned.
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 84d27c32d238ca7a7b115bf190e7e527b7f70e92
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Thu May 28 14:48:51 2015 -0700
i965: Remove break after return
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 2e42deb29c878fb4c52aed6d2d54833aacba18ae
Author: Jürgen Rühle <j-r at online.de>
Date: Sat Jun 6 18:37:20 2015 +0200
nv50/ir: OP_JOIN is a flow instruction
OP_JOIN instructions are assumed to be flow instructions and mercilessly
casted to FlowInstruction.
This patch fixes an instance where an OP_JOIN is created as a plain
instruction. This can cause crashes in the ir printer.
[imirkin: add ->fixed = 1]
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 061c9bc2042b0686867e4321d94ba18761a6a1a7
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sun Jun 14 16:43:21 2015 +0100
docs: add news item and link release notes for mesa 10.6.0
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit f9e04413284ce29214527b4d6369c8462000cb3d
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sun Jun 14 16:40:00 2015 +0100
docs: Add sha256sums for the 10.6.0 release
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit 5d327b373531861f86a726db669b3d656f1b5f8d)
commit 311abe7fbd590505fd86e22a3030e00445218cb0
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sun Jun 14 16:26:40 2015 +0100
docs: Update 10.6.0 release notes
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit 3b9cde5c8138fb5cc45c652f2a5c15c5fa222bd7)
commit 94ab56367169ba2902e83aded409db2df3d25eb1
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Jun 15 11:24:47 2015 +0800
ilo: add ilo_state_raster_{line,poly}_stipple
Initialize hardware stipple states on bound instead of on emission.
commit 7cb853d52ae795b76adec41c98870166b41c9e6f
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Jun 15 12:01:29 2015 +0800
ilo: add ilo_state_sample_pattern
Move sample pattern initialization from ilo_render to
ilo_state_sample_pattern.
commit 8f37e8e64fc897180603a7247e2fd47bf0ffb834
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Jun 15 11:57:10 2015 +0800
ilo: add 3DSTATE_AA_LINE_PARAMETERS to ilo_state_raster
Utilize ilo_state_raster to avoid redundant state change.
commit b0a2280e45e5abc56e5301f84f33226469000d6c
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun May 10 20:35:15 2015 +0200
gallium/util: add util_last_bit64
This will be needed by radeonsi.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 2489054f663baa69e659e0878cb39f4e7197ee0b
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jun 6 14:12:34 2015 +0200
glsl: fix "tesselation" typo
Trivial.
commit 790510808e614ee6c5f55ba773734838041902cb
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Jun 5 19:09:21 2015 +0200
r600g: handle TGSI input/output array declarations correctly
Most of this code could be removed if r600g used tgsi_shader_info.
commit 117926debb72e5027faae885f9aa7f1ca61f6a9c
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Thu Jun 11 07:36:28 2015 +0800
ilo: merge ilo_state_3d*.[ch] to ilo_state.[ch]
With most code replaced to ilo_state_*, what was left did not belong there
anymore.
commit 54e0a8ed5dcaaa0ef483d5960ae86f88e0bf8990
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Jun 12 15:08:02 2015 +0800
ilo: add ilo_state_ps to ilo_shader_cso
commit 30fcb31c9b095451ce5ac5a10c3c6b177dc03e20
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Jun 12 14:47:02 2015 +0800
ilo: add ilo_state_{vs,hs,ds,gs} to ilo_shader_cso
commit da6e45fcbc4570df0ec4b8c8885f33a206da3552
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Tue Jun 2 23:09:53 2015 +0800
ilo: embed ilo_state_sbe in ilo_shader
commit 5a52627c4f9215649b0f244af96512b9aafceaa1
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Tue Jun 2 14:57:48 2015 +0800
ilo: embed ilo_state_vf in ilo_ve_state
commit 9bfa987fb00a4e0471bcdb4948c8f416d7c5b562
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Thu May 28 13:43:56 2015 +0800
ilo: embed ilo_state_urb in ilo_state_vector
commit eaf2c738991d43ec8e7b36bed05727deaf8151b6
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri May 29 15:25:13 2015 +0800
ilo: embed ilo_state_sol in ilo_shader
commit 960ca7d5e32997a5367cf798f7930cbb890b3ab4
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon May 11 19:48:52 2015 +0800
ilo: embed ilo_state_cc in ilo_blend_state
commit 402e155cd3a757a583f81fa6545c855b63947e7c
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Jun 5 10:23:24 2015 +0800
ilo: embed ilo_state_raster in ilo_rasterizer_state
commit ded7d412d04cf702596e91f36ba586b18f1933a2
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon May 18 00:00:37 2015 +0800
ilo: embed ilo_state_viewport in ilo_viewport_state
commit 4b5c0a83415137ba1f894d70a6cf73db83d21f15
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Thu May 21 17:18:37 2015 +0800
ilo: replace ilo_sampler_cso with ilo_state_sampler
commit 745ef2c07b23e1cf227eb26871fc464198b956e8
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Wed May 20 21:44:30 2015 +0800
ilo: replace ilo_view_surface with ilo_state_surface
commit c10c1ac0cfb0ae42742f369d9f3fa2f4fba8639a
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon May 18 23:32:10 2015 +0800
ilo: replace ilo_zs_surface with ilo_state_zs
commit 6dad848d1acfe781c735120c3db97f1a2f0c28fa
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Jun 12 14:56:56 2015 +0800
ilo: add ilo_state_ps
We want to make ilo_shader_cso a union of ilo_state_{vs,hs,ds,gs,ps}.
commit df9f846ac6153e171fbcf661bad19168b336a703
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Sat May 30 00:58:51 2015 +0800
ilo: add ilo_state_{vs,hs,ds,gs}
We want to make ilo_shader_cso a union of ilo_state_{vs,hs,ds,gs} and ps
payload.
commit a0bb1c2d1787cf2bd14620bf81d6d59cebfa766a
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Jun 12 14:02:37 2015 +0800
ilo: add ilo_state_sbe
We want to replace ilo_kernel_routing with ilo_state_sbe.
commit 1ccab943b66de70b49cdbf3f14071fec9fe833cc
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Sun May 31 00:00:49 2015 +0800
ilo: add ilo_state_vf
We want to replace ilo_ve_state with ilo_state_vf.
commit 9c77ebef2499a79fc9a0816971a6d16d50cf2954
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Thu May 28 13:21:02 2015 +0800
ilo: add ilo_state_urb
commit 3ff40be0eecfd6bbcc17471590e44042b3ffa5d3
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri May 29 13:08:18 2015 +0800
ilo: add ilo_state_sol
commit 62bb6437187b439d5959ccab094762163713a992
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon May 11 14:23:49 2015 +0800
ilo: add ilo_state_cc
We want to replace ilo_dsa_state and ilo_blend_state with ilo_state_cc.
commit 6be8b6053de356a679707a0de92b083a4ea83937
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Sun May 10 13:52:21 2015 +0800
ilo: add ilo_state_raster
We want to replace ilo_rasterizer_state with ilo_state_raster.
commit 4fa7ed99a1e9334d96c1efd42344774dae19f466
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Tue May 12 23:43:50 2015 +0800
ilo: add ilo_state_viewport
We want to replace ilo_viewport_cso and ilo_scissor_state with
ilo_state_viewport.
commit 61fea171af64288bdf622e7ecf07e3ca42f83974
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Wed May 13 13:10:54 2015 +0800
ilo: add ilo_state_sampler
We want to replace ilo_sampler_cso with ilo_state_sampler.
commit f5f2007322b5468aa3025e7e259b4c50c7a7a0bd
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Thu May 14 09:46:42 2015 +0800
ilo: add ilo_state_surface
We want to replace ilo_view_surface with ilo_state_surface.
commit b91250a56b0af51b82bf4152a4f98e74fab22ed4
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Sat May 16 08:27:24 2015 +0800
ilo: add ilo_state_zs
We want to replace ilo_zs_surface with ilo_state_zs. One noteworthy
difference is that ilo_state_zs always aligns level 0 to 8x4 when HiZ is
enabled. HiZ will not be enabled for 1D surfaces as a result.
commit 9af1fc590d90fdda65aa0cf145773480af52a4e5
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Sat May 9 21:39:34 2015 +0800
ilo: update genhw headers
Generate these new enums
enum gen_reorder_mode;
enum gen_clip_mode;
enum gen_front_winding;
enum gen_fill_mode;
enum gen_cull_mode;
enum gen_pixel_location;
enum gen_sample_count;
enum gen_inputattr_select;
enum gen_msrast_mode;
enum gen_prefilter_op;
Correct the type of GEN6_SAMPLER_DW0_BASE_LOD. Rename gen_logicop_function,
gen_sampler_mip_filter, gen_sampler_map_filter, gen_sampler_aniso_ratio, and
others.
commit 9cb0df4b50593e69f65b65704f5b64f3a12be9b5
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri May 22 14:21:22 2015 +0800
ilo: add ilo_image_disable_aux()
When aux bo allocation fails, ilo_image_disable_aux() should be called to
disable aux buffer.
commit f0de65cbc29b45fffbe4bf4e1ce299ddb8be9eda
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Tue May 26 15:46:44 2015 +0800
ilo: add array_size and level_count to ilo_image
We will use them for bound checking.
commit f9d2bbe967fb1fbbe7102c0765f067b3155f5ca6
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Sun May 17 11:55:05 2015 +0800
ilo: add pipe_texture_target to ilo_image
Save the target in ilo_image instead of passing it around.
commit 9da9cf729ff74684902cbb4b53b5cccd442df28e
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri May 15 10:39:05 2015 +0800
ilo: fix "Render Cache Read Write Mode"
It needs be set to R/W only when using certain messages via DP render cache.
Since we only use RT wrties with the render cache, we never need to set it.
commit 1885ac490834e70d831b5b4a287c272b4148761c
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Thu May 21 16:30:03 2015 +0800
ilo: avoid resource owning in core
It is up to the users whether to reference count the BOs or not.
commit ab7229b9b6b160e805d14d600a432e76a5e88ef8
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri May 22 13:49:20 2015 +0800
ilo: assert core objects are zero-initialized
Core objects are usually embedded inside calloc()'ed objects and we expect
them to be zero-initialized.
commit 4d35eef326e49cc8da50879d30a1c5088d4775e1
Author: Tom Stellard <thomas.stellard at amd.com>
Date: Thu Jun 11 15:42:25 2015 +0000
radeon/llvm: Handle LLVM backend rename from R600 to AMDGPU
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 3e7412233739c882548f50fe01d9f6c5f0dd4bbb
Author: Tom Stellard <thomas.stellard at amd.com>
Date: Wed May 27 16:51:43 2015 -0700
gallivm: Only build lp_profile() body when PROFILE is defined
The only use of lp_profile() is wrapped in #if defined(PROFILE),
so there is no reason to build it unless this macro is defined.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit faf7670ee86253cb7bf9422bf7937a0a63f4956f
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Wed Jun 10 18:35:08 2015 +1000
glsl: fix compile error message
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 935f1f60da71df07aa45a3da92fa764a1830e0fb
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Thu May 14 09:28:37 2015 -0700
i965/gen8+: Add aux buffer alignment assertions
This helped find the incorrect HALIGN values from the previous patches.
v2: Add PRM references for assertions (Chad)
v3: Remove duplicated part of commit message, assert num_samples > 1, instead of
num_samples > 0. (Chad)
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Chad Versace <chad.versace at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit a2421623db9b900d2ab0026539e8f7f6294475ea
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Fri May 22 15:57:37 2015 -0700
i965/gen9: Set HALIGN_16 for all aux buffers
Just like the previous patch, but for the GEN9 constraints.
v2:
bugfix: Gen9 HALIGN was being set for all miptree buffers (Chad). To address
this, move the check to where the gen8 check is, and do the appropriate
conditional there.
v3:
Remove stray whitespace introduced in v2 (Chad)
Rework comment to show AUX_CCS and AUX_MCS specifically. Remove misworded part
about gen7 (Chad).
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com> (v1)
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com> (v1)
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit c4aa041a611dfeb0a880c2173cb35c9c08dc79ca
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Thu May 14 09:30:02 2015 -0700
i965/gen8: Correct HALIGN for AUX surfaces
This restriction was attempted in this commit:
commit 47053464630888f819ef8cc44278f1a1220159b9
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Fri Feb 13 11:21:21 2015 -0800
i965/gen8: Use HALIGN_16 if MCS is enabled for non-MSRT
However, the commit itself doesn't achieve the desired goal as determined by the
asserts which the next patch adds. mcs_mt is NULL (never set) we're in the
process of allocating the mcs_mt miptree when we get to this function. I didn't
check, but perhaps this would work with blorp, however, meta clears allocate the
miptree structure (which AFAICT needs the alignment also) way before it
allocates using meta clears where the renderbuffer is allocated way before the
aux buffer.
The restriction is referenced in a few places, but the most concise one [IMO]
from the spec is for Gen9. Gen8 loosens the restriction in that it only requires
this for non-msrt surface.
When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E, HALIGN 16 must
be used.
With the code before the miptree layout flag rework (patches preceding this),
accomplishing this workaround is very difficult.
v2:
bugfix: Don't set HALIGN16 for gens before 8 (Chad)
v3:
non-trivial rebase
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Cc: Neil Roberts <neil at linux.intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit e92fbdcf9cf69e6b135c17c2851d50e256da8c29
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Thu May 21 22:47:37 2015 -0700
i965: Extract tiling from fast clear decision
There are several constraints when determining if one can fast clear a surface.
Some of these are alignment, pixel density, tiling formats, and others that vary
by generation. The helper function which exists today does a suitable job,
however it conflates "BO properties" with "Miptree properties" when using
tiling. I consider the former to be attributes of the physical surface, things
which are determined through BO allocation, and the latter being attributes
which are derived from the API, and having nothing to do with the underlying
surface.
Determining tiling properties and creating miptrees are related operations
(when we allocate a BO for a miptree) with some disjoint constraints. By
extracting the decisions into two distinct choices (tiling vs. miptree
properties), we gain flexibility throughout the code to make determinations
about when we can or cannot fast clear strictly on the miptree.
To signify this change, I've also renamed the function to indicate it is a
distinction made on the miptree. I am torn as to whether or not it was a good
idea to remove "non_msrt" since it's a really nice thing for grep.
v2:
Reword some comments (Chad)
intel_is_non_msrt_mcs_tile_supported->intel_tiling_supports_non_msrt_mcs (Chad)
Make full if ladder for gens in above function (Chad)
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Cc: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Chad Versace <chad.versace at linux.intel.com>
commit b91a110d5ce946abe0ee84625498676ac4bcf7aa
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Fri May 22 18:13:24 2015 -0700
i965/gen9: Only allow Y-Tiled MCS buffers
For GEN9, much of the logic to use X-Tiled buffers has been stripped out. It is
still supported in some places, but it's never desirable. Unfortunately we don't
yet have the ability to have Y-Tiled scanout (see:
http://patchwork.freedesktop.org/patch/46984/),
NOTE: This patch shouldn't actually do anything since SKL doesn't yet use fast
clears (they are disabled because they are causing regressions). THerefore, the
only case we can get to this function on SKL is by way of
intel_update_winsys_renderbuffer_miptree.
v2: Update commit message to be more clear that the NOTE is for SKL only.
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Chad Versace <chad.versace at intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit b5c5aac687ca4e203695790e334c1f7f3315c240
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Thu May 21 16:04:43 2015 -0700
i965: Consolidate certain miptree params to flags
I think pretty much everyone agrees that having more than a single bool as a
function argument is bordering on a bad idea. What sucks about the current
code is in several instances it's necessary to propagate these boolean
selections down to lower layers of the code. This requires plumbing (mechanical,
but still churn) pretty much all of the miptree functions each time. By
introducing the flags paramater, it is possible to add miptree constraints very
easily.
The use of this, as is already the case, is sometimes we have some information
at the time we create the miptree that needs to be known all the way at the
lowest levels of the create/allocation, disable_aux_buffers is currently one
such example. There will be another example coming up in a few patches.
v2:
Tab fix. (Ben)
Long line fixes (Topi)
Use anonymous enum instead of #define for layout flags (Chad)
Use 'X != 0' instead of !!X (everyone except Chad)
v3:
Some non-trivial conflict resolution on top of Anuj's patches.
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Cc: "Pohjolainen, Topi" <topi.pohjolainen at intel.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 0d2068a92d74f421960947e589cf56a2b125035f
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Wed Jun 10 19:40:07 2015 +1000
glsl: enforce restriction on AoA interface blocks in GLSL ES 3.10
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit 94d669b0d2f56d58a494a40f9e8acdef01306496
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Fri Jun 12 16:03:56 2015 +1000
glsl: enforce fragment shader input restrictions in GLSL ES 3.10
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit 3d78bdea3155ff3f19a782e0eb3a55612bfd8dd0
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Wed Jun 10 18:46:22 2015 +1000
glsl: enforce output variable rules for GLSL ES 3.10
Some rules are already applied this just adds the missing ones.
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias at igalia.com>
commit f0e772392f1c61df6e3f253dc236eb9737fb6146
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Fri Mar 13 12:03:52 2015 -0700
i965/nir: Support barrier intrinsic function
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit f7ef8ec9d8f56b77029534952628c3204c4d5f63
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Wed Aug 27 11:32:08 2014 -0700
i965/fs: Implement support for ir_barrier
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit 7953c000731ec1310fdbb5d8a13720fe0cdbf6f4
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Tue Nov 4 18:11:37 2014 -0800
i965: Add brw_barrier to emit a Gateway Barrier SEND
This will be used to implement the Gateway Barrier SEND needed to implement
the barrier function.
v2:
* notify => gateway_notify (Ken)
* combine short lines of brw_barrier proto/decl (mattst88)
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit 0d250cc210f971f566bbe5b1e54cf3cd114537e9
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Tue Nov 4 18:05:04 2014 -0800
i965: Add brw_WAIT to emit wait instruction
This will be used to implement the barrier function.
v2:
* Rename to brw_WAIT (mattst88)
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit b925f1a1df86120d2846bf09797bb0967040f9c6
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Tue Nov 4 17:52:42 2014 -0800
i965: Add notification register
This will be used by the wait instruction when implementing the barrier()
function.
v2:
* Changes suggested by mattst88
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit bdbbec33cf23193e1c81e0ecf28f2cc793d507bf
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Tue Nov 4 17:51:19 2014 -0800
i965: Disassemble Gateway SEND messages
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit 69659546a6a352239c5989624f9d9f084c643d7d
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Tue Nov 4 18:07:52 2014 -0800
i965/inst: Add gateway_notify and gateway_subfuncid fields
These fields will be used when emitting a send for the barrier function.
Reference: IVB PRM Volume 4, Part 2, Section 1.1.1 Message Descriptor
v2:
* notify => gateway_notify (Ken)
* define bits for gen4-gen6 (bwidawsk, Ken)
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 1b9cc257d4b805e86af4860bb356dbedf5e054c6
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Tue Nov 4 17:48:44 2014 -0800
i965: Add GATEWAY_SFID definitions
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit 2867f2e8cd54e2cbb38140e2e0f5521973091ace
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Fri Mar 13 12:03:15 2015 -0700
nir: Add barrier intrinsic function
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit 86855365b4059c60a9e1dcc0b7713941a2507bd0
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Sun Sep 7 19:29:50 2014 +1200
glsl: Add builtin barrier() function
[jordan.l.justen at intel.com: Add CS support]
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit e7f628c2fc5ef42672e3281e224226c3d47b1bac
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Sun Sep 7 19:24:15 2014 +1200
glsl: Add ir node for barrier
v2:
* Changes suggested by mattst88
[jordan.l.justen at intel.com: Add nir support]
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit 86b4acb409a2103d6a12f83de7ec04af6cc05fec
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Thu Jun 11 09:44:54 2015 -0700
i965/cs: Use exec all for CS terminate
This prevents an assertion from being hit with SIMD16:
Assertion `inst->exec_size == dispatch_width() || force_writemask_all' failed.
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit cfc175b40995ca4e590cd30897f6bb017e1376a3
Author: Chad Versace <chad.versace at intel.com>
Date: Wed Jun 10 09:50:47 2015 -0700
i965/fs: Fix unused variable warning
Annotate offset_components with attribute 'unused'.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit d15c06b514936fb927b174a716c24af8f5892542
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Jun 10 23:50:21 2015 +0100
vc4: automake: enable subdir-objects
Silence the warnings about the future incompatibility with automake 2.0
Cc: Eric Anholt <eric at anholt.net>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 634f2002563b4fca68490c0a39518ea838f28fb1
Author: Erik Faye-Lund <kusmabite at gmail.com>
Date: Wed Jun 10 23:35:04 2015 +0100
mesa: build xmlconfig to a separate static library
As we use the file from both the dri modules and loader, we end up with
multiple definition of the symbols provided in our gallium dri modules.
Additionally we compile the file twice.
Resolve both issues, effectively enabling the build on toolchains which
don't support -Wl,--allow-multiple-definition.
v2: [Emil Velikov]
- Fix the Scons/Android build.
- Resolve libgbm build issues (bring back the missing -lm)
Cc: Julien Isorce <j.isorce at samsung.com>
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90310
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90905
Acked-by: Matt Turner <mattst88 at gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 83b5648a1e0b7c21536af18c0d29da2f2a31215e
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Apr 15 14:34:00 2015 +0100
targets/nine: link against libnir/libglsl_util
Based on commit 101142c4010(xa: support for drivers which use NIR)
Cc: "10.6" <mesa-stable at lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90466
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit ba512cc7fa5db0aeeb2fc0708920914cd3a5bf95
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Apr 15 12:46:30 2015 +0100
pipe-loader: add libnir and libglsl_util to the link
Based on commit 101142c4010(xa: support for drivers which use NIR)
Cc: Rob Clark <robclark at freedesktop.org>
Cc: "10.6" <mesa-stable at lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90466
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 1df5a6c71ee4a3c08b5da3f8bae24880af16b74c
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Apr 15 13:40:55 2015 +0100
mesa; add a dummy _mesa_error_no_memory() symbol to libglsl_util
Rather than forcing everyone to provide their own definition of the symbol
provide a common (dummy) one.
This helps us resolve the build of the standalone pipe-drivers (amongst
others), which are missing the symbol.
Cc: Rob Clark <robclark at freedesktop.org>
Cc: "10.6" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 4722743f4b920c6986a7148ef3ce76b4fd12db46
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Apr 15 11:42:55 2015 +0100
gallium: use $(top_builddir) when referencing static archives
Just like every other place in gallium.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 3f5dc9b94fc47f25821cec0a052df3d8f4cb5a1f
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Apr 15 11:28:38 2015 +0100
freedreno: use CXX linker rather than explicit link against libstdc++
Cc: Rob Clark <robclark at freedesktop.org>
Cc: "10.6" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 0e55db3b8a9a360511d8679953b8e4b890d66ed7
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Jun 11 13:08:00 2015 +0100
egl/haiku: coding style fixes
Cc: Alexander von Gluck IV <kallisti5 at unixzen.com>
Acked-by: Brian Paul <brianp at vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit b0f33e9736116a1a6a7bd8bade51d473d7373daa
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Jun 11 13:07:08 2015 +0100
egl/haiku: plug some obvious memory leaks
Cc: Alexander von Gluck IV <kallisti5 at unixzen.com>
Acked-by: Brian Paul <brianp at vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit e77a32fcaed30815d0f95e0d05432e8637ab0f3e
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Jun 11 12:33:55 2015 +0100
egl/haiku: minor surface management cleanups
Drop the stub/unused function haiku_create_surface() and add some basic implementation for destroy_surface()
Cc: Alexander von Gluck IV <kallisti5 at unixzen.com>
Acked-by: Brian Paul <brianp at vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit d38a80ba6c75b8f594a4ff88e59ede254075a859
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Jun 11 12:22:28 2015 +0100
egl/haiku: kill off haiku_log()
It's an incomplete copy of the default _eglLog() implementation. Just
use the default logger.
Cc: Alexander von Gluck IV <kallisti5 at unixzen.com>
Acked-by: Brian Paul <brianp at vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 667fe2f5e9508a9591eeabdd7a01596006d87e5f
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Jun 11 12:20:34 2015 +0100
egl/haiku: we don't use src/loader, drop all the references to it
Cc: Alexander von Gluck IV <kallisti5 at unixzen.com>
Acked-by: Brian Paul <brianp at vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit d0af2833039dca2963f3ddf241e3084e4bf7e840
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Jun 11 12:18:35 2015 +0100
egl/haiku: remove unused variables in struct haiku_egl_driver
Cc: Alexander von Gluck IV <kallisti5 at unixzen.com>
Acked-by: Brian Paul <brianp at vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 46f87b2c19dc0a326c963c652b174384d59e3943
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Jun 11 12:17:23 2015 +0100
egl/haiku: handle memory allocation failure
Cc: Alexander von Gluck IV <kallisti5 at unixzen.com>
Acked-by: Brian Paul <brianp at vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit ed9dcdf927b9badd1325130b6b88ad26b04d2ec1
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Jun 11 12:02:45 2015 +0100
egl/haiku: use CALL/TRACE/ERROR over _eglLog() for haiku specifics
Cc: Alexander von Gluck IV <kallisti5 at unixzen.com>
Acked-by: Brian Paul <brianp at vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 0b652fedb5e097bcdea79e3b922e946d143148f6
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Jun 11 11:31:40 2015 +0100
egl/haiku: remove commented out code
It serves little to no purpose. As the driver gets updated, one can
look at the existing implementation (dri2) for reference rather than
letting the commented functions bitrot.
Cc: Alexander von Gluck IV <kallisti5 at unixzen.com>
Acked-by: Brian Paul <brianp at vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit c3036f4bb1c4ad788200afc877d42e63b64f330e
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Jun 11 11:24:17 2015 +0100
egl/haiku: use correct version variable
Earlier commit folded the two separate variables into one, but forgot to
update the haiku driver.
Fixes: 0e4b564ef28(egl: combine VersionMajor and VersionMinor into one
variable)
Cc: Marek Olšák <marek.olsak at amd.com>>
Cc: Alexander von Gluck IV <kallisti5 at unixzen.com>
Acked-by: Brian Paul <brianp at vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 0dde821bcc96c579ac1f26e26fc03ca117caa377
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Fri Jun 12 12:13:41 2015 +0100
trace: Add missing p_compiler.h include.
For boolean.
Trivial.
commit 8d3c48eed24f351c86361707978647c78010bb7f
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jun 10 14:40:33 2015 +0300
i965/fs: Remove one more fixed brw_null_reg() from the visitor.
Instead use fs_builder::null_reg_f() which has the correct register
width. Avoids the assertion failure in fs_builder::emit() hit by the
"ES3-CTS.shaders.loops.for_dynamic_iterations.unconditional_break_fragment"
GLES3 conformance test introduced by 4af4cfba9ee1014baa4a777660fc9d53d57e4c82.
Reported-and-reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 16658f426dbd81fcbc317b21ae9a3f7c9b6448fb
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Jun 9 09:20:58 2015 -0700
Revert "i965: Advertise a line width of 40.0 on Cherryview and Skylake."
This reverts commit f3b709c0ac073cd0ec90a3a0d91d1ee94668e043.
The "dEQP-GLES3.functional.rasterization.fbo.rbo_multisample_4.
interpolation.lines_wide" test appears to be broken on Cherryview when
we expose line widths greater than 12.0. I'm not sure why.
For now, just go back to the limits we used on older platforms.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90902
Acked-by: Matt Turner <mattst88 at gmail.com>
commit f4310cdbd08f20276237fbefa3eba406aa109636
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Jun 10 01:46:13 2015 -0700
i965: Re-index SSA definitions before printing NIR code.
This makes the SSA definitions use sequential numbers (0, 1, 2, ...)
instead of seemingly random ones. There's not much point normally,
but it makes debug output much easier to read.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 1a6e4f46ed117b393e26aff326e5b05d4aea7fb0
Author: Brian Paul <brianp at vmware.com>
Date: Wed Jun 10 10:59:37 2015 -0600
gallium: remove explicit values from PIPE_CAP_ enums
The other PIPE_CAPF_ and PIPE_SHADER_CAP_ enums don't have explicit values.
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 9fed4f9bf5146af1fcd093422b39353845f2267a
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Thu Jun 11 13:32:21 2015 +0100
mesa/main: Don't use ONCE_FLAG_INIT as a r-value.
It should only be used as an initializer expression.
Trivial, and fixes Windows builds.
Nevertheless, overwriting an once_flag like this seems dangerous and
should be revised.
commit 0f1fe649b7fdfb3ab8c7b14e642bc0e3831fc092
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Thu Jun 11 08:49:46 2015 +0200
i965/gen8: Fix antialiased line rendering with width < 1.5
The same fix Marius implemented for gen6 (commit a9b04d8a) and
gen7 (commit 24ecf37a).
Also, we need the same code to handle special cases of line width
in gen6, gen7 and now gen8, so put that in the helper function
we use to compute the line width.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 5b61cb12366f65a5d7e21b47fa3501a03fd884ee
Author: Martin Peres <martin.peres at linux.intel.com>
Date: Tue May 26 15:32:21 2015 +0300
glsl: fix constructing a vector from a matrix
Without this patch, the following constructs (not an extensive list)
would crash mesa:
- mat2 foo = mat2(1); vec4 bar = vec4(foo);
- mat3 foo = mat3(1); vec4 bar = vec4(foo);
- mat3 foo = mat3(1); ivec4 bar = ivec4(foo);
The first case is explicitely allowed by the GLSL spec, as seen on
page 101 of the GLSL 4.40 spec:
"vec4(mat2) // the vec4 is column 0 followed by column 1"
The other cases are implicitely allowed also.
The actual changes are quite minimal. We first split each column of
the matrix to a list of vectors and then use them to initialize the
vector. An additional check to make sure that we are not trying to
copy 0 elements of a vector fix the (i)vec4(mat3) case as the last
vector (3rd column) is not needed at all.
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Signed-off-by: Martin Peres <martin.peres at linux.intel.com>
commit 83624c141d3568217190933945c3243913e7ba2c
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Wed May 6 13:43:54 2015 +0300
mesa/es3.1: enable DRAW_INDIRECT_BUFFER_BINDING for gles3.1
(increases ES31-CTS.draw_indirect.basic.* passing tests)
v2: only expose DRAW_INDIRECT_BUFFER_BINDING for GL core + ES3.1
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 56e9f3b493a8677e60e4473ca0faf0e3d1a79888
Author: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
Date: Fri Mar 20 15:40:26 2015 +0200
mesa/main: avoid null access in format_array_table_init()
If _mesa_hash_table_create failed we'd get null pointer. Report
error and go away.
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit fd00c738c08e54c9dfdc195e59f780f30d2f9e07
Author: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
Date: Fri Mar 20 15:13:14 2015 +0200
mesa/main: Remove _mesa_HashClone()
I didn't find this being used anywhere.
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit bd38f91f8d80897ca91979962d80d4bc0acef586
Author: Alexander Monakov <amonakov at gmail.com>
Date: Tue Jun 9 20:58:22 2015 +0300
i965: do_blit_drawpixels: decode array formats
Correct a regression introduced by commit 922c0c9fd526 by converting "array
format", if received from _mesa_format_from_format_and_type, to mesa_format.
References: https://bugs.freedesktop.org/show_bug.cgi?id=90839
Signed-off-by: Alexander Monakov <amonakov at gmail.com>
Tested-by: AnAkkk <anakin.cs at gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Cc: mesa-stable at lists.freedesktop.org
commit f9a18acb56c69b24c1e47cd326dc98e14fadcf94
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Wed Jun 10 09:07:32 2015 +0200
i965: do not round line width when multisampling or antialiaing are enabled
In commit fe74fee8fa721a we rounded the line width to the nearest integer to
match the GLES3 spec requirements stated in section 13.4.2.1, but that seems
to break a dEQP test that renders wide lines in some multisampling scenarios.
Ian noted that the Open 4.4 spec has the following similar text:
"The actual width of non-antialiased lines is determined by rounding the
supplied width to the nearest integer, then clamping it to the
implementation-dependent maximum non-antialiased line width."
and suggested that when ES removed antialiased lines, they removed
"non-antialised" from that paragraph but probably should not have.
Going by that note, this patch restricts the quantization implemented in
fe74fee8fa721a only to regular aliased lines. This seems to keep the
tests fixed with that commit passing while fixing the broken test.
v2:
- Drop one of the clamps (Ken, Marius)
- Add a rule to prevent advertising line widths that when rounded go beyond
the limits allowed by the hardware (Ken)
- Update comments in the code accordingly (Ian)
- Put the code in a utility function (Ian)
Fixes:
dEQP-GLES3.functional.rasterization.fbo.rbo_multisample_max.primitives.lines_wide
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90749
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Cc: "10.6" <mesa-stable at lists.freedesktop.org>
commit f83b9e58f6e8a748def367c7d523eb7285b1aeb7
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Jun 9 14:33:47 2015 -0700
i965: Momentarily pretend to support ARB_texture_stencil8 for blits.
Broadwell's stencil blitting code attempts to bind a renderbuffer as a
texture, using dd->BindRenderbufferTexImage().
This calls _mesa_init_teximage_fields(), which then attempts to set
img->_BaseFormat = _mesa_base_tex_format(ctx, internalFormat), which
assert fails if internalFormat is GL_STENCIL_INDEX8 but
ARB_texture_stencil8 is unsupported.
To work around this, just pretend to support the extension momentarily,
during the blit. Meta has already munged a variety of other things in
the context (including the API!), so it's not that much worse than what
we're already doing.
Fixes regressions since commit f7aad9da20b13c98f77d6a690b327716f39c0a47
(mesa/teximage: use correct extension for accept stencil texture.).
v2: Add an XXX comment explaining the situation (requested by Jason
Ekstrand and Martin Peres), and an assert that we don't support
the extension so we remember to remove this hack (requested by
Neil Roberts).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 7217faf39f63f81b74f268d62fbdd94d445b0e6f
Author: Brian Paul <brianp at vmware.com>
Date: Wed Jun 10 07:28:40 2015 -0600
llvmpipe: simplify lp_resource_copy()
Just implement it in terms of util_resource_copy_region(). Both the
original code and util_resource_copy_region() boil down to mapping,
calling util_copy_box() and unmapping.
No piglit regressions. This will also help to implement GL_ARB_copy_image.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 5b0d6f5c1bc3f7bd37c6efebf48f80ca6ff3ef87
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Tue Jun 9 12:26:48 2015 +0300
mesa: add GL_RED, GL_RG support for floating point textures
Mesa supports EXT_texture_rg and OES_texture_float. This patch adds
support for using unsized enums GL_RED and GL_RG for floating point
targets and writes proper checks for internalformat when format is
GL_RED or GL_RG and type is of GL_FLOAT or GL_HALF_FLOAT.
Later, internalformat will get adjusted by adjust_for_oes_float_texture
after these checks.
v2: simplify to check vs supported enums
v3: follow the style and break out if internalFormat ok (Kenneth)
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90748
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 07e4f12e66f64c8075c0d3fd1c23cbd7c657970c
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Mon Jun 8 14:53:26 2015 +0300
mesa: allow unsized formats GL_RG, GL_RED for GLES 3.0 with half float
v2: && -> ||, we enable on gles3 or if ARB_texture_rg is enabled
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90748
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit adee54f8269c5e9f4fde91d19f0e465afc8f14d8
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Tue Jun 9 16:53:55 2015 +1000
glsl: remove restriction on unsized arrays in GLSL ES 3.10
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 563706c14641fde2ab604d590b5425680354f280
Author: Dave Airlie <airlied at gmail.com>
Date: Wed Jun 10 13:51:59 2015 +1000
st/dri: check pscreen is valid before querying param
we don't check the validity of pscreen until dri_init_screen_helper
hit this trying to init glamor on a device with no driver (udl).
Acked-by: Michel Dänzer <michel.daenzer at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit c6877c9e5983287a0741b26a358b7d744aebe232
Author: Dave Airlie <airlied at gmail.com>
Date: Wed Jun 10 13:26:56 2015 +1000
nouveau: set imported buffers to what the kernel gives us
When we import a dma-buf fd from another driver the kernel
gives us the right info, and this trashes it.
Convert the kernel bo flags into the domain flags.
This helps getting reverse prime and glamor working.
Cc: mesa-stable at lists.freedesktop.org
Acked-by: Ben Skeggs <bskeggs at redhat.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 9dca3beb62e894bbd720c5eecb47c0fd2c6132f9
Author: Eric Anholt <eric at anholt.net>
Date: Sun Jun 7 12:02:02 2015 -0700
vc4: Drop qir include from vc4_screen.h
We didn't need any of it except for the list header, and qir.h pulls in
nir.h, which is not really interesting to winsys.
commit 8d10b2a0460ca01a5c65a87184717c6c2e4bcaeb
Author: Eric Anholt <eric at anholt.net>
Date: Wed Jun 3 10:18:04 2015 -0700
vc4: Drop subdirectory in vc4 build.
Just because we put the source in a subdir, doesn't mean we need helper
libraries in the build. This will also simplify the Android build setup.
commit e67b12eaf89acc9c446de77b77120a2f6cdbbe12
Author: Eric Anholt <eric at anholt.net>
Date: Mon Jun 1 12:50:49 2015 -0700
vc4: Update to current kernel validation code.
After profiling on real hardware, I found a few ways to cut down the
kernel overhead.
commit c5e11e5f7f67fe5a1d28b1446f87af7aa3ba68d8
Author: Chih-Wei Huang <cwhuang at android-x86.org>
Date: Wed May 20 11:25:39 2015 +0800
android: build with libcxx on android lollipop
On Lollipop, apparently stlport is gone and libcxx must be used instead.
We still support stlport when building on earlier android releases.
Signed-off-by: Chih-Wei Huang <cwhuang at linux.org.tw>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 1842832660c4eade037caa760110b58a2d7f055b
Author: Chih-Wei Huang <cwhuang at android-x86.org>
Date: Wed May 20 11:25:34 2015 +0800
android: enable the radeonsi driver
Based on the nice work of Paulo Sergio Travaglia <pstglia at gmail.com>.
The main modifications are:
- Include paths for LLVM header files and shared/static libraries
- Set C++ flag "c++11" to avoid compiling errors on LLVM header files
- Set defines for LLVM
- Add GALLIVM source files
- Changes path of libelf library for lollipop
Signed-off-by: Chih-Wei Huang <cwhuang at linux.org.tw>
Acked-by: Eric Anholt <eric at anholt.net>
commit 1e4081f54aa5c6cba566ed549389d847bf7e6799
Author: Chih-Wei Huang <cwhuang at android-x86.org>
Date: Wed May 20 11:25:33 2015 +0800
android: generate files by $(call es-gen)
Use the pre-defined macro es-gen to generate new added files
instead of writing new rules manually. The handmade rules
that may generate the files before the directory is created
result in such an error:
/bin/bash: out/target/product/x86/gen/STATIC_LIBRARIES/libmesa_st_mesa_intermediates/main/format_pack.c: No such file or directory
make: *** [out/target/product/x86/gen/STATIC_LIBRARIES/libmesa_st_mesa_intermediates/main/format_pack.c] Error 1
Signed-off-by: Chih-Wei Huang <cwhuang at linux.org.tw>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit c3b5afbd4e682f76e16ea85883af571165bd24ee
Author: Chih-Wei Huang <cwhuang at android-x86.org>
Date: Wed May 20 11:25:30 2015 +0800
android: try to load gallium_dri.so directly
This avoids needing hardlinks between all of the DRI driver .so names,
since we're the only loader on the system.
v2: Add early exit on success (like previous block) and log message on
failure.
Signed-off-by: Chih-Wei Huang <cwhuang at linux.org.tw>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit ac296aee58158ccf1953e812a04f99eb5f8eb57b
Author: Chih-Wei Huang <cwhuang at android-x86.org>
Date: Wed May 20 11:25:29 2015 +0800
android: Depend on gallium_dri from EGL, instead of linking in gallium.
The Android gallium build used to use gallium_egl, which was removed back
in March. Instead, we will now use a normal Mesa libEGL loader with
dlopen()ing of a DRI module.
v2: add a clean step to rebuild all dri modules properly.
v3: Squish the 2 patches doing this together (change by anholt).
Signed-off-by: Chih-Wei Huang <cwhuang at linux.org.tw>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 933df3d3350867282d7334c94abf1ec677d78029
Author: Chih-Wei Huang <cwhuang at android-x86.org>
Date: Wed May 20 11:25:28 2015 +0800
android: add rules to build a gallium_dri.so
This single .so includes all of the enabled gallium drivers.
Signed-off-by: Chih-Wei Huang <cwhuang at linux.org.tw>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit f4f609b27e4fbefb52b84b617051fb4cdba45c8f
Author: Chih-Wei Huang <cwhuang at android-x86.org>
Date: Wed May 20 11:25:27 2015 +0800
android: add rules to build gallium/state_trackers/dri
Signed-off-by: Chih-Wei Huang <cwhuang at linux.org.tw>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 581aa208fa8fc653dce50d95c1f3400bb0c68ab2
Author: Chih-Wei Huang <cwhuang at android-x86.org>
Date: Wed May 20 11:25:26 2015 +0800
android: export more dirs from libmesa_dri_common
The include paths of libmesa_dri_common are also used by modules
that need libmesa_dri_common.
Signed-off-by: Chih-Wei Huang <cwhuang at linux.org.tw>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit b8213bbe4cec5bab89e07aab8d225e617d4a2087
Author: Chih-Wei Huang <cwhuang at android-x86.org>
Date: Wed May 20 11:25:25 2015 +0800
android: loader: export the path to be included
Signed-off-by: Chih-Wei Huang <cwhuang at linux.org.tw>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 30ba4faf5dcb9f55352eed1b37a3e820e8efe2ad
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Mon Jun 8 14:52:07 2015 -0700
i965/gen9: Use raw PS invocation count for queries
Previously the number needed to be divided by 4 to get the proper results. Now
the hardware does the right thing. Through experimentation it seems Braswell
(CHV) does also need the division by 4.
Fixes piglit test:
arb_pipeline_statistics_query-frag
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit c10dc485f395d3b8d616bf2857bcdef9712dc47b
Author: Brian Paul <brianp at vmware.com>
Date: Tue Jun 9 09:14:17 2015 -0600
glsl: fix comment typo: s/accpet/accept/
commit 37e0677870febefdd8b89be335f0e97bfd4a7c9b
Author: Brian Paul <brianp at vmware.com>
Date: Fri Jun 5 08:00:09 2015 -0600
mesa: remove some MAX_NV_FRAGMENT_PROGRAM_* macros
GL_NV_fragment_program support was removed a while ago. This is just
some clean-up.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 670862a5069f2759418450698aa4ab7d9f0e079f
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Sat Jun 6 12:08:00 2015 -0700
fs/reg_allocate: Remove the MRF hack helpers from fs_visitor
These are helpers that only exist in this one file. No reason to put them
in the visitor.
Reviewed-by: Neil Roberts <neil at linux.intel.com>
commit 86e5afbfee5492235cab1a7be4ea49ac02be1644
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Sat Jun 6 12:15:30 2015 -0700
i965/fs: Don't let the EOT send message interfere with the MRF hack
Previously, we just put the message for the EOT send as high in the file as
it would go. This is because the register pre-filling hardware will stop
all over the early registers in the file in preparation for the next thread
while you're still sending the last message. However, if something happens
to spill, then the MRF hack interferes with the EOT send message and, if
things aren't scheduled nicely, will stomp on it.
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90520
Reviewed-by: Neil Roberts <neil at linux.intel.com>
commit 65bd4159b35c7213e0ac27c6299495e08a105ab4
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Tue Jun 9 14:43:21 2015 +0100
rtasm: Generalize executable memory allocator to all Unices.
We're only using fairly portable standard Unix calls here, so might as
well save ourselves future trouble by enabling on all Unices by default.
https://bugs.freedesktop.org/show_bug.cgi?id=90904
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit 698c391521561a1f0e4ff2570e35417be9968eaa
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jun 3 18:17:50 2015 +0300
i965/fs: Drop fs_inst::force_uncompressed.
This is now unused. Saves a whole bit of memory per instruction.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 44928b799adbbf2671c482431b3b7a390118725c
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jun 8 19:32:18 2015 +0300
i965/fs: Remove dead IR construction code from the visitor.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 51948085a2e5d97dbf2cd3c255a5873d509773eb
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jun 3 18:16:30 2015 +0300
i965/fs: Migrate test_fs_cmod_propagation to the IR builder.
v2: Use set_predicate/condmod. Use fs_builder::OPCODE instead of
::emit.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 76c8142d0af45ab9907ebc9cfd2855fa753735b6
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jun 3 18:15:22 2015 +0300
i965/fs: Migrate test_fs_saturate_propagation to the IR builder.
v2: Use set_saturate. Use fs_builder::OPCODE instead of ::emit.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit bf83a1a219af8bf82c3c721888bbe0dfc3eced34
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jun 3 21:02:57 2015 +0300
i965/fs: Migrate translation of NIR texturing instructions to the IR builder.
v2: Don't remove assignments of base_ir just yet.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 979fe2ffee3956186017fe6c115aed53fc87ad3d
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jun 3 21:01:32 2015 +0300
i965/fs: Migrate translation of NIR intrinsics to the IR builder.
v2: Use fs_builder::SEL instead of ::emit. Use set_condmod().
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit fe88c7ae38c72ea09ced69fb12ff00f58bdf1d6e
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jun 3 20:59:26 2015 +0300
i965/fs: Migrate translation of NIR ALU instructions to the IR builder.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 3632c28bde071950dc57e42eb62a65fb838c8bdc
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jun 3 20:57:12 2015 +0300
i965/fs: Migrate translation of NIR control flow to the IR builder.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 9976731485abb68eb3b5ae6f11a7838977b95b5b
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jun 3 21:17:36 2015 +0300
i965/fs: Migrate NIR variable handling to the IR builder.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 09733f220ac9921ce7d8c3524bc5327d8203c446
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jun 3 21:12:49 2015 +0300
i965/fs: Migrate NIR emit_percomp() to the IR builder.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit d5cb2e513794f6c26259665bc93cf507e86ae3b8
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jun 3 21:08:43 2015 +0300
i965/fs: Migrate CS terminate message to the IR builder.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit e522f12f03bcb0edb1384adff894918bf8d6d1b6
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jun 3 22:43:00 2015 +0300
i965/fs: Migrate VS output writes to the IR builder.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit e32c16c47f7a3cf25e2b4d2f3b97d0f8f89669c0
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jun 3 21:07:52 2015 +0300
i965/fs: Migrate FS framebuffer writes to the IR builder.
The explicit call to fs_builder::group() in emit_single_fb_write() is
required by the builder (otherwise the assertion in fs_builder::emit()
would fail) because the subsequent LOAD_PAYLOAD and FB_WRITE
instructions are in some cases emitted with a non-native execution
width. The previous code would always use the channel enables for the
first quarter, which is dubious but probably worked in practice
because FB writes are never emitted inside non-uniform control flow
and we don't pass the kill-pixel mask via predication in the cases
where we have to fall-back to SIMD8 writes.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 840cbef416b47fa1a92d6491cdd2895442f063bc
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jun 3 21:07:34 2015 +0300
i965/fs: Migrate FS alpha test to the IR builder.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit ad68853f17868081a69b3f73f4bf4c1bc8b2571d
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jun 3 20:45:54 2015 +0300
i965/fs: Migrate FS discard handling to the IR builder.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 46f264638ad97a0b806e6fad7117d62a2cf914b6
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jun 3 21:56:20 2015 +0300
i965/fs: Migrate FS gl_SamplePosition/ID computation code to the IR builder.
v2: Use fs_builder::AND/SHR/MOV instead of ::emit.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 31477226ec6cbe956a4bbdcae81cc7ca5ad28cc6
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jun 3 21:54:54 2015 +0300
i965/fs: Migrate FS interpolation code to the IR builder.
v2: Fix some preexisting trivial codestyle issues.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit d3c10ad42729c1fe74a7f7c67465bd2beb7f9e75
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jun 3 20:43:09 2015 +0300
i965/fs: Migrate shader time to the IR builder.
v2: Change null register destination type to UD so it can be compacted.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 35e64f2a769c915bedeafdb86152b0c4a2067b35
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jun 3 21:06:13 2015 +0300
i965/fs: Migrate untyped surface read and atomic to the IR builder.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit db83d9d2d0f2743cf64ece731c753f21aba87da6
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jun 3 21:05:28 2015 +0300
i965/fs: Migrate texturing implementation to the IR builder.
v2: Remove tabs from modified lines.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 546839ef639bf871feaa62ab7d811f2fc783bdcd
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jun 3 22:22:39 2015 +0300
i965/fs: Migrate pull constant loads to the IR builder.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 8f626c14989f005599f7841b89144d2bf58b5704
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jun 3 22:22:10 2015 +0300
i965/fs: Migrate Gen4 send dependency workarounds to the IR builder.
v2: Change brw_null_reg() to bld.null_reg_f().
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 4af4cfba9ee1014baa4a777660fc9d53d57e4c82
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jun 3 20:49:32 2015 +0300
i965/fs: Migrate lower_integer_multiplication to the IR builder.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit efa60e49f2e5dd56f1c81487e9aad9f89136d8b4
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jun 3 20:36:47 2015 +0300
i965/fs: Migrate lower_load_payload to the IR builder.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 8f8c6b7bdab1fc25fe8277705ebb1818ab220821
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jun 3 19:05:54 2015 +0300
i965/fs: Migrate register spills and fills to the IR builder.
Yes, it's incorrect to use the 0-th channel enable group
unconditionally without considering the execution and regioning
controls of the instruction that uses the spilled value, but it
matches the previous behaviour exactly, the builder just makes the
preexisting problem more obvious because emitting an instruction of
non-native SIMD width without having called .group() or .exec_all()
explicitly would have led to an assertion failure.
I'll fix the problem in a follow-up series, as the solution is going
to be non-trivial.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 3e6ac0bcedfe1b5d092d6ee19323c3ef87b99dba
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jun 3 21:05:45 2015 +0300
i965/fs: Migrate try_replace_with_sel to the IR builder.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 6114ba4dccfdb8f7c657feeed8f8c9b69debba91
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jun 3 20:46:31 2015 +0300
i965/fs: Migrate opt_sampler_eot to the IR builder.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit a800ec04ad84abeb6243897a276facc4ef6cac82
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jun 3 19:51:47 2015 +0300
i965/fs: Migrate opt_peephole_sel to the IR builder.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 78f7c9edeb21ec4e7a4f96aa12b51cecc40e9688
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jun 3 19:33:44 2015 +0300
i965/fs: Create and emit instructions in one step in opt_peephole_sel.
This simplifies opt_peephole_sel() slightly by emitting the SEL
instructions immediately after they are created, what makes the
sel_inst and mov_imm_inst arrays unnecessary and will make it possible
to get rid of the explicit inserts when the pass is migrated to the IR
builder.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 74c2458ecf492f2dd344b4f6114b13a376f90657
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Jun 4 16:13:35 2015 +0300
i965/fs: Migrate opt_cse to the IR builder.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit e7069fbc701de68b65a876e1b4bfde4f111dd084
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Jun 4 16:09:47 2015 +0300
i965/fs: Don't drop force_writemask_all and _sechalf when copying a CSE temporary.
LOAD_PAYLOAD instructions need the same treatment as any other
generator instructions, at least FB writes and typed surface messages
will need a payload built with non-zero execution controls.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 497d238ae72aa59fb32b21191a1a0444ca09fc10
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Jun 4 16:05:33 2015 +0300
i965/vec4: Take into account all instruction fields in CSE instructions_match().
Most of these fields affect the behaviour of the instruction, but
apparently we currently don't CSE the kind of instructions for which
these fields could make a difference in the VEC4 back-end. That's
likely to change soon though when we start using send-from-GRF for
texture sampling and surface access messages.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 8013b8147ae5fc652799c7ff01c2d419ebebe3db
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Jun 4 15:09:10 2015 +0300
i965/fs: Take into account all instruction fields in CSE instructions_match().
Most of these fields affect the behaviour of the instruction so it
could actually break the program if we CSE a pair of otherwise
matching instructions with different values of these fields.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit d86c2e6e539db518dca162145c096b7440d043a7
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jun 3 18:22:17 2015 +0300
i965/fs: Migrate opt_peephole_predicated_break to the IR builder.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 35e5f118a5116685b30ad3305c1c153f1af37f66
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jun 3 18:20:50 2015 +0300
i965/fs: Migrate opt_combine_constants to the IR builder.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit e04b4156a745fc09afa066c892c1913362eae9df
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jun 3 19:59:44 2015 +0300
i965/fs: Allocate a common IR builder object in fs_visitor.
v2: Call fs_builder::at_end() to point the builder at the end of the
program explicitly.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 8ea8f83c8f6b932749ada32ac666d151a9636508
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Apr 22 14:02:47 2015 +0300
i965/fs: Introduce FS IR builder.
The purpose of this change is threefold: First, it improves the
modularity of the compiler back-end by separating the functionality
required to construct an i965 IR program from the rest of the visitor
god-object, what in turn will reduce the coupling between other
components and the visitor allowing a more modular design. This patch
doesn't yet remove the equivalent functionality from the visitor
classes, as it involves major back-end surgery.
Second, it improves consistency between the scalar and vector
back-ends. The FS and VEC4 builders can both be used to generate
scalar code with a compatible interface or they can be used to
generate natural vector width code -- 1 or 4 components respectively.
Third, the approach to IR construction is somewhat different to what
the visitor classes currently do. All parameters affecting code
generation (execution size, half control, point in the program where
new instructions are inserted, etc.) are encapsulated in a stand-alone
object rather than being quasi-global state (yes, anything defined in
one of the visitor classes is effectively global due to the tight
coupling with virtually everything else in the compiler back-end).
This object is lightweight and can be copied, mutated and passed
around, making helper IR-building functions more flexible because they
can now simply take a builder object as argument and will inherit its
IR generation properties in exactly the same way that a discrete
instruction would from the same builder object.
The emit_typed_write() function from my image-load-store branch is an
example that illustrates the usefulness of the latter point: Due to
hardware limitations the function may have to split the untyped
surface message in 8-wide chunks. That means that the several
functions called to help with the construction of the message payload
are themselves required to set the execution width and half control
correctly on the instructions they emit, and to allocate all registers
with half the default width. With the previous approach this would
require the used helper functions to be aware of the parameters that
might differ from the default state and explicitly set the instruction
bits accordingly. With the new approach they would get a modified
builder object as argument that would influence all instructions
emitted by the helper function as if it were the default state.
Another example is the fs_visitor::VARYING_PULL_CONSTANT_LOAD()
method. It doesn't actually emit any instructions, they are simply
created and inserted into an exec_list which is returned for the
caller to emit at some location of the program. This sort of two-step
emission becomes unnecessary with the builder interface because the
insertion point is one more of the code generation parameters which
are part of the builder object. The caller can simply pass
VARYING_PULL_CONSTANT_LOAD() a modified builder object pointing at the
location of the program where the effect of the constant load is
desired. This two-step emission (which pervades the compiler back-end
and is in most cases redundant) goes away: E.g. ADD() now actually
adds two registers rather than just creating an ADD instruction in
memory, emit(ADD()) is no longer necessary.
v2: Drop scalarizing VEC4 builder.
v3: Take a backend_shader as constructor argument. Improve handling
of debug annotations and execution control flags.
v4: Drop Gen6 IF with inline comparison. Rename "instr" variable.
Initialize cursor to NULL by default and add method to explicitly
point the builder at the end of the program.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 6e040657292d8d0a6fe8fe7d4d94e9808f29e924
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jun 3 21:24:50 2015 +0300
i965: Define consistent interface to enable instruction result saturation.
v2: Use set_ prefix.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 7624f8410f64a7ce0ba125a2025904c70610c076
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jun 3 21:24:18 2015 +0300
i965: Define consistent interface to enable instruction conditional modifiers.
v2: Use set_ prefix.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 239dfc5410d98f3b31a06652ceff13d9858c1f9b
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jun 3 21:23:46 2015 +0300
i965: Define consistent interface to predicate an instruction.
v2: Use set_ prefix.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit f9367191b30956b9cfe578dd8e426b28d2417b6b
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jun 8 14:49:31 2015 +0300
mesa: Drop include of simple_list.h from mtypes.h.
simple_list.h defines a number of macros with short non-namespaced
names that can easily collide with other declarations (first_elem,
last_elem, next_elem, prev_elem, at_end), and according to the comment
it was only being included because of struct simple_node, which is no
longer used in this file.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 277b94f172c44cb4199a740722f42bc701d591dc
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jun 8 14:48:29 2015 +0300
dri/nouveau: Include simple_list.h explicitly in nv*_state_tnl.c.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 7065c8153b5bea3fe4f364dbb922488f755bc1db
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jun 8 14:47:17 2015 +0300
tnl: Include simple_list.h explicitly in t_context.c.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 08a1046f6777c589f90eae3fd1e7e41ca364c45c
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Jun 8 14:46:58 2015 +0300
mesa: Include simple_list.h explicitly in errors.c.
This seems to be the only user of simple_list in core mesa not
including the header explicitly.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit f7aad9da20b13c98f77d6a690b327716f39c0a47
Author: Dave Airlie <airlied at gmail.com>
Date: Sun Apr 5 16:48:47 2015 +1000
mesa/teximage: use correct extension for accept stencil texture.
This was using the wrong extension, ARB_stencil_texturing
doesn't mention any changes in this area.
Fixes "dEQP-GLES3.functional.fbo.completeness.renderable.texture.
stencil.stencil_index8."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90751
Signed-off-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 556b2fbd240bff5d20c5137827757e053c00c3a8
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Tue Apr 14 22:06:47 2015 -0700
i965: Make a helper function intel_miptree_set_total_width_height()
and some more code refactoring. No functional changes in this patch.
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 9111377978edf1c688811f877896942be9f8a332
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Tue Apr 14 22:06:48 2015 -0700
i965/gen9: Set vertical alignment for the miptree
v3: Use ffs() and a switch loop in
tr_mode_horizontal_texture_alignment() (Ben)
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit 447410b66436acde4440aeae45f701b0e4502e97
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Tue Apr 14 22:06:48 2015 -0700
i965/gen9: Set horizontal alignment for the miptree
v3: Use ffs() and a switch loop in
tr_mode_vertical_texture_alignment() (Ben)
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit 126078faca7a9da0f825d3ad07ce9b1183737240
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Tue Apr 14 22:06:47 2015 -0700
i965/gen9: Set tiled resource mode for the miptree
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit ef6b9985ea6b60a562daed3a9ed3be0f91f21e01
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Tue Apr 14 22:06:47 2015 -0700
i965: Pass miptree pointer as function parameter in intel_vertical_texture_alignment_unit
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 9edac38f2a7aaa55bc4f33eb268155ba76908925
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Tue Apr 14 22:06:47 2015 -0700
i965: Move intel_miptree_choose_tiling() to brw_tex_layout.c
and change the name to brw_miptree_choose_tiling().
V3: Remove redundant function parameters. (Topi)
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 2cbe730ac53a8510d0decde20a42f1acd51a93a9
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Tue Apr 14 22:06:47 2015 -0700
i965: Choose tiling in brw_miptree_layout() function
This refactoring is required by later patches in this series.
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 4f2f5c8d81673473dce8bee3d66b524b4908a823
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Mon Dec 22 19:29:24 2014 -0800
i965: Disallow saturation for MACH operations.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
commit 922c0c9fd526ce19b87bc74a3159dec7705c1de1
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Fri Jun 5 14:45:18 2015 +0100
i965: Export format comparison for blitting between miptrees
Since the introduction of
commit 536003c11e4cb1172c540932ce3cce06f03bf44e
Author: Boyan Ding <boyan.j.ding at gmail.com>
Date: Wed Mar 25 19:36:54 2015 +0800
i965: Add XRGB8888 format to intel_screen_make_configs
winsys buffers no longer have an alpha channel. This causes
_mesa_format_matches_format_and_type() to reject previously working BGRA
uploads from using the BLT fast path. Instead of using the generic
routine for matching formats exactly, export the slightly more relaxed
check from intel_miptree_blit() which importantly allows the blitter
routine to apply a small number of format conversions.
References: https://bugs.freedesktop.org/show_bug.cgi?id=90839
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Jason Ekstrand <jason at jlekstrand.net>
Cc: Alexander Monakov <amonakov at gmail.com>
Cc: Kristian Høgsberg <krh at bitplanet.net>
Cc: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Cc: mesa-stable at lists.freedesktop.org
commit c2d0606827412b710dcaed80268fc665de8c9c5d
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Fri Jun 5 14:33:36 2015 +0100
i915: Blit RGBX<->RGBA drawpixels
The blitter already has code to accommodate filling in the alpha channel
for BGRX destination formats, so expand this to also allow filling the
alpha channgel in RGBX formats.
More importantly for the next patch is moving the test into its own
function for the purpose of exporting the check to the callers.
v2: Fix alpha expansion as spotted by Alexander with the fix suggested by
Kenneth
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Jason Ekstrand <jason at jlekstrand.net>
Cc: Alexander Monakov <amonakov at gmail.com>
Cc: Kristian Høgsberg <krh at bitplanet.net>
Cc: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by Kenneth Graunke <kenneth at whitecape.org>
Cc: mesa-stable at lists.freedesktop.org
commit 8da79b8378ae87474d8c47ad955e4833edf98359
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Fri Jun 5 13:49:08 2015 +0100
i965: Fix HW blitter pitch limits
The BLT pitch is specified in bytes for linear surfaces and in dwords
for tiled surfaces. In both cases the programmable limit is 32,767, so
adjust the check to compensate for the effect of tiling.
v2: Tweak whitespace for functions (Kenneth)
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Kristian Høgsberg <krh at bitplanet.net>
Cc: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by Kenneth Graunke <kenneth at whitecape.org>
Cc: mesa-stable at lists.freedesktop.org
commit 8614b9e489e65bb672ab16053d30ce8708856214
Author: Martin Peres <martin.peres at linux.intel.com>
Date: Fri Jun 5 15:19:01 2015 +0300
softpipe/query: force parenthesis around a logical not
This makes GCC5 happy.
Reviewed-by: Brian Paul <brianp at vmware.com>
Signed-off-by: Martin Peres <martin.peres at linux.intel.com>
commit 184e4de3a126fa21945fe59f68b8a29977919fc4
Author: Martin Peres <martin.peres at linux.intel.com>
Date: Fri Jun 5 15:03:19 2015 +0300
main/version: make sure all the output variables get set in get_gl_override
This fixes 2 warnings in gcc 5.1.
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Martin Peres <martin.peres at linux.intel.com>
commit 56e38edc960bf08213cdb0282838ccec3e5ea10e
Author: Michel Dänzer <michel.daenzer at amd.com>
Date: Tue May 26 16:27:15 2015 +0900
radeonsi: Add CIK SDMA support
Based on the corresponding SI support. Same as that, this is currently
only enabled for one-dimensional buffer copies due to issues with
multi-dimensional SDMA copies.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
commit 79f2acb8f89704c609dd87d969353a506e03b05e
Author: Michel Dänzer <michel.daenzer at amd.com>
Date: Wed Nov 19 15:31:24 2014 +0900
r600g,radeonsi: Assert that there's enough space after flushing
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
commit 9538902c4f0e94e57228f939489d31676c43a778
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sun Jun 7 13:44:37 2015 +0100
docs: add news item and link release notes for mesa 10.5.7
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit f7db7fe6ea3d6044b4ceda0c2c477642302e3997
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sun Jun 7 11:45:25 2015 +0100
docs: Add sha256sums for the 10.5.7 release
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit eb3a704bb0008c1d046abae31dcb0b2b980c66b1)
commit 56efe81ab163a0c7af15fc53821ac56c0d7641d8
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sun Jun 7 11:13:19 2015 +0100
Add release notes for the 10.5.7 release
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit 495bcbc48cf4e7cee0f2de11c1166a1fd6eb3969)
commit 7b8f20ec5505a25958bcd98aabe73a7ca2b6cbba
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Jun 4 17:00:17 2015 -0700
prog_to_nir: Fix fragment depth writes.
In the ARB_fragment_program specification, the result.depth output
variable is treated as a vec4, where the fragment depth is stored in the
.z component, and the other three components are undefined.
This is different than GLSL, which uses a scalar value (gl_FragDepth).
To make this consistent for driver backends, this patch makes
prog_to_nir use a scalar output variable for FRAG_RESULT_DEPTH,
moving result.depth.z into the first component.
Fixes Glean's fragProg1 "Z-write test" subtest.
Cc: mesa-stable at lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90000
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 52e5ad7bf8c731280ca4506b7d38e8c7a8e734b9
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Wed Jun 3 12:11:27 2015 +1200
i965: Set max texture buffer size to hardware limit
Previously we were leaving this at the default of 64K, which meets the
spec but is too small for some real uses. The hardware can handle up to
128M.
User was complaining about this on freenode ##OpenGL today.
Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit b639ed2f1b170d1184c6d94c88c826c51ffc8726
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Thu Jun 4 23:59:23 2015 -0700
i965: Add gen8 fast clear perf debug
In an ideal world I would just implement this instead of adding the perf debug.
There are some errata involved which lead me to believe it won't be so simple as
flipping a few bits.
There is room to add a thing for Gen9s flexibility, but since I am actively
working on that I have opted to ignore it.
Example:
Multi-LOD fast clear - giving up (256x128x8).
v2: Use braces for if statements because they are multiple lines (Ken)
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 77a44512d9ed56be5e53ebf09e917b5aeeba0189
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Thu Jun 4 22:05:13 2015 -0700
i965: Add buffer sizes to perf debug of fast clears
When we cannot do the optimized fast clear it's important to know the buffer
size since a small buffer will have much less performance impact.
A follow-on patch could restrict printing the message to only certain sizes.
Example:
Failed to fast clear 1400x1056 depth because of scissors. Possible 5% performance win if avoided.
Recommended-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 6acb61fc9c2c5f81569d17d90a480abc48ec6055
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue May 12 22:53:00 2015 +0200
clover: clarify and fix the EGL interop error case
Cc: 10.6 <mesa-stable at lists.freedesktop.org>
commit a1cb407b049bb431b0f6f21e6e376d11f136af67
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon May 11 22:18:04 2015 +0200
egl: expose EGL 1.5 if all requirements are met
There's no driver support yet, because EGL_KHR_gl_colorspace isn't
implemented.
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit 51c8c66e1d81d03f0db6aee0a510aa85c277053e
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue May 12 21:41:32 2015 +0200
egl: return correct invalid-type error from eglCreateSync
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit 820a4d402ad3891ec460882feab3801fbc646a65
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue May 12 21:06:41 2015 +0200
egl: add new platform functions (v2)
These are just wrappers around the existing extension functions.
v2: return BAD_ALLOC if _eglConvertAttribsToInt fails
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit 515f04ed6fe0c914b2cd22c7ea65db6e34c362e3
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue May 12 20:42:05 2015 +0200
egl: add eglCreateImage (v2)
v2: - use calloc
- return BAD_ALLOC if calloc fails
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit 1e79e054e7dff0c45538fff1257e1f81a206d7c9
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue May 12 18:14:31 2015 +0200
egl: add eglGetSyncAttrib (v2)
v2: - don't modify "value" in eglGetSyncAttribKHR after an error
- rename _egl_api::GetSyncAttribKHR -> GetSyncAttrib
- rename GetSyncAttribKHR_t -> GetSyncAttrib_t
- rename _eglGetSyncAttribKHR to _eglGetSyncAttrib
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit 7524592da6305d52e95d718691d5a6665738aade
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue May 12 18:13:31 2015 +0200
egl: add eglWaitSync
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit 2885ba0e4cea102d77832e2af4b212d00ab5edd4
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue May 12 20:54:22 2015 +0200
egl: add EGL 1.5 functions that don't need any changes from extensions
Declare the functions without the suffix, so that the core names are exported.
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit d333d30632516b1fc5b60181c2c237653e55a8e1
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue May 12 17:34:57 2015 +0200
egl: use EGL 1.5 types without suffixes
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit 706466f4619b76f2475120f187c34d01ab5aa727
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue May 12 00:44:56 2015 +0200
egl: add context attribs from EGL 1.5
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit f9f894447e4e7442d5dfa489bb43f2823e2fc71d
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue May 12 00:44:20 2015 +0200
egl: fix setting context flags
Cc: 10.6 10.5 10.4 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit 0e4b564ef288159f16f7a6886b6cfc0110411af8
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue May 12 16:40:29 2015 +0200
egl: combine VersionMajor and VersionMinor into one variable
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit efda9c56491f5cb90e77f5fe7979477fc9b2b529
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon May 11 22:16:52 2015 +0200
egl: set the EGL version in common code
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit 3a83adeb7c6340104e9417beefc086f7d33183bc
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon May 11 21:38:55 2015 +0200
egl: remove unused _egl_global::ClientExtensions
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit 20249d355989668bfdcfed61708a6959794b9710
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri May 15 19:59:59 2015 +0200
egl: import platform headers from registry (v2)
v2: don't remove local Mesa changes
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit 6b31f22338656c154e028b4bc2cbd14ab733a957
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri May 15 19:58:51 2015 +0200
egl: import eglext.h from registry and cleanup eglmesaext.h (v2)
v2: include mesa and chromium extensions in eglext.h so as not to break
existing users
v3: keep PFNEGLSWAPBUFFERSREGIONNOK because piglit uses it
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit 49ae822183aa4daf6c6df9ef33e0b9a148d1a0d1
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri May 15 19:55:24 2015 +0200
egl: import egl.h from registry (v2)
v2: split the commit into 3 patches
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit f52e8572ae1d91bcb6aef9fd3aac02ede62dee4e
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu May 28 16:13:37 2015 +0200
mesa: remove unused gl_config::colorIndexMode
Reviewed-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 4312b4f5704ddd88e27b3bf2c17eaf054567f067
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu May 28 18:14:29 2015 +0200
mesa: use GL_GEOMETRY_PROGRAM_NV instead of MESA_GEOMETRY_PROGRAM
There's no reason to use our own definition.
Tessellation will use the NV definitions too.
Reviewed-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 3b2721ce1145cc60bf35e41e9f50a92849142a06
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu May 28 18:10:08 2015 +0200
mesa: use _mesa_has_geometry_shader in get_programiv
Reviewed-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit b7ef7903b8f582438172ef1bdc72788be3aa0860
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu May 28 16:28:39 2015 +0200
mesa: remove useless gl_compute_program_state::Current
This is for user assembly shaders only (not GLSL). We won't support those.
Reviewed-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit e8b040477e271324a88d35c003775337848a500c
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu May 28 16:09:23 2015 +0200
mesa: remove unused geometry shader variables
These states are for GS assembly shaders only. We don't support those.
Reviewed-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 3d16b5af1dca889ccc3716470f38c1fa84713f26
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue May 26 19:07:35 2015 +0200
tgsi/ureg: fix a coverity defect in emit_decls
Reported by Ilia Mirkin.
commit 6aff87bb01d2bd583ac629d02ebf56ecbf86ec2c
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue May 26 19:07:35 2015 +0200
r600g: fix a coverity defect in streamout code
Reported by Ilia Mirkin.
commit 6bf3729a3fa32a779e9593ffdf1c14e7a4f6dbad
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed May 20 11:43:55 2015 +0200
glsl_to_tgsi: use TGSI array declarations for VS,GS arrays of outputs (v2)
v2: don't use PIPE_MAX_SHADER_ARRAYS
commit 9b1921100ef5f265403b278fab26ae404db719da
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun May 10 13:03:27 2015 +0200
glsl_to_tgsi: use TGSI array declarations for GS,FS arrays of inputs (v2)
v2: don't use PIPE_MAX_SHADER_ARRAYS
commit 26c8a49bc40839298d5cd986181d4bee31a48936
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat May 9 23:54:35 2015 +0200
glsl_to_tgsi: remove some emit functions by using C++ default values
commit 85cd1cf4b88aff9bd2667359e36e6fbb7be92122
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat May 9 23:38:52 2015 +0200
glsl_to_tgsi: rename emit -> emit_asm
My editor thinks "emit" is a keyword, which breaks code indexing.
commit 30b74c02cd57463591588274ad638ca80b34cb57
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue May 26 15:18:27 2015 +0200
glsl_to_tgsi: remove memset after calloc
commit 6ae3bc256927b583690729b8940a4418e75b0596
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue May 26 15:09:20 2015 +0200
glsl_to_tgsi: don't use a static array size for st_translate::arrays
commit 57c98e22db3397efe42268ba0750f319cea3b0fd
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue May 26 15:09:20 2015 +0200
glsl_to_tgsi: don't use a static array size for "array_sizes"
commit b6ebe7eabf54936a02acc0968e718e0c264a73f5
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon May 25 19:30:44 2015 +0200
tgsi/ureg: don't emit in/out arrays if drivers don't support ranged declarations
Softpipe, llvmpipe, r300g, and radeonsi pass tests. Other drivers need testing.
Freedreno and nv30 are definitely broken. Other drivers seem to be alright.
commit a015b3952f568ad3da1ddfe42ff7ce6568f52780
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed May 20 11:11:43 2015 +0200
tgsi/ureg: add support for output array declarations
commit 1fa6c99e24890359e9cee2a9da02f21ea77b9f15
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun May 10 16:17:35 2015 +0200
tgsi/ureg: add support for GS input array declarations
commit d3fbc659868ecdbfe14600a75eafe28174f7d99e
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun May 10 16:51:32 2015 +0200
tgsi/ureg: merge input and fs_input arrays
commit 3b1d15775190945b1a639dd9b2581b4032cd2ac6
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun May 10 13:10:03 2015 +0200
tgsi/ureg: rename and simplify ureg_DECL_gs_input
There is nothing special about it and it's used for tessellation shaders
too.
commit 918ca4031f670066f054cdebcfe68ad75c963ac6
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun May 10 12:52:02 2015 +0200
tgsi/ureg: add support for FS input array declarations
commit cf2c9265a3977d43beb9a9894a5b934af74df7d7
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun May 10 17:41:26 2015 +0200
tgsi/scan: get more information about arrays and handle arrays correctly (v2)
v2: use less memory for the information
commit 78395dbf9ff429d98523f8b4a340f7188d8b4db0
Author: Tapani <tapani.palli at intel.com>
Date: Fri Jun 5 08:22:07 2015 +0300
mesa: fix program resource queries for builtin variables
Patch fixes special cases with gl_VertexID and sets all builtin
variables locations as '-1' as specified by the extension spec.
Fixes ES 3.1 conformance test failure:
ES31-CTS.program_interface_query.input-built-in
v2: comments + use is_gl_identifier() (Martin)
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
commit cb277cde6f2a210b0515cd04269964fd409307e9
Author: Alan Coopersmith <alan.coopersmith at oracle.com>
Date: Sat May 23 00:03:53 2015 -0700
glsl_compiler: Remove unused extra argument to printf in usage_fail
Flagged by Oracle's parfait static analyzer:
Error: Format string argument mismatch (CWE 628)
In call to printf with format string "usage: %s [options] <file.vert | file.geom | file.frag>\n\nPossible options are:\n"
Too many arguments for format string (got more than 1 arguments)
at line 285 of src/glsl/main.cpp in function 'usage_fail'.
Signed-off-by: Alan Coopersmith <alan.coopersmith at oracle.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 00d8733120276fc5bdd3ecb7fea6e04b7940d71b
Author: Roland Scheidegger <sroland at vmware.com>
Date: Fri Jun 5 02:25:03 2015 +0200
docs: add note about llvmpipe supporting GL_ARB_shader_stencil_export
commit 6e5970ffee0129fb94d8b7f0ebd4fac3992e7dce
Author: Roland Scheidegger <sroland at vmware.com>
Date: Thu Jun 4 14:35:59 2015 +0200
draw: (trivial) fix NULL pointer dereference
This probably got broken when the samplers were converted to be indexed
by shader type.
Seen when looking at bug 89819 though I'm not sure if that really was what
the bug was about...
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit c820407ef0aac87546d1a778e169cfa1a915a219
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Jun 2 20:40:54 2015 -0700
i965/fs: Print mlen in dump_instructions() output.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 15a12795c6f3edef0e1cbab39b6da3d5b8f64fc3
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Jun 4 01:24:07 2015 -0700
prog_to_nir: Make RSQ properly take the absolute value of its argument.
I just botched this when writing the original code.
From the ARB_vertex_program specification:
"The RSQ instruction approximates the reciprocal of the square root of
the absolute value of the scalar operand and replicates it to all four
components of the result vector."
Fixes a Glean vertProg1 subtest:
RSQ test 2 (reciprocal square root of negative value)
Cc: mesa-stable at lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90547
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 71e94578779e4344066d434004fd85ca493de552
Author: Martin Peres <martin.peres at linux.intel.com>
Date: Thu Jun 4 14:09:31 2015 +0300
main: fix a regression in uniform handling introduced by 87a4bc5
The comment was accurate but the condition was reversed...
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Signed-off-by: Martin Peres <martin.peres at linux.intel.com>
commit 87a4bc511811327a00f9bbc1b6870b7fa46675f7
Author: Martin Peres <martin.peres at linux.intel.com>
Date: Thu May 21 15:51:09 2015 +0300
mesa: reference built-in uniforms into gl_uniform_storage
This change introduces a new field in gl_uniform_storage to
explicitely say that a uniform is built-in. In the case where it is,
no storage is defined to make it clear that it is read-only from the
mesa side. I fixed all the places in the code that made use of the
structure that I changed. Any place making a wrong assumption and using
the storage straight away will just crash.
This patch seems to implement the path of least resistance towards
listing built-in uniforms in GL_ACTIVE_UNIFORM (and other APIs).
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Signed-off-by: Martin Peres <martin.peres at linux.intel.com>
commit 4fd42a7c2798d03476c84b79cb855984a15c222c
Author: Roland Scheidegger <sroland at vmware.com>
Date: Wed Jun 3 01:34:06 2015 +0200
llvmpipe: Implement stencil export
Pretty trivial, fixes the issue that we're expected to be able to blit
stencil surfaces (as the blit just relies on util blitter code which needs
stencil export to do it).
2 piglits skip->pass, 11 fail->pass
v2: prettify, keep different stencil ref value handling out of depth/stencil
test itself.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit d46d04529b9c1e55b4c3b65a7078bbbd7ab1a810
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Jun 2 17:46:38 2015 -0700
i965: Use UW-typed immediate in multiply inst.
Some hardware reads only the low 16-bits even if the type is UD, but
other hardware like Cherryview can't handle this.
Fixes spec at arb_gpu_shader5@execution at sampler_array_indexing@fs-simple on
Cherryview.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90830
Reviewed-by: Neil Roberts <neil at linux.intel.com>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit 54a70a8ef20a9a875f0828acb42332cf69217ff5
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Jun 1 16:46:29 2015 -0700
program: Replace gl_inst_opcode with enum prog_opcode.
Both were introduced at the same time. I'm not sure why we needed two.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit fb011d31578ada40c2755314db783522477d0ad4
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Jun 1 16:27:46 2015 -0700
program: Remove dead Aux field from prog_instruction.
Appears to have been last used by the i965 driver (removed by commit
098acf6c).
Reviewed-by: Brian Paul <brianp at vmware.com>
commit ef3f89e53e76332ddb300b08f4698347e17d1633
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Jun 1 16:22:55 2015 -0700
program: Shrink and rename SaturateMode field to Saturate.
It was 2 bits to accommodate SATURATE_PLUS_MINUS_ONE (removed by commit
09b566e1). A similar change was made to TGSI recently in commit
e1c4e8aa.
Reducing the size from 2 bits to 1 reduces the size of the bit fields
from 17 bits to 16, which is a much nicer number.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 56b2b3d385170ab33934ec71fd9d0a6e0e1af9a8
Author: Brian Paul <brianp at vmware.com>
Date: Fri May 15 12:12:04 2015 -0600
mesa: move no-change glDepthFunc check earlier
If the incoming func matches the current state it must be a legal
value so we can do this before the switch statement.
Signed-off-by: Brian Paul <brianp at vmware.com>
commit 4dd72fe70d6800525302c734d161be411ed9f7e0
Author: Brian Paul <brianp at vmware.com>
Date: Fri May 15 12:09:54 2015 -0600
mesa: restore GL_EXT_depth_bounds_test state in glPopAttrib()
Spotted by inspection. Untested (no piglit test).
Signed-off-by: Brian Paul <brianp at vmware.com>
commit 6139195606d97b43a739500627c906baf804fab0
Author: Brian Paul <brianp at vmware.com>
Date: Fri May 15 11:22:25 2015 -0600
mesa: fix glPushAttrib(0) / glPopAttrib() error
If the glPushAttrib() mask value was zero we didn't actually push
anything onto the attribute stack. A subsequent glPopAttrib() call
would generate a GL_STACK_UNDERFLOW error. Now push a dummy attribute
in that case to prevent the error.
Mesa now matches nvidia's behavior.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 86a74e9b6b8953a55de234f185a14defd646f489
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Tue Jun 2 19:26:42 2015 +1000
nir: use src for ssa helper
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 5f7b8fa4811ae0acb49de5d0ef44ae1573eb5ccc
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Mon Jun 1 08:00:14 2015 +1000
nir: remove extra semicolon
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 5da809d70fb50eb4b290ee7cbe1b8f09e9286f4e
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Jun 1 12:22:54 2015 -0700
prog_to_nir: Remove OPCODE_MOV special case.
OPCODE_MOV is in the op_trans[] array.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 576f7241b6ce0ae22aa52a3e91fb1ac913d4b7b2
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Jun 1 12:19:30 2015 -0700
prog_to_nir: Remove from op_trans[] opcodes handled in the switch.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 5b226a12420993a0f4aae2295b33aaa305242a3d
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Tue Jun 2 13:42:46 2015 +0200
nir: prevent use-after-free condition in should_lower_phi()
lower_phis_to_scalar() pass recurses the instruction dependence graph to
determine if all the sources of a given instruction are scalarizable.
To prevent cycles, it temporary marks the phi instruction before recursing in,
then updates the entry with the resulting value. However, it does not consider
that the entry value may have changed after a recursion pass, hence causing
a use-after-free situation and a crash.
This patch fixes this by reloading the entry corresponding to the 'phi'
after recursing and before updating its value.
The crash can be reproduced ~20% of times with the dEQP test:
dEQP-GLES3.functional.shaders.loops.while_constant_iterations.nested_sequence_fragment
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 762395736be3adcc810274e1e96acd4bdceb10c6
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat May 30 11:19:28 2015 -0700
i965: Add Gen8+ VS dispatch_mode assertion.
Suggested by Ben Widawsky.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit a2655e0dd422599c07c572472855abd98d20d21a
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri May 29 23:02:56 2015 -0700
i965: Drop LOAD_PAYLOAD workaround in fs_visitor::emit_urb_writes().
Now that Jason's LOAD_PAYLOAD improvements have landed, we don't need
this. Passing 1 for the number of header registers already takes care
of setting force_writemask_all on the header copy.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
commit 386bf336c400104fbc80bf8a21f745eca5771ec1
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed May 13 14:45:45 2015 -0700
i965: Use proper pitch for scalar GS pull constants and UBOs.
See the corresponding code in brw_vs_surface_state.c.
v2: const more things (requested by Topi Pohjolainen)
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit 0f8ec779ddff4126837a7d4216ecf1d4b97e93d2
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Mar 11 21:18:42 2015 -0700
i965: Create a shader_dispatch_mode enum to replace VS/GS fields.
We used to store the GS dispatch mode in brw_gs_prog_data while
separately storing the VS dispatch mode in brw_vue_prog_data::simd8.
This patch introduces an enum to represent all possible dispatch modes,
and stores it in brw_vue_prog_data::dispatch_mode, unifying the two.
Based on a suggestion by Matt Turner.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit 9945573d65f4f66d127df7cbb62648889d09a7ed
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sun May 10 23:33:30 2015 -0700
i965: Drop "Vector Mask Enable" bit from 3DSTATE_GS on Gen8+.
The documentation makes it pretty clear that we shouldn't use this:
"Under normal conditions SW shall specify DMask, as the GS stage
will provide a Dispatch Mask appropriate to SIMD4x2 or SIMD8 thread
execution (as a function of dispatch mode). E.g., for SIMD4x2
execution, the GS stage will generate a Dispatch Mask that is equal
to what the EU would use as the Vector Mask. For SIMD8 execution
there is no known usage model for use of Vector Mask (as there is
for PS shaders)."
I also managed to find descriptions of DMask and VMask, in the "State
Register" (sr0.2/3) field descriptions:
"Dispatch Mask (DMask). This 32-bit field specifies which channels
are active at Dispatch time."
"Vector Mask (VMask). This 32-bit field contains, for each 4-bit
group, the OR of the corresponding 4-bit group in the dispatch
mask."
SIMD4x2 shaders process one or two vec4 values, with each 4-bit group
corresponding to xyzw channel enables (either all on, or all off).
Thus, DMask = VMask in SIMD4x2 mode. But in SIMD8 mode, 4-bit groups
are meaningless, so it just messes up your values.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit f97166e550f17f69f8de7e51775e745a5218d3e7
Author: Brian Paul <brianp at vmware.com>
Date: Mon Jun 1 07:40:34 2015 -0600
docs: update GL_ARB_copy_image, GL_ARB_clear_texture gallium status
VMware is working on these.
Signed-off-by: Brian Paul <brianp at vmware.com>
commit 51d08d55f46655715cb4a4ef5d14fb7d051b989a
Author: Brian Paul <brianp at vmware.com>
Date: Fri May 29 16:02:44 2015 -0600
gallium/util: silence silence unused var warnings for non-debug build
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 54070a9d1db332853609a31e5da76126d8f9445a
Author: Brian Paul <brianp at vmware.com>
Date: Fri May 29 16:01:37 2015 -0600
egl/dri2: silence uninitialized variable warnings
And update assertions to be more informative.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 87813c504a8a72198a6a4e8de9e5905fd751ac2c
Author: Brian Paul <brianp at vmware.com>
Date: Fri May 29 16:00:52 2015 -0600
gallivm: silence unused var warnings for non-debug build
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 71afc13eda53f36827f19e96404ff782561b523b
Author: Brian Paul <brianp at vmware.com>
Date: Fri May 29 16:00:14 2015 -0600
pipebuffer: silence unused var warnings for non-debug build
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 875918587156e139a82ac9ece9c1290b8019d007
Author: Brian Paul <brianp at vmware.com>
Date: Fri May 29 15:59:50 2015 -0600
st/mesa: silence unused var warnings for non-debug build
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit ae5d6db924d304a6b4af4f802e4ca1e1e2f25489
Author: Brian Paul <brianp at vmware.com>
Date: Fri May 29 15:59:27 2015 -0600
draw: silence unused var warnings for non-debug build
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 512117ce0e1b32b4e3086a638bf50b966a4724bc
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Fri May 29 14:33:18 2015 +0100
gallivm: Remove stub disassemblerSymbolLookupCB.
It's incompletete -- it wasn't filling ReferenceType so it was causing
garbagge on the disassembly. Furthermore it seems impossible to get the
jump information through this interface.
The solution for function size problem is to effectively book-keep the
machine code start and end address while JIT'ing.
commit 7f62fdae1629d75dd581d1c57b28c2f099c5ef6b
Author: Neil Roberts <neil at linux.intel.com>
Date: Fri May 29 13:41:48 2015 +0100
i965: Don't add base_binding_table_index if it's zero
When calculating the binding table index for non-constant sampler
array indexing it needs to add the base binding table index which is a
constant within the generated code. Often this base is zero so we can
avoid a redundant instruction in that case.
It looks like nothing in shader-db is doing non-constant sampler array
indexing so this patch doesn't make any difference but it might be
worth having anyway.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
Acked-by: Ben Widawsky <ben at bwidawsk.net>
commit 6c846dc57b1d6f3e015a604dba1976f96c4be9e9
Author: Neil Roberts <neil at linux.intel.com>
Date: Thu May 28 15:27:31 2015 +0100
i965: Don't use a temporary when generating an indirect sample
Previously when generating the send instruction for a sample
instruction with an indirect sampler it would use the destination
register as a temporary store. This breaks when used in combination
with the opt_sampler_eot optimisation because that forces the
destination to be null. This patch fixes that by avoiding the temp
register altogether.
The reason the temporary register was needed was because it was trying
to ensure the binding table index doesn't overflow a byte by and'ing
it with 0xff. The result is then or'd with samper_index<<8. This patch
instead just and's the whole thing by 0xfff. This will ensure that a
bogus sampler index won't overflow into the rest of the message
descriptor but unlike the previous code it won't ensure that the
binding table index doesn't overflow into the sampler index. It
doesn't seem like that should matter very much though because if the
shader is generating a bogus sampler index then it's going to just get
garbage out either way.
Instead of doing sampler_index<<8|(sampler_index+base_table_index) the
new code avoids one operation by doing
sampler_index*0x101+base_table_index which should be equivalent.
However if we wanted to avoid the multiply for some reason we could do
this by adding an extra or instruction still without needing the
temporary register.
This fixes a number of Piglit tests on Skylake that were using
indirect samplers such as:
spec at arb_gpu_shader5@execution at sampler_array_indexing@fs-simple
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
Acked-by: Ben Widawsky <ben at bwidawsk.net>
Tested-by: Anuj Phogat <anuj.phogat at gmail.com>
commit ec1c72d38ea4c709a39c6be9e0ff96bc2a90940f
Author: Eric Anholt <eric at anholt.net>
Date: Fri May 29 21:27:53 2015 -0700
vc4: Don't bother with safe list traversal in CSE.
We don't remove or move instructions.
commit 78c773bb3646295e4a4f1fe7d6d10f05758ee48b
Author: Eric Anholt <eric at anholt.net>
Date: Fri May 29 18:19:42 2015 -0700
vc4: Convert from simple_list.h to list.h
list.h is a nicer and more familiar set of list functions/macros.
commit 21a22a61c02a1d1807ff03df8eb8fa16ebdd1b74
Author: Eric Anholt <eric at anholt.net>
Date: Fri May 29 18:06:32 2015 -0700
vc4: Make sure we allocate idle BOs from the cache.
We were returning the most recently freed BO, without checking if it
was idle yet. This meant that we generally stalled immediately on the
previous frame when generating a new one. Instead, allocate new BOs
when the *oldest* BO is still busy, so that the cache scales with how
much is needed to keep some frames outstanding, as originally
intended.
Note that if you don't have some throttling happening, this means that
you can accidentally run the system out of memory. The kernel is now
applying some throttling on all execs, to hopefully avoid this.
commit c821ccf0e3a051e5e867792898ae9b8f08e4601a
Author: Eric Anholt <eric at anholt.net>
Date: Fri May 29 17:21:15 2015 -0700
vc4: Fix return value handling for BO waits.
If the wait ever returned -ETIME, we'd abort because the errno was
stored in errno and not drmIoctl()'s return value.
commit fcc79af9e25d5770b8de1f4102901cbf97857a34
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Fri May 29 21:47:53 2015 +1000
mesa: remove unused function declaration
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 82305f7b003879a3d08e1445f8ac4b1c6bee6330
Author: Brian Paul <brianp at vmware.com>
Date: Fri May 29 11:28:58 2015 -0600
dri_util: make version var unsigned to silence warnings
_mesa_override_gl_version_contextless() takes an unsigned version
parameter.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit b307921c3ff3b36607752f881a180272366a79cf
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Wed May 27 17:55:02 2015 -0700
i965: Disable compaction for EOT send messages
AFAICT, there is no real way to make sure a send message with EOT is properly
ignored from compact, nor can I see a way to actually encode EOT while
compacting. Before the single send optimization we'd always bail because we hit
the is_immediate && !is_compactable_immediate case. However, with single send,
is_immediate is not true, and so we end up trying to compact the un-compactible.
Without this, any compacting single send instruction will hang because the EOT
isn't there. I am not sure how I didn't hit this when I originally enabled the
optimization. I didn't check if some surrounding code changed.
I know Neil and Matt were both looking into this. I did a quick search and
didn't see any patches out there to handle this. Please ignore if this has
already been sent by someone. (Direct me to it and I will review it).
Reported-by: Neil Roberts <neil at linux.intel.com>
Reported-by: Mark Janes <mark.a.janes at intel.com>
Tested-by: Mark Janes <mark.a.janes at intel.com>
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit c0d2b83f0bb15c1a10e53ef85c167febf699921a
Author: Roland Scheidegger <sroland at vmware.com>
Date: Fri May 29 18:17:24 2015 +0200
gallivm: make sampling more robust when the sampler setup is bogus
Pure integer formats cannot be sampled with linear tex / mip filters. In GL
such a setup would make the texture incomplete.
We shouldn't rely on the state tracker though to filter that out, just return
all zeros instead of dying in the lerp.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 0ad15e55bfbca3d6b829b985f9e7ea7e3e69bc61
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Fri May 29 12:13:36 2015 +0100
configure.ac: Link mcdisassembler component.
gallivm now depends on it. And depending on particular LLVM version /
configure options, the build can fail without this change due to
undefined reference to `LLVM*Disasm*' symbols.
Trivial.
commit 9119cd7d2c959e437c40c86f214d08dc198bfa69
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Fri May 29 11:58:58 2015 +0100
configure.ac: Don't bother checking whether LLVM's MCJIT component is available.
Now that we require LLVM 3.3, MCJIT is guaranteed to be available.
Trvial.
commit 0db4ef9df152da1d0f3601bbccc68ac1c94d4a3b
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Thu May 28 16:55:10 2015 +0100
gallivm: Use the LLVM's C disassembly interface.
It doesn't do everything we want. In particular it doesn't allow to
detect jumps or return opcodes. Currently we detect the x86's RET
opcode.
Even though it's worse for LLVM 3.3, it's an improvement for LLVM 3.7,
which was totally busted.
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit 29203e77388f11e36db3190834809c3196ee47b5
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Thu May 28 15:35:14 2015 +0100
gallivm: Disable frame pointer omission on LLVM 3.7.
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit dd048543e944d95b4471572454cfa902392e3f61
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue May 26 12:47:03 2015 +0200
configure.ac: enable building GLES1 and GLES2 by default
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 25e9ae2b79f32631e7255807a242e5fc4e39984c
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue May 26 19:32:36 2015 +0200
st/dri: fix postprocessing crash when there's no depth buffer
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89131
Cc: 10.6 10.5 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 7116250b7a3aa8863f11d18032a3fbd24e2eee73
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed May 27 00:15:16 2015 +0200
radeon/llvm: reset temps_count on deallocation
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 7afc992c20a94883b876fe53e155b9fec6e5fb27
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue May 26 15:35:10 2015 +0200
radeon/llvm: don't use a static array size for radeon_llvm_context::arrays (v2)
v2: - don't use realloc (tgsi_shader_info provides the size)
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 065978d36b8a8ba5aa23248c6bcd0f0e4d6e86de
Author: Dave Airlie <airlied at gmail.com>
Date: Wed May 27 11:11:06 2015 +1000
softpipe: fix offset wrapping calculations (v2)
Roland pointed out my previous attempt was lacking, so I enhanced the
texwrap piglit test, and tested them. This fixes the offset calculations
in a number of areas by adding the offset first, it also fixes the fastpaths,
which I forgot to address in the previous commit.
v2: try and avoid divides in most paths, the repeat mirror path
really was ugly no matter which way I went, so I left it having
the divide.
Also fix the gather lod calculation bug.
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit b95ec49e57f81bdd75795dc93022533704efe509
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed May 20 12:03:33 2015 -0700
i965/vs: Rework the logic for generating NIR from ARB vertex programs
Whether or not to use NIR is now equivalent to brw->scalar_vs. We can
simplify the logic and make it far less confusing.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 78644ffc4d341deb431145108f0b2d377e59b61e
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed May 20 10:35:34 2015 -0700
i965/fs: Remove the ir_visitor code
Now that everything is running through NIR, this is all dead.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 66a03a4c4bb416a30b65e0334b248660a268c6a8
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed May 20 10:39:03 2015 -0700
i965: Remove the old fragment program code
Now that everything is running through NIR, this is all dead.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 114497afff4e49139b8c7d61f11a7872b81398bf
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed May 20 10:03:50 2015 -0700
i965: Make NIR non-optional for scalar shaders
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 8b9ecfff360711cffc41a0a062de5ad810f9cf2b
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed May 20 09:45:47 2015 -0700
i965: Make fs/vec4_visitor inherit from ir_visitor directly
This is using multiple inheritance in C++. However, ir_visitor is really
just an interface with no data so it shouldn't be so bad.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 99cb4233205edcfa1a1e2967eef7bb16ff19bec4
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed May 20 09:44:01 2015 -0700
i965: Rename backend_visitor to backend_shader
The backend_shader class really is a representation of a shader. The fact
that it inherits from ir_visitor is somewhat immaterial.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 1ca60de4c00e864bffbee8265f631b2267c8ea29
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon May 18 13:56:45 2015 -0700
mesa: Enable ARB_direct_state_access by default for core profile
And core profile only.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
Cc: "10.6" <mesa-stable at lists.freedesktop.org>
commit ef4dd0fc3e6b5ffbad6bd286ef9c6c25d0b25bae
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed May 20 20:19:07 2015 -0700
dispatch_sanity: Validate the compatibility profile dispatch table too
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Suggested-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.6" <mesa-stable at lists.freedesktop.org>
commit 49ab670f52947dda04585cc5156e55b89f0c1c4a
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed May 20 20:17:19 2015 -0700
dispatch_sanity: Split list of GL 3.1 functions in to core and common
The next patch will add a test for compatibility profile dispatch, and
it seems to make more sense to share the lists.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Cc: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.6" <mesa-stable at lists.freedesktop.org>
commit a6fa74e6bb65f852ad1608f43dd0731e854ea42f
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed May 20 20:13:12 2015 -0700
mesa: Don't install glVertexAttribL* functions in compatibility profile
GL_ARB_vertex_attrib_64bit is exclusive to core profile, and none of the
other functions added by the extension are advertised in other profiles.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Cc: Dave Airlie <airlied at redhat.com>
Cc: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.6" <mesa-stable at lists.freedesktop.org>
commit 4e5efa9e7ddb6d5273996cf9b09677d918759d17
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue May 19 11:48:11 2015 -0700
glapi: Make GL_ARB_direct_state_access functions exclusive to core profile
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Cc: Dave Airlie <airlied at redhat.com>
Cc: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: Dylan Baker <baker.dylan.c at gmail.com>
Cc: "10.6" <mesa-stable at lists.freedesktop.org>
commit f20899b7276b73e1b60c3ed8d8abdf959e787c0c
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue May 19 11:24:26 2015 -0700
glapi: Store exec table version info outside the XML
Currently on the functions that are exclusive to core-profile are
implemented. The remainder continue to live in the XML. Additional
functions can be moved later.
The functions for GL_ARB_draw_indirect and GL_ARB_multi_draw_indirect
are put in the dispatch table inside the VBO module, so they do not need
to be moved over.
The diff of src/mesa/main/api_exec.c before and after this patch is as
expected. All of the functions listed in apiexec.py moved out of a 'if
(_mesa_is_desktop(ctx))' block into a new 'if (ctx->API ==
API_OPENGL_CORE)' block.
v2: Remove stray shebang line in apiexec.py. Suggested by Ilia.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: Dave Airlie <airlied at redhat.com>
Cc: Dylan Baker <baker.dylan.c at gmail.com>
Cc: "10.6" <mesa-stable at lists.freedesktop.org>
commit 5c4aab58ee79a8bfa3d96f3ec442f37da587ff45
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon May 18 13:55:04 2015 -0700
Revert "mesa: Add an extension flag for ARB_direct_state_access"
This reverts commit 30dcaaec356cc117d7227c6680620cd50ff534e7.
Acked-by: Fredrik Höglund <fredrik at kde.org>
Cc: "10.6" <mesa-stable at lists.freedesktop.org>
commit 832ea2345a96388950bb39ce8a2e4ca8bfdb4fe5
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed May 20 17:19:29 2015 -0700
mesa: Use the profile instead of an extension bit to validate GL_TEXTURE_CUBE_MAP
The extension on which this depends will always be enabled in core
profile, and the extension bit is about to be removed.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
Cc: "10.6" <mesa-stable at lists.freedesktop.org>
commit 90e98ea215906bb7e9ecadc4d30d2718ba2186ad
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon May 18 13:54:55 2015 -0700
Revert "mesa: Add ARB_direct_state_access checks in XFB functions"
This reverts commit 7d212765a470972f4712e42caf6406b257220369.
Acked-by: Fredrik Höglund <fredrik at kde.org>
Cc: "10.6" <mesa-stable at lists.freedesktop.org>
commit cab233f277936f4cdc49aa0bbfc7ed1a85c925f1
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon May 18 13:54:39 2015 -0700
Revert "mesa: Add ARB_direct_state_access checks in buffer object functions"
This reverts commit 339ed0984d4f54fca91235a1df2ce3a850f6123f.
Acked-by: Fredrik Höglund <fredrik at kde.org>
Cc: "10.6" <mesa-stable at lists.freedesktop.org>
commit 8bcd14fab9a86276980a8859740999a1db4c55d5
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon May 18 13:54:35 2015 -0700
Revert "mesa: Add ARB_direct_state_access checks in FBO functions"
This reverts commit 6ad0b7e07a0445e9e0f368e079c4f7b8a6757bb3.
Acked-by: Fredrik Höglund <fredrik at kde.org>
Cc: "10.6" <mesa-stable at lists.freedesktop.org>
commit f3e8596a371c3708e9d9d68a021c39982c676cf1
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon May 18 13:54:29 2015 -0700
Revert "mesa: Add ARB_direct_state_access checks in renderbuffer functions"
This reverts commit cb49940766b581c6656473d89c221653c69fa0f9.
Acked-by: Fredrik Höglund <fredrik at kde.org>
Cc: "10.6" <mesa-stable at lists.freedesktop.org>
commit 1ac6a8f1d1952a20d54df3e513c253d7988402ac
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon May 18 13:54:25 2015 -0700
Revert "mesa: Add ARB_direct_state_access checks in texture functions"
This reverts commit 8940957238e8584ce27295791cee4cc3d6f7cf1e.
Acked-by: Fredrik Höglund <fredrik at kde.org>
Cc: "10.6" <mesa-stable at lists.freedesktop.org>
commit 92e362191e6c1c15e3944464fbf6bbda9e7d9892
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon May 18 13:54:21 2015 -0700
Revert "mesa: Add ARB_direct_state_access checks in VAO functions"
This reverts commit 36b05793372b86b914d9b95d0188f5f387e01d68.
Acked-by: Fredrik Höglund <fredrik at kde.org>
Cc: "10.6" <mesa-stable at lists.freedesktop.org>
commit ae5457754492b594c55911433a9b3675216c46c1
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon May 18 13:54:18 2015 -0700
Revert "mesa: Add ARB_direct_state_access checks in sampler object functions"
This reverts commit 9e7149c8986348bf9567f049444783ef52775f4e.
Acked-by: Fredrik Höglund <fredrik at kde.org>
Cc: "10.6" <mesa-stable at lists.freedesktop.org>
commit a9dcf45cd88b6e4d7816f45756d0b96d9c77cffe
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon May 18 13:54:15 2015 -0700
Revert "mesa: Add ARB_direct_state_access checks in program pipeline functions"
This reverts commit bebf3c6ab314bde05ac5a3b4d3e63fd36243c58e.
Acked-by: Fredrik Höglund <fredrik at kde.org>
Cc: "10.6" <mesa-stable at lists.freedesktop.org>
commit a9f678a8f4d4f9806dc4e931477fad300c61b4a1
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon May 18 13:54:11 2015 -0700
Revert "mesa: Add ARB_direct_state_access checks in query object functions"
This reverts commit d3368e0c9e27ced6059eb2ecdf2aa999a00e90b0.
Acked-by: Fredrik Höglund <fredrik at kde.org>
Cc: "10.6" <mesa-stable at lists.freedesktop.org>
commit f1fcf79e3c8e4f3594dc1b6d268430f8e8d4eb97
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon May 18 13:54:08 2015 -0700
Revert "i915: Enable ARB_direct_state_access"
This reverts commit 121030eed8fc41789d2f4f7517bbc0dd6199667b.
Acked-by: Fredrik Höglund <fredrik at kde.org>
Cc: "10.6" <mesa-stable at lists.freedesktop.org>
commit 4bc00b1a4b34abc3e6e26f126686608ccfa33f52
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon May 18 13:53:58 2015 -0700
Revert "i965: Enable ARB_direct_state_access"
This reverts commit a57feba0a35de35728269aeb26b039e4f2393d69.
Acked-by: Fredrik Höglund <fredrik at kde.org>
Cc: "10.6" <mesa-stable at lists.freedesktop.org>
commit 73cf10e6236fbf119c8262e69cd24f55557116f1
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon May 18 13:53:49 2015 -0700
Revert "st/mesa: Enable ARB_direct_state_access"
This reverts commit 357bf80caade9e0be20dcc88ec38884e34abc986.
Acked-by: Fredrik Höglund <fredrik at kde.org>
Cc: "10.6" <mesa-stable at lists.freedesktop.org>
commit 9b5e92f4ccc6ee1cb9caea947f6efaad2b391cf1
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Apr 29 16:12:40 2015 -0700
mesa: Allow overriding the version of ES2+ contexts
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 03fd6704db9f1d0f203bf8da18bd587c7e35ce60
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue May 26 12:07:13 2015 -0700
mesa: Add support for a new override string MESA_GLES_VERSION_OVERRIDE
The string is only applied when the context is API_OPENGLES2.
The bulk of the change is to prevent overriding the context to
API_OPENGL_CORE based on the requested version. If the context is
API_OPENGL_ES2, don't change it.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 464c56d3d5ca2c9d6e437e756950f0fa2996d8da
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue May 26 12:14:39 2015 -0700
dri_util: Use _mesa_override_gl_version_contextless
Remove _mesa_get_gl_version_override. We don't need two functions that
do basically the same thing. This change seemed easier (esp. with the
next patch) than going the other way.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 1fe243938b11be740417cf016d8c50cd69228628
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Apr 28 13:13:47 2015 -0700
mesa/es3.1: Enable ES 3.1 API and shading language version
This is a bit of a hack for now. Several of the extensions required for
OpenGL ES 3.1 have no support, at all, in Mesa. However, with this
patch and a patch to allow MESA_GL_VERSION_OVERRIDE to work with ES
contexts, people can begin testing the ES "version" of the functionality
that is supported.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 366ceacf72258a4a81d9c6b412dd565a4c611b17
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Apr 28 18:00:43 2015 -0700
gles/es3.1: Enable dispatch of almost all new GLES 3.1 functions
A couple functions are missing because there are no implementations of
them yet. These are:
glFramebufferParameteri (from GL_ARB_framebuffer_no_attachments)
glGetFramebufferParameteriv (from GL_ARB_framebuffer_no_attachments)
glMemoryBarrierByRegion
v2: Rebase on updated dispatch_sanity.cpp test.
v3: Add support for glDraw{Arrays,Elements}Indirect in vbo_exec_array.c.
The updated dispatch_sanity.cpp test discovered this omission.
v4: Rebase on glapi changes.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 8bbe7fa7a853d8ebf69e5d2d0fdc4343a20b638f
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon May 25 09:31:55 2015 -0700
i965/fs: Properly handle explicit depth in SIMD16 with dual-source blend
Cc: "10.6" <mesa-stable at lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90629
Tested-by: Markus Wick <markus at selfnet.de>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit e354cc9b791cf025d26de7e19c58d499b83a3570
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed May 27 12:19:07 2015 -0700
i965: Silence warning in 3-src type-setting.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 0596134410a0decc2f6bba77bfedb82d308aabbe
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed May 27 10:44:45 2015 -0700
i965/fs: Fix lowering of integer multiplication with cmod.
If the multiplication's result is unused, except by a conditional_mod,
the destination will be null. Since the final instruction in the lowered
sequence is a partial-write, we can't put the conditional mod on it and
we have to store the full result to a register and do a MOV with a
conditional mod.
Cc: "10.6" <mesa-stable at lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90580
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 2231cf0ba3a79d9abb08065e0f72811c5eea807f
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Thu May 28 09:06:33 2015 +0200
nir: Fix output swizzle in get_mul_for_src
When we compute the output swizzle we want to consider the number of
components in the add operation. So far we were using the writemask
of the multiplication for this instead, which is not correct.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 09d6243aed016eed4518435c9885275dbb6d2aa9
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Thu May 28 10:11:36 2015 +0100
gallivm: Workaround LLVM PR23628.
Temporarily undefine DEBUG macro while including LLVM C++ headers,
leveraging the push/pop_macro pragmas, which are supported both by GCC
and MSVC.
https://bugs.freedesktop.org/show_bug.cgi?id=90621
Trivial.
commit 10aacf5ae8f3e90e2f0967fbdcf96df93e346e20
Author: Eric Anholt <eric at anholt.net>
Date: Tue Apr 14 22:42:02 2015 -0700
vc4: Just stream out fallback IB contents.
The idea I had when I wrote the original shadow code was that you'd see a
set_index_buffer to the IB, then a bunch of draws out of it. What's
actually happening in openarena is that set_index_buffer occurs at every
draw, so we end up making a new shadow BO every time, and converting more
of the BO than is actually used in the draw.
While I could maybe come up with a better caching scheme, for now just
do the simple thing that doesn't result in a new shadow IB allocation
per draw.
Improves performance of isosurf in drawelements mode by 58.7967% +/-
3.86152% (n=8).
commit f8de6277bfa1a7db9a8c0f0baaa441276264a982
Author: Eric Anholt <eric at anholt.net>
Date: Wed May 27 16:20:28 2015 -0700
vc4: Don't try to put our dmabuf-exported BOs into the BO cache.
We'd sometimes try to reallocate something that X was using as a new
pipe_resource, and potentially conflict in our rendering. But even
worse, if we reallocated the BO as a shader, the kernel would reject
rendering using the shader.
commit b0edc19a521853371a63e9ffbc519424c8f82942
Author: Eric Anholt <eric at anholt.net>
Date: Wed May 27 16:01:00 2015 -0700
vc4: Don't forget to make our raster shadow textures non-raster.
Not sure what happened in my testing that made the previous shadow
code fix glxgears swapbuffering, but this also fixes lots of CopyArea
in X (like dragging xlogo around in metacity).
commit 41630c0653578db0c237296aaeec0a85a4e7f4ad
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Fri May 22 12:45:43 2015 +0200
vc4: make vc4_begin_query() return a boolean
I forgot to make the change in 96f164f6f047833091eb98a73aa80c31dc94f962.
This fixes a warning with GCC and probably an error with Clang.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit e2d84d99f5a66738e8f584bdfea66182f36fe46c
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Wed May 20 19:20:14 2015 -0700
i965: Emit 3DSTATE_MULTISAMPLE before WM_HZ_OP (gen8+)
Starting with GEN8, there is documentation that the multisample state command
must be emitted before the 3DSTATE_WM_HZ_OP command any time the multisample
count changes. The 3DSTATE_WM_HZ_OP packet gets emitted as a result of a
intel_hix_exec(), which is called upon a fast clear and/or a resolve. This can
happen before the state atoms are checked, and so the multisample state must be
put directly in the function.
v1:
- In v0, I was always emitting the command, but Ken came up with the condition to
determine whether or not the sample count actually changed.
- Ken's recommendation was to set brw->num_multisamples after emitting
3DSTATE_MULTISAMPLE. This doesn't work. I put my best guess as to why in the XXX
(it was causing 7 regressions on BDW).
v2:
Flag NEW_MULTISAMPLE state. As Ken found, in state upload we check for the
multisample change to determine whether or not to emit certain packets. Since
the hiz code doesn't actually care about the number of multisamples, set the
flag and let the later code take care of it.
Jenkins results:
http://otc-mesa-ci.jf.intel.com/view/dev/job/bwidawsk/136/
Fixes around 200 piglit tests on SKL. I'm somewhat surprised that it seems to
have no impact on BDW as the restriction is needed there as well.
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Neil Roberts <neil at linux.intel.com> (v0)
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org> (v2)
commit 147ffd48166d851341cadd12de98895f32ec25a2
Author: Vinson Lee <vlee at freedesktop.org>
Date: Tue May 26 22:18:28 2015 -0700
gallivm: Do not use NoFramePointerElim with LLVM 3.7.
TargetOptions::NoFramePointerElim was removed in llvm-3.7.0svn r238244
"Remove NoFramePointerElim and NoFramePointerElimOverride from
TargetOptions and remove ExecutionEngine's dependence on CodeGen. NFC."
Signed-off-by: Vinson Lee <vlee at freedesktop.org>
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
commit 70c6f2323e602d115b21db8f2bf212223fdef921
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu May 21 07:53:09 2015 -0700
i965: Remove _NEW_MULTISAMPLE dirty bit from 3DSTATE_PS_EXTRA.
BRW_NEW_NUM_SAMPLES is sufficient.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit bb18df008e31dd93a364289d003697587d7d78fa
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat May 23 14:27:40 2015 -0700
i965: Delete GS scratch space workaround warning.
This workaround is documented in the 3DSTATE_GS documentation. It
appears to only apply to early steppings of Broadwell and Skylake.
I don't think it ever affected production hardware, so at this point it
probably makes sense to delete it.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 40665362fd660a8d58f9edbdfec79a33d44b1534
Author: EdB <edb+mesa at sigluy.net>
Date: Mon May 11 17:45:08 2015 +0200
clover: Log build options when dumping clc source.
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 2b8c51834bcc34a70dec9b470a28c0ef972d6993
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue May 26 11:41:44 2015 -0700
glapi: Encapsulate nop table knowledge in new _mesa_new_nop_table function
Encapsulate the knowledge about how to build the nop table in a new
_mesa_new_nop_table function. This makes it easier for dispatch_sanity
to keep working now and in the future.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Tested-by: Mark Janes <mark.a.janes at intel.com>
Cc: 10.6 <mesa-stable at lists.freedesktop.org>
commit 8d813d14e1f5c690c6737c6cd6fc01937a7d4246
Author: Thomas Helland <thomashelland90 at gmail.com>
Date: Tue May 26 12:14:00 2015 -0600
docs: Fix some typos in the developer notes
Found when double-checking my review on Brian's series.
Signed-off-by: Thomas Helland <thomashelland90 at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit be71bbfaa2ad201b570b56847a13328fc359d0ee
Author: Brian Paul <brianp at vmware.com>
Date: Fri May 15 09:08:14 2015 -0600
mesa: do not use _glapi_new_nop_table() for DRI builds
Commit 4bdbb588a9d38 introduced new _glapi_new_nop_table() and
_glapi_set_nop_handler() functions in the glapi dispatcher (which
live in libGL.so). The calls to those functions from context.c
would be undefined (i.e. an ABI break) if the libGL used at runtime
was older.
For the time being, use the old single generic_nop() function for
non-Windows builds to avoid this problem. At some point in the future
it should be safe to remove this work-around. See comments for more
details.
v2: Incorporate feedback from Emil. Use _WIN32 instead of
GLX_DIRECT_RENDERING to control behavior, move comments.
Cc: 10.6 <mesa-stable at lists.freedesktop.org>
Reviewed-and-tested-by: Ian Romanick <ian.d.romanick at intel.com>
commit 2ab0ca36c155cc77e3d5c950270c70a24efee3d3
Author: Brian Paul <brianp at vmware.com>
Date: Tue May 26 11:30:22 2015 -0600
docs: add information about reviewing patches
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit c6184f84b7227e1548947e42bca3ff3ddb7e379c
Author: Brian Paul <brianp at vmware.com>
Date: Mon May 25 10:18:35 2015 -0600
docs: update the coding style information
This hasn't been updated in a long time and from recent discussion on
the mailing list, it's not always clear what's expected. Hopefully,
this will help a bit.
v2: document function brace placement, per Thomas Helland.
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
commit d959885b9109878acc427b9321e46d8c6d133d1a
Author: Brian Paul <brianp at vmware.com>
Date: Mon May 25 09:42:04 2015 -0600
docs: update documentation about patch formatting, testing, etc
v2: correctly escape < and > chars.
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
commit 98f2f47f7a1d893bb482d508a690c417c2453c6e
Author: Brian Paul <brianp at vmware.com>
Date: Mon May 25 09:13:09 2015 -0600
docs: reorganize devnotes.html file
Move "Adding Extensions" to the end. Add a simple table of contents
at the top.
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
commit eec904d29c0d996fb05f24771a2fdd33e152f519
Author: Brian Paul <brianp at vmware.com>
Date: Fri May 22 13:39:03 2015 -0700
xlib: fix X_GLXCreateContextAtrribs/Attribs typo
In case the glproto.h file isn't up to date, we provide the #define
for X_GLXCreateContextAttribsARB.
v2: fix other occurances, improve #ifndef test, per Jose.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit dce53a7d2453c0b2b69a345340455866e75f0a8d
Author: Brian Paul <brianp at vmware.com>
Date: Fri May 22 17:26:12 2015 -0700
mesa: add some comments in copyimage.c
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 0b76541ce0cc34020ef1057a17149cbf9cb3dbe1
Author: Brian Paul <brianp at vmware.com>
Date: Fri May 22 17:22:47 2015 -0700
mesa: move decls, add const qualifiers in copyimage.c
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 8369675a55ab300a84b3a82632042a33883ca255
Author: Brian Paul <brianp at vmware.com>
Date: Fri May 22 17:20:57 2015 -0700
mesa: code clean-ups in textureview.[ch]
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 3ddd1cf7d128018639de7e4c8bc17896233ebdb7
Author: Brian Paul <brianp at vmware.com>
Date: Fri May 22 16:42:21 2015 -0700
mesa: const qualify, return bool for _mesa_texture_view_compatible_format()
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 09eabf5be68b901999ef15733a22dfcb82dfec5f
Author: Brian Paul <brianp at vmware.com>
Date: Fri May 22 16:39:32 2015 -0700
mesa: add const qualifer on _mesa_is_compressed_format()
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit b787f48ed2a7e1855100afd943ae6b407abb401f
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Tue May 26 11:01:57 2015 +0100
glapi: Avoid argparse type argument for API XML input files.
argparse type is a nice type saver for simple data types, but it doesn't
look a good fit for the input XML file:
- Certain implementations of argparse (particularly python 2.7.3's)
invoke the type constructor for the default argument even when an
option is passed in the command line. Causing `No such file or
directory: 'gl_API.xml'` when the current dir is not
src/mapi/glapi/gen.
- The parser takes multiple arguments. This is currently worked around
using lambdas, but that unnecessarily complex and hard to read.
Furthermore it's odd to have a side-effect as heavy as parsing XML
happening deep inside the argument parsing.
https://bugs.freedesktop.org/show_bug.cgi?id=90600
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 224a77cc60cc0e7f8a14e35ebca6e42544af39b1
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Feb 22 15:38:21 2015 +0100
radeonsi: use a switch statement in si_delete_shader_selector
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 0c5a309cee868cd6e3870f439f560f5f32eb7c40
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Feb 22 15:21:59 2015 +0100
radeonsi: use a switch statement in si_shader_selector_key
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit fa7f606e89dc4447f07fec0b84d396a4ff25ee7e
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon May 18 14:56:34 2015 +0200
radeonsi: fix scratch buffer setup for geometry shaders
Cc: 10.6 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit f41517242aaad3cb67fb7f6c9a03dc34198ca500
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun May 10 18:03:47 2015 +0200
radeonsi: remove unused cases from si_shader_io_get_unique_index
These can't occur between VS and GS, because GS is only supported
in the core profile.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit af4b9c7c2e119d373f9684119b833a8b62cbb756
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon May 18 14:50:19 2015 +0200
radeonsi: don't count special outputs for the VS export count
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit e4339bc9886a26d75b924ad045c3ddd003f802c3
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat May 9 19:36:17 2015 +0200
radeonsi: add support for PIPE_CAP_TGSI_TEXCOORD
Without it, texcoords are mapped to GENERIC[0..7], PointCoord is mapped to
GENERIC[8], and user-defined varyings start from GENERIC[9]. Since texcoords
can only be used between VS and PS, and PointCoord is PS-only, it's silly to
always start from GENERIC[9] in all other shaders (such as LS, HS, ES, GS).
This adds support for TEXCOORD and PCOORD semantics. As a result, st/mesa
will use GENERIC[0] as a base for user-defined varyings, which should make
linking ES and GS as well as tessellation shaders at runtime easier.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 3d35027fdc383c2bd009f3690b2b160e3b39d58b
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon May 18 02:23:04 2015 +0200
tgsi/ureg: enable creating tessellation shaders with ureg_create_shader
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit c1266f28d6af7788e19634f0d36257e78d1139be
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon May 18 02:21:47 2015 +0200
tgsi/text: enable parsing tessellation shaders
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 0d84b6cf84971f3378bb95c85f7d39e0c6680b8f
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon May 18 13:52:30 2015 +0200
gallium: rename TGSI tessellation processor types to match pipe shader names
I forgot to do this when pushing the interface changes.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 92c31bb0dd8149d3e5db48b8dec62b242be80d28
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon May 18 12:34:44 2015 +0200
gallium: use const in set_tess_state
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 967825d053f71c5f5fc3ba31eabc0c6004fde4f1
Author: Koop Mast <kwm at rainbow-runner.nl>
Date: Tue May 26 10:24:40 2015 +0200
clover: Build fix for FreeBSD.
Cc: 10.6 10.5 <mesa-stable at lists.freedesktop.org>
commit 5ae6c7bfce5c9fb91ab6cef2ea74a39af091d5f6
Author: Neil Roberts <neil at linux.intel.com>
Date: Wed May 20 19:26:02 2015 +0100
i965/skl: Add a message header for the TXF_MCS instruction in vec4vs
When using SIMD4x2 on Skylake, the sampler instructions need a message
header to select the correct mode. This was added for most sample
instructions in 0ac4c2727 but the TXF_MCS instruction is emitted
separately and it was missed.
This fixes a bunch of Piglit tests which test texelFetch in a geometry
shader, for example:
spec/arb_texture_multisample/texelfetch/2-gs-sampler2dms
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 3ec18152858fd9aadb398d78d5ad2d2b938507c1
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon May 25 17:46:45 2015 -0400
nv30: falling back to draw path for edgeflag does no good
The problem is that the EDGEFLAG has to be toggled at vertex submission
time. This can be done from either the draw or the regular paths. Avoid
falling back to draw just because there's an edgeflag.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
commit 25be70462dbb7ee994e69ffccc3de94e4114e667
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat May 23 22:11:38 2015 -0400
nv30/draw: switch varying hookup logic to know about texcoords
Commit 8acaf862dfe switched things over to use TEXCOORD instead of
GENERIC, but did not update the nv30 swtnl draw paths. This teaches the
draw logic about TEXCOORD.
Among other things, this fixes a crash in demos/arbocclude when using
swtnl. Curiously enough, the point-sprite piglit works without this.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
commit c3d36a2e1a87a4aded662db7a5d320ee7ac3a8b5
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon May 25 21:14:13 2015 -0400
nv30/draw: allocate vertex buffers in gart
These are only used once per draw, so it makes sense to keep them in
GART. Also take this opportunity to modernize the buffer mapping API
usage.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Ben Skeggs <bskeggs at redhat.com>
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
commit fdad7dfbdae07b9273fc8f57e63258dbe542c9b5
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon May 25 21:12:46 2015 -0400
nv30/draw: only use the DMA1 object (GART) if the bo is not in VRAM
Instead of always having it in the data, let the bo placement decide it.
This fixes glxgears with swtnl forced on.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Ben Skeggs <bskeggs at redhat.com>
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
commit 3600439897c79d37c3c654546867ddfa0c420743
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon May 25 20:15:09 2015 -0400
nv30/draw: fix indexed draws with swtnl path and a resource index buffer
The map = assignment was missing.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
commit 5646f0f18a620292524eebcd77353ff3d3687eb2
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun May 17 17:56:44 2015 -0400
glsl: avoid leaking linked gl_shader when there's a late linker error
This makes piglit mixing-clip-distance-and-clip-vertex-disallowed have 0
definitely lost blocks with valgrind. (Same non-0 number of possibly
lost blocks though.)
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de>
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
commit 6a111e54d7578abee6bce4a75ce1399ed369ab5f
Author: Roland Scheidegger <sroland at vmware.com>
Date: Mon May 25 22:24:05 2015 +0200
llvmpipe: (trivial) add parantheses in (!x == y) expression
Apparently some compilers think we probably wanted to do !(x == y) instead
and issue a warning, so just shut it up... No functional change, obviously.
Cc: <mesa-stable at lists.freedesktop.org>
commit bb973723a5e1f27817b6be2c2fa4fb3ea28e733c
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun May 17 17:32:24 2015 -0400
st/mesa: don't leak glsl_to_tgsi object on link failure
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
commit 147816375d22a653176ab28ed650fa811ceea83f
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon May 25 14:06:01 2015 -0400
nv30/draw: draw expects constbuf size in bytes, not vec4 units
This fixes glxgears with NV30_SWTNL=1 forced on. Probably fixes a bunch
of other situations where we fall back to the swtnl path.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
commit 89585edf3c01c94b62d163adf0209568efa68568
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun May 24 11:56:21 2015 -0400
nv30/draw: avoid leaving stale pointers in draw state
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
commit cc3d2755577dab8c930f0bccff2756cb92aef8bc
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon May 25 09:27:08 2015 -0700
Fix an unused variable warning
Trivial. Deleted the 2 unneeded lines.
commit 843ff4ba2af0b19a377a3bf1c9ae7b2b1f2c0e4c
Author: Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de>
Date: Mon May 25 15:57:09 2015 +0200
docs: Mark ARB_cull_distance as in progress
Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
commit 3dec892d9b873f6c8a2a963a7646af90ada361bc
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Mon May 25 09:40:01 2015 +0200
docs: Mark ARB_shader_storage_buffer_object as in progress
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit 7518fc3c66e9b5703b987bccca7970a344deadfa
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat May 23 20:58:53 2015 -0400
nv30: fix clip plane uploads and enable changes
nv30_validate_clip depends on the rasterizer state. Also we should
upload all the new clip planes on change since next time the plane data
won't have changed, but the enables might.
This fixes fixed-clip-enables and vs-clip-vertex-enables shader tests.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de>
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
commit aba3392541f38f82e3ebde251fdcca78e90adbf3
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Mar 5 12:10:15 2015 -0500
nv30: avoid doing extra work on clear and hitting unexpected states
Clearing can happen at a time when various state objects are incoherent
and not ready for a draw. Some of the validation functions don't handle
this well, so only flush the framebuffer state. This has the advantage
of also not doing extra work.
This works around some crashes that can happen when clearing.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de>
commit 207ae2b0efcdb48a39fd91b05181c7e6d81e5002
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sun May 24 10:47:48 2015 +0100
docs: add news item and link release notes for mesa 10.5.6
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 81d5d78573f821fb0983523bbd698d6691c4bb34
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sun May 24 10:43:31 2015 +0100
docs: Add sha256sums for the 10.5.6 release
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit 8cb28bc49d7799d5accb1feb7e355ec48518e20b)
commit 3ab4556b84a944278dbddc21fba40b328a77c2e9
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat May 23 09:02:41 2015 +0100
Add release notes for the 10.5.6 release
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit b1cf9cfb1618f0b73e673745d3c8612aea61723d)
commit 9870ed05dd333a20662479b9b1e3a8db542924c4
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun May 24 02:23:16 2015 -0400
nv30: avoid leaking render state and draw shaders
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
commit 605ce36d7f4a90c4062d6940bea82ab483bbe3b2
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun May 24 01:31:11 2015 -0400
nv30: don't leak fragprog consts
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
commit fa7f9f123b70f313d3c073b52c9c16b4b8df28f8
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat May 23 01:57:41 2015 -0400
nv50/ir: avoid messing up arg1 of PFETCH
There can be scenarios where the "indirect" arg of a PFETCH becomes
known, and so the code will attempt to propagate it. Use this
opportunity to just fold it into the first argument, and prevent the
load propagation pass from touching PFETCH further.
This fixes gs-input-array-vec4-index-rd.shader_test and
vs-output-array-vec4-index-wr-before-gs.shader_test on nvc0 at least.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de>
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
commit f972b223c4cb4ec58a9451cbac5d120ac9deb336
Author: Grigori Goronzy <greg at chown.ath.cx>
Date: Tue May 19 09:28:30 2015 +0200
clover: try userptr for CL_MEM_USE_HOST_PTR
According to spec, CL_MEM_USE_HOST_PTR should directly use host memory,
if possible. This is just what userptr is for, so use it.
In case the memory cannot be mapped, a fallback similar to
CL_MEM_COPY_HOST_PTR is used.
v2: constify, drop unneeded cast
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 5c495e86388b55af067677e8608eb124a5d70d29
Author: Grigori Goronzy <greg at chown.ath.cx>
Date: Tue May 12 02:22:12 2015 +0200
clover: implement CL_MEM_ALLOC_HOST_PTR
This flag is typically used to request pinned host memory, to avoid
any copies between GPU and CPU.
This improves throughput with an older OpenCL app which I unfortunately
can't publish due to its licensing.
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit c922758685932e86d935972980df3be22d7b2fdf
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat May 23 19:07:48 2015 -0400
nv30: check nouveau_bo_map output of notify bo
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 921917c8d8e707dd854e7be05fba7a3e55bc71bf
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat May 23 17:35:42 2015 -0400
nvc0: a geometry shader can have up to 1024 vertices output
The 1024 is already reported everywhere, not sure where this 0x1ff came
from.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
commit 6ca67f62e885f0e42c0cef2db5c0ae837adfe646
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue May 19 17:35:29 2015 -0700
i965/fs: Fix implied_mrf_writes for scratch writes
We build the entire message in the generator so all the MRF writes are
implied.
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 58aed1031d40e62c9f41f7c512b3165dd5913d1e
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue May 19 16:25:02 2015 -0700
prog_to_nir: Use a variable for uniform data
Previously, the prog_to_nir pass was directly generating uniform load/store
intrinsics. This converts it to use a single giant "parameters" variable
and we now depend on lowering to get the uniform load/store intrinsics.
One advantage of this is that we now have one code-path after we do the
initial conversion into NIR.
No shader-db changes.
Signed-off-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit c783fd476c61fae41bddead4e47740e23d0cf2eb
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Sat May 23 18:50:25 2015 +0200
nv50: fix PIPE_QUERY_TIMESTAMP_DISJOINT, based on nvc0
PIPE_QUERY_TIMESTAMP_DISJOINT could not work because q->ready was always
set to FALSE. To fix this issue, add more different states for queries
according to nvc0.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 217301843aea0299ab245e260b20af7ad250e9d8
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri May 22 19:03:58 2015 -0400
nvc0/ir: LOAD's can't be used for shader inputs
We forgot to convert to VFETCH in case of indirect access. Fix that.
This avoids crashes on the new gs-input-array-vec4-index-rd and
vs-output-array-vec4-index-wr-before-gs but they still fail.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
commit 0bab3962f5f313ea829c95920c02f32afb23715d
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri May 22 19:02:41 2015 -0400
nv50/ir: guess that the constant offset is the starting slot of array
When we get something like IN[ADDR[0].x+5], we will now guess that we
should look at IN[5] for the "base" information.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
commit d1eea18a595a468dbc2267a8d14197a3b1a5a4b6
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri May 22 16:40:08 2015 -0400
nvc0/ir: set ftz when sources are floats, not just destinations
In the case of a compare, the destination might be a predicate, but we
still want to flush denorms.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
commit a85aba190dfab02ffccf744bad5ad10357394de0
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri May 8 23:46:53 2015 -0400
nv50/ir: allow OP_SET to merge with OP_SET_AND/etc as well as a neg
This covers the pattern where a KILL_IF is used, which triggers a
comparison of -x to 0. This can usually be folded into the comparison whose
result is being compared to 0, however it may, itself, have already been
combined with another comparison. That shouldn't impact the logic of
this pass however. With this and the & 1.0 change, code like
00000020: 001c0001 80081df4 set b32 $r0 lt f32 $r0 0x3e800000
00000028: 001c0000 201fc000 and b32 $r0 $r0 0x3f800000
00000030: 7f9c001e dd885c00 set $p0 0x1 lt f32 neg $r0 0x0
00000038: 0000003c 19800000 $p0 discard
becomes
00000020: 001c001d b5881df4 set $p0 0x1 lt f32 $r0 0x3e800000
00000028: 0000003c 19800000 $p0 discard
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit d2a474e8d4b03f10aec57c7f7740addad1e1ea9d
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun May 3 22:15:16 2015 -0400
nvc0/ir: optimize set & 1.0 to produce boolean-float sets
This has started to happen more now that the backend is producing
KILL_IF more often.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de>
commit e5ad19a46e87ed22943d7f6ad046f974fd5977e1
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri May 8 23:00:05 2015 -0400
nvc0/ir: allow iset to produce a boolean float
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 0ec6b8ea8ce0929ecacf6edc8db198b7b9604f18
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun May 3 18:38:52 2015 -0400
nvc0/ir: avoid jumping to a sched instruction
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 491adb61d25eef8afe2615e0fd842dda20b17004
Author: Brian Paul <brianp at vmware.com>
Date: Fri May 22 13:18:54 2015 -0700
glx: fix Scons build
Replace -h with --header-tag as was done for the Makefile build.
Reviewed-by: Dylan Baker <baker.dylan.c at gmail.com>
commit 3f823cc55a15bc0b54d09e2c3fb5944a645b09e4
Author: Dylan Baker <baker.dylan.c at gmail.com>
Date: Wed May 20 15:51:40 2015 -0700
glapi: glX_proto_size.py: use a main function
Signed-off-by: Dylan Baker <dylanx.c.baker at intel.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit 9ace0b542241c77ae82a0835ac8a09e2a7510eaf
Author: Dylan Baker <baker.dylan.c at gmail.com>
Date: Wed May 20 15:49:11 2015 -0700
glapi: glX_proto_size.py: use argparse instead of getopt
This is roughly equivalent to the original getopt, except that it
removes the '-h' short option, which argparse reserves for
auto-generated help messages. It does retain the long option specified
by the getopt version, and changes the makefile to use that.
Signed-off-by: Dylan Baker <dylanx.c.baker at intel.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit 1c7cc67778073fd802773390da55980702637547
Author: Dylan Baker <baker.dylan.c at gmail.com>
Date: Wed May 20 15:20:09 2015 -0700
glapi: glX_proto_recv.py: Use a main function
Signed-off-by: Dylan Baker <dylanx.c.baker at intel.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit d986cb7c70db3b512f6ee0bbc95ba2565606c222
Author: Dylan Baker <baker.dylan.c at gmail.com>
Date: Wed May 20 15:19:28 2015 -0700
glapi: glX_proto_recv.py: use argparse instead of getopt
Signed-off-by: Dylan Baker <dylanx.c.baker at intel.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit 67d3ec0bb8f6a8c918b371ed03ef21814899f07d
Author: Dylan Baker <baker.dylan.c at gmail.com>
Date: Wed May 20 11:49:40 2015 -0700
glapy: gl_genexec.py: use a main function
Signed-off-by: Dylan Baker <dylanx.c.baker at intel.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit 79c4e595bce563d6075fed176c2256bf2e7e99a5
Author: Dylan Baker <baker.dylan.c at gmail.com>
Date: Wed May 20 11:49:10 2015 -0700
glapi: gl_genexec.py: use argparse instead of getopt
Signed-off-by: Dylan Baker <dylanx.c.baker at intel.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit 9097a4a103f2f7abf5af3e1056467c21051405ca
Author: Dylan Baker <baker.dylan.c at gmail.com>
Date: Tue Feb 10 15:20:57 2015 -0800
glapi: glX_proto_send.py: use a main function.
Signed-off-by: Dylan Baker <dylanx.c.baker at intel.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit 9eed4e6232b9ca936ad8e87aa21f97ffb81981ce
Author: Dylan Baker <baker.dylan.c at gmail.com>
Date: Tue Feb 10 15:20:18 2015 -0800
glapi: glX_proto_send.py: use argparse instead of getopt
Signed-off-by: Dylan Baker <dylanx.c.baker at intel.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit dddac8cac3ab883b6beeb4af9ca27bb2f3b4ebec
Author: Dylan Baker <baker.dylan.c at gmail.com>
Date: Fri Feb 13 16:41:03 2015 -0800
glapi: glX_server_table.py: use argparse instead of getopt
Signed-off-by: Dylan Baker <dylanx.c.baker at intel.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit 952bd305c6862113c60d3b62402fc5a32dbb65ca
Author: Dylan Baker <baker.dylan.c at gmail.com>
Date: Fri Feb 13 15:54:17 2015 -0800
glapi: gl_SPARC_asm.py: use main function
Signed-off-by: Dylan Baker <dylanx.c.baker at intel.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit 86c9fb526ed9b0a68eb7bb29d661b7f61415d3f0
Author: Dylan Baker <baker.dylan.c at gmail.com>
Date: Fri Feb 13 15:49:16 2015 -0800
glapi: gl_SPARC_asm.py use argparse instead of getopt
Also drop -m switch, which only accepted a single value or raised an
error, and was unused in the makefile.
Signed-off-by: Dylan Baker <dylanx.c.baker at intel.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit f2e78bd697e168c4f8cb1fd7f939713f8319eb78
Author: Dylan Baker <baker.dylan.c at gmail.com>
Date: Thu Feb 12 14:05:46 2015 -0800
glapi: gl_x86-64_asm.py: Use a main function
Signed-off-by: Dylan Baker <dylanx.c.baker at intel.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit 2e3da443f16e479997cdc5a2a137b9823f8617df
Author: Dylan Baker <baker.dylan.c at gmail.com>
Date: Thu Feb 12 14:04:03 2015 -0800
glapi: gl_x86_64_asm.py: Use argparse instead of getopt
Also removes the redundant -m argument, which could only be set to
'generic', or it would raise an exception. This option wasn't used in
the makefile.
Signed-off-by: Dylan Baker <dylanx.c.baker at intel.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit 48924567994c43e734f97a4b9150e87fa72b6c11
Author: Dylan Baker <baker.dylan.c at gmail.com>
Date: Wed Feb 11 18:05:35 2015 -0800
glapi: gl_x86_asm.py: use a main function
Signed-off-by: Dylan Baker <dylanx.c.baker at intel.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit fc96122fb6450dd9b8c90dc5efb6bb0ab235fe0e
Author: Dylan Baker <baker.dylan.c at gmail.com>
Date: Wed Feb 11 18:04:22 2015 -0800
glapi: gl_x86_asm.py: use argparse instead of getopt
Signed-off-by: Dylan Baker <dylanx.c.baker at intel.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit 5998d32f09777b9bbcd422dfbab9261f1b0e07b8
Author: Dylan Baker <baker.dylan.c at gmail.com>
Date: Tue Feb 10 14:33:12 2015 -0800
glapi: gl_gentable.py: use a main function
Signed-off-by: Dylan Baker <dylanx.c.baker at intel.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit d36fa4472ea408eb2a1ecadc44268bce4bab92ea
Author: Dylan Baker <baker.dylan.c at gmail.com>
Date: Tue Feb 10 14:32:40 2015 -0800
glapi: gl_gentable.py: Replace getopt with argparse
Signed-off-by: Dylan Baker <dylanx.c.baker at intel.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit 3317cea0488075f291744ebc4eaa48fc73d293de
Author: Dylan Baker <baker.dylan.c at gmail.com>
Date: Tue Feb 10 10:57:08 2015 -0800
glapi: gl_apitemp.py: Use a main function
Signed-off-by: Dylan Baker <dylanx.c.baker at intel.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit 24ec03bd05153bf0c8b1063d4e6a68b073e57840
Author: Dylan Baker <baker.dylan.c at gmail.com>
Date: Tue Feb 10 10:55:45 2015 -0800
glapi: gl_apitemp.py: Convert to argparse instead of getopt
Signed-off-by: Dylan Baker <dylanx.c.baker at intel.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit 6c4dcef6dc704156115b8d3ad19c3020663c7ffc
Author: Dylan Baker <baker.dylan.c at gmail.com>
Date: Mon Feb 9 14:19:23 2015 -0800
glapi: gl_enums.py: use main() function for if __name__ == "__main__"
Signed-off-by: Dylan Baker <dylanx.c.baker at intel.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit fd5f1dd6c72e34a8f0522c4706cd5eec624e80cf
Author: Dylan Baker <baker.dylan.c at gmail.com>
Date: Mon Feb 9 14:18:30 2015 -0800
glapi: gl_enums.py: use argparse instead of getopt.
Signed-off-by: Dylan Baker <dylanx.c.baker at intel.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit e51530ba1665af7120be852653bbff930fa1ca33
Author: Dylan Baker <dylanx.c.baker at intel.com>
Date: Mon Nov 24 14:14:12 2014 -0800
glapi: gl_procs.py: Use argparse rather than getopt
Signed-off-by: Dylan Baker <dylanx.c.baker at intel.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit 28ecdd6be7e6f58eabfc9aa0461fb8db7dd8133d
Author: Dylan Baker <dylanx.c.baker at intel.com>
Date: Thu Nov 20 17:07:48 2014 -0800
glapi: gl_procs.py: Fix a few low hanging style things
Shuts up analysis tools to make them return actual problems.
Signed-off-by: Dylan Baker <dylanx.c.baker at intel.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit 622fee43c8aa339e6b642fc8a90c759dcf28c6e7
Author: Dylan Baker <dylanx.c.baker at intel.com>
Date: Thu Nov 20 14:07:15 2014 -0800
glapi: remap_helper.py: use argparse instead of optparse
Make the code simpler, cleaner, and easier to work with.
Signed-off-by: Dylan Baker <dylanx.c.baker at intel.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit bdae3bc1ffb14b705a0c6fef3e90380dfd0eed97
Author: Dylan Baker <dylanx.c.baker at intel.com>
Date: Thu Nov 20 14:01:40 2014 -0800
glapi: remap_helper.py: Fix some low hanging style issues
This makes the tools shut up about a bunch of problems, making them more
useful for catching actual problems.
Signed-off-by: Dylan Baker <dylanx.c.baker at intel.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit cf718cc964f86dc49c1fc9ed5e39aa5bd87ad931
Author: Dylan Baker <dylanx.c.baker at intel.com>
Date: Wed Nov 19 13:36:35 2014 -0800
glapi: gl_table.py: replace getopt with argparse.
This results in slightly less code, but code that is much more readable.
It has the advantage of putting everything together in one place, all of
the code is self documenting, help messages are auto-generated, choices
are automatically enforced, and the syntax is much less C like, taking
advantage of python features and idioms.
Signed-off-by: Dylan Baker <dylanx.c.baker at intel.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit b6298c7a7143eafea3c1be6e98af1d0239fdf5b7
Author: Dylan Baker <dylanx.c.baker at intel.com>
Date: Wed Nov 19 13:17:48 2014 -0800
glapi: gl_table.py: Fix some low hanging style issues
Making the tools shut up about worthless errors so you can see real ones
is very useful
Signed-off-by: Dylan Baker <dylanx.c.baker at intel.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit a1c070c1a7c6b37a36f591bd8caf4619e4457eae
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon May 18 15:23:28 2015 -0700
i965/disasm: Skip swizzle disassembly when using 3-src repctrl.
... since it's always .x, and also always print the subreg offset when
using repctrl.
commit 5614bcc416cf2ff1d816d52198e644565ca23bcd
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon May 18 14:59:13 2015 -0700
nir: Remove sRGB colorspace conversion round-trip.
Some shaders in Civilization V and Beyond Earth do
pow(pow(x, 2.2), 0.454545)
which is converting to and from sRGB colorspace.
A more general rule that replaces pow(pow(a, b), c) with pow(a, b * c)
actually regresses two shaders in Sun Temple in which the result of the
inner pow is used twice, once by another pow and once by another
instruction. Also, since 2.2 * 0.454545 isn't exactly one, the more
general pattern would have still left us with a pow, and I'm 2.2 *
0.454545 percent sure that's not what they want.
instructions in affected programs: 934 -> 886 (-5.14%)
helped: 16
commit a21d23e191696ca130fd63617b8d177055b73dda
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Thu May 21 20:14:44 2015 +0200
nv50: fix PIPELINE_STATISTICS with HUD, based on nvc0
Tested on NVA8. No regression for ARB_pipeline_statistics piglit tests.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 867fd2b5f586085c137af264e3eb640094e88526
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Thu May 21 20:06:19 2015 +0200
nv50: fix 64-bit queries with HUD, based on nvc0
A sequence number is written for 32-bits queries to make sure they are
ready, but not for 64-bits queries. Instead, we have to use a fence in
order to fix the HUD because it doesn't wait until the result is ready.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 6921ea42a17c715c4b5b2d0092f9b9f4df42b10c
Author: Christian König <christian.koenig at amd.com>
Date: Thu Mar 26 10:00:09 2015 +0100
radeon/vce: adapt new firmware interface changes
v2: make this also compatible with original released firmware
v3 (chk): switch to original idea of separate files for fw versions
Signed-off-by: Leo Liu <leo.liu at amd.com>
Signed-off-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com> (v2)
commit 2b40c306d238e2e738d8901e10f351a109b02687
Author: Christian König <christian.koenig at amd.com>
Date: Thu Mar 26 09:52:37 2015 +0100
radeon/vce: move CPB handling function into common code
They are not firmware version dependent.
Signed-off-by: Christian König <christian.koenig at amd.com>
commit 7c1a00174b2bec102030b19b6094ebcab23fe04d
Author: Dave Airlie <airlied at redhat.com>
Date: Thu May 21 11:23:06 2015 +1000
u_math: uses assert, include assert.h
this fixes a build problem found on RHEL s390.
not sure what configure options caused it, I couldn't get it on
x86 here.
Reviewed-by: Brian Paul <brianp at vmware.com>
Cc: "10.6" mesa-stable at lists.freedesktop.org
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit d67515b7be1ebd9482970ac1867ee4e9bbbf96d5
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Thu Apr 30 20:45:54 2015 +1000
glsl: remove element_type() helper
We now have is_array() and without_array() that make the
code much clearer and remove the need for this.
For all remaining calls to this we already knew that
the type was an array so returning a null wasn't adding any value.
v2: use without_array() in _mesa_ast_array_index_to_hir() and don't use
without_array() in lower_clip_distance_visitor() as we want to make sure the
array is 2D.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 51ccdb63467b1e848db025670f126eccb051f8f2
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue May 19 07:38:40 2015 -0700
glsl: Use AM_V_GEN/AM_V_at in NIR rules.
commit 6cdb29d52fc51e3d904b50bb7003c9fa38bb7896
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed May 20 04:00:16 2015 -0400
freedreno/a3xx: set .zw of sprite coords to .01
Fixes non-determinism in bin/point-sprite rendering, and the stars on
the intro screen to neverball.
Cc: "10.6" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 3e7bc6728520b469ed53a2588ead28287f8b88f0
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Apr 27 23:47:40 2015 -0400
freedreno/ir3: fix immediate usage in tgsi tex fe
get_immediate will return a const reference, the requested immediate
isn't necessarily in the x slot. Make sure to use the swizzle.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org
commit 36438f0db6c7c696df73ced12684f4df9d2b47e5
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed May 20 21:51:52 2015 +0100
targets/osmesa: drop the -module tag from LDFLAGS
Gallium equivalent of commit 06ff751f97f(darwin: Fix install name of
libOSMesa)
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 06ff751f97fbeb62a23936cd8f9c54733920d082
Author: Jeremy Huddleston Sequoia <jeremyhu at apple.com>
Date: Wed Feb 11 02:32:33 2015 -0800
darwin: Fix install name of libOSMesa
Passing -module to glibtool causes the resulting library to be called
libSomething.so rather than libSomething.dylib on darwin.
Regardless if libOSMesa is a library or a module, it has been used as
the former for quite some time. Update the build to reflect that and
resolve the naming issue.
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Jeremy Huddleston Sequoia <jeremyhu at apple.com>
[Emil Velikov: Tweak the commit message.]
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 31cd2d75dc3844e40143f649fe383de17c152a13
Author: Alan Coopersmith <alan.coopersmith at oracle.com>
Date: Fri May 15 19:05:45 2015 -0700
swrast: Build fix for Solaris
Fixes regression from commit 5b2d3480f57168d50ad24cf0b8c9244414bd3701
Cc: "10.5 10.6" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Alan Coopersmith <alan.coopersmith at oracle.com>
Reviewed-by: Jeremy Huddleston Sequoia <jeremyhu at apple.com>
commit 2126c68e5cba79709e228f12eb3062a9be634a0e
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue May 19 16:57:43 2015 -0700
nir: Get rid of the array elements parameter on load/store intrinsics
Previously, we used intrinsic->const_index[1] to represent "the number of
array elements to load" for load/store intrinsics. However, this set to 1
by every pass that ever creates a load/store intrinsic. Also, while it
might make some sense for registers, it makes no sense whatsoever in SSA.
On top of that, the i965 backend was the only backend to ever support it;
freedreno and vc4 just assert that it's always 1. Let's just delete it.
Signed-off-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Rob Clark <robclark at freedesktop.org>
commit e1c4e8aaaafddd0e04cf2a16e28ef8f1e09d8b44
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun May 17 16:35:14 2015 +0200
gallium: remove TGSI_SAT_MINUS_PLUS_ONE
It's a remnant of some old NV extension. Unused.
I also have a patch that removes predicates if anyone is interested.
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit e4201bb618f02a279fda59a1c528d7218e6900a5
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon May 18 11:26:10 2015 +0200
cso: add context cleanup code from st/mesa
This fixes a crash in nouveau which can't handle
set_constant_buffer(PIPE_SHADER_TESS_*).
Cc: 10.6 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 4ee69a97bb0af0cc216539c48b246ea2abf8f208
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Wed May 13 12:18:31 2015 +0200
mesa/main: validate name syntax for array variables only
From ARB_program_interface_query:
"Note that if an interface enumerates a single active resource list
entry for an array variable (e.g., "a[0]"), a <name> identifying
any array element other than the first (e.g., "a[1]") is not
considered to match."
It doesn't apply to arrays of interface blocks but just to array
variables.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 1b052906763a36465e384366b875235b962ac143
Author: Dave Airlie <airlied at redhat.com>
Date: Wed May 20 12:36:14 2015 +1000
GL3.txt: update softpipe ARB_gpu_shader5 status
texture gather and it already supported the new instructions.
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 55a7b5165d40b831fd303079f8f80962d195d6ee
Author: Dave Airlie <airlied at redhat.com>
Date: Tue May 19 16:29:39 2015 +1000
softpipe: start adding gather support (v2)
This adds both ARB_texture_gather and the enhanced gather
for ARB_gpu_shader5.
This passes all the piglit tests, it relies on the GLSL
lowering pass to make textureGatherOffsets work.
v2: use inline to get gather component (Brian)
fix function name, add asserts (Brian)
Reviewed-by: Brian Paul <brianp at vmware.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 0108eae2911d2fc8f2ae0ef0fc6fc503fbfc600d
Author: Dave Airlie <airlied at redhat.com>
Date: Tue May 19 16:22:35 2015 +1000
softpipe: use arrays to make gather easier
This is a prep change for gather, and it makes more sense
to use an array in these cases.
Reviewed-by: Brian Paul <brianp at vmware.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit a6861ecfc91973ba97989def97dd571e0e096888
Author: Dave Airlie <airlied at redhat.com>
Date: Tue May 19 16:16:07 2015 +1000
tgsi: handle TG4 opcode in tgsi exec
This just adds a new modifier interface for drivers to implement.
Reviewed-by: Brian Paul <brianp at vmware.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 3f5c67d6510fe0210079ddecc0d30227a6cc4111
Author: Dave Airlie <airlied at redhat.com>
Date: Tue May 19 16:12:45 2015 +1000
softpipe: add textureOffset support.
This was an oversight when GLSL1.30 was enabled, I think my
misunderstanding.
This fixes a bunch of tex-miplevel-selection tests under softpipe,
and is required for textureGather support.
I'm not sure this won't make sampling slowering, but its softpipe,
correctness first and all that.
Reviewed-by: Brian Paul <brianp at vmware.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 8bec83a30761d52088fa5cd2301b469b7aacf755
Author: Dave Airlie <airlied at redhat.com>
Date: Tue May 19 15:39:47 2015 +1000
softpipe: move control into a filter args struct
more stuff for offsets and gather will go in here later.
Reviewed-by: Brian Paul <brianp at vmware.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 99e583120cde8820aae94eb0f8beb723509398fc
Author: Dave Airlie <airlied at redhat.com>
Date: Tue May 19 15:31:06 2015 +1000
softpipe: move some image filter parameters into a struct
This moves some of the image filter args into a struct,
and passes that instead, this is prep work for adding texture
gather support which needs new arguments.
review: make filter args const.
Reviewed-by: Brian Paul <brianp at vmware.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit b9b516248e0441a5aa06bdeb58525b4ef8dd0001
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Tue May 19 11:59:50 2015 +0100
Post-branch version bump to 10.7.0-devel, add release notes template
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 0c9e0b7a6c79a32702140c91146c7267f1658cc4
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Tue May 19 12:51:19 2015 +0100
glapi: track GL_ARB_program_interface_query.xml
Add the file to the API_XML list, otherwise there will be no knowledge
by the build that it should be included in the tarball.
Thus the (scons) build will fail.
Fixes: b297fc27aa9(glapi: add GL_ARB_program_interface_query skeleton)
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 0148c0ae6a6795b5decc7ed7385be37a37e18a1f
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Tue May 19 12:15:02 2015 +0100
i965: add brw_cs.h to the sources list
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 7af2601a078047ed79c9fb81b6c4f98f22a5d049
Author: Alexander von Gluck IV <kallisti5 at unixzen.com>
Date: Sun May 17 08:50:43 2015 -0500
mesa/driver/haiku: Drop Mesa swrast renderer
This just created extra upkeep and the push to move extern
C's into mesa code would mean a large number of extern's
in core Mesa driver interfaces. The Haiku Gallium renderers
are mostly insulated via the C-based Haiku state tracker.
As any future hardware support in Haiku will be gallium
based, lets just drop swrast.
Haiku has a Mesa 7.12 fork for gcc2 that uses swrast.
This commit fixes the last of the Haiku build issues.
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 42298b05d1ebd8b17b89411723ae13295643e496
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu May 7 15:07:49 2015 -0700
i965: Use NIR by default for vertex shaders on GEN8+
GLSL IR vs. NIR shader-db results for SIMD8 vertex shaders on Broadwell:
total instructions in shared programs: 2742062 -> 2681339 (-2.21%)
instructions in affected programs: 1514770 -> 1454047 (-4.01%)
helped: 5813
HURT: 1120
The gained programs are ARB vertext programs that were previously going
through the vec4 backend. Now that we have prog_to_nir, ARB vertex
programs can go through the scalar backend so they show up as "gained" in
the shader-db results.
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit e6f912f07e729649fb9e9e9a458482925552f778
Author: Rob Clark <robclark at freedesktop.org>
Date: Fri May 8 15:56:23 2015 -0400
freedreno: fence fix
A fence can outlive the ctx, so we shouldn't deref the ctx to get at the
screen. We need some updates in libdrm_freedreno API to completely
handle fences properly, but this is at least an improvement.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 8427ad91252d22db6dbd45ae37c6d5a18de8fc68
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Thu Apr 16 19:24:36 2015 -0700
i965: Add gen8 blend state
OLD:
0x00007340: 0x00800000: BLEND:
0x00007344: 0x84202100: BLEND:
NEW:
0x00007340: 0x00800000: BLEND: Alpha blend/test
0x00007344: 0x0000000b84202100: BLEND_ENTRY00:
Color Buffer Blend factor ONE,ONE,ONE,ONE (src,dst,src alpha, dst alpha)
function ADD,ADD (color, alpha), Disables: ----
0x0000734c: 0x0000000b84202100: BLEND_ENTRY01:
Color Buffer Blend factor ONE,ONE,ONE,ONE (src,dst,src alpha, dst alpha)
function ADD,ADD (color, alpha), Disables: ----
0x00007354: 0x0000000b84202100: BLEND_ENTRY02:
Color Buffer Blend factor ONE,ONE,ONE,ONE (src,dst,src alpha, dst alpha)
function ADD,ADD (color, alpha), Disables: ----
0x0000735c: 0x0000000b84202100: BLEND_ENTRY03:
Color Buffer Blend factor ONE,ONE,ONE,ONE (src,dst,src alpha, dst alpha)
function ADD,ADD (color, alpha), Disables: ----
0x00007364: 0x0000000b84202100: BLEND_ENTRY04:
Color Buffer Blend factor ONE,ONE,ONE,ONE (src,dst,src alpha, dst alpha)
function ADD,ADD (color, alpha), Disables: ----
0x0000736c: 0x0000000b84202100: BLEND_ENTRY05:
Color Buffer Blend factor ONE,ONE,ONE,ONE (src,dst,src alpha, dst alpha)
function ADD,ADD (color, alpha), Disables: ----
0x00007374: 0x0000000b84202100: BLEND_ENTRY06:
Color Buffer Blend factor ONE,ONE,ONE,ONE (src,dst,src alpha, dst alpha)
function ADD,ADD (color, alpha), Disables: ----
0x0000737c: 0x0000000b84202100: BLEND_ENTRY07:
Color Buffer Blend factor ONE,ONE,ONE,ONE (src,dst,src alpha, dst alpha)
function ADD,ADD (color, alpha), Disables: ----
v2: Line length fixes, and const usage (Topi)
Safer initialization of name string (Topi)
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit fa284d6f2f9a929497714c795d09e56547bccf44
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Fri May 15 21:18:12 2015 -0700
i965: Add renderbuffer surface indexes to debug
This patch is optional in the series. It does make the output much cleaner, but
there is some risk.
Sample output (v3):
0x00007e80: 0x231d7000: SURF000: 2D R8G8B8A8_UNORM VALIGN4 HALIGN4 Y-tiled
0x00007e84: 0x05000000: SURF000: MOCS: 0x5 Base MIP: 0.0 (0 mips) Surface QPitch: 0
0x00007e88: 0x009f009f: SURF000: 160x160 [AUX_NONE]
0x00007e8c: 0x0000027f: SURF000: 1 slices (depth), pitch: 640
0x00007e90: 0x00000000: SURF000: min array element: 0, array extent 1, MULTISAMPLE_1
0x00007e94: 0x00000000: SURF000: x,y offset: 0,0, min LOD: 0
0x00007e98: 0x00000000: SURF000: AUX pitch: 0 qpitch: 0
0x00007e9c: 0x09770000: SURF000: Clear color: R(0)G(0)B(0)A(0)
0x00007ea0: 0x00001000: SURF000: 0x00001000
0x00007ea4: 0x00000000: SURF000: 0x00000000
0x00007ea8: 0x00000000: SURF000: 0x00000000
0x00007eac: 0x00000000: SURF000: 0x00000000
0x00007e40: 0x234df000: SURF001: 2D R11G11B10_FLOAT VALIGN4 HALIGN16 Y-tiled
0x00007e44: 0x09000000: SURF001: MOCS: 0x9 Base MIP: 0.0 (0 mips) Surface QPitch: 0
0x00007e48: 0x009f009f: SURF001: 160x160 [AUX_CCS_D (Uncompressed, MULTISAMPLE_COUNT=1)]
0x00007e4c: 0x0000027f: SURF001: 1 slices (depth), pitch: 640
0x00007e50: 0x00000000: SURF001: min array element: 0, array extent 1, MULTISAMPLE_1
0x00007e54: 0x00000000: SURF001: x,y offset: 0,0, min LOD: 0
0x00007e58: 0x00000001: SURF001: AUX pitch: 0 qpitch: 0
0x00007e5c: 0x09770000: SURF001: Clear color: R(0)G(0)B(0)A(0)
0x00007e60: 0x0002b000: SURF001: 0x0002b000
0x00007e64: 0x00000000: SURF001: 0x00000000
0x00007e68: 0x0002a000: SURF001: 0x0002a000
0x00007e6c: 0x00000000: SURF001: 0x00000000
v2: Rebased on Topi's recent series which changed around some of the gen8
surface setup code.
v3: Use ralloc_asprintf instead of asprintf to be more friendly to non-GNU
platforms.
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
commit c14bb072301f68b68dcc9fff3e49210cb0819912
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Fri May 15 21:25:36 2015 -0700
i965: Add Gen9 surface state decoding
Gen9 surface state is very similar to the previous generation. The important
changes here are aux mode, and the way clear colors work.
NOTE: There are some things intentionally left out of this decoding.
v2: Redo the string for the aux buffer type to address compressed variants.
v3: Use the shift for compression enable (instead of compression mode) (Topi)
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 313abbb8ca1f41b28c58571ca8217332d52283c7
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Thu Apr 16 13:46:57 2015 -0700
i965: Add gen8 surface state debug info
AFAICT, none of the old data was wrong (the gen7 decoder), but it wa smissing a
bunch of stuff.
Adds a tick (') to denote the beginning of the surface state for easier reading.
This will be replaced later with some better, but more risky code.
OLD:
0x00007980: 0x23016000: SURF: 2D BRW_SURFACEFORMAT_B8G8R8A8_UNORM
0x00007984: 0x18000000: SURF: offset
0x00007988: 0x00ff00ff: SURF: 256x256 size, 0 mips, 1 slices
0x0000798c: 0x000003ff: SURF: pitch 1024, tiled
0x00007990: 0x00000000: SURF: min array element 0, array extent 1
0x00007994: 0x00000000: SURF: mip base 0
0x00007998: 0x00000000: SURF: x,y offset: 0,0
0x0000799c: 0x09770000: SURF:
0x00007940: 0x231d7000: SURF: 2D BRW_SURFACEFORMAT_R8G8B8A8_UNORM
0x00007944: 0x78000000: SURF: offset
0x00007948: 0x001f001f: SURF: 32x32 size, 0 mips, 1 slices
0x0000794c: 0x0000007f: SURF: pitch 128, tiled
0x00007950: 0x00000000: SURF: min array element 0, array extent 1
0x00007954: 0x00000000: SURF: mip base 0
0x00007958: 0x00000000: SURF: x,y offset: 0,0
0x0000795c: 0x09770000: SURF:
NEW (v1):
0x00007980: 0x23016000: SURF': 2D B8G8R8A8_UNORM VALIGN4 HALIGN4 X-tiled
0x00007984: 0x18000000: SURF: MOCS: 0x18 Base MIP: 0.0 (0 mips) Surface QPitch: 0
0x00007988: 0x00ff00ff: SURF: 256x256 [AUX_NONE]
0x0000798c: 0x000003ff: SURF: 1 slices (depth), pitch: 1024
0x00007990: 0x00000000: SURF: min array element: 0, array extent 1, MULTISAMPLE_1
0x00007994: 0x00000000: SURF: x,y offset: 0,0, min LOD: 0
0x00007998: 0x00000000: SURF: AUX pitch: 0 qpitch: 0
0x0000799c: 0x09770000: SURF: Clear color: ----
0x00007940: 0x231d7000: SURF': 2D R8G8B8A8_UNORM VALIGN4 HALIGN4 Y-tiled
0x00007944: 0x78000000: SURF: MOCS: 0x78 Base MIP: 0 (0 mips) Surface QPitch: ff0000
0x00007948: 0x001f001f: SURF: 32x32 [AUX_NONE]
0x0000794c: 0x0000007f: SURF: 1 slices (depth), pitch: 128
0x00007950: 0x00000000: SURF: min array element: 0, array extent 1, MULTISAMPLE_1
0x00007954: 0x00000000: SURF: x,y offset: 0,0, min LOD: 0
0x00007958: 0x00000000: SURF: AUX pitch: 0 qpitch: 0
0x0000795c: 0x09770000: SURF: Clear color: ----
0x00007920: 0x00007980: BIND0: surface state address
0x00007924: 0x00007940: BIND1: surface state address
v2: Style cleanups (Matt)
Fix aux mode dword 7->6 (Topi)
Use exp2 instead of pow (Matt)
Add dwords 8-12 to the dump
v3: Needed to update the surface format name getter for the change in the first
patch in the series
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Cc: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 7f0c7a5f90d084b1fb1e059367856436a19dca5a
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Thu Apr 16 17:13:00 2015 -0700
i965: Add gen7+ sampler state to batch debug
OLD:
0x00007e00: 0x10000000: WM SAMP0: filtering
0x00007e04: 0x000d0000: WM SAMP0: wrapping, lod
0x00007e08: 0x00000000: WM SAMP0: default color pointer
0x00007e0c: 0x00000090: WM SAMP0: chroma key, aniso
NEW:
0x00007e00: 0x10000000: SAMPLER_STATE 0: Disabled = no, Base Mip: 0.0, Mip/Mag/Min Filter: NONE/NEAREST/NEAREST, LOD Bias: 0.0
0x00007e04: 0x000d0000: SAMPLER_STATE 0: Min LOD: 0.0, Max LOD: 13.0
0x00007e08: 0x00000000: SAMPLER_STATE 0: Border Color
0x00007e0c: 0x00000090: SAMPLER_STATE 0: Max aniso: RATIO 2:1, TC[XYZ] Address Control: CLAMP|CLAMP|WRAP
v2: Move GET_BITS macro to here (with paren protection) Ben/Topi
Add const to the sampler pointer (Topi)
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 1fa0789a9452627ce9845b2fb334c995584f1ffa
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Thu Apr 16 14:50:33 2015 -0700
i965: Add viewport extents (gen8) to batch decode
0x00007da0: 0xc1da740e: SF_CLIP VP: guardband xmin = -27.306667
0x00007da4: 0x41da740e: SF_CLIP VP: guardband xmax = 27.306667
0x00007da4: 0x41da740e: SF_CLIP VP: guardband ymin = -23.405714
0x00007da8: 0xc1bb3ee7: SF_CLIP VP: guardband ymax = 23.405714
0x00007db0: 0x00000000: SF_CLIP VP: Min extents: 0.00x0.00
0x00007db8: 0x00000000: SF_CLIP VP: Max extents: 299.00x349.00
While here, fix the wrong offsets for the guardband (I didn't check if it used
to be valid on GEN4).
v2: Remove leftover GET_BITS which belongs later in the series. (Topi)
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit e45a292556df95280bd06ca78db901e39c0660e1
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Thu Apr 16 09:16:19 2015 -0700
i965: Add all surface types to the batch decode
It's true that not all surfaces apply for every gen, but for the most part this
is what we want. (The unfortunate case is when we use a valid surface, but not
for the specific GEN).
This was automated with a vim macro.
v2: Shortened common forms such as R8G8B8A8->RGBA8. Note that this makes some of
the sample output in subsequent commits slightly incorrect.
v3: Use the name from the table (Ken). This requires declaring the surface
format array as extern, and declaring the struct in the .h file.
v4: Move the struct back and create a helper function to obtain the name (Ken)
Get rid of the now useless helper in the state_dump.c
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com> (v3)
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 421e396bb7bcc029ad457dd79064df7aeadd8e48
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Wed Apr 29 22:20:35 2015 -0400
i965: Add string for surface format to table
Recommended-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit f7df169ba13d22338e9276839a7e9629ca0a6b4f
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed May 13 18:34:03 2015 -0700
i965/fs: Implement integer multiply without mul/mach.
Ivybridge and Baytrail can't use mach with 2Q quarter control, so just
do it without the accumulator. Stupid accumulator.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 0a9e3a0160bbda8ea23aeb049f9c3dfc0478bbf5
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu May 14 15:58:20 2015 -0700
i965/fs: Rework compression control selection.
The next commit uses an add(16) with a UW destination with a stride of
2, which needs compression control since it's writing two registers. The
old code would have failed to set compression control correctly.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 4ec09c77471e39e6ff81c99f1edde2e1713a7f24
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue May 12 15:51:44 2015 -0700
i965/fs: Support integer multiplication in SIMD16 on Haswell.
Ivybridge (and presumably Baytrail) have a bug that prevents this from
working.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 0592ee457dbddd9483e4294097e5d7f2e1c39308
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue May 12 15:51:05 2015 -0700
i965/fs: Add set_sechalf() method.
Used in the next commit.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 81deefc45ba7b7d3b2b5e7ccf9e1680df6e31e3a
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu May 14 22:23:22 2015 -0700
i965/fs: Unrestrict constant propagation into integer multiply.
Gen8+'s MUL instruction doesn't ignore the high 16-bits of one source
like on earlier platforms, so we can constant propagate into it without
worry. Integer multiplies (not into the accumulator, which is done for
imul_high) are lowered in lower_integer_multiplication(), so it's safe
there as well.
On Broadwell, fragment shaders only:
total instructions in shared programs: 4377769 -> 4377451 (-0.01%)
instructions in affected programs: 48064 -> 47746 (-0.66%)
helped: 156
On Broadwell, vertex shaders only:
total instructions in shared programs: 2858885 -> 2856313 (-0.09%)
instructions in affected programs: 26380 -> 23808 (-9.75%)
helped: 134
On Broadwell, vertex shaders only (with INTEL_USE_NIR=1):
total instructions in shared programs: 2911688 -> 2865984 (-1.57%)
instructions in affected programs: 1421715 -> 1376011 (-3.21%)
helped: 6186
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 1e4e17fbd9296cc5064aabdb351a894d10190cb6
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon May 11 09:29:56 2015 -0700
i965/fs: Lower integer multiplication after optimizations.
32-bit x 32-bit integer multiplication requires multiple instructions
until Broadwell. This patch just lets us treat the MUL instruction in
the FS backend like it operates on Broadwell, and after optimizations
we lower it into a sequence of instructions on older platforms.
Doing this will allow us to some extra optimization on integer
multiplies.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit ae405d429ff62e279cb4bb84d29581d4f7467b52
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon May 18 12:57:31 2015 -0400
gk110/ir: switch to gk104-style sched codes rather than all-in-one
Matches change to envydis/envyas tools.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 9f4eaba36f002f4ea86bc11fd3d0f8dce485b9d8
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Mon May 11 13:24:20 2015 +0300
glsl: add stage references for UBO uniforms
Patch marks uniforms inside UBO properly referenced by stages.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90397
commit 845ad2667ab2466752f06ea30bdb9c837116c308
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Tue Feb 10 16:40:48 2015 +0100
i965: Fix textureSize for Lod > 0 with non-mipmap filters
Currently, when the MinFilter is GL_LINEAR or GL_NEAREST we hide the
actual miplevel count from the hardware (and we avoid re-creating
the miptree structure with all the levels), since we don't expect
levels other than the base level to be needed. Unfortunately,
GLSL's textureSize() function is an exception to this rule. This
function takes a lod parameter that we need to use to return the
size of the appropriate miplevel (if it exists). The spec only
requires that the miplevel exists, so even if the sampler is
configured with a linear or nearest MinFilter, as far as the user
has uploaded miplevels for the texture, textureSize() should return
the appropriate sizes.
This patch fixes this by exposing the actual miplevel count for all
sampling engine textures while keeping the original implementation
for render targets (for render targets textures we do not provide
the miplevel count but the actual LOD we are wrting to, so we
want to make sure that we make this the base level).
Fixes 28 dEQP tests in the following category:
dEQP-GLES3.functional.shaders.texture_functions.texturesize.*
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit 5a55f681f6208122cd4921b283cffd54ea335128
Author: Fredrik Höglund <fredrik at kde.org>
Date: Sat May 16 19:43:39 2015 +0200
mesa: Check the lookup_framebuffer return value in NamedFramebufferRenderbuffer
Found by Coverity.
Reported-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit d7081828cc62df7efbc23ca1037a42d69dab94a7
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Jul 13 14:26:05 2014 -0400
tgsi/dump: fix declaration printing of tessellation inputs/outputs
mareko: only output second dimension for non-patch semantics
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit dfc3bced2ceebd1e3abacd07acd83f932b45c639
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Jul 21 21:18:14 2014 -0400
tgsi/ureg: allow ureg_dst to have dimension indices
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit ec67d73a73f74011b33f6ab59bed4c88ebaa7497
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Mar 19 23:31:41 2015 +0100
tgsi/ureg: use correct limit for max input count
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit 93c940736f03b3eaf53d3a5703963b87a506747e
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Jul 12 20:06:03 2014 -0400
tgsi/sanity: set implicit in/out array sizes based on patch sizes
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit 5b45cbe7e2bcf1709ab1fcc50dfc877b3e43bcae
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Jul 12 21:37:45 2014 -0400
tgsi/scan: allow scanning tessellation shaders
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit 2420ee497a14ca36ea05b275ea74e5c3a4432a59
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Oct 14 11:06:48 2014 +0200
gallium: disable tessellation shaders for meta ops
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit ed1b273ffcab0e2089899f3be7e31b2bc49f7ef3
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Sep 23 15:54:02 2014 +0200
gallium/cso: set NULL shaders at context destruction
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit 2a7da1bddbee2be09ae6c2276a04c658807720b0
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Mar 2 16:32:25 2015 +0100
gallium/cso: add support for tessellation shaders
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit 267ad27ab64956dff857b8584c4862da2e7dfc78
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Sep 23 18:40:27 2014 +0200
gallium/u_blitter: disable tessellation for all operations
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit 66630290dfd90c095ed9268ad02f6a8930a8043f
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Mar 19 23:26:54 2015 +0100
gallium/util: print vertices_per_patch in util_dump_draw_info
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit 369aca1b4a5dd9998fad4b660a8665a77ce4a02a
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Jan 11 20:37:37 2015 +0100
trace: implement new tessellation functions
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit 6b262061203a6be8fe76402aa86e838254f937b8
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Jul 20 11:36:49 2014 -0400
gallium: add set_tess_state to configure default tessellation parameters
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit 4dbfe6b6274760412cf4ea8e6a910874ca12d998
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Jul 21 18:43:53 2014 -0400
gallium: add vertices_per_patch to draw info
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit 9e1ba1d6895ff1a80fe676e153799695653cfb2a
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Jul 19 10:09:28 2014 -0400
gallium: add tessellation shader properties
v2: Marek: rename tess spacing definitions
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit 18bce2f19437f9a6b86e33324cb559cd54470d51
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Jul 11 22:09:38 2014 -0400
gallium: add interfaces for controlling tess program state
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit 7ffc1fb928268f8493e88d45e9a006208d05f0f6
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Mar 19 23:27:10 2015 +0100
gallium: bump shader input and output limits
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit 018aa279532f5c9d07c3c73604e33b49569eb4e6
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Jul 19 09:39:18 2014 -0400
gallium: add new semantics for tessellation
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit 88c4f5d0a54baf7711cf030e3c1d5eca63560716
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Jul 19 09:27:46 2014 -0400
gallium: add new PATCHES primitive type
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit 398b0b3e36603188ada03f2df5e2c81b3e8b62a2
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Jul 19 09:26:09 2014 -0400
gallium: add tessellation shader types
v2: Marek: rename shader types
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit 35c28103b02598bb5f7b4888384b02d31ee371b5
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue May 12 19:46:44 2015 -0700
glapi: Remove offset from the DTD
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit a75910071e33184211773a1f019b53b23f8762eb
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue May 12 19:43:33 2015 -0700
glapi: Whitespace clean up after the previous commit
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit f507d33d4fd0834529b77c2e24271904a14247ac
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue May 12 19:15:09 2015 -0700
glapi: Remove all offset tags from the XML
Changes generated by:
cd src/mapi/glapi/gen
for i in *.xml; do
cat $i |\
sed 's/[[:space:]]*offset="[^"]*">/>/' |\
sed 's/[[:space:]]*offset="[^"]*"[[:space:]]*$//' |\
sed 's/[[:space:]]*offset="[^"]*"[[:space:]]*/ /' > x
mv x $i
done
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 2b419e0db92248ca768d2d26aa2f8276c70356e2
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Fri May 8 19:33:13 2015 -0700
glapi: Use the offsets from static_data.py instead of from the XML
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Dylan Baker <baker.dylan.c at gmail.com>
commit 0fe7eab8d9a8c984ceb7aa333715799840ea7ec0
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue May 12 18:09:13 2015 -0700
glapi: Add a list of functions that are not used but still need dispatch slots
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit d2ee60cd5286695f738117c87c24b04b08340c6b
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue May 12 17:27:26 2015 -0700
glapi: Remove static dispatch for functions that didn't exist in NVIDIA
Comparing the output of
nm -D libGL.so.349.16 | grep ' T gl[^X]' | sed 's/.* T //'
between Catalyst NVIDIA 349.16 and this commit, the only change is a bunch
of functions that NVIDIA exports that Mesa does not.
If a function is not statically exported by either of the major binary
drivers on Linux, there is almost zero chance that any application
statically links with it.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 4adfc6ed31983bcf52e106469f22bb121a56532b
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue May 12 16:56:37 2015 -0700
glapi: Remove static dispatch for functions that didn't exist in fglrx
Comparing the output of
nm -D arch/x86_64/usr/X11R6/lib64/fglrx/fglrx-libGL.so.1.2 |\
grep ' T gl[^X]' | sed 's/.* T //'
between Catalyst 14.6 Beta and this commit, the only change is a bunch
of functions that AMD exports that Mesa does not and some OpenGL ES
1.1 functions that Mesa exported but AMD does not.
The OpenGL ES 1.1 functions (e.g., glAlphaFuncx) are added by extensions
in desktop. Our infrastructure doesn't allow us to statically export a
function in one lib and not in another. The GLES1 conformance tests
expect to be able to link with these functions, so we have to export
them.
If a function is not statically exported by either of the major binary
drivers on Linux, there is almost zero chance that any application
statically links with it.
As a side note... I find it odd that AMD exports glTextureBarrierNV but
not glTextureBarrier.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 90a1a4e2345fe25517f5189cca1188162992f39b
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue May 12 16:01:17 2015 -0700
glapi: Remove static dispatch for functions that didn't exist in 10.3
Comparing the output of
nm libGL.so | grep ' T gl[^X]' | sed 's/.* T //'
between 10.3.7 and this commit, the only change is the removal of
glFramebufferTextureFaceARB. This function was removed a couple commits
previously.
glClipControl was, at the time 10.3 shipped, a very new function. It
was added by GL_ARB_clip_control. That extension was ratified by the
Khronos Board of Promoters on August 7, 2014. It's less than a year
old, and I don't think it's is likely that there are many applications
using that extension... much less statically linking with the function.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit c1ad2bac71fab362e397219d7274af842ef83878
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue May 12 15:47:41 2015 -0700
glapi: Remove static dispatch for functions that didn't exist in 10.4
Comparing the output of
nm libGL.so | grep ' T gl[^X]' | sed 's/.* T //'
between 10.4.7 and this commit, the only change is the removal of
glFramebufferTextureFaceARB. This function was removed a couple commits
previously.
None of these functions are particuarly new. If applications were not
statically linking them with 10.4.7, there's approximately zero chance
they will for 10.6.
Almost all of these functions are for GL_ARB_direct_state_access.
Since the whole DSA API wasn't statically exported (and the extension
wasn't enabled!), I think there's exactly zero chance anyone linked
against these symbols.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 832d43bbb6e5e04d71dd3d6e2de94a1c38b3485f
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue May 12 15:24:03 2015 -0700
glapi: Remove static dispatch for functions that didn't exist in 10.5
Comparing the output of
nm libGL.so | grep ' T gl[^X]' | sed 's/.* T //'
between 10.5.5 and this commit, the only change is the removal of
glFramebufferTextureFaceARB. This function was removed a couple commits
previously.
None of these functions are particuarly new. If applications were not
statically linking them with 10.5.5, there's approximately zero chance
they will for 10.6.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit ea54b3ea1adb19b55d6aa55f9afaa0eba3f4e865
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue May 12 17:17:11 2015 -0700
glapi: Remove static_dispatch from the DTD
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 7a22e78704427bb34280cf2c6f3774c2d830bebb
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue May 12 16:43:15 2015 -0700
glapi: Whitespace clean up after the previous commit
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Dylan Baker <baker.dylan.c at gmail.com>
commit 44e67398cc5b7aed6f78807e485f600e9eb834bb
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue May 12 16:27:12 2015 -0700
glapi: Remove all static_dispatch tags from the XML
Changes generated by:
cd src/mapi/glapi/gen
for i in *.xml; do
cat $i |\
sed 's/[[:space:]]*static_dispatch="[^"]*">/>/' |\
sed 's/[[:space:]]*static_dispatch="[^"]*"[[:space:]]*$//' |\
sed 's/[[:space:]]*static_dispatch="[^"]*"[[:space:]]*/ /' > x
mv x $i
done
Comparing the output of
nm libGL.so | grep ' T gl[^X]' | sed 's/.* T //'
before and after this commit showed no differences.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Dylan Baker <baker.dylan.c at gmail.com>
commit d9be1db4b69a04f58a951351051ef9798d55da98
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue May 12 15:11:09 2015 -0700
glapi: Store list of functions with static dispatch in a separate table
The set of functions with static dispatch is (supposed to be) defined by
the Linux OpenGL ABI. We export quite a few more functions than that
for historical reasons. However, this list should never grow.
This table is used instead of the static_dispatch tag in the XML to
generate the static dispatch functions. I used
nm libGL.so | grep ' T gl[^X]' | sed 's/.* T //'
before and after the change. diff showed no differences.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Dylan Baker <baker.dylan.c at gmail.com>
commit d649fcf727bffa11a5426ebcf38f51f478664b17
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Fri May 8 18:50:11 2015 -0700
glapi: Store static dispatch offsets in a separate table
Since the set of functions with static will never change, there is no
reason to store it in the XML. It's just one of those fields that
confuses people adding new functions.
This is split out from the rest of the series so that in-code assertions
can be used to verify that the data in the Python code matches the XML.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Dylan Baker <baker.dylan.c at gmail.com>
commit 5aaabd7630ca6fd72a3333687249574e6fcbe663
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue May 12 12:24:04 2015 -0700
mesa: Remove all vestiges of glFramebufferTextureFaceARB
Mesa does not (and probably never will) support GL_ARB_geometry_shader4,
so this function will never exist. Having a function that is
exec="skip" and offset="assign" is just weird.
There are still a couple 'exec="skip" offset="assign"' functions
remaining. These remain because we either support GLX protocol for them
(glSampleMaskSGIS and glSamplePatternSGIS) or older DRI drivers still
need them in the dispatch table (glResizeBuffersMESA). The SGIS
functions can be removed later.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 0784bb01b5e42db7d7241e9baa793f647ef5be52
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue May 12 11:37:42 2015 -0700
glapi: Mark a couple functions "ignore" for GLX
Without this the next patch will try to put these functions in the
dispatch table in indirect_init.c.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit b3059bb7c53d33764b96b76971b3ff98675198c1
Author: Fredrik Höglund <fredrik at kde.org>
Date: Fri May 15 19:30:38 2015 +0200
st/mesa: Flush the bitmap cache in st_BlitFramebuffer
With DSA we can no longer rely on this being done in st_validate_state
in response to the framebuffer bindings having changed.
This fixes the ext_framebuffer_multisample-bitmap piglit test.
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit d43aed9646972c4aca44f47d1b445bd8e67024d7
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Fri May 15 11:55:46 2015 -0700
i965: Fix FS unit tests
Commit 3687d75 changed the fs_visitor constructors, but it didn't update
all the users. As a result, 'make check' fails.
I added the explicit cast to the gl_program* parameter to make it more
clear which NULL was which.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at Whitecape.org>
commit 7de484871dae1643cbecf346066968f61684f06f
Author: Alexander von Gluck IV <kallisti5 at unixzen.com>
Date: Thu May 14 17:30:35 2015 -0500
target/haiku-softpipe: Move api init into st code
We also reduce the amount of need-to-know information about st_api
to require one less extern "C" in st_manager.h
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 9b5da7f06a4052b1298e4684d992a319fb4153ba
Author: Alexander von Gluck IV <kallisti5 at unixzen.com>
Date: Thu May 14 17:29:00 2015 -0500
st/hgl: Move st_api creation to st and extern "C" it
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 73aef2d1d8a0fe417df1ab4a35029be74891ee37
Author: Alexander von Gluck IV <kallisti5 at unixzen.com>
Date: Thu May 14 17:27:14 2015 -0500
winsys/hgl: Add needed extern "C" to hgl winsys
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 624b38add99c21e2deb2029b157e92c3f0e7cdd4
Author: Alexander von Gluck IV <kallisti5 at unixzen.com>
Date: Thu May 14 17:20:17 2015 -0500
gallium/drivers: Add extern "C" wrappers to public entry
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 40a8b2f92a8aef25199324046114023c4ed3d772
Author: Alexander von Gluck IV <kallisti5 at unixzen.com>
Date: Thu May 14 17:19:44 2015 -0500
gallium/aux: Add needed extern "C" wrappers
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 3687d752e51829b4723c9abb07ae56d2bbcda570
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Mar 11 22:41:49 2015 -0700
i965/fs: Combine the fs_visitor constructors.
For scalar GS support, we either need to add a fourth constructor which
takes the GS structures, or combine the existing two and pass the shader
stage.
Given that they're not significantly different, I opted for the latter.
v2: Remove more stuff from the .h file (Jason and Jordan).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 0c4eef6a2cad72571efb15a5fdca2726f0540d07
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu May 14 18:50:22 2015 +0000
egl: remove remaining EGL_MESA_copy_context skeleton
With earlier commit (7a58262e58d egl: Remove skeleton implementation of
EGL_MESA_screen_surface) we've removed the skeleton implementation of
eglCopyContextMESA(). Just like EGL_MESA_screen_surface this extension
was never implemented in mesa.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Adam Jackson <ajax at redhat.com>
commit 448e01b2918c76dfff8abfbd56a606fdff8c356c
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Tue May 12 00:30:16 2015 +0100
egl/main: fix EGL_KHR_get_all_proc_addresses
The extension requires that the address of the core functions should be
available via eglGetProcAddress. Currently the list is guarded by
_EGL_GET_CORE_ADDRESSES, which was only set for the scons (windows)
build.
Unconditionally enable it for all the builds (automake, android and
haiku) considering that the extension is not platform specific and is
always enabled.
v2: Drop the _EGL_GET_CORE_ADDRESSES macro altogether.
Cc: mesa-stable at lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit ffc94e32a38b3948fe4ae2717a3f55802eb8aae8
Author: Marc-André Lureau <marcandre.lureau at gmail.com>
Date: Mon May 11 23:43:49 2015 +0100
egl: more define fixes for EGL_MESA_image_dma_buf_export
s/EGL_MESA_dma_buf_image_export/EGL_MESA_image_dma_buf_export as defined by the spec
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit e3cc5ad49d2f3f08c29d0b64d1c0c52560789d93
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon May 11 23:43:48 2015 +0100
egl/main: expose only core EGL functions statically
The EGL 1.3, 1.4 and 1.5 spec (as quoted below) explicitly mentions that
providing static symbols for functions provided by EGL extensions is not
portable. Considering that relatively recently we've seen a non-mesa
desktop EGL implementation, the fact that we opt for such behaviour has
gone unnoticed.
From the EGL 1.5 specification:
For functions that are queryable with eglGetProcAddress,
implementations may choose to also export those functions
statically from the object libraries implementing those
functions. However, portable clients cannot rely on this
behavior.
To encourage devs against writing such non-portable code, let's hide the
symbols similar to the official binary driver from NVIDIA.
v2: Quote the EGL 1.5 spec, as suggested by Chad.
Cc: Brian Paul <brianp at vmware.com>
Cc: Chad Versace <chad.versace at intel.com>
Cc: Daniel Kurtz <djkurtz at chromium.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit f9bf9133ccc3764dc38f6359a26004e12b888af3
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon May 11 23:43:47 2015 +0100
egl: fix the EGL_MESA_image_dma_buf_export header declarations
Similar to other EGL extensions - guard the function prototypes by
EGL_EGLEXT_PROTOTYPES as the libEGL library does (should) not provide
the symbols statically.
Instead users should call eglGetProcAddress, which returns the function
pointer. The latter of which was missing the type declaration (typedef).
Cc: Dave Airlie <airlied at redhat.com>
Cc: Marc-André Lureau <marcandre.lureau at gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit 97909881234dc32fdbe2baa889997af540c4464e
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon May 11 23:43:46 2015 +0100
egl/main: Update README.txt
The driver search/load is not done at eglGetDisplay (or eglOpenDisplay
as the readme called it) time, but during eglInitialize().
Drop _eglMain (available only for external drivers) reference. Mention
we use function(s), specific to the built-in driver(s).
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit 1fac38ee3238d5e4429f4a7250e160bc9db2c9f4
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon May 11 23:43:45 2015 +0100
egl/main: cleanup function prototypes
Cleanup the function propotypes which were part of the previous EGL
drivers.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit 209360bbb91bb10346ebc509db3d8173ea32f6b1
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon May 11 23:43:44 2015 +0100
egl/main: drop support for external egl drivers
The only user (egl_gallium) is not longer around.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit 4925c35660b777ae6b33a1f87a2f74f3436c7c41
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed May 13 14:36:03 2015 -0400
freedreno: fix bug in tile/slot calculation
This was causing corruption with hw binning on a306. Unlikely that it
is a306 specific, but rather the smaller gmem size resulted in different
tile configuration which was triggering the bug at certain resolutions.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Cc: "10.4" and "10.5" and "10.6" <mesa-stable at lists.freedesktop.org>
commit fcc7d6323bbea489219225f467d59192d538e95f
Author: Rob Clark <robclark at freedesktop.org>
Date: Tue May 12 14:46:50 2015 -0400
freedreno: enable a306
Whitelist adreno 306 (as found in msm8916/apq8016). Works pretty much
out of the box, although the smaller GMEM size requires more tiles to
fit 1920x1080, so bump up the max # of tiles as well.
Since it is just whitelist + trivial change, it makes sense to land on
all the active release branches.
Note that a305c ends up with gpu-id "306", hence a306 ends up with
gpu-id of "307". Apparently that is what happens when you let the
marketing dept name things.
Cc: "10.4" and "10.5" and "10.6" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 0fbf49ce574ca645c68fdbb24d35c61fdd64921b
Author: Alexander von Gluck IV <kallisti5 at unixzen.com>
Date: Wed May 13 17:14:10 2015 -0500
egl/haiku: Drop extern "C". No longer needed
Reviewed-â by: Brian Paul <brianp at vmware.com>
commit 8362068c1b28eb2d3e334abc980c4711957d61fd
Author: Alexander von Gluck IV <kallisti5 at unixzen.com>
Date: Wed May 13 17:13:37 2015 -0500
egl: Add needed extern "C" for C++ access
* Haiku's egl driver is C++ due to the interface natively being C++
Reviewed-â by: Brian Paul <brianp at vmware.com>
commit 175cbb447ae85b93b8b0244f345064763131481f
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Tue May 12 17:13:15 2015 +0200
nvc0: remove unused nv50_tsc_wrap_mode() function
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit ac1ac94b38d051b2413ea8f58b16891f1a55757d
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Tue May 12 17:13:14 2015 +0200
nv50/ir: silence compiler warnings about mismatched tags
These warnings have been detected by Clang 3.6.
codegen/nv50_ir_from_tgsi.cpp:1319:10: warning: struct 'Source' was
previously declared as a class [-Wmismatched-tags] const struct tgsi::Source *code;
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 70651b7041c9d90f4fb6c693c4ebb643a50dd9d0
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Tue May 12 17:13:13 2015 +0200
nv50/ir: remove unused private field cycle to SchedDataCalculator
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 7469f2fd2305fac1444dbbef5752958afd53e66d
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Tue May 12 17:35:17 2015 +0200
nv30: remove unused nvfx_fp_memcpy() function and comment nv40_fp_bra()
The nv40_fp_bra() function in the same file is also unused but this is
the only place where the nv30/nv40 isa is documented.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 48c84a36dd04774489ab655a583ecb9266476856
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Mon May 11 21:36:16 2015 +0200
nvc0: do not expose MP counters for nvf0 (GK110+)
This fixes a crash when trying to monitor MP counters because compute
support is not implemented for nvf0.
Reported-by: Ilia Mirkin <imirkin at alum.mit.edu>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit b9cb7c19806e8ec33a626c289788876499cd8a27
Author: Fredrik Höglund <fredrik at kde.org>
Date: Thu May 7 20:29:46 2015 +0200
docs/relnotes: Mark off ARB_direct_state_access for 10.6
v2: Make it clear that ARB_direct_state_access is only available on
drivers that support GL 2.0+
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
Reviewed-by: Adam Jackson <ajax at redhat.com>
commit d9109cc2111a765f09fbf54072b77528e35c156d
Author: Fredrik Höglund <fredrik at kde.org>
Date: Thu May 7 20:29:21 2015 +0200
docs: Update the ARB_direct_state_access status
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
Reviewed-by: Adam Jackson <ajax at redhat.com>
commit 357bf80caade9e0be20dcc88ec38884e34abc986
Author: Fredrik Höglund <fredrik at kde.org>
Date: Sun May 10 21:06:52 2015 +0200
st/mesa: Enable ARB_direct_state_access
Assume that all drivers that advertise support for NPOT textures
are able to support GL 2.0.
v2: Add a comment.
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
Reviewed-by: Adam Jackson <ajax at redhat.com>
commit a57feba0a35de35728269aeb26b039e4f2393d69
Author: Fredrik Höglund <fredrik at kde.org>
Date: Sun May 10 21:05:11 2015 +0200
i965: Enable ARB_direct_state_access
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
Reviewed-by: Adam Jackson <ajax at redhat.com>
commit 121030eed8fc41789d2f4f7517bbc0dd6199667b
Author: Fredrik Höglund <fredrik at kde.org>
Date: Sun May 10 21:04:22 2015 +0200
i915: Enable ARB_direct_state_access
This extension requires OpenGL 2.0, so enable it on gen3 and later.
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
Reviewed-by: Adam Jackson <ajax at redhat.com>
commit d3368e0c9e27ced6059eb2ecdf2aa999a00e90b0
Author: Fredrik Höglund <fredrik at kde.org>
Date: Sun May 10 20:57:29 2015 +0200
mesa: Add ARB_direct_state_access checks in query object functions
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
Reviewed-by: Adam Jackson <ajax at redhat.com>
commit bebf3c6ab314bde05ac5a3b4d3e63fd36243c58e
Author: Fredrik Höglund <fredrik at kde.org>
Date: Sun May 10 20:56:18 2015 +0200
mesa: Add ARB_direct_state_access checks in program pipeline functions
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
Reviewed-by: Adam Jackson <ajax at redhat.com>
commit 9e7149c8986348bf9567f049444783ef52775f4e
Author: Fredrik Höglund <fredrik at kde.org>
Date: Sun May 10 20:55:31 2015 +0200
mesa: Add ARB_direct_state_access checks in sampler object functions
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
Reviewed-by: Adam Jackson <ajax at redhat.com>
commit 36b05793372b86b914d9b95d0188f5f387e01d68
Author: Fredrik Höglund <fredrik at kde.org>
Date: Sun May 10 20:54:18 2015 +0200
mesa: Add ARB_direct_state_access checks in VAO functions
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
Reviewed-by: Adam Jackson <ajax at redhat.com>
commit 8940957238e8584ce27295791cee4cc3d6f7cf1e
Author: Fredrik Höglund <fredrik at kde.org>
Date: Sun May 10 20:52:49 2015 +0200
mesa: Add ARB_direct_state_access checks in texture functions
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
Reviewed-by: Adam Jackson <ajax at redhat.com>
commit cb49940766b581c6656473d89c221653c69fa0f9
Author: Fredrik Höglund <fredrik at kde.org>
Date: Sun May 10 20:49:15 2015 +0200
mesa: Add ARB_direct_state_access checks in renderbuffer functions
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
Reviewed-by: Adam Jackson <ajax at redhat.com>
commit 6ad0b7e07a0445e9e0f368e079c4f7b8a6757bb3
Author: Fredrik Höglund <fredrik at kde.org>
Date: Sun May 10 20:48:11 2015 +0200
mesa: Add ARB_direct_state_access checks in FBO functions
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
Reviewed-by: Adam Jackson <ajax at redhat.com>
commit 339ed0984d4f54fca91235a1df2ce3a850f6123f
Author: Fredrik Höglund <fredrik at kde.org>
Date: Sun May 10 20:46:36 2015 +0200
mesa: Add ARB_direct_state_access checks in buffer object functions
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
Reviewed-by: Adam Jackson <ajax at redhat.com>
commit 7d212765a470972f4712e42caf6406b257220369
Author: Fredrik Höglund <fredrik at kde.org>
Date: Sun May 10 20:44:07 2015 +0200
mesa: Add ARB_direct_state_access checks in XFB functions
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
Reviewed-by: Adam Jackson <ajax at redhat.com>
commit 03420eac0c53280beae5f72783e52950fd1e3fba
Author: Fredrik Höglund <fredrik at kde.org>
Date: Wed Apr 29 19:44:06 2015 +0200
mesa: Make GL_TEXTURE_CUBE_MAP valid in FramebufferTextureLayer
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
Reviewed-by: Adam Jackson <ajax at redhat.com>
commit 30dcaaec356cc117d7227c6680620cd50ff534e7
Author: Fredrik Höglund <fredrik at kde.org>
Date: Sun May 10 20:34:03 2015 +0200
mesa: Add an extension flag for ARB_direct_state_access
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
Reviewed-by: Adam Jackson <ajax at redhat.com>
commit 9de7a81626304dae5ced4e202a820e353f8fc1e9
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Mon Feb 9 14:08:00 2015 -0800
main: Add entry point for NamedFramebufferDrawBuffers.
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
commit 68c6964b376df7ef2248fab83e0f8abc6df56d47
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Mon Feb 9 13:33:13 2015 -0800
main: Refactor DrawBuffers.
This could have added a new DD table entry for DrawBuffers that takes an
arbitrary draw buffer, but, after looking at the existing DD functions,
Kenneth Graunke recommended that we just skip calling the DD functions in the
case of ARB_direct_state_access. The DD implementations for DrawBuffer(s)
have limited functionality, especially with respect to
ARB_direct_state_access.
[Fredrik: Call the driver function when fb is the bound draw buffer]
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
commit 1f0a5f32d328e54483dd623ad09bd3f6b119f7a6
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Fri Feb 6 15:36:52 2015 -0800
main: Add entry point for NamedFramebufferReadBuffer.
[Fredrik: Fix the name of the buf parameter in the XML file]
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
commit 7518c6b5b2ae8b2a6e931d4be1d5976d553983a0
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Fri Feb 6 15:23:05 2015 -0800
main: Refactor _mesa_ReadBuffer.
This could have added a new DD table entry for ReadBuffer that takes an
arbitrary read buffer, but, after looking at the existing DD functions,
Kenneth Graunke recommended that we just skip calling the DD functions in the
case of ARB_direct_state_access. The DD implementations for ReadBuffer
have limited functionality, especially with respect to
ARB_direct_state_access.
[Fredrik: Call the driver function when fb is the bound read buffer]
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
commit 642fb71277b6e4c5d57ad7a7d6f2d5aae9b746ef
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Fri Feb 6 14:44:43 2015 -0800
main: Add entry point for NamedFramebufferDrawBuffer.
[Fredrik: Fix the name of the buf parameter in the XML file]
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
commit 2f32e4847d154a9d16869cf03ce66f719d37ec4a
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Fri Feb 6 10:57:57 2015 -0800
main: Refactor _mesa_DrawBuffer.
This could have added a new DD table entry for DrawBuffer that takes an
arbitrary draw buffer, but, after looking at the existing DD functions,
Kenneth Graunke recommended that we just skip calling the DD functions in the
case of ARB_direct_state_access. The DD implementations for DrawBuffer(s)
have limited functionality, especially with respect to
ARB_direct_state_access.
[Fredrik: Call the driver function when fb is the bound draw buffer]
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
commit f8fd8dfee8647a3bd2215fce49626953ecdbdbec
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Fri Feb 6 10:34:24 2015 -0800
main: Refactor _mesa_drawbuffers.
[Fredrik: Whitespace fix]
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
commit 9f1db78a83feebefb9e1ef889b3b6b0532482c14
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Thu Feb 5 16:38:11 2015 -0800
main: Add stubs for [Get]NamedFramebufferParameteri[v].
The ARB_direct_state_access specification says (as of 2015.02.05):
"Interactions with OpenGL 4.3 or ARB_framebuffer_no_attachments
If neither OpenGL 4.3 nor ARB_framebuffer_no_attachments are supported,
ignore the support for NamedFramebufferParameteri and
GetNamedFramebufferParameteriv."
This commit adds stubs for these entry points.
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
commit a0329c7b40de3db22d22c74793a7c268e8904e53
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Thu Feb 5 13:43:12 2015 -0800
main: Fake entry point for glClearNamedFramebufferfi.
Mesa's ClearBuffer framework is very complicated and thoroughly married to the
object binding model. Moreover, the OpenGL spec for ClearBuffer is also very
complicated. At some point, we should implement buffer clearing for arbitrary
framebuffer objects, but for now, we will just wrap ClearBuffer.
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
commit bbd9c55d0217c697cbe090057bfbf830b551ed36
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Thu Feb 5 13:38:39 2015 -0800
main: Fake entry point for glClearNamedFramebufferfv.
Mesa's ClearBuffer framework is very complicated and thoroughly married to the
object binding model. Moreover, the OpenGL spec for ClearBuffer is also very
complicated. At some point, we should implement buffer clearing for arbitrary
framebuffer objects, but for now, we will just wrap ClearBuffer.
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
commit 43db4b8465c203f9748cd2a7e08d8242573116f1
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Thu Feb 5 13:30:50 2015 -0800
main: Fake entry point for glClearNamedFramebufferuiv.
Mesa's ClearBuffer framework is very complicated and thoroughly married to the
object binding model. Moreover, the OpenGL spec for ClearBuffer is also very
complicated. At some point, we should implement buffer clearing for arbitrary
framebuffer objects, but for now, we will just wrap ClearBuffer.
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
commit 6236c477990d67499f494b3c95844217fbd9a3dd
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Thu Feb 5 13:24:43 2015 -0800
main: Fake entry point for glClearNamedFramebufferiv.
Mesa's ClearBuffer framework is very complicated and thoroughly married to the
object binding model. Moreover, the OpenGL spec for ClearBuffer is also very
complicated. At some point, we should implement buffer clearing for arbitrary
framebuffer objects, but for now, we will just wrap ClearBuffer.
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
commit d890fc710f6d3472ea3837e074fafc100d41e01f
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Wed Feb 4 14:21:48 2015 -0800
main: Add entry points for InvalidateNamedFramebuffer[Sub]Data.
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
commit 65d4a20f1c1923498220637f9474d2ae399df52d
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Wed Feb 4 09:49:58 2015 -0800
main: Refactor invalidate_framebuffer_storage.
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
commit b4368ac09db75cea412121ada6c12af1414feb50
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Wed Feb 4 14:21:17 2015 -0800
main: Complete error conditions for glInvalidate*Framebuffer.
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
Reviewed-by: Adam Jackson <ajax at redhat.com>
Cc: "10.4 10.5" <mesa-stable at lists.freedesktop.org>
commit 6b284f08ab399154ad10e2166440b44cbbdcb2c5
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Tue Feb 3 14:47:00 2015 -0800
main: _mesa_blit_framebuffer updates its arbitrary framebuffers.
Previously, we used _mesa_update_state to update the currently bound
framebuffers prior to performing a blit. Now that _mesa_blit_framebuffer
uses arbitrary framebuffers, _mesa_update_state is not specific enough.
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
commit 47b910d27587f738dd81cdb9a879726785c0bc54
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Mon Feb 2 16:27:46 2015 -0800
main: Add entry point for BlitNamedFramebuffer.
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
commit b590c617256720e82fff0428a5e0e4a64115fac2
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Tue Feb 3 14:41:26 2015 -0800
main: Refactor _mesa_update_draw_buffer_bounds.
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
commit 39be0c5f6c1922e2e2f3c4243dd8257c2e7deef8
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Tue Mar 3 15:05:16 2015 -0800
main: Refactor _mesa_get_clamp_read_color.
This wasn't neccessary for ARB_direct_state_access, but felt like a good idea
for the sake of completeness.
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
commit 2cabfd9636a55f6adee04f4199ba83a39598d51c
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Tue Mar 3 14:03:33 2015 -0800
main: Refactor _mesa_[update|get]_clamp_fragment_color.
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
commit c1fe8d841c4746a6371dde569c6c88c6c2bad4e6
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Tue Feb 3 11:42:17 2015 -0800
main: Refactor _mesa_[update|get]_clamp_vertex_color.
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
commit 9036a6c0aa0637a1cd756836006dc8565b15a478
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Tue Feb 3 11:03:01 2015 -0800
main: Refactor _mesa_update_framebuffer.
_mesa_update_framebuffer now operates on arbitrary read and draw framebuffers.
This allows BlitNamedFramebuffer to update the state of its arbitrary read and
draw framebuffers.
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
commit 1a314f3c51bf1884cc3bf880e32461f304d5030b
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Mon Feb 2 16:17:47 2015 -0800
main: Refactor glBlitFramebuffer.
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
commit df032ef7e04977112871edc1f1e82e35e6dbac76
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Mon Feb 2 16:18:11 2015 -0800
main: Fix whitespace in blit.c
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
commit f22fa307de780723e182d62a03c2c4c4f8a937f7
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Thu Jan 29 17:11:37 2015 -0800
main: Add entry point GetNamedFramebufferAttachmentParameteriv.
[Fredrik: - Update one of the error messages to reflect that the
framebuffer might not be the bound framebuffer.
- Whitespace fixes.]
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
commit f93f95928d39b13e6c263b480b3e4bfdfa218df8
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Thu Jan 29 13:15:37 2015 -0800
main: Add entry point for CheckNamedFramebufferStatus.
[Fredrik: - Retain the debugging code in CheckFramebufferStatus.
- Whitespace fixes.]
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
commit 80e9bf2641d3bc2504fc12977c3e6a1ab7a3f49f
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Mon Mar 2 16:52:55 2015 -0800
main: Fix indents in former get_texture_for_framebuffer functions.
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
commit 085c67dc77ab3c00d3f68ba52f8343f8ff0cab53
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Mon Mar 2 16:48:59 2015 -0800
main: Major refactor of get_texture_for_framebuffer.
This splits off the (still) rather large chunk that is
get_texture_for_framebuffer into lots of smaller functions specialized to
service the wide variety of unique needs of *FramebufferTexture* entry points.
The result is much cleaner because, rather than having a pile of branches and
confusing conditions (like the boolean layered), the uniqueness is baked into
the entry points. The entry points know whether or not they are layered or use
a textarget.
[Fredrik: - Mention the value of <textarget> in the error message.
- Rename check_zoffset to check_layer, and zoffset to layer.
The zoffset parameter was renamed to layer in
ARB_framebuffer_object.
- Make layered a GLboolean since the value is visible to the API.
- Remove EXT suffixes in refactored code.
- Whitespace fixes.]
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
commit d78c831a147e8af6f6fc1a610f4c2e490e75fad1
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Wed Jan 28 13:19:57 2015 -0800
main: Add entry points for glNamedFramebufferTexture[Layer].
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
commit a602b21f94ded038f9781cc02ab46cdaab868f14
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Mon Mar 2 13:43:09 2015 -0800
main: Fix indentation in get_texture_for_framebuffer.
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
commit a9f73f7f42081594d0ba9ff6cb7a0a743c3cad93
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Mon Mar 2 13:41:13 2015 -0800
main: Refactor get_texture_for_framebuffer.
This moves a few blocks around so that the control flow is more obvious. If
the texture is 0, just return true at the beginning of the function.
Likewise, if the texObj is NULL, return true at the beginning of the function
as well.
[Fredrik: Fix the texObj NULL check]
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
commit a245e3bdeb1cf38b56df4f208a7e20d0f0de6045
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Tue Jan 27 16:11:52 2015 -0800
main: Split framebuffer_texture.
Split apart utility function framebuffer_texture to better prepare for
implementing NamedFramebufferTexture and NamedFramebufferTextureLayer. This
should also pave the way for some future cleanup work.
[Fredrik: - Mention which limit was exceeded when <layer> is out of range.
- Update a comment to reflect that <fb> might not be the bound
framebuffer.
- Make it clear that the error message in glFramebufferTexture*D
refers to the <textarget> parameter.
- Remove EXT suffixes.]
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
commit 69bdc9dcb8e5d3648e8d96029d5988b8971de8dc
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Mon Apr 20 17:21:20 2015 +0200
main: Fix an error generated by FramebufferTexture
gl*FramebufferTexture should generate GL_INVALID_VALUE when the
texture doesn't exist.
[Fredrik: Split this change out from the next commit]
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
Reviewed-by: Adam Jackson <ajax at redhat.com>
Cc: "10.4 10.5" <mesa-stable at lists.freedesktop.org>
commit 8ba7ad8abc7d71131e17970203c991ccb1befbe6
Author: Fredrik Höglund <fredrik at kde.org>
Date: Sat May 9 15:31:45 2015 +0200
mesa: Generate GL_INVALID_VALUE in framebuffer_texture when layer < 0
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
Reviewed-by: Adam Jackson <ajax at redhat.com>
Cc: "10.4 10.5" <mesa-stable at lists.freedesktop.org>
commit f9f5c822845698482d0d81eaa64bc13c2fd8852a
Author: Fredrik Höglund <fredrik at kde.org>
Date: Thu May 7 20:28:23 2015 +0200
main: Require that the texture exists in framebuffer_texture
Generate GL_INVALID_OPERATION if the texture hasn't been created.
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
Reviewed-by: Adam Jackson <ajax at redhat.com>
Cc: "10.4 10.5" <mesa-stable at lists.freedesktop.org>
commit 8f78c6889d508d40c82229ea3fa09a78b4ea2e17
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Tue Jan 27 14:11:13 2015 -0800
main: Fix the indentation in framebuffer_texture
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
commit a29318bf0a0385fa4fdedbdc3fb6e1f6f0d87884
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Fri Feb 27 17:27:30 2015 -0800
main: Add entry point for NamedFramebufferRenderbuffer.
[Fredrik: - Remove the DummyRenderbuffer checks now that they are
done in _mesa_lookup_renderbuffer_err.
- Fix the <renderbuffertarget> name in error messages.
- Make the error message in _mesa_framebuffer_renderbuffer
reflect that <fb> might not be the bound framebuffer.
- Remove EXT suffixes from GL tokens.]
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
commit 3d100372f15c377bb1cff3d23621f1f5958f4c53
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Fri Feb 27 17:23:59 2015 -0800
main: Rename framebuffer renderbuffer software fallback.
Rename _mesa_framebuffer_renderbuffer to _mesa_FramebufferRenderbuffer_sw in
preparation for adding the ARB_direct_state_access backend function for
FramebufferRenderbuffer and NamedFramebufferRenderbuffer to share.
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
commit 2bb138e7ec24b9e56715a53f9c4e911b99d4a97b
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Fri Jan 23 16:38:36 2015 -0800
main: Add utility function _mesa_lookup_renderbuffer_err.
[Fredrik: Generate an error for non-existent renderbuffers]
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
commit f868de7d6b1370105414eb3d83b4b38b598bff66
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Fri Jan 23 14:54:48 2015 -0800
main: Add glCreateFramebuffers.
[Fredrik: Whitespace fixes]
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
commit 6d8eff4af7816d675f8ee91f99106fa118cda424
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Thu Jan 22 10:23:35 2015 -0800
main: Add utility function _mesa_lookup_framebuffer_err.
[Fredrik: Generate an error for non-existent framebuffers]
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Signed-off-by: Fredrik Höglund <fredrik at kde.org>
commit adcf8f8a13717f7eb53b2aa86c4b56e344f2f317
Author: Roland Scheidegger <sroland at vmware.com>
Date: Wed May 13 22:56:07 2015 +0200
softpipe: enable ARB_texture_view
Some bits were already there for texture views but some were missing.
In particular for cube map views things needed to change a bit.
For simplicity I ended up removing the separate face addr bit (just use
the z bit) - cube arrays didn't use it already, so just follow the same
logic there. (In theory using separate bits could allow for better hash
function but I don't think anyone ever did some measurements of that so
probably not worth the trouble, if we'd reintroduce it we'd certainly
wanted to use the same logic for cube arrays and cube maps.)
Also extend the seamless cube sampling to cube arrays - as there were no
piglit failures before this is apparently untested, but things now generally
work quite the same for cube textures and cube array textures so there
hopefully shouldn't be any trouble...
49 new piglits, 47 pass, 2 fail (both due to fake multisampling).
v2: incorporate Brian's feedback, add sampler view validation,
function rename, formatting fixes.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit e6c66f4fb060cf2566d2b5e091b76a098566344d
Author: Roland Scheidegger <sroland at vmware.com>
Date: Wed May 13 22:16:44 2015 +0200
llvmpipe: enable ARB_texture_view
All the functionality was pretty much there, just not tested.
Trivially fix up the missing pieces (take target info from view not
resource), and add some missing bits for cubes.
Also add some minimal debug validation to detect uninitialized target values
in the view...
49 new piglits, 47 pass, 2 fail (both related to fake multisampling,
not texture_view itself). No other piglit changes.
v2: move sampler view validation to sampler view creation, update docs.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 2712f70d57a0df25db6371496eb567564a588e13
Author: Roland Scheidegger <sroland at vmware.com>
Date: Tue May 12 17:27:59 2015 +0200
gallium/util: fix blitter sampler view target initialization
This was missing, and drivers relying on the target in the view could get
into quite some trouble.
Signed-off-by: Roland Scheidegger <sroland at vmware.com>
Reviewed-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit cf71e7093c301a1d3dc3e19d88d44a043ccadc7d
Author: Alexander von Gluck IV <kallisti5 at unixzen.com>
Date: Wed May 13 14:22:57 2015 -0400
glapi/hgl: Drop extern "C" as it was added to glapi
Reviewed-by: Brian Paul <brianp at vmware.com>
commit d27b114eaf75b1a61cc9600eed1b9cde352d8409
Author: Alexander von Gluck IV <kallisti5 at unixzen.com>
Date: Wed May 13 14:22:00 2015 -0400
glapi: Add extern "C" to glapi_priv.h
* The Haiku glapi has a C++ wrapper around the dispatch code.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 915d808a5653653b5c7b5413c4f667db017239ec
Author: Alexander von Gluck IV <kallisti5 at unixzen.com>
Date: Wed May 13 09:40:01 2015 -0500
gallium/st + hgl: Build fixes for Haiku
* No impact risk to any other platforms
* Tracing printf needs stdio.h now due to child header change
* Add missing #/src include directory for util/macros.h
commit d247615e0d67a7c8eaeea3fece837229c8c9658c
Author: Francisco Jerez <currojerez at riseup.net>
Date: Sat Jan 31 20:04:55 2015 +0200
i965: Fix PBO cache coherency issue after _mesa_meta_pbo_GetTexSubImage().
This problem can easily be reproduced with a number of
ARB_shader_image_load_store piglit tests, which use a buffer object as
PBO for a pixel transfer operation and later on bind the same buffer
to the pipeline as shader image -- The problem is not exclusive to
images though, and is likely to affect other kinds of buffer objects
that can be bound to the 3D pipeline, including vertex, index,
uniform, atomic counter buffers, etc.
CC: 10.5 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 58715b72396133350c1549381553121f936a198e
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Tue May 12 14:24:08 2015 +0300
i965/fs: set execution size to 8 with simd8 ddy instruction
Commit dd5c825 changed the way how execution size for instructions
get set. Previously it was based on destination register width, now
it is set explicitly when emitting instructions.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90258
commit 71fc52072b1ecf01764c37d64ad160fcbfe19e11
Author: Dave Airlie <airlied at redhat.com>
Date: Wed May 13 09:59:59 2015 +1000
i965/cs: drop explicit initialisers in C++ file
gcc 4.4.7 really doesn't like them, and they aren't standard
C++, they seem to be a gcc extension.
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit c696a318ef1eb58f65fb867d5616bbefd1def31e
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Tue May 12 18:58:17 2015 -0400
nouveau: document nouveau_heap
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit d06ce2f1df54edd234b1abde37bba524ed599acb
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun May 10 01:57:56 2015 -0400
nvc0: switch mechanism for shader eviction to be a while loop
This aligns it to work similarly to nv50. However there's no library
code there, so the whole thing can be freed. Here we end up with an
allocated node that's not attached to a specific program.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86792
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org
commit 380f7611b5d23b72684ce1eb848f956945e4c39b
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Apr 24 19:17:11 2015 -0400
st/mesa: update stencil surface if it comes from texture
Now that ARB_texture_stencil8 is supported, this might happen.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit 71ba30f7788167c04d0968d286a387fce16afcce
Author: Alex Deucher <alexander.deucher at amd.com>
Date: Tue May 12 13:13:05 2015 -0400
radeonsi: add new bonaire pci id
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
Cc: mesa-stable at lists.freedesktop.org
commit 0ea1047d8c0636fa1f6bcbac56be329e19ada205
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Apr 29 17:54:26 2015 +0200
st/mesa: translate st_api robustness flags to gl_context flags
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit f1c42475a589531919194c95b97e7558b448eb5c
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Apr 29 17:52:02 2015 +0200
st/dri: add support for create_context_robustness GLX and EGL extensions
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit a0ad18580335d2255d4e1bf222886418c8e2302e
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Apr 29 15:05:19 2015 +0200
st/mesa: implement GetGraphicsResetStatus
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 79ffc08ae8641e5b22d8cd4d9edc7ca7f0cf3aa8
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Apr 29 15:44:55 2015 +0200
gallium: add PIPE_CAP_DEVICE_RESET_STATUS_QUERY
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit cacd0e290a7f510fe9cd78fde3156cd42f35a8b6
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Apr 29 15:04:34 2015 +0200
gallium: add an interface for querying a device reset status
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit a533d4edf1ea346dd9e343c71b2cd500fa550ef8
Author: Francisco Jerez <currojerez at riseup.net>
Date: Sat May 9 16:01:23 2015 +0300
clover: Implement locking of the wait_count, _chain and _status members of event.
Tested-by: Tom Stellard <thomas.stellard at amd.com>
CC: 10.5 <mesa-stable at lists.freedesktop.org>
commit 4022a468b2976c65e0d2afe9c9ac5804729e8641
Author: Francisco Jerez <currojerez at riseup.net>
Date: Sat May 9 16:22:33 2015 +0300
clover: Wrap event::_status in a method to prevent unlocked access.
Tested-by: Tom Stellard <thomas.stellard at amd.com>
CC: 10.5 <mesa-stable at lists.freedesktop.org>
commit 2232b929fd9ca6f00c8dab9dc45c386986be922d
Author: Francisco Jerez <currojerez at riseup.net>
Date: Sat May 9 14:47:38 2015 +0300
clover: Refactor event::trigger and ::abort to prevent deadlock and reentrancy issues.
Refactor ::trigger and ::abort to split out the operations that access
concurrently modified data members and require locking from the
recursive and possibly re-entrant part of these methods. This will
avoid some deadlock situations when locking is implemented.
Tested-by: Tom Stellard <thomas.stellard at amd.com>
CC: 10.5 <mesa-stable at lists.freedesktop.org>
commit d91d6b3f03f36d4cfef5e9aacac1534f12372c9f
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue May 5 23:10:56 2015 +0300
nir: Translate memory barrier intrinsics from GLSL IR.
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit f8f8b318476cb40650b0bc2597b21978fc456d78
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue May 5 23:04:46 2015 +0300
nir: Translate image load, store and atomic intrinsics from GLSL IR.
v2: Undefine coordinate components not applicable to the target.
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 6de78e6b0c8aa4bd6bdd89e3ca33c2ccb9a5ac3d
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue May 5 23:02:05 2015 +0300
nir: Fix indexing of atomic counter arrays with a constant value.
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit f1269a3e013e23135b2482e4f137d69ed6cc1734
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue May 5 23:00:51 2015 +0300
nir: Add memory barrier intrinsic.
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit d9e930997f1addafe37e10ddc0f56d0684be0086
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue May 5 22:58:39 2015 +0300
nir: Define image load, store and atomic intrinsics.
v2: Undefine coordinate components not applicable to the target.
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit ee1a8b5a8cc118b49b47c7074fa18cf1b4820885
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Apr 30 19:29:54 2015 +0300
i965/fs: Have component() set the register stride to zero.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 4171ef371a25fccf9e96c0908a4848ea79dcfef2
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Apr 22 14:46:17 2015 +0300
i965/fs: Fix offset() for registers with zero stride.
stride == 0 implies that the register has one channel per vector
component.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 0db663503ea86579d3352fe83d428d573a8d2b03
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu May 7 19:33:57 2015 +0300
i965: Don't forget the force_sechalf flag in lower_load_payload().
Regression from commit 41868bb6824c6106a55c8442006c1e2215abf567.
Fixes a bunch of ARB_shader_image_load_store tests.
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
commit cbf204069d00e99055a539e5f79566e2021fa8f4
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed May 6 17:37:12 2015 +0300
i965: Document brw_mask_reg().
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 95774ca258d216d42877f9a8da7e1bb4212a6500
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Mon May 11 14:50:19 2015 +0300
nir: fix sampler lowering pass for arrays
This fixes bugs with special cases where we have arrays of
structures containing samplers or arrays of samplers.
I've verified that patch results in calculating same index value as
returned by _mesa_get_sampler_uniform_value for IR. Patch makes
following ES3 conformance test pass:
ES3-CTS.shaders.struct.uniform.sampler_array_fragment
v2: remove unnecessary comment (Topi)
simplify changes and the overall code (Jason)
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90114
commit 426023050d1d3cd1b5fc0b3508dd7e1ee3b061e7
Author: Neil Roberts <neil at linux.intel.com>
Date: Tue Nov 4 19:15:00 2014 +0000
i965: Use predicate enable bit for conditional rendering w/o stalling
Previously whenever a primitive is drawn the driver would call
_mesa_check_conditional_render which blocks waiting for the result of
the query to determine whether to render. On Gen7+ there is a bit in
the 3DPRIMITIVE command which can be used to disable the primitive
based on the value of a state bit. This state bit can be set based on
whether two registers have different values using the MI_PREDICATE
command. We can load these two registers with the pixel count values
stored in the query begin and end to implement conditional rendering
without stalling.
Unfortunately these two source registers were not in the whitelist of
available registers in the kernel driver until v3.19. This patch uses
the command parser version from intel_screen to detect whether to
attempt to set the predicate data registers.
The predicate enable bit is currently only used for drawing 3D
primitives. For blits, clears, bitmaps, copypixels and drawpixels it
still causes a stall. For most of these it would probably just work to
call the new brw_check_conditional_render function instead of
_mesa_check_conditional_render because they already work in terms of
rendering primitives. However it's a bit trickier for blits because it
can use the BLT ring or the blorp codepath. I think these operations
are less useful for conditional rendering than rendering primitives so
it might be best to leave it for a later patch.
v2: Use the command parser version to detect whether we can write to
the predicate data registers instead of trying to execute a
register load command.
v3: Simple rebase
v4: Changes suggested by Kenneth Graunke: Split the
load_64bit_register function out to a separate patch so it can be
a shared public function. Avoid calling
_mesa_check_conditional_render if we've already determined that
there's no query object. Some styling fixes.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 9585879d46fe412cbcfd50510e59e8ffe85b055f
Author: Neil Roberts <neil at linux.intel.com>
Date: Mon May 11 14:00:42 2015 +0100
i956: Add a function to load a 64-bit register from a buffer
Adds brw_load_register_mem64 which is similar to brw_load_register_mem
except that it queues two GEN7_MI_LOAD_REGISTER_MEM commands in order
to load both halves of a 64-bit register. The function is implemented
by splitting the 32-bit version into an internal helper function which
takes a size.
This will later be used to set the 64-bit predicate source registers.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 8a59f2f26fb7bb036ad524cdec668716664d2a82
Author: Neil Roberts <neil at linux.intel.com>
Date: Fri Nov 7 18:20:17 2014 +0000
i965: Store the command parser version number in intel_screen
In order to detect whether the predicate source registers can be used
in a later patch we will need to know the version number for the
command parser. This patch just adds a member to intel_screen and does
an ioctl to get the version.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 971be2b7c9c4459e383059f02d20a35e469b429e
Author: Roland Scheidegger <sroland at vmware.com>
Date: Tue May 12 04:48:48 2015 +0200
docs/GL3: (trivial) mark some tf extensions as done for softpipe/llvmpipe
Those extensions were enabled for ages already.
commit 95089bfaebcff449289494267c3461704f48452e
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon May 11 22:07:46 2015 +0100
docs: add news item and link release notes for mesa 10.5.5
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit d4125c41f999a09521effa1579c0964441411a13
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon May 11 22:02:03 2015 +0100
docs: Add sha256 sums for the 10.5.5 release
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit 8ee1a1c08b168d7583b806a2f8a2dc2ae28be62a)
commit 22aaa746bdbe153effcbba7d5690bd9db880c76f
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon May 11 20:19:33 2015 +0100
Add release notes for the 10.5.5 release
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit d88fb4050561a62fa824bec59ffedf2a826c2083)
commit 2b5355c8ab383d86bb6332dd29c417a6a1bc52bd
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed May 6 23:29:33 2015 -0400
st/mesa: make sure to create a "clean" bool when doing i2b
i2b has to work for all integers, not just 1. INEG would not necessarily
result with all bits set, which is something that other operations can
rely on by e.g. using AND (or INEG for b2i).
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Cc: mesa-stable at lists.freedesktop.org
commit 9c4dc98b298c74015f2a7c21571bccf0a5b6cc98
Author: Tom Stellard <thomas.stellard at amd.com>
Date: Thu Mar 26 19:33:24 2015 +0000
clover: Fix a bug with multi-threaded events v2
It was possible for some events never to get triggered if one thread
was creating events and another threads was waiting for them.
This patch consolidates soft_event::wait() and hard_event::wait()
into event::wait() so that hard_event objects will now wait for
all their dependencies to be submitted before flushing the command
queue.
v2:
- Rename variables
- Use mutable varibales so we can keep event::wait() const
- Open code signalled() call so mutex can be atted to signalled
without deadlocking.
CC: 10.5 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit f546902d9597429713c83e2caf6b69856bd7ba4d
Author: Tom Stellard <thomas.stellard at amd.com>
Date: Thu May 7 13:57:14 2015 +0000
clover: Add a mutex to guard queue::queued_events
This fixes a potential crash where on a sequence like this:
Thread 0: Check if queue is not empty.
Thread 1: Remove item from queue, making it empty.
Thread 0: Do something assuming queue is not empty.
CC: 10.5 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 73f4010082cf0fc2fe34c59e2eb5801eed10762b
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon May 11 10:46:59 2015 -0700
i965/fs: Add missing initializer in fs_visitor().
commit 7a58262e58d8edac3308777def0950032628edee
Author: Adam Jackson <ajax at redhat.com>
Date: Wed Apr 1 10:39:45 2015 -0400
egl: Remove skeleton implementation of EGL_MESA_screen_surface
No backend wires this up to anything, and the extension spec has been
marked obsolete for 4+ years.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Adam Jackson <ajax at redhat.com>
commit 13fa84e1bcf1e07c69bb678508f8cdb0912b57c5
Author: Axel Davy <axel.davy at ens.fr>
Date: Fri May 1 19:08:37 2015 +0200
egl/swrast: Enable config extension for swrast
Enables to use dri config for swrast, like vblank_mode.
Reviewed-by: Dave Airlie <airlied at redhat.com>
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit cdcfe48fb0431184fabb40aa5a244d086f551df5
Author: Axel Davy <axel.davy at ens.fr>
Date: Fri May 1 11:11:20 2015 +0200
egl/wayland: Implement swrast support
Reviewed-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Daniel Stone <daniels at collabora.com>.
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit cd25e52f6bb5279cd7b1992e5907df3966b900ce
Author: Axel Davy <axel.davy at ens.fr>
Date: Fri May 1 11:16:41 2015 +0200
egl/wayland: Simplify dri2_wl_create_surface
This function is always used with EGL_WINDOW_BIT. Pixmaps are forbidden
for Wayland, and PBuffers are unimplemented.
Reviewed-by: Daniel Stone <daniels at collabora.com>.
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit f1cc478d89986c87f01fdaae510335965e19493c
Author: Axel Davy <axel.davy at ens.fr>
Date: Fri May 1 11:12:46 2015 +0200
egl/x11: move dri2_x11_swrast_create_image_khr to egl_dri2_fallback.h
Reviewed-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Daniel Stone <daniels at collabora.com>
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 4cd546df82c557b9a765e40db2f96c4faa299846
Author: Axel Davy <axel.davy at ens.fr>
Date: Fri May 1 01:16:24 2015 +0200
egl/wayland: Implement DRI_PRIME support
When the server gpu and requested gpu are different:
. They likely don't support the same tiling modes
. They likely do not have fast access to the same locations
Thus we do:
. render to a tiled buffer we do not share with the server
. Copy the content at every swap to a buffer with no tiling
that we share with the server.
This is similar to the glx dri3 DRI_PRIME implementation.
Reviewed-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Daniel Stone <daniels at collabora.com>
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit fb0960a14bd6980aa63deef45ec3cf1ab99bcf0a
Author: Axel Davy <axel.davy at ens.fr>
Date: Fri May 1 01:30:10 2015 +0200
egl/wayland: Add support for render-nodes
It is possible the server advertises a render-node.
In that case no authentication is needed,
and Gem names are forbidden.
Reviewed-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Daniel Stone <daniels at collabora.com>
Signed-off-by: Axel Davy <axel.davy at ens.fr>
v2: do not check for __DRI_IMAGE_DRIVER, but instead
do not advertise __DRI_DRI2_LOADER when on a render-node.
commit c4ff6d00cd7dde4646ff96733f68d3ddbf540c2c
Author: Axel Davy <axel.davy at ens.fr>
Date: Fri May 1 00:20:34 2015 +0200
glx/dri3: Add additional check for gpu offloading case
Checks blitImage is implemented.
Initially having the __DRIimageExtension extension
at version 9 at least meant blitImage was supported.
However some implementation do advertise version >= 9
without implementing it.
CC: 10.5 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Daniel Stone <daniels at collabora.com>
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 05ac39ac497ad7835cac7a161491282b5f69d711
Author: Axel Davy <axel.davy at ens.fr>
Date: Fri May 1 00:06:31 2015 +0200
doc/egl: Remove depreciated EGL_SOFTWARE
EGL_SOFTWARE is not supported anywhere in the code,
whereas LIBGL_ALWAYS_SOFTWARE is.
Reviewed-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Daniel Stone <daniels at collabora.com>
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 6aaf09b93b668a24b557e05195b9897e8cee8559
Author: Axel Davy <axel.davy at ens.fr>
Date: Fri May 1 00:03:32 2015 +0200
egl/wayland: properly destroy wayland objects
the wl_registry and the wl_queue allocated weren't destroyed.
CC: 10.5 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Daniel Stone <daniels at collabora.com>
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit bfdae9149e00bd5c2521db3e75669ae043eed5cc
Author: Neil Roberts <neil at linux.intel.com>
Date: Fri May 8 17:35:18 2015 +0100
i965/fs: Disable opt_sampler_eot for textureGather
The opt_sampler_eot optimisation seems to break when the last
instruction is SHADER_OPCODE_TG4. A bunch of Piglit tests end up doing
this so it causes a lot of regressions. I can't find any documentation
or known workarounds to indicate that this is expected behaviour, but
considering that this is probably a pretty unlikely situation in a
real use case we might as well disable it in order to avoid the
regressions. In total this fixes 451 tests.
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit abf3fefa1aa734844e0ca8e95e8c3a501909aa33
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Thu May 7 08:07:30 2015 +0300
mesa: use _mesa_has_compute_shaders instead of extension check
This was really the original purpose, for enabling the path for
ES3.1 tests without the extension being set. Set also fallthrough
comment for Coverity (caught by Matt).
v2: .. and test the right way, not wrong one (Ilia Mirkin)
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 4a8cd2799c2467b9916dd0ba672f05a394aa9b9f
Author: Marta Lofstedt <marta.lofstedt at linux.intel.com>
Date: Thu May 7 17:13:47 2015 +0200
main: glGetIntegeri_v fails for GL_VERTEX_BINDING_STRIDE
The return type for GL_VERTEX_BINDING_STRIDE is missing,
this cause glGetIntegeri_v to fail.
Signed-off-by: Marta Lofstedt <marta.lofstedt at linux.intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Cc: "10.4 10.5" <mesa-stable at lists.freedesktop.org>
commit 9ab90c058fdb86e9364af258fca7c4de23adbe50
Author: Dave Airlie <airlied at gmail.com>
Date: Mon May 11 06:24:03 2015 +1000
r600: use pipe->hw prim convert from radeonsi
This avoids future addition to PIPE_PRIM_ from causing regressions
on r600g.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 1cbdafc47a46fa55fcd5afa9193525e694099944
Author: Rob Clark <robclark at freedesktop.org>
Date: Sun May 10 06:03:49 2015 -0400
freedreno/ir3/nir: fix build break after f752effa
Our lower if/else pass was missed when converting NIR to use linked
lists rather than hashsets to track use/def sets.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit da136dc07ddb6147d181c96f475b94f6281efd73
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat May 9 03:26:07 2015 -0400
nv50/ir: only enable mul saturate on G200+
Commit 44673512a84 enabled support for saturating fmul. However
experimentally this does not seem to work on the older chips. Restrict
the feature to G200 (NVA0) and later.
Reported-by: Pierre Moreau <pierre.morrow at free.fr>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90350
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Tested-by: Pierre Moreau <pierre.morrow at free.fr>
Reviewed-by: Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de>
Cc: mesa-stable at lists.freedesktop.org
commit 7892210400e8f3bd14697c0a3dd56e98454a45df
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat May 9 13:25:51 2015 -0400
nvc0: reset the instanced elements state when doing blit using 3d engine
Since we update num_vtxelts here, we could otherwise end up with stale
instancing information in the upper bits which wouldn't otherwise get
reset. (Also we run the risk of the previous draw having set the first
element as instanced.)
This appears as one of the causes for the test pointed out in fdo#90363
to fail on nvc0.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90363
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org
commit e9b1ea29bf1e8f09e83bd6358d0d2068053f09d4
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri May 8 00:26:24 2015 -0400
nvc0: keep track of PGRAPH state in nvc0_screen
See identical commit for nv50. Destroying the current context and then
creating a new one or switching to another existing context would cause
the "current" state to not be properly initialized, so we save it off in
the screen.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org
commit f617029db3f8786d94c64f1a73c42b89b6d261fa
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri May 8 00:15:22 2015 -0400
nv50: keep track of PGRAPH state in nv50_screen
Normally this is kept in nv50_context, and on switching the active
context, the state is copied from the previous context. However when the
last context is destroyed, this is lost, and a new context might later
be created. When the currently-active context is destroyed, save its
state in the screen, and restore it when setting the current context.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90363
Reported-by: Matteo Bruni <matteo.mystral at gmail.com>
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Tested-by: Matteo Bruni <matteo.mystral at gmail.com>
Cc: mesa-stable at lists.freedesktop.org
commit d6fb155f30ac2bd7853da32ddf99e9f7840a8f01
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri May 8 19:36:19 2015 -0700
nir: Fix aggressive typos in nir_from_ssa.c.
s/agressive/aggressive/g
Trivial.
commit fb5f411248d9c342ed249228f7dac713dcfd3d06
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri May 8 09:48:33 2015 -0700
nir/search: Save/restore the variables_seen bitmask when matching
Shader-db results on Broadwell:
total instructions in shared programs: 7152330 -> 7137006 (-0.21%)
instructions in affected programs: 1330548 -> 1315224 (-1.15%)
helped: 5797
HURT: 76
GAINED: 0
LOST: 8
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit e0cfe59c37245d8555202a12b9b29866894d6d18
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri May 8 09:42:05 2015 -0700
nir/search: Assert that variable id's are in range
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 13facfbd5b067daedc972c1a4fb2f2142fcbc190
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri May 8 08:33:01 2015 -0700
nir/search: handle explicitly sized sources in match_value
Previously, this case was being handled in match_expression prior to
calling match_value. However, there is really no good reason for this
given that match_value has all of the information it needs. Also, they
weren't being handled properly in the commutative case and putting it in
match_value gives us that for free.
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit f752effa087f29faddabac047683d16416d178d9
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Apr 24 10:16:27 2015 -0700
nir/nir: Use a linked list instead of a hash set for use/def sets
This commit switches us from the current setup of using hash sets for
use/def sets to using linked lists. Doing so should save us quite a bit of
memory because we aren't carrying around 3 hash sets per register and 2 per
SSA value. It should also save us CPU time because adding/removing things
from use/def sets is 4 pointer manipulations instead of a hash lookup.
Running shader-db 50 times with USE_NIR=0, NIR, and NIR + use/def lists:
GLSL IR Only: 586.4 +/- 1.653833
NIR with hash sets: 675.4 +/- 2.502108
NIR + use/def lists: 641.2 +/- 1.557043
I also ran a memory usage experiment with Ken's patch to delete GLSL IR and
keep NIR. This patch cuts an aditional 42.9 MiB of ralloc'd memory over
and above what we gained by deleting the GLSL IR on the same dota trace.
On the code complexity side of things, some things are now much easier and
others are a bit harder. One of the operations we perform constantly in
optimization passes is to replace one source with another. Due to the fact
that an instruction can use the same SSA value multiple times, we had to
iterate through the sources of the instruction and determine if the use we
were replacing was the only one before removing it from the set of uses.
With this patch, uses are per-source not per-instruction so we can just
remove it safely. On the other hand, trying to iterate over all of the
instructions that use a given value is more difficult. Fortunately, the
two places we do that are the ffma peephole where it doesn't matter and GCM
where we already gracefully handle duplicates visits to an instruction.
Another aspect here is that using linked lists in this way can be tricky to
get right. With sets, things were quite forgiving and the worst that
happened if you didn't properly remove a use was that it would get caught
in the validator. With linked lists, it can lead to linked list corruption
which can be harder to track. However, we do just as much validation of
the linked lists as we did of the sets so the validator should still catch
these problems. While working on this series, the vast majority of the
bugs I had to fix were caught by assertions. I don't think the lists are
going to be that much worse than the sets.
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 2c2cd368aad9167816547aa86009c9cb489255c0
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Apr 27 20:40:11 2015 -0700
util/list: Add a list validation function
Acked-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Rob Clark <robclark at freedesktop.org>
commit addcf41066d28a5d2d5ed112a65a3958b056bd19
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Apr 27 20:39:37 2015 -0700
util/list: Add list_empty and list_length functions
v2: Don't use C99 when iterating over the list
Acked-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Rob Clark <robclark at freedesktop.org>
commit b31d8983ba5d68f3bcb5520b9281a4553d66fb95
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Apr 27 18:56:02 2015 -0700
util/list: Add C99-based iterator macros
v2: Use LIST_ENTRY instead of container_of in iterators
Acked-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Rob Clark <robclark at freedesktop.org>
commit 7a30668ad665f3315106e1a959c6186dea79a24a
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Apr 27 17:41:27 2015 -0700
util: Move gallium's linked list to util
The linked list in gallium is pretty much the kernel list and we would like
to have a C-based linked list for all of mesa. Let's not duplicate and
just steal the gallium one.
Acked-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Rob Clark <robclark at freedesktop.org>
commit 258b4194c8314ffc57ff676ad2528b741b47031e
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Apr 27 16:58:29 2015 -0700
gallium/double_list: s/INLINE/inline and remove the p_compiler include
Acked-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Rob Clark <robclark at freedesktop.org>
commit ecc2cfc8b60191c1df340467e086cd15b52b9fb7
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Apr 21 12:12:26 2015 -0700
nir: Use nir_instr_rewrite_src in copy propagation
We were rolling our own rewrite_src variant in copy-propagation. Let's
stop doing that and use the ones in core NIR.
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit f72a8d1cf06da55c215a61c085e1f29a5102182b
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Apr 24 10:34:30 2015 -0700
nir: Add a function for rewriting the condition of an if statement
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 300d72943675a49091ecb49597b56f7bdfefd22d
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Apr 21 18:00:21 2015 -0700
nir: Add and use initializer #defines for nir_src and nir_dest
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 6702ebce5760aae0eb15f410c2a83b6e893b005c
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Apr 21 11:16:04 2015 -0700
nir: Modernize the out-of-SSA pass
The out-of-SSA pass was one of the first passes written when getting SSA
up-and-going (for obvious reasons). As such, it came before a lot of the
nifty SSA-based helpers were introduced. This commit modernizes it so that
we're no longer doing nearly as much manual banging on use/def sets.
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 7ee0216e2d576a02de9d938488a6d6ba55ccb115
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Apr 23 17:10:42 2015 -0700
nir/validate: Validate SSA def parent instructions
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit c4ac09e30e2520b0ac6d403eb6c77f23e7f24f49
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri May 8 18:54:08 2015 -0400
nv50/ir: only propagate saturate up if some actual folding took place
The former logic would copy the saturate up to any mul with an immediate
if there was a subsequent mul with a saturate. However we only want to
do that if we collapsed 2 muls by multiplying their immediates (or were
able to put the immediate in as a post-multiplier).
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org
commit 3bdbc1e436828606d0b549b9480e7cc28b42d159
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed May 6 17:04:15 2015 -0700
nir: Delete all traces of nir_op_flog
Nothing produces it, and nothing can consume it.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Acked-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit ad51f9b4213d90489362d98f5aa2bf1956ef6f53
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed May 6 17:01:37 2015 -0700
nir: Don't produce nir_op_flog from GLSL IR
All paths that produce GLSL IR for NIR lower ir_unop_log. All paths
that consume NIR will explode if they geta nir_op_flog.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Acked-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit e0a17f6e31a8cefc173ced5f53cb2d28a842fbb6
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed May 6 17:00:18 2015 -0700
nir: Delete all traces of nir_op_fexp
Nothing produces it, and nothing can consume it.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Acked-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit a45d55f17c7895c55214d2babeb0f0b03442c8a8
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed May 6 16:57:22 2015 -0700
nir: Don't produce nir_op_fexp from GLSL IR
All paths that produce GLSL IR for NIR lower ir_unop_exp. All paths
that consume NIR will explode if they geta nir_op_fexp.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Acked-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 5e0dca62a7c8d02ab01bec4259cc67324bb2075d
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed May 6 16:54:06 2015 -0700
prog_to_nir: OPCODE_EXP is not nir_op_fexp
It's a weird thing that provides some values related to 2**x. It's also
already handled by a case in the switch.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Acked-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit f98c3f3e44abb0c8cb158c589418def111d72052
Author: Neil Roberts <neil at linux.intel.com>
Date: Fri May 8 16:13:52 2015 +0100
i965/fs: Improve a comment about stripping trailing zeroes
Originally I wrote that removing the first parameter doesn't work but
I didn't know why. I now found a mention of this in the PRM so it's
probably worthing adding it to the comment.
commit b004510072a2995463f57f3b79d43429729134d2
Author: Fredrik Höglund <fredrik at kde.org>
Date: Wed Mar 18 20:50:06 2015 +0100
docs: Update the ARB_direct_state_access status
Reviewed-by: Laura Ekstrand <laura at jlekstrand.net>
commit 97b268f1de6efc1fe15fbb63b9f36da2c6d858bb
Author: Fredrik Höglund <fredrik at kde.org>
Date: Mon Mar 2 19:07:52 2015 +0100
mesa: Implement GetVertexArrayIndexed[64]iv
v2: Fix the name of the entry point in the error messages.
Reviewed-by: Laura Ekstrand <laura at jlekstrand.net>
commit 2ad0268871a4a35c3a9cd77969ef0563a887299f
Author: Fredrik Höglund <fredrik at kde.org>
Date: Mon Mar 2 19:04:16 2015 +0100
mesa: Add support for querying GL_VERTEX_ATTRIB_ARRAY_LONG
This parameter was added in OpenGL 4.3 and GL_ARB_direct_state_access.
Reviewed-by: Laura Ekstrand <laura at jlekstrand.net>
commit 4f5160300dd143de8860e4e42d3dbfc7b534cfe2
Author: Fredrik Höglund <fredrik at kde.org>
Date: Mon Mar 2 18:58:36 2015 +0100
mesa: Add a vao parameter to get_vertex_array_attrib
This is needed to implement glGetVertexArrayIndexediv and
glGetVertexArrayIndexed64iv.
v2: Make the vao parameter const.
Reviewed-by: Laura Ekstrand <laura at jlekstrand.net>
commit 1085c0112128e6bbb6cdc7ef3ae40e5e69499098
Author: Fredrik Höglund <fredrik at kde.org>
Date: Mon Mar 2 18:56:31 2015 +0100
mesa: Implement GetVertexArrayiv
Reviewed-by: Laura Ekstrand <laura at jlekstrand.net>
commit 0a895c379e649b64efd5c0978fb6252dabf9d285
Author: Fredrik Höglund <fredrik at kde.org>
Date: Mon Mar 2 18:52:36 2015 +0100
mesa: Implement VertexArrayBindingDivisor
Reviewed-by: Laura Ekstrand <laura at jlekstrand.net>
commit f2ef09d44adc4a00ed6ae18377c588320022d284
Author: Fredrik Höglund <fredrik at kde.org>
Date: Mon Mar 2 18:50:49 2015 +0100
mesa: Add a vao parameter to vertex_binding_divisor
This is needed to implement VertexArrayBindingDivisor.
Reviewed-by: Laura Ekstrand <laura at jlekstrand.net>
commit dc2eaaf912c342ee85c88dcc467a3c59875af874
Author: Fredrik Höglund <fredrik at kde.org>
Date: Mon Mar 2 18:49:06 2015 +0100
mesa: Implement VertexArrayAttribBinding
Reviewed-by: Laura Ekstrand <laura at jlekstrand.net>
commit ade0179f77fff7d2d88d7dd9e23990051815a1dc
Author: Fredrik Höglund <fredrik at kde.org>
Date: Mon Mar 2 18:46:42 2015 +0100
mesa: Add a vao parameter to vertex_attrib_binding
This is needed to implement VertexArrayAttribBinding.
Reviewed-by: Laura Ekstrand <laura at jlekstrand.net>
commit f0030b0f1fd6f8c7790e28e65ead3af6c3bab3eb
Author: Fredrik Höglund <fredrik at kde.org>
Date: Mon Mar 2 18:44:00 2015 +0100
mesa: Implement VertexArrayAttrib[I|L]Format
Reviewed-by: Laura Ekstrand <laura at jlekstrand.net>
commit fa350eadfbe892c21be30d945fa6d61f09541cae
Author: Fredrik Höglund <fredrik at kde.org>
Date: Mon Mar 2 18:41:09 2015 +0100
mesa: Add a vao parameter to update_array_format
This is needed to implement VertexArrayAttrib*Format.
Reviewed-by: Laura Ekstrand <laura at jlekstrand.net>
commit bc6668e35d3cbadf4ec37a2d4490df1b4b002729
Author: Fredrik Höglund <fredrik at kde.org>
Date: Mon Mar 2 18:39:50 2015 +0100
mesa: Refactor VertexAttrib[I|L]Format
The only difference between these functions is the legal types and
sizes, so consolidate the code into a single vertex_attrib_format()
function and call it from all three entry points.
Reviewed-by: Laura Ekstrand <laura at jlekstrand.net>
commit 308926853d132a4d096e70447a262bef1e576789
Author: Fredrik Höglund <fredrik at kde.org>
Date: Mon Mar 2 18:37:27 2015 +0100
mesa: Implement VertexArrayVertexBuffers
Reviewed-by: Laura Ekstrand <laura at jlekstrand.net>
commit cc9b68e9c91165ef125338542aebf27a9c8c1406
Author: Fredrik Höglund <fredrik at kde.org>
Date: Mon Mar 2 18:35:10 2015 +0100
mesa: Implement VertexArrayVertexBuffer
Reviewed-by: Laura Ekstrand <laura at jlekstrand.net>
commit c59b5317fc1ad7648b8b945d175b7e1b841c5098
Author: Fredrik Höglund <fredrik at kde.org>
Date: Mon Mar 2 18:33:14 2015 +0100
mesa: Add a vao parameter to bind_vertex_buffer
This is needed to implement VertexArrayVertexBuffer and
VertexArrayVertexBuffers.
Reviewed-by: Laura Ekstrand <laura at jlekstrand.net>
commit 7ccc4f3f2392fa9acbbc034e03e3693c78127f70
Author: Fredrik Höglund <fredrik at kde.org>
Date: Mon Mar 2 18:30:12 2015 +0100
mesa: Implement VertexArrayElementBuffer
v2: Add a doxygen comment.
Reviewed-by: Laura Ekstrand <laura at jlekstrand.net>
commit c99efbd3c2d496dc7e62adf11ab56b7eb006bbc3
Author: Fredrik Höglund <fredrik at kde.org>
Date: Mon Mar 2 18:27:58 2015 +0100
mesa: Implement EnableVertexArrayAttrib
Reviewed-by: Laura Ekstrand <laura at jlekstrand.net>
commit 96b646346372ec0e2b9336ef26e0d2a084b69400
Author: Fredrik Höglund <fredrik at kde.org>
Date: Mon Mar 2 18:27:18 2015 +0100
mesa: Implement DisableVertexArrayAttrib
Reviewed-by: Laura Ekstrand <laura at jlekstrand.net>
commit 6c37acfbedb88b460d2997f8b2d7b0e04a8782df
Author: Fredrik Höglund <fredrik at kde.org>
Date: Mon Mar 2 18:25:45 2015 +0100
mesa: Keep track of the last looked-up VAO
This saves the cost of repeated hash table lookups when the same
vertex array object is referenced in a sequence of calls such as:
glVertexArrayAttribFormat(vao, ...);
glVertexArrayAttribBinding(vao, ...);
glEnableVertexArrayAttrib(vao, ...);
...
Note that VAO's are container objects that are not shared between
contexts.
Reviewed-by: Laura Ekstrand <laura at jlekstrand.net>
commit 2830c2fbeb9601c1760a9fffe45cd04f8c635d25
Author: Fredrik Höglund <fredrik at kde.org>
Date: Mon Mar 2 18:24:36 2015 +0100
mesa: Add _mesa_lookup_vao_err
This is a convenience function that generates GL_INVALID_OPERATION
when the array object doesn't exist.
Reviewed-by: Laura Ekstrand <laura at jlekstrand.net>
commit a1f48268b4ee166eb9fde21bceaaef12a6e0c89a
Author: Fredrik Höglund <fredrik at kde.org>
Date: Mon Mar 2 18:22:50 2015 +0100
mesa: Implement CreateVertexArrays
v2: Update the documentation for gen_vertex_arrays().
Reviewed-by: Laura Ekstrand <laura at jlekstrand.net>
commit e51bad669a4c42845c44a925bbb5d8885799c28f
Author: Neil Roberts <neil at linux.intel.com>
Date: Thu May 7 14:20:17 2015 +0100
i965/skl: In opt_sampler_eot always set destination register to null
opt_sampler_eot enables a direct write to framebuffer from a sample.
In order to do this the sample message needs to have a message header
so if there wasn't one already then the function adds one. In addition
the function sets the destination register to null because it's no
longer used. However it was only doing this in cases where it was
adding a message header. This patch just moves setting the destination
so that it happens even if there's a messge header. In practice this
doesn't seem to make any difference but it's a bit cleaner.
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 1c5de556c5972c3020b4095c586a9b439b20cf69
Author: Neil Roberts <neil at linux.intel.com>
Date: Thu May 7 18:55:55 2015 +0100
i965/fs: Set the header_size on LOAD_PAYLOAD in opt_sampler_eot
Commit 94ee908448 added a header size parameter to the function to
create the LOAD_PAYLOAD instruction. However this broke
opt_sampler_eot which manually constructs the instruction and so
wasn't setting the header_size. This ends up making the parameters for
the send message all have the wrong location and it all falls apart.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit e4b297360780740599afdc93f61bd8be425f0d75
Author: Martin Peres <martin.peres at linux.intel.com>
Date: Thu May 7 16:57:48 2015 +0300
docs: document the LIBGL_DRI3_DISABLE environment variable
Suggested-by: Axel Davy <axel.davy at ens.fr>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Martin Peres <martin.peres at linux.intel.com>
commit ff64411c84b2260fef80516ec4981d70c38aa3ca
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Apr 24 12:50:21 2015 +1000
docs: update ARB_vertex_attrib_64bit status
Add to GL3.txt and release notes.
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit ef83c9b762ee083a2bf1948befdb5dd0fb8df00b
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Feb 20 11:42:19 2015 +1000
st/mesa: add double input support including lowering (v3.1)
This takes a different approach to previously, we cannot index into the
inputMapping with anything but the mesa attribute index, so we can't use
the just add one to index trick, we need more info to add one to it
after we've mapped the input.
(Fixed copy propgation and cleaned up a little)
v2: drop float64 format check, just attr->Doubles.
merge enable patch.
v3: cleanup code a bit.
v3.1: minor review fixups (comment, newline) (Ilia)
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit c4254ee526145ce9bab227264226f5d6f741ff0e
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Feb 20 11:41:01 2015 +1000
mesa/vbo: add support for 64-bit vertex attributes. (v1)
This adds support in the vbo and array code to handle
double vertex attributes.
v0.2: merge code to handle doubles in vbo layer.
v1: don't use v0, merge api_array elt code.
Acked-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit ad208d975a6d3aebe14f7c2c16039ee200d8b30c
Author: Dave Airlie <airlied at redhat.com>
Date: Thu Apr 30 10:42:06 2015 +1000
glsl: check total count of multi-slot double vertex attribs
The spec is vague all over the place about this, but this seems
to be the intent, we can probably make this optional later if
someone makes hw that cares and writes a driver.
Basically we need to double count some of the d types but
only for totalling not for slot number assignment.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 023fc344daae3e38f5e250cd0ea36ea674cd84f9
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Apr 8 14:38:19 2015 +1000
glsl: track which program inputs are doubles
instead of doing the attempts at dual slot handling here,
let the backend do it.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 5d6190e496b4793b5bea667be3f8704135745b9c
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Feb 20 11:38:12 2015 +1000
glsl: add ARB_vertex_attrib_64bit support. (v2)
Just more boilerplate stuff.
v2:
bad fallthrough on versioning,
this is my ugly but self contained solution (Ian)
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit fc71ae7c5705ef1a80f4f43d113c7fb39d49b164
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Feb 20 11:32:55 2015 +1000
mesa: add ARB_vertex_attrib_64bit to extensions. (v2)
Just add the boilerplate bits.
v2: add to version.c
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 5a7f04925f60a0222c66de8e3e4e788a0a550d5b
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Feb 20 11:26:33 2015 +1000
mapi: add GL_ARB_vertex_attrib_64bit support
This just adds the glapi bits.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 731b7c49bb78d6d1be25f9010af0087146de0b48
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Feb 20 13:58:18 2015 +1000
st/glsl_to_tgsi: fix ir_assignment hack doing bad things for doubles
This hack for fixing gl_FragDepth apparantly caused a GLSL shader
outputting a single double to try and output a dvec4, but we hadn't
assigned outputs for the secondary bit.
This avoids going into the hack code for scalar doubles.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit b1119ce838462ff533512188c969fc28ab6a89a9
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Thu May 7 16:07:15 2015 +0300
i965/wm/gen6: Add option for disabling statistics collection
Normally this is always needed but for internal blits and clears
we need to be able to disable it.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit dae7183cdd3a73a14b1b9098d1fc8456dd5a8f93
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Wed May 6 20:31:49 2015 +0300
i965/wm/gen6: Refactor state setup
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit d14f3e14b43fd02ad46f697af53d21c40833452c
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Wed May 6 15:11:42 2015 -0700
i965: Remove unused variables
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 15259d63e808a08d755d2b44efaa62d5a8ca7655
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Wed Apr 15 11:46:53 2015 -0700
i965: Change the order of conditions tested in if
Reduces the number of conditions tested in if to one in case of
non-integer formats. Makes no functional changes.
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 8e029105c2e6959390a68116ac6d1d277815519f
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue May 5 22:54:59 2015 -0700
nir: Allow feq/fne/ieq/ine to be optimized with inot.
instructions in affected programs: 380 -> 376 (-1.05%)
helped: 2
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Glenn Kennard <glenn.kennard at gmail.com>
commit f5cf74d8ba8ce30b9d53b2198e5122ed72f1dcff
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue May 5 20:25:07 2015 -0700
nir: Recognize (a < c || b < c) as min(a, b) < c.
... and (a >= c) || (b >= c) as max(a, b) >= c.
Similar to commit 97e6c1b9.
total instructions in shared programs: 6182276 -> 6182180 (-0.00%)
instructions in affected programs: 6400 -> 6304 (-1.50%)
helped: 68
HURT: 4
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Glenn Kennard <glenn.kennard at gmail.com>
commit ceb8b739ce37ee041b903643656d9d16c371ff95
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue May 5 20:20:30 2015 -0700
nir: Recognize trivial min/max.
No changes, but does prevent some regressions in the next commit.
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Glenn Kennard <glenn.kennard at gmail.com>
commit 8ae559971a692b417acb9fec04386e1e95c619ec
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue May 5 19:56:27 2015 -0700
nir: Recognize i2b(b2i(x)) as x.
Helps the same set of programs as the previous commit.
instructions in affected programs: 4490 -> 4346 (-3.21%)
helped: 8
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Glenn Kennard <glenn.kennard at gmail.com>
commit 74697e2844a0850ef6b91fb4d34bfa3f6f4bff32
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue May 5 19:50:58 2015 -0700
nir: Recognize imul(b2i(a), b2i(b)) as a logical AND.
Four shaders in Unreal 4's Sun Temple are helped, and gain SIMD16
because we avoid an integer multiplication.
instructions in affected programs: 2353 -> 2245 (-4.59%)
helped: 4
GAINED: 4
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Glenn Kennard <glenn.kennard at gmail.com>
commit c636284ee8ee95bb3f3ad31aaf26a9512ec5006c
Author: Chad Versace <chad.versace at intel.com>
Date: Tue May 5 19:05:32 2015 -0700
i965/sync: Implement DRI2_Fence extension
This enables EGL_KHR_fence_sync and EGL_KHR_wait_sync.
Below is the difference in piglit results, before and after this patch.
No regressions and several tests improve from 'skip' to 'pass'. Out of
EGL_KHR_fence_sync tests, two of the multithreaded tests skip; all other
tests pass.
cmdline: piglit run -p gbm -t sync tests/quick.py
mesa: master at 1ac7db0
piglit: 4069bec
hw: Ivybridge
| before after
------+-------------
pass | 32 46
fail | 0 0
crash | 0 0
skip | 35 21
total | 67 67
v2:
- Set fence->signalled = true in brw_fence_has_completed() too.
Reviewed-by: Daniel Stone <daniels at collabora.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 2516d835b17563b097efa3a980c3b9b5e77d7f00
Author: Chad Versace <chad.versace at intel.com>
Date: Tue May 5 19:05:32 2015 -0700
i965/sync: Replace prefix 'intel_sync' -> 'intel_gl_sync'
I'm about to implement DRI2_Fenc in intel_syncobj.c. To prevent
madness, we need to prefix functions for GL_ARB_sync with 'gl' and
functions for DRI2_Fence with 'dri'. Otherwise, the file will become
a jumble of similiarly named functions.
For example:
old-name: intel_client_wait_sync()
new-name: intel_gl_client_wait_sync()
soon-to-come: intel_dri_client_wait_sync()
I wrote this renaming commit separately from the commit that implements
DRI2_Fence because I wanted the latter diff to be reviewable.
Reviewed-by: Daniel Stone <daniels at collabora.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 19b5a82fdafd583317265e86fd13c23e52839131
Author: Chad Versace <chad.versace at intel.com>
Date: Tue May 5 19:05:31 2015 -0700
i915/sync: Return early when calloc fails
Reviewed-by: Daniel Stone <daniels at collabora.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 00f3c7baeb3e8f00ce7bc8a1384ef545e648f1d9
Author: Chad Versace <chad.versace at intel.com>
Date: Tue May 5 19:05:30 2015 -0700
i965/sync: Return NULL when calloc fails
Reviewed-by: Daniel Stone <daniels at collabora.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 9cf9a2dec5b3fe3aad878b8ab99d50fbd51e1b9c
Author: Chad Versace <chad.versace at intel.com>
Date: Tue May 5 19:05:29 2015 -0700
i915/sync: Don't crash when deleting sync object
Don't pass NULL to drm_intel_bo_unreference(). It doesn't like that.
Bug found by code inspection.
Reviewed-by: Daniel Stone <daniels at collabora.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit a93ab73a074e0c25ff5ceca7fc1141a9bea82c8f
Author: Chad Versace <chad.versace at intel.com>
Date: Tue May 5 19:05:28 2015 -0700
i965/sync: Don't crash when deleting sync object
Don't pass NULL to drm_intel_bo_unreference(). It doesn't like that.
Bug found by code inspection.
Reviewed-by: Daniel Stone <daniels at collabora.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit a6bfdd7b46170bd8105303063717c45f7e6fafee
Author: Chad Versace <chad.versace at intel.com>
Date: Thu May 7 08:09:07 2015 -0700
egl/dri2: Fix codestyle in a comment
Pointed out by Kenneth Graunke. Trivial fix.
commit cedd5008dad7750835cc4a4a318afc82fe351eac
Author: Martin Peres <martin.peres at linux.intel.com>
Date: Wed May 6 13:31:30 2015 +0300
glx: report which DRI version is used when in verbose debug mode
This should make it more obvious in bug reports while also removing
any sort of guesswork for developers.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Martin Peres <martin.peres at linux.intel.com>
commit cf5e015f71496e0626cd5c6262af1c5099391850
Author: Vinson Lee <vlee at freedesktop.org>
Date: Wed May 6 12:39:09 2015 -0700
glapi: Add positional argument specifier.
Fix build error introduced with commit 1c5a57a "glapi/es3.1: Add support
for GLES versions > 3.0" with Python < 2.7.
File "src/mapi/glapi/gen/gl_genexec.py", line 230, in <module>
printer.Print(api)
File "src/mapi/glapi/gen/gl_XML.py", line 120, in Print
self.printBody(api)
File "src/mapi/glapi/gen/gl_genexec.py", line 187, in printBody
condition_parts.append('(ctx->API == API_OPENGLES2 && ctx->Version >= {})'.format(int(f.api_map['es2'] * 10)))
ValueError: zero length field name in format
Signed-off-by: Vinson Lee <vlee at freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 55b66dc4dee489e43b8e7a170fbc9ddd19a33aac
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed May 6 20:48:40 2015 -0400
nv50/ir: add SHL to the list of U32 opcodes
Having the wrong inferred type prevents a number of optimizations,
including constant propagation (since float immediates work differently
than integer immediates).
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 51e3453785bc57087bb868dc93afbf620935b703
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Apr 21 13:43:32 2015 +0900
i965: Sort extension enable lists
Sort by GEN, then sort by extension name.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 382b1a36e33c2d1f985996ecea54bdda547587d7
Author: Vinson Lee <vlee at freedesktop.org>
Date: Wed May 6 10:09:38 2015 -0700
r600g: Fix Clang return-type build error.
Fix Clang return-type error introduced with commit
96f164f6f047833091eb98a73aa80c31dc94f962 "gallium: make
pipe_context::begin_query return a boolean".
CC r600_query.lo
r600_query.c:443:3: error: non-void function 'r600_begin_query' should return a value [-Wreturn-type]
return;
^
Signed-off-by: Vinson Lee <vlee at freedesktop.org>
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
commit 0c0ca557117edd3a57443f4f454c3a8da1d4e0b5
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Mar 10 04:18:06 2015 -0700
i965/fs: Allow copy propagation on ATTR file registers.
This especially helps with NIR because we currently emit MOVs at the top
of the shader to copy from various ATTR registers to a giant VGRF array
of all inputs. (This could potentially be done better, but since
there's only ever one write to each register, it should be trivial to
copy propagate away...)
With NIR - only vertex shaders:
total instructions in shared programs: 3129373 -> 2889581 (-7.66%)
instructions in affected programs: 3119717 -> 2879925 (-7.69%)
helped: 20833
Without NIR - only vertex shaders:
total instructions in shared programs: 2745901 -> 2724483 (-0.78%)
instructions in affected programs: 693426 -> 672008 (-3.09%)
helped: 3516
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 7a75b55a01d355090d186357896e3cb141b9775e
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Apr 1 18:15:42 2015 -0700
i965/fs_inst: Get rid of the effective_width field
The effective_width field was an ill-concieved hack to get around issues in
the LOAD_PAYLOAD instruction. Now that the LOAD_PAYLOAD instruction is far
more sane, this field can die.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 41868bb6824c6106a55c8442006c1e2215abf567
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Mar 24 17:00:04 2015 -0700
i965/fs: Rework the fs_visitor LOAD_PAYLOAD instruction
The newly reworked instruction is far more straightforward than the
original. Before, the LOAD_PAYLOAD instruction was lowered by a the
complicated and broken-by-design pile of heuristics to try and guess
force_writemask_all, exec_size, and a number of other factors on the
sources.
Instead, we use the header_size on the instruction to denote which sources
are "header sources". Header sources are required to be a single physical
hardware register that is copied verbatim. The registers that follow are
considered the actual payload registers and have a width that correspond's
to the LOAD_PAYLOAD's exec_size and are treated as being per-channel. This
gives us a fairly straightforward lowering:
1) All header sources are copied directly using force_writemask_all and,
since they are guaranteed to be a single register, there are no
force_sechalf issues.
2) All non-header sources are copied using the exact same force_sechalf
and force_writemask_all modifiers as the LOAD_PAYLOAD operation itself.
3) In order to accommodate older gens that need interleaved colors,
lower_load_payload detects when the destination is a COMPR4 register
and automatically interleaves the non-header sources. The
lower_load_payload pass does the right thing here regardless of whether
or not the hardware actually supports COMPR4.
This patch commit itself is made up of a bunch of smaller changes squashed
together. Individual change descriptions follow:
i965/fs: Rework fs_visitor::LOAD_PAYLOAD
We rework LOAD_PAYLOAD to verify that all of the sources that count as
headers are, indeed, exactly one register and that all of the non-header
sources match the destination width. We then take the exec_size for
LOAD_PAYLOAD directly from the destination width.
i965/fs: Make destinations of load_payload have the appropreate width
i965/fs: Rework fs_visitor::lower_load_payload
v2: Don't allow the saturate flag on LOAD_PAYLOAD instructions
i965/fs_cse: Support the new-style LOAD_PAYLOAD
i965/fs_inst::is_copy_payload: Support the new-style LOAD_PAYLOAD
i965/fs: Simplify setup_color_payload
Previously, setup_color_payload was a a big helper function that did a
lot of gen-specific special casing for setting up the color sources of
the LOAD_PAYLOAD instruction. Now that lower_load_payload is much more
sane, most of that complexity isn't needed anymore. Instead, we can do
a simple fixup pass for color clamps and then just stash sources
directly in the LOAD_PAYLOAD. We can trust lower_load_payload to do the
right thing with respect to COMPR4.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 94ee908448405c8271e8662914a1c49df8d623b2
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Mar 24 10:37:33 2015 -0700
i965/fs: Make LOAD_PAYLOAD take a header size
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 74dccdad4b018dd37a2e8ba49f502e17edbea9ab
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Mar 24 13:55:10 2015 -0700
i965/fs: Make emit_single_fb_write take an explicit exec_size
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 32af7d4188e286a525081ada9965070dd41dbab7
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Apr 1 15:38:23 2015 -0700
i965/fs_inst: Add an is_copy_payload helper
This commit adds a new is_copy_payload helper to fs_inst that takes the
place of the similarly named functions in cse and register coalesce. The
two is_copy_payload functions in CSE and register coalesce were subtly
different and potentially subtly broken. The new version unifies the two
and should be more correct.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 76c1086f2dfb37a1edf6d2df6eebbe11ccbfc50b
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Mar 24 10:17:32 2015 -0700
i965: Change header_present to header_size in backend_instruction
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit a9ccb14d141de57487933d9535479acd3612aa9e
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Mar 24 15:06:24 2015 -0700
i965/fs_cse: Factor out code to create copy instructions
v2: Get rid of the block parameter and make src a const reference
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit cf4607e85339c3cfd6ab5fd4a28985c9fafb0b86
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue May 5 15:57:11 2015 -0700
i965/fs: Make half(fs_reg, unsigned) handle register files more explicitly
Previously, we had a special case for uniforms and immediates and then a
bunch of asserts for various other pessimal things. This commit changes it
so that it explicitly does something on each register file. Some of them
are disallowed and others are treated properly.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 88414de45e723a7fe8f052a3ab616aa7bc568519
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Apr 22 15:01:24 2015 +0300
i965/fs: Fix passing an immediate to half().
Immediates are generally uniform, they yield the same value to both
halves of any instruction.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 5b2d3480f57168d50ad24cf0b8c9244414bd3701
Author: Jeremy Huddleston Sequoia <jeremyhu at apple.com>
Date: Thu Jan 1 19:48:40 2015 -0800
swrast: Build fix for darwin
Fixes regression from commit 64b1dc44495890cbc2c7c5509cb830264020998c
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90147
Signed-off-by: Jeremy Huddleston Sequoia <jeremyhu at apple.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
CC: Emil Velikov <emil.l.velikov at gmail.com>
CC: jon.turney at dronecode.org.uk
CC: ionic at macports.org
commit b0f410a2a05e046c31c32e169b9463cb6b4af8ae
Author: Chad Versace <chad.versace at intel.com>
Date: Tue May 5 19:05:20 2015 -0700
egl/dri2: Check return value of __DRI2fence::create_fence()
If it returns NULL, then return early with an error.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit b8a1495106a8b70e9026b7798a5df2fb9737c55e
Author: Roland Scheidegger <sroland at vmware.com>
Date: Wed May 6 15:56:17 2015 +0200
draw: (trivial) fix out-of-bounds vector initialization
Was off-by-one. llvm says inserting an element with an index higher than the
number of elements yields undefined results. Previously such inserts were
ignored but as of llvm revision 235854 the vector gets replaced with undef,
causing failures.
This fixes piglit gl-3.2-layered-rendering-gl-layer, as mentioned in
https://llvm.org/bugs/show_bug.cgi?id=23424.
Reviewed-by: Brian Paul <brianp at vmware.com>
Cc: mesa-stable at lists.freedesktop.org
commit 9891fc329b2d43c8433bec6d715b6b1684ea31c5
Author: Martin Peres <martin.peres at linux.intel.com>
Date: Mon May 4 16:59:54 2015 +0300
main/queryobj: add GL_QUERY_TARGET support to GetQueryObjectiv()
This was missing from my patchset to support the query-related entry
points of Direct State Access.
Reported-by: Ilia Mirkin <imirkin at alum.mit.edu>
Signed-off-by: Martin Peres <martin.peres at linux.intel.com>
commit ef5d4bcc3a21f1aa3e6a919c8888f26ec754707f
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Wed May 6 16:32:28 2015 +0800
ilo: silence a compiler warning
Silence
ilo_query.c:120:7: warning: 'return' with no value, in function returning non-void
since commit 96f164f6.
commit 818cc90535404d76b69b22145f203106491d86a2
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Wed May 6 09:36:15 2015 +0300
mesa: support compute stage in _mesa_program_resource_prop
Increases pass rate of ES31-CTS.*program_interface_query* tests
when run with MESA_EXTENSION_OVERRIDE='GL_ARB_compute_shader'. Many
of the negative tests that happen to use compute stage in queries
start passing.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
commit 3706e5dbc96aa9cc29c58dad661aa10f20574503
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Thu Apr 30 09:27:00 2015 +0300
glsl: mark special built-in inputs referenced by vertex stage
Refactoring done on active attribute queries did not take in to
account special built-in inputs for the vertex stage. This commit
sets them referenced by vertex stage so that they get enumerated
properly.
Fixes Piglit test 'get-active-attrib-returns-all-inputs' failure.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90243
Acked-by: Jose Fonseca <jfonseca at vmware.com>
Tested-by: Dieter Nützel <Dieter at nuetzel-hh.de>
Reviewed-By: Martin Peres <martin.peres at linux.intel.com>
commit 1fcdb2ce794d14545b06640b2316c629a3bde3ee
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Wed May 6 19:05:17 2015 +1200
relnotes: Note support for viewport arrays on i965/Gen6.
Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
commit 5fc23375e80dd2084f30700bdd3216082f662acc
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Wed May 6 17:45:11 2015 +1200
i965/gen6: Enable ARB_viewport_array and AMD_vertex_shader_viewport_index
Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit c41f6252006e9730097b1dab01f6dff1769413de
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Wed May 6 17:35:37 2015 +1200
i965/gen6: Upload all the SF viewports
Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 2a8835d4854a49087fb032a927209dac50dfa827
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Wed May 6 17:34:27 2015 +1200
i965/gen6: Upload all the clip viewports
Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 0374159b0ce3c4634364ca5ab257e305765d4879
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Wed May 6 14:43:34 2015 +1200
i965/gen6: setup limits for ARB_viewport_array
Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 212f26bb6070d6a1ddb9513d32233614a993e1d4
Author: Brian Paul <brianp at vmware.com>
Date: Tue May 5 15:49:56 2015 -0600
st/mesa: fix pipe_query_result result initializer
Fixes MSVC build error.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 062e2b06b2978efad2cc3ab61e2eda0a1111f043
Author: Brian Paul <brianp at vmware.com>
Date: Tue May 5 15:42:34 2015 -0600
st/mesa: fix st_NewPerfMonitor() declaration
Was missing the context parameter. Fixes MSVC warning.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 0beaf1cd9a9a882b4f896dc1865622d72488ff31
Author: Brian Paul <brianp at vmware.com>
Date: Tue May 5 15:41:15 2015 -0600
glsl: add parens in shader_integer_mix() to silence compiler warning
Silences gcc warning:
builtin_functions.cpp:204:23: warning: suggest parentheses around '&&'
within '||' [-Wparentheses]
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit f7bdb2f3724808d6a280471847300abe192d4f5a
Author: Brian Paul <brianp at vmware.com>
Date: Tue Apr 28 15:48:56 2015 -0600
st/mesa: also try PIPE_FORMAT_R10G10B10A2_UNORM for GL_RGB10
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit cea910bc28d5647ae5a9f66abe0c9ef75ab1c69b
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Tue Jul 8 14:23:01 2014 +0200
nvc0: all queries use an unsigned 64-bits integer by default
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Martin Peres <martin.peres at free.fr>
commit 35a9286be67c0520093c521b7c9cc0ba25fa4cc2
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Sat Jul 5 12:54:26 2014 +0200
nvc0: make begin_query return false when all MP counters are used
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Martin Peres <martin.peres at free.fr>
commit 3a365df6657e1d7b54d82fe0bc58e76e44b4cb5c
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Tue Jul 8 00:43:59 2014 +0200
docs: mark GL_AMD_performance_monitor on nvc0 for the 10.6.0 release
Other drivers which want to enable this extension must expose groups of
GPU hardware performance counters.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Martin Peres <martin.peres at free.fr>
commit ed7d3886cc25240ad92055b7813e038ba1a5e77c
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Fri Jul 4 11:43:53 2014 +0200
nvc0: define driver-specific query groups
This patch defines "Driver statistics" and "MP counters" groups, but
only the latter will be exposed through GL_AMD_performance_monitor.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Martin Peres <martin.peres at free.fr>
commit 4cd1cfb9831d4d4081cbe80b0d72b340c8fd0c2c
Author: Christoph Bumiller <e0425955 at student.tuwien.ac.at>
Date: Fri Jul 4 13:02:06 2014 +0200
st/mesa: implement GL_AMD_performance_monitor
This is based on the original patch of Christoph Bumiller.
v2 (Samuel Pitoiset):
- improve Gallium interface for this extension
- rewrite some parts of the original code
- fix compilation errors and piglit tests
v3:
- only enable this extension when the underlying driver expose GPU counters
- get rid of the ring buffer of queries
v4:
- add a debug message when the maximum number of counters has been
reached
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Martin Peres <martin.peres at free.fr>
commit 96f164f6f047833091eb98a73aa80c31dc94f962
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Sat Jul 5 12:46:03 2014 +0200
gallium: make pipe_context::begin_query return a boolean
GL_AMD_performance_monitor must return an error when a monitoring
session cannot be started.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Martin Peres <martin.peres at free.fr>
commit 546ec980f850fee067fd1dddad19a8dfd6b7e672
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Mon Jul 7 23:49:14 2014 +0200
gallium: replace pipe_driver_query_info::max_value by a union
This allows queries to return different numeric types.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Martin Peres <martin.peres at free.fr>
commit d5b2832c1151337d37217a30bcb55d7f90dd1b47
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Wed Jul 9 13:00:37 2014 +0200
gallium: add new numeric types to pipe_query_result
This will be used by GL_AMD_performance_monitor.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Martin Peres <martin.peres at free.fr>
commit b620829b5e4364e9d5ed30e8603de41087ff454f
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Fri Jul 4 11:41:46 2014 +0200
gallium: add new fields to pipe_driver_query_info
According to the spec of GL_AMD_performance_monitor, valid type values
returned are UNSIGNED_INT, UNSIGNED_INT64_AMD, PERCENTAGE_AMD, FLOAT.
This also introduces the new field group_id in order to categorize
queries into groups.
v2: add PIPE_DRIVER_QUERY_TYPE_BYTES
v3: fix incorrect query type for radeon and svga drivers
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Martin Peres <martin.peres at free.fr>
commit f137f5c691f5bd97a8b7f881f1f6837bff0ebc7a
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Fri Jul 4 11:24:02 2014 +0200
gallium: add pipe_screen::get_driver_query_group_info
Driver queries are organized as a single hierarchy where queries are
categorized into groups. Each group has a list of queries and a maximum
number of queries that can be sampled. The list of available groups can
be obtained using pipe_screen::get_driver_query_group_info.
This will be used by GL_AMD_performance monitor.
v2: add group type (CPU/GPU)
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Martin Peres <martin.peres at free.fr>
commit ce01c0af70f2475fbbb1c3ab90d43a19047abc5c
Author: Tim Rowley <timothy.o.rowley at intel.com>
Date: Mon May 4 16:54:27 2015 -0500
mesa: fix shininess check for ffvertex_prog v2
Switch to using VERT_BIT_GENERIC macro, as varying_vp_inputs is a
bitmask.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org
commit 24ecf37ac070bd3c49b8e1146abe47ab24134191
Author: Marius Predut <marius.predut at intel.com>
Date: Thu Apr 23 18:41:29 2015 +0300
i965/aa: fixing anti-aliasing bug for thinnest width lines - GEN7
On SNB and IVB hw, for 1 pixel line thickness or less,
the general anti-aliasing algorithm give up - garbage line is generated.
Setting a Line Width of 0.0 specifies the rasterization of
the “thinnest†(one-pixel-wide), non-antialiased lines.
Lines rendered with zero Line Width are rasterized using
Grid Intersection Quantization rules as specified
by bspec section 6.3.12.1 Zero-Width (Cosmetic) Line Rasterization.
v2: Daniel Stone: Fix = used instead of == in an if-statement.
v3: Ian Romanick: Use "._Enabled" flag insteed ".Enabled".
Add code comments. re-word wrap the commit message.
Add a complete bugzillia list.
Improve the hardcoded values to produce better results.
v4: Matt Turner: typo fixes and adjust <= 1.49 to become < 1.5
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=28832
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=9951
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=27007
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60797
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=15006
Acked-by: Chris Forbes <chrisf at ijw.co.nz>
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Marius Predut <marius.predut at intel.com>
commit d376c3549b2d9c764d92e2c1e46b20e9c04223a4
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue May 5 11:46:56 2015 -0700
i965: Fix missing type in local variable declaration.
Trivial. Fixes the following compiler warning (from GCC 5.1.0):
brw_context.c:629:10: warning: type defaults to ‘int’ in declaration
of ‘simd_size’ [-Wimplicit-int]
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
commit 07b49f126a6b52b3b7dac8e332975d5f6ca9adfe
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue May 5 11:35:51 2015 -0700
i965/vec4: Use same type for immediate, for compaction.
commit a9b04d8a0d96922a49ac7eb1b91b3a376a959f64
Author: Marius Predut <marius.predut at intel.com>
Date: Thu Apr 23 18:41:14 2015 +0300
i965/aa: fixing anti-aliasing bug for thinnest width lines - GEN6
On SNB and IVB hw, for 1 pixel line thickness or less,
the general anti-aliasing algorithm give up - garbage line is generated.
Setting a Line Width of 0.0 specifies the rasterization of
the “thinnest†(one-pixel-wide), non-antialiased lines.
Lines rendered with zero Line Width are rasterized using
Grid Intersection Quantization rules as specified
by bspec section 6.3.12.1 Zero-Width (Cosmetic) Line Rasterization.
v2: Daniel Stone: Fix = used instead of == in an if-statement.
v3: Ian Romanick: Use "._Enabled" flag insteed ".Enabled".
Add code comments. re-word wrap the commit message.
Add a complete bugzillia list.
Improve the hardcoded values to produce better results.
v4: Matt Turner: typo fixes and adjust <= 1.49 to become < 1.5
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=28832
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=9951
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=27007
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60797
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=15006
Acked-by: Chris Forbes <chrisf at ijw.co.nz>
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Marius Predut <marius.predut at intel.com>
commit 6da2d7188866ddc8e461004dfae4332071ec3015
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Apr 21 14:45:19 2015 -0700
i965: Remove end-of-thread SEND alignment code.
This was present in Eric's initial implementation of the compaction code
for Sandybridge (commit 077d01b6). There is no documentation saying this
is necessary, and removing it causes no regressions in piglit on any
platform.
commit 28090b30dd6b5977de085f48c620574214b6b4ba
Author: Boyan Ding <boyan.j.ding at gmail.com>
Date: Wed Mar 25 19:36:54 2015 +0800
i965: Add XRGB8888 format to intel_screen_make_configs
Some application, such as drm backend of weston, uses XRGB8888 config as
default. i965 doesn't provide this format, but before commit 65c8965d,
the drm platform of EGL takes ARGB8888 as XRGB8888. Now that commit
65c8965d makes EGL recognize format correctly so weston won't start
because it can't find XRGB8888. Add XRGB8888 format to i965 just as
other drivers do.
Cc: mesa-stable at lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89689
Signed-off-by: Boyan Ding <boyan.j.ding at gmail.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 8da47e8a69a2f7feed99fed6aae02d6e6aa74ddc
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Tue May 5 14:39:08 2015 +0100
nir: add nir_array.h to the sources list
Otherwise `make distcheck' will fail.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 08a4639e81f20954b2d78b0ff5bc268731372570
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Mon Feb 9 10:36:36 2015 +0100
glsl: don't lower fragdata array if the output data types don't match
Commit 7e414b58640aee6e243d337e72cea290c354f632 broke the gl_FragData array
into separate gl_FragData[i] variables, so drivers can eliminate useless
writes to gl_FragData improving their performance.
The problem occurs when GLSL IR code is linked in the following case:
* The FS output variable base data type does not match gl_FragData one (float
vector)
* The FS output variable is replaced by gl_out_FragDataX because of commit
7e414b58640aee6 with X from 0 to GL_MAX_DRAW_BUFFERS.
Then the FS output variable base data type is lost in the resulting GLSL IR,
making that the driver does a wrong assignment to gl_out_FragData components
because of unmatching data types.
This patch reverts the fragdata array lowering when the output var base data type
doesn't match gl_out_FragData, i.e., when output variable base data type is
not a float or a float vector.
This patch fixes 250 dEQP tests (tested in an Intel Haswell machine)
dEQP-GLES3.functional.fragment_out.random.* (22 failed tests)
dEQP-GLES3.functional.fragment_out.array.uint.* (120 failed tests)
dEQP-GLES3.functional.fragment_out.array.int.* (108 failed tests)
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 4ab8d59a23e0142239dad66155b1a7a149755325
Author: Neil Roberts <neil at linux.intel.com>
Date: Thu Feb 19 19:33:43 2015 +0000
i965/skl: Align compressed textures to four times the block size
On Skylake it is possible to choose your own alignment values for
compressed textures but they are expressed as a multiple of the block
size. The minimum alignment value we can use is 4 so we effectively
have to align to 4 times the block size. This patch makes it initially
set mt->align_[wh] to the large alignment value and then later divides
it by the block size so that it can be uploaded as part of the surface
state.
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit b5045e29917a783be74becee5e72566e2b0e3535
Author: Dave Airlie <airlied at redhat.com>
Date: Tue May 5 09:10:34 2015 +1000
egl: image_dma_buf_export - use KHR 64-bit type
After talking to Jon Leech he suggested this should be fine.
update spec to the version in the registry.
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 1c5a57aee109ef513df0d281aadc69db293cc3d8
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Apr 29 13:15:06 2015 -0700
glapi/es3.1: Add support for GLES versions > 3.0
Make the checks in the Python script and the generated code more generic
to support arbitrary GLES versions >= 2.0.
The updated dispatch_sanity.cpp test discovered this problem. Without
this, the next patch would erroneously enable GLES 3.1 functions in GLES
2.0 and GLES 3.0.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 23d2f63b588fba37a2362db61927aff862333a71
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Apr 28 15:12:58 2015 -0700
glsl/es3.1: Allow misc ARB_gpu_shader5 built-ins in GLSL ES 3.10
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit cea605d373673878f6911906dce78b3c9bdce622
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Apr 28 15:00:22 2015 -0700
glsl/es3.1: Allow textureGather and textureGatherOffset in GLSL ES 3.10
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 0e1655c6bdf2d8efa5e2030ea36e59c098f82540
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Apr 28 14:38:13 2015 -0700
glsl/es3.1: Allow enhnaced packing functions in GLSL ES 3.10
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit ad14f44b3e89cf4d05d29f2aaf9f64fe0e42af3b
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Apr 28 12:50:51 2015 -0700
glsl/es3.1: Allow interger mix built-ins in GLSL ES 3.10
v2: Add missing lexer support. Noticed by Tapani.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu> [v1]
commit dd61475d56f3b94c3586889333931ebe50a32c3e
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Apr 28 12:46:46 2015 -0700
glsl/es3.1: Allow separate shader objects in GLSL ES 3.10
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 2dcc535300d57a8ec50337df54438faa17a82745
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Apr 28 12:38:46 2015 -0700
glsl/es3.1: Allow explicit uniform locations in GLSL ES 3.10
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 7038370bd166a8d6f4a24db05da70f713ef7ed37
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Apr 28 12:13:21 2015 -0700
glsl/es3.1: Allow 3.10 ES shaders in a GLES 3.1 context
Currently no 3.10 ES features (beyond 3.00 ES) are enabled. That will
come later.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 7efc11e071a6f80611539a1c135cc2bd65a47f8c
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Apr 28 11:58:56 2015 -0700
mesa/es3.1: Add _mesa_is_gles31 helper
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 56030a75eddca225abe3618c03b027fd136e03aa
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Apr 28 18:01:00 2015 -0700
docs/GL3: Update GLES 3.1 dependencies
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 6c9c317cafdaefdec01389778fd96300022c37ab
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Apr 28 13:15:46 2015 -0700
glsl: Add glsl_parser_state::has_atomic_counters helper
v2: Change GL version from 400 to 420. Noticed by Tapani and Ilia.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit fa3475b26931fceeeda7ee7f5ffa61927aacaafb
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Apr 28 11:57:39 2015 -0700
mesa: Use bool in _mesa_is_ helpers instead of GLboolean
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Dylan Baker <baker.dylan.c at gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 1ec6523fcfa7c55af6bcaae9375f41d4c06271eb
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Apr 28 11:26:33 2015 -0700
mesa: Trivial coding standards cleanups
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Dylan Baker <baker.dylan.c at gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 5a845cf898897cd3a4cdd752ab7e355e89b416fa
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Apr 28 11:18:42 2015 -0700
mesa: Use bool instead of GLboolean
v2: Squash in whitespace fixes.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Dylan Baker <baker.dylan.c at gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 8b103cf636759d2f0e8488220063133b6ca58f1f
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Apr 22 08:58:59 2015 +0900
glsl: Silence unused parameter warnings
I opted to comment out "last_field" because it was not obvious what the
meaning of the dangling bool would be. For the other parameters, the
meaning was more intuitive without the name.
link_uniform_blocks.cpp:70:65: warning: unused parameter 'name' [-Wunused-parameter]
virtual void enter_record(const glsl_type *type, const char *name,
^
link_uniform_blocks.cpp:77:65: warning: unused parameter 'name' [-Wunused-parameter]
virtual void leave_record(const glsl_type *type, const char *name,
^
link_uniform_blocks.cpp:93:62: warning: unused parameter 'record_type' [-Wunused-parameter]
bool row_major, const glsl_type *record_type,
^
link_uniform_blocks.cpp:94:34: warning: unused parameter 'last_field' [-Wunused-parameter]
bool last_field)
^
link_uniforms.cpp:547:65: warning: unused parameter 'name' [-Wunused-parameter]
virtual void enter_record(const glsl_type *type, const char *name,
^
link_uniforms.cpp:556:65: warning: unused parameter 'name' [-Wunused-parameter]
virtual void leave_record(const glsl_type *type, const char *name,
^
link_uniforms.cpp:567:34: warning: unused parameter 'last_field' [-Wunused-parameter]
bool last_field)
^
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Dylan Baker <baker.dylan.c at gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit 778c7f149a0e29d135b05f27bb0a6837decdb533
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Apr 29 11:53:18 2015 -0700
mesa: Restore functionality to dispatch sanity test
Along with a couple secondary goals, the dispatch sanity test had two
major, primary goals.
1. Ensure that all functions part of an API version are set in the
dispatch table.
2. Ensure that functions that cannot be part of an API version are not
set in the dispatch table.
Commit 4bdbb58 removed the tests ability to fulfill either of its
primary goals by removing anything that used _mesa_generic_nop(). It
seems like the problem on Windows could have been resolved by adding the
NULL context pointer check from nop_handler to _mesa_generic_nop().
There is, however, some debugging benefit to actually getting the
(supposed) function name logged in the "unsupported function called"
message.
The preceding commit added a function, _glapi_new_nop_table, that
allocates a table of per-entry point no-op functions. Restore the
ability to actually validate the sanity of the dispatch table by using
_glapi_new_nop_table.
Previous to this commit removing a function from one of the
*_functions_possible lists would not cause the test to fail. With this
commit removing such a function will result in failure, as is expected.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit e1ae0c3bc37be7b1de21ee248d674671d01da8e6
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Feb 19 14:49:10 2015 +0200
i965: Fix variable indexing of sampler arrays under non-uniform control flow.
ARB_gpu_shader5 requires sampler array indexing expressions to be
dynamically uniform, this however doesn't have any implications on the
control flow that leads to the evaluation of that expression being
uniform. Use emit_uniformize() to obtain an arbitrary live value from
the binding table index calculation instead of assuming that the first
channel is always live.
Fixes the following Piglit test cases:
arb_gpu_shader5/execution/sampler_array_indexing/fs-nonuniform-control-flow.shader_test
arb_gpu_shader5/execution/sampler_array_indexing/vs-nonuniform-control-flow.shader_test
part of the series:
http://lists.freedesktop.org/archives/piglit/2015-February/014615.html
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit b234537cc3e513ded9b5385d876e4c531f72af94
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Feb 19 14:48:29 2015 +0200
i965: Fix variable indexing of UBO arrays under non-uniform control flow.
ARB_gpu_shader5 requires UBO array indexing expressions to be
dynamically uniform, this however doesn't have any implications on the
control flow that leads to the evaluation of that expression being
uniform. Use emit_uniformize() to obtain an arbitrary live value from
the binding table index calculation instead of assuming that the first
channel is always live.
Fixes the following Piglit tests:
arb_gpu_shader5/execution/ubo_array_indexing/fs-nonuniform-control-flow.shader_test
arb_gpu_shader5/execution/ubo_array_indexing/vs-nonuniform-control-flow.shader_test
part of the series:
http://lists.freedesktop.org/archives/piglit/2015-February/014616.html
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 046abc998c6951ea8a4aee0a2c1b832f6c877b73
Author: Francisco Jerez <currojerez at riseup.net>
Date: Fri Mar 20 14:16:09 2015 +0200
i965: Define helper function to copy an arbitrary live component from some register.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 3da9f708d4f1375d674fae4d6c6eb06e4c8d9613
Author: Francisco Jerez <currojerez at riseup.net>
Date: Fri Feb 20 20:25:04 2015 +0200
i965: Perform basic optimizations on the FIND_LIVE_CHANNEL opcode.
v2: Save some CPU cycles by doing 'return progress' rather than
'depth++' in the discard jump special case.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 715bc6d8b16a0bbdc17fe1e1e46b88a679bf312b
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Apr 23 14:42:53 2015 +0300
i965: Introduce the FIND_LIVE_CHANNEL pseudo-opcode.
This instruction calculates the index of an arbitrary channel enabled
in the current execution mask. It's expected to be used as input for
the BROADCAST opcode, but it's implemented as a separate instruction
rather than being baked into BROADCAST because FIND_LIVE_CHANNEL has
no dependencies so it can always be CSE'ed with other instances of the
same instruction within a basic block.
v2: Whitespace fixes.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit f2fad0dc80627e853eea558498f18a9fa769992e
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Feb 19 14:52:24 2015 +0200
i965: Perform basic optimizations on the BROADCAST opcode.
v2: Style fixes.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit c74511f5dc239eefb8604294c6c1e57b3a394111
Author: Francisco Jerez <currojerez at riseup.net>
Date: Fri Feb 20 20:14:24 2015 +0200
i965: Introduce the BROADCAST pseudo-opcode.
The BROADCAST instruction picks the channel from its first source
given by an index passed in as second source. This will be used in
situations where all channels from the same SIMD thread have to agree
on the value of something, e.g. a surface binding table index.
This is in particular the case for UBO, sampler and image arrays,
which can be indexed dynamically with the restriction that all active
SIMD channels access the same index, provided to the shared unit as
part of a single scalar field of the message descriptor. Simply
taking the index value from the first channel as we were doing until
now is incorrect, because it might contain an uninitialized value if
the channel had previously been disabled by non-uniform control flow.
v2: Minor style fixes. Improve commit message.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit ce0e15172157b6fa11feabb3ff0672abfb273884
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jan 28 17:42:37 2015 +0200
glsl: Keep track of the early_fragment_tests flag in gl_shader.
And rename _mesa_glsl_parse_state::early_fragment_tests to
fs_early_fragment_tests for consistency with other FS-specific flags in the
same struct.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 6c1f6f8291859209a9b585f65258e090d91f0347
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Dec 4 10:54:13 2014 +0200
glsl: Error out on invalid uses of the early_fragment_tests layout qualifier.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit b5994d24d821082965636a5fe6e94079975777d0
Author: Francisco Jerez <currojerez at riseup.net>
Date: Sat Jan 31 22:07:47 2015 +0200
glsl: Forbid use of image qualifiers in declarations of type other than image.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 3f8558650d0db1f0f7a5a03cc781cbf2785cc2c8
Author: Francisco Jerez <currojerez at riseup.net>
Date: Sat Jan 31 22:01:35 2015 +0200
glsl: Split off memory qualifiers from storage qualifiers.
Image memory qualifiers (coherent, volatile, restrict, readonly and writeonly)
follow slightly different rules from storage qualifiers, e.g. the uniqueness
rule doesn't apply. Make them a separate non-terminal.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit f64edfdc44d955adfe3e99154559e7935a2efd45
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Dec 4 10:42:11 2014 +0200
glsl: Forbid opaque variables as operands of the ternary operator.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit b5854ee72b25078616f04b49004011036fef5a87
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Jan 21 16:47:02 2015 +0200
mesa: Update image unit state when glBindImageTexture is called with texture=0.
There's no indication in the spec that the image unit state other than the
bound texture object shouldn't be updated when glBindImageTexture() is called
passing the zero texture as argument. It's very unlikely that any application
would ever have relied on this, but it's easy to get right, and it fixes the
"state" ARB_shader_image_load_store piglit test.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit b663d6bc6f4de9439107fc6444e436d14e21ee79
Author: Francisco Jerez <currojerez at riseup.net>
Date: Sat Jan 31 17:00:19 2015 +0200
mesa: Initialize image units to default state on context creation.
This is the required initial image unit state according to "Table 23.45. Image
State (state per image unit)" of the OpenGL 4.3 specification.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 1b9990e37333076fdc112295ae09193bbe8d57db
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue Jan 20 17:50:15 2015 +0200
mesa: Implement image uniform queries.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit cad0cf4ceeaac708591d064642e12d3b8daa4e05
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue Jan 20 16:12:18 2015 +0200
mesa: Validate original image internal format rather than derived mesa format.
This matches what _mesa_BindImageTextures() does. The derived image format
(gl_texture_image::TexFormat) isn't necessarily equivalent to the internal
format of the texture image. If a forbidden internal format has been
specified we need to mark the image unit as invalid as required by the spec,
regardless of the derived format. Fixes the "invalid"
ARB_shader_image_load_store piglit test.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 4e4855f1dec566c8af825101445f13b1f824a309
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue Jan 20 14:42:48 2015 +0200
mesa: Call _mesa_test_texobj_completeness() before using _MaxLevel in image validation.
gl_texture_object::_MaxLevel doesn't have any meaningful value until
_mesa_test_texobj_completeness() has been run. Fixes the "level"
ARB_shader_image_load_store piglit test.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit f74ba58f84ad41f485957fe7edfb175a21c2ac24
Author: Francisco Jerez <currojerez at riseup.net>
Date: Fri Nov 14 20:31:13 2014 +0200
mesa: Add support for binding a buffer texture to a shader image unit.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 8424cafbac5c9747f0ee9ae55d8633e8172ee47f
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Nov 12 03:47:13 2014 +0200
mesa: Add extern "C" guards to shaderimage.h to allow inclusion from C++ code.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit dded5271e4e811fa6df5005df0961295f58d3a1d
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue Nov 18 14:14:46 2014 +0200
mesa: Export shader image format to mesa format conversion function.
This function will be useful for back-ends to translate an image internal
format as specified in GLSL code into a mesa format.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 96142a3e87abb9e61ee87e895df64f5f64606e83
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Mon May 4 09:58:36 2015 +0200
swrast: Fix rgba_draw_pixels with GL_COLOR_INDEX
When we implemented the format conversion rewrite we forgot to handle
GL_COLOR_INDEX here, which needs special handling.
Fixes the following piglit test:
bin/gl-1.0-drawpixels-color-index -auto -fbo
Buzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90213
Tested-by: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit f1d1d17db6bdeac0519652aa7432048507154a28
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Apr 23 14:30:28 2015 +0300
i965: Add memory fence opcode.
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit f118e5d15fd9b35cf27a975a702c5fb81d3157aa
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Apr 23 14:28:25 2015 +0300
i965: Add typed surface access opcodes.
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 0775d8835ac8d1f2ab75d04f0cddbad36b6787fe
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Apr 23 14:24:14 2015 +0300
i965: Add untyped surface write opcode.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
commit c97a7705ea61f0d1e78bcfe91c0c8e05c79b45cb
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Mar 19 15:12:01 2015 +0200
i965: Reorder sources of the untyped atomic opcode.
This is consistent with the untyped surface read opcode. From now on
all typed and untyped surface access opcodes will follow the same
pattern: src[0] will be the message payload, src[1] will be the
surface index and src[2] will be a control immediate (atomic operation
for atomic opcodes and number of vector components for surface read
and write opcodes).
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
commit ac747ca5f72332b1ff97041cc808be551596a26f
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Mar 19 15:11:28 2015 +0200
i965: Pass the number of components as a source of the untyped surface read opcode.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
commit 20915130ace4cc0f700ece2a99c0353581a156bb
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Feb 26 17:42:47 2015 +0200
i965/vec4: Add support for untyped surface message sends from GRF.
This doesn't actually enable untyped surface message sends from GRF
yet, the upcoming atomic counter and image intrinsic lowering code
will.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
commit 8865fe309da2597398071f5171808c27aac787b4
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Feb 26 17:41:46 2015 +0200
i965: Don't request untyped atomic writeback message if the destination is null.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
commit 0519a6259b0e6b83eaeafdf0ed30a67713c4b6ed
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Apr 22 21:10:43 2015 +0300
i965: Simplify generator code for untyped surface messages.
The generate_untyped_*() methods do nothing useful other than calling
the corresponding function from brw_eu_emit.c. The calls to
brw_mark_surface_used() will go away too in a future commit.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
commit 2f1c16df3e997771bcedb60ae7f16a21c4c60144
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Apr 23 14:21:31 2015 +0300
i965: Fix the untyped surface opcodes to deal with indirect surface access.
Change brw_untyped_atomic() and brw_untyped_surface_read() to take the
surface index as a register instead of a constant and to use
brw_send_indirect_message() to emit the indirect variant of send with
a dynamically calculated message descriptor. This will be required to
support variable indexing of image arrays for
ARB_shader_image_load_store.
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 4348046a2f08d9795a158b96f8579f13f5e693e6
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Sat May 2 15:33:27 2015 +0800
ilo: use ilo_image exclusively in core
Initialize ilo_view_surface and ilo_zs_surface from ilo_image instead of
ilo_texture.
commit 9b705ec32d8cd527ab8d6ebc89f6550d52908c62
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Sat May 2 15:36:59 2015 +0800
ilo: add ilo_image_can_enable_aux()
It replaces ilo_texture_can_enable_hiz().
commit 430594c34ff594b5bf47417b7240a62fc93509e9
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Sat May 2 15:06:36 2015 +0800
ilo: make ilo_image more self-contained
Add depth0, sample_count, and scanout to ilo_image.
commit f6ca4084c7eca649e5444ac20218d94bd2a88057
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Sat May 2 14:14:15 2015 +0800
ilo: add ilo_image_init_for_imported()
It replaces ilo_image_update_for_imported_bo() and enables more error
checkings for imported textures.
commit 938c9b8cea4d4f38b4edac7dbeb24481fbbeeca7
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Sat May 2 14:25:17 2015 +0800
ilo: prepare for image init for imported bo
Refactoring in prepraration for ilo_image_init_for_imported().
commit 3f9415077b1c8abcf8f93231f8d72b5017ea6343
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Sat May 2 14:24:04 2015 +0800
ilo: constify ilo_image_params
Make ilo_image_params const in functions that do not modify it.
commit c209aa7a8f08acb89f7294328589f47a88b44703
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Sat May 2 12:04:26 2015 +0800
ilo: improve readability of ilo_image
Improve docs, rename struct fields, and reorder walk types. No real changes.
commit 9b72bf5bd22c14c4cc17b6945d4b74f4c0eae80a
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri May 1 15:33:56 2015 +0800
ilo: move command builder to core
commit 9e24c49e6443c076ad892e6004e04956560e446a
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri May 1 11:47:13 2015 +0800
ilo: move ilo_state_3d* to core
ilo state structs (struct ilo_xxx_state) are moved as well.
commit 8ab18262c5984736b11b28a30a7facda0d6c65e8
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri May 1 15:07:13 2015 +0800
ilo: add ilo_buffer.h to core
Rename the original ilo_buffer to ilo_buffer_resource to avoid name conflict.
commit 3afbeb115ab19164fb2e5bf8df88b6d03d39254b
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Wed Mar 25 12:22:40 2015 +0800
ilo: move BOs from ilo_texture to ilo_image
We want to work with ilo_image instead of ilo_texture in core.
commit ac47563cb40a79ec2bf149c6d9916a9d66361753
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Sun Mar 8 13:39:02 2015 +0800
ilo: move ilo_layout.[ch] to core as ilo_image.[ch]
Move files and s/layout/image/.
commit 82527655324b09c0d347a948e9bc66e79e48f201
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Wed Mar 25 10:18:46 2015 +0800
ilo: add ilo_format.[ch] to core
The original ilo_format.[ch] are removed.
commit 9b7080c8b35b02b16f58fb8b869b45de9857e8e5
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Sat Mar 7 13:31:52 2015 +0800
ilo: add ilo_fence.h to core
Implement pipe_fence_handle on top of ilo_fence.
commit 2182beb431a3e866022fb76199a5a58dfb23d1e4
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Sun Mar 8 04:45:16 2015 +0800
ilo: add ilo_dev_init() to core
Move init_dev() from ilo_screen.c to core.
commit 7562f9e907d9bb00832c6b75b833acd169bfe0ea
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Sun Mar 8 04:37:02 2015 +0800
ilo: rename ilo_dev_info to ilo_dev
With intel_winsys being embedded in it, drop the "_info" suffix.
commit 19351af53dfffb8543d21a58be9c9f9a52b3ba62
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Sun Mar 8 04:33:49 2015 +0800
ilo: move intel_winsys to ilo_dev_info
We want to use ilo_dev_info instead of ilo_screen in core.
commit b3197fe5f4bfd3f75e6bb64c05c2709bb7985b2c
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Sun Mar 8 04:22:19 2015 +0800
ilo: add ilo_dev.h to core
Move what are remaining in ilo_common.h (that is, ilo_dev_*) to ilo_dev.h.
commit 7bb4fa72c04459c800be8ab79690da07e426d71c
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Sun Mar 8 04:18:14 2015 +0800
ilo: add ilo_debug.[ch] to core
They consist of the debug helpers that used to live in ilo_common.h and
ilo_screen.c.
commit a5797873d054b2fa6c4aec460ca56dacb153bf02
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Sun Mar 8 04:16:34 2015 +0800
ilo: add ilo_core.h to core
ilo_core.h includes the common gallium headers that were included in
ilo_common.h.
commit bbe91576b7f5d69dc201f411cce5e619498cfef5
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Sun Mar 8 04:26:45 2015 +0800
ilo: move intel_winsys.h to core
Add a new subdirectory and start moving files that do not depend on
ilo_screen/ilo_context to it.
commit eeee212e53feac673ea4ac0345fe493418b187df
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Wed Aug 27 11:10:35 2014 -0700
i965: Upload atomic buffer state for compute shaders
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 5328ffbe799bf40a971ebe804404ade91abddd33
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Thu Aug 28 00:48:16 2014 -0700
i965/cs: Emit MEDIA_STATE_FLUSH after WALKER
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 8d87070af295140fb3558b6784dc6303fde11a67
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Thu Aug 28 14:47:19 2014 -0700
i965/cs: Implement brw_emit_gpgpu_walker
Tested on Ivybridge, Haswell and Broadwell.
v2:
* Use SET_FIELD. (Ken)
* Use simd_size / 16 to support SIMD8/16/32. Ken suggested
that we might be able to do it arithmetically rather than just
supporting SIMD8 and SIMD16 with a conditional.
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 0e0e23ef537c9add672ff322f34e129a07edc55e
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Wed Apr 22 11:43:50 2015 -0700
i965/state: Emit pipeline select when changing pipelines
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 013031b2291e87f2559a67c2c54b9004c71ef91b
Author: Paul Berry <stereotype441 at gmail.com>
Date: Thu Jan 9 19:43:18 2014 -0800
i965: Implement DispatchCompute() back-end
brw_emit_gpgpu_walker will be implemented in a subsequent patch.
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 8f1423b2c484de358bad6cee548f630d87d145da
Author: Paul Berry <stereotype441 at gmail.com>
Date: Thu Jan 9 19:21:41 2014 -0800
main/cs: Implement front end code for glDispatchCompute().
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 4d0f3d2319169aca112f9387ef7509290713dc75
Author: Paul Berry <stereotype441 at gmail.com>
Date: Thu Jan 9 18:54:35 2014 -0800
mesa/cs: Add DispatchCompute() to driver function table.
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 5f70b49d4bffaaa073d6cc2a958ec655c201fd10
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Wed Mar 11 22:51:00 2015 -0700
i965/cs: Emit state base address
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit b750e14fbbeb20a6daa869ae642c0c1e1ce6e6d2
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Wed Apr 15 18:27:50 2015 -0700
i965/fs: Add CS shader time support
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 6b1b484b60890380a5899517a4e91a674be0c4a2
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Thu Aug 28 15:35:57 2014 -0700
i965/cs: Upload brw_cs_state
v3:
* Add defines. Misc cleanup suggestions. (Ken)
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
commit 6ec6c1581c2963423917ee1598ffb07cab3f2ddc
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Sat Mar 14 12:55:54 2015 -0700
i965/cs: Support CS program precompile
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 17233f9bbcbf570f0c7633c63dbd5ed88634ed60
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Tue Apr 21 00:31:12 2015 -0700
i965: Add brw_setup_tex_for_precompile. Use in VS, GS & FS.
Suggested-by: Kristian Høgsberg <krh at bitplanet.net>
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 932045061b5850368e8a4a5b3e6609eba6ed8d66
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Thu Aug 28 15:27:22 2014 -0700
i965/cs: Emit compute shader code and upload programs
v2:
* Don't bother checking for 'gen > 5' (krh)
* Populate sampler data in key (krh)
v3:
* Drop no8 support, and simplify code in several places (Ken)
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit cb18f3f0213c010e657fd0b41e681e960a20b790
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Wed Apr 29 10:54:17 2015 -0700
i965/cs: Set invocation counts based on max_cs_threads
For ES, we set the max counts based on SIMD8, which is currently
accurate.
For desktop GL, we set the max counts based on SIMD16, which can fail
in some cases where a SIMD16 program is not currently supported.
Therefore, this value is not currently accurate, but will work fine in
many cases, and lets us run more test cases. Eventually we want to
always be able to generate a SIMD16 program.
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 73cb2d3a73425c5efa4f98b71393e7dad4f387c7
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Fri Mar 13 16:42:40 2015 -0700
i965/cs: Add max_cs_threads
Add values for gen7 & gen8. These are the number threads in a
subslice.
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit ea888c771c47d9a670f6fa6a3bab43b37da14f7f
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Mon Apr 13 12:25:39 2015 -0700
i965: Remove comment about chv device numbers being preliminary
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit c380973a9564be57acdae5ab6c6a9efcb72cf6c9
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Sat Aug 30 19:57:39 2014 -0700
i965/fs: Support compute programs in fs_visitor
v2:
* Clean out some unneeded code copied from run_fs (krh)
* Always use NIR
* Split shader time out into a separate commit
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit ae6308a41e9d11b4b166fb2f821e7252ca2761e8
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Sat Mar 14 17:06:26 2015 -0700
i965/cache: Add support for CS in program state cache
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 92a57e7207f86ac6557661e84503d3871931926a
Author: Paul Berry <stereotype441 at gmail.com>
Date: Fri Jan 10 21:39:25 2014 -0800
i965/cs: Add brw_cs_prog_data, brw_cs_prog_key and brw_context::cs.
jordan.l.justen at intel.com:
* Added brw_cs_prog_key structure
* Added brw_cs_prog_data::dispatch_grf_start_reg_16
* Added brw_cs_prog_data::local_size
* Added brw_cs_prog_data::simd_size
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 2a4df9c524f05e2ee3d01ba03f21310b23f8e395
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Wed Aug 27 11:33:25 2014 -0700
i965/cs: Add generator support for CS_OPCODE_CS_TERMINATE
v2:
* Don't rely on brw_eu* to generate the send instruction. We now
generate the send here, and drop the "i965/cs: Add support for the
SEND message that terminates a CS thread" brw_eu* patch.
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit dff4a426766f08a9073ab235f74d96b4b23c6981
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Sat Sep 27 11:15:28 2014 -0700
i965/cs: Mark g0 as used by CS_OPCODE_CS_TERMINATE
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit d79cdee1d9d14c74e9838fd8248e8c7a4588f9e4
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Sun Apr 12 02:06:57 2015 -0700
i965/fs: Add emit_cs_terminate to emit CS_OPCODE_CS_TERMINATE
v2:
* Do more work at the visitor level. g0 is loaded and sent to the
generator now.
v3:
* Use Ken's comment explaining g0 usage
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit eeb4b68224560b199d2e7f12c770adc511eb5e60
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Wed Aug 27 11:32:08 2014 -0700
i965/cs: Add CS_OPCODE_CS_TERMINATE
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit f002176d5d3b982787e8109a419de929fd77a2b7
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Sat Jan 24 21:35:54 2015 -0800
i965/cs: Add BRW_NEW_CS_PROG_DATA and BRW_CACHE_CS_PROG
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit d94a9e7041a0816747d25ec99089d1bc161d46e0
Author: Paul Berry <stereotype441 at gmail.com>
Date: Fri Jan 10 21:39:25 2014 -0800
i965: Add an INTEL_DEBUG=cs option.
At the moment it's not wired up to anything. Later patches will hook
it up to the compute shader back-end.
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit bf058dad6b97aaa2422c3ed462c4f27490719800
Author: Paul Berry <stereotype441 at gmail.com>
Date: Fri Jan 10 21:39:25 2014 -0800
mesa/cs: Add compute support to update_program().
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit abb049dab6155ee4994cf7df88b7913897078dff
Author: Paul Berry <stereotype441 at gmail.com>
Date: Fri Jan 10 21:39:25 2014 -0800
mesa/cs: Update program.c for compute shaders.
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 56d5c5ab5c15a3cace676dcfb362c19fe0591f60
Author: Paul Berry <stereotype441 at gmail.com>
Date: Fri Jan 10 21:39:25 2014 -0800
mesa/cs: Add inline functions for dealing with compute shaders.
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 6ee4dac1ef7db88b1fd5b27b215fb8baa7bc9c66
Author: Paul Berry <stereotype441 at gmail.com>
Date: Fri Jan 10 21:39:25 2014 -0800
i965/cs: Add BRW_NEW_COMPUTE_PROGRAM state flag.
Also add code to brw_upload_state to set it when the compute program
changes.
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 02e9773bc8526f64e4d79e3d9ac11f49882c022f
Author: Neil Roberts <neil at linux.intel.com>
Date: Thu Apr 23 16:56:53 2015 -0700
i965/fs: Strip trailing constant zeroes in sample messages
If a send message is emitted with a message length that is less than
required for the message then the remaining parameters default to
zero. We can take advantage of this to save a register when a shader
passes constant zeroes as the final coordinates to the sample
function.
I think this might be useful for GLES applications that are using 2D
textures to simulate 1D textures.
On Skylake it will be useful for shaders that do
texelFetch(tex,something,0) which I think is fairly common. This helps
more on Skylake because in that case the order of the instruction
operands are u,v,lod,r which is good for 2D textures whereas before
they were u,lod,v,r which is only good for 1D textures.
On Haswell:
total instructions in shared programs: 8535730 -> 8533261 (-0.03%)
instructions in affected programs: 236968 -> 234499 (-1.04%)
helped: 1174
On Skylake:
total instructions in shared programs: 10345646 -> 10341237 (-0.04%)
instructions in affected programs: 293011 -> 288602 (-1.50%)
helped: 1218
Reviewed-by: Matt Turner <mattst88 at gmail.com>
v2: Applied suggestions by Kenneth Graunke:
- Only apply on Gen5+
- Apply to all texture opcodes, not just TEX and TXF.
Moved the optimisation into the loop as suggested by Matt Turner.
Fix the array index when there is a header.
commit be119e80c9414aaf5101809c44ad4bf64e8676bf
Author: Neil Roberts <neil at linux.intel.com>
Date: Thu Apr 23 10:09:52 2015 -0700
i965/skl: Force the exec size to 8 when initing header for SIMD4x2
On Gen9+ there needs to be a header when sampling using SIMD4x2. The
header is set up by copying from the g0 register. Commit 07c571a39f
tried to fix this mov instruction to always use an exec size of 8
because previously it was incorrectly using 4. It did this by casting
the type of the destination register to vec8. This was done because
there is code in brw_set_dest to guess the exec size based on the
width of the dest register. However I misunderstood how this works
because it is actually only used when the width is less than 8. That
means the patch actually changed it to use the default exec size which
on SIMD16 would be 16 and the MOV would clobber over the first
register in the send message. This patch makes it additionally set the
default exec size to 8. This is similar to how the message is set up
in fs_generator::generate_tex.
I think this wasn't picked up by any Piglit tests because we don't
have any fragment shaders that hit this code path so nothing was using
SIMD16. However the patch caused failures in deqp tests.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90153
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Tested-by: Tapani Pälli <tapani.palli at intel.com>
commit 1ac7db07b363207e8ded9259f84bbcaa084b8667
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Mar 12 05:37:43 2015 -0700
i965: Unhardcode a few more stage names and abbreviations.
The stage_abbrev and stage_name fields in backend_visitor provide what
we need without any additional effort. It also means we'll get the
right names for compute shaders, SIMD8 geometry shaders, and both kinds
of tessellation shaders.
This does unfortunately change the capitalization of the stage
abbreviation in the INTEL_DEBUG=optimizer output filenames. It doesn't
seem worth adding code to handle, though.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 1db5d3c19ee8d91686dfe3c1927a3e2dfa83830c
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Apr 29 20:33:21 2015 +0200
docs/relnotes: document the new EGL sync extensions
commit e70de9b0327009dd9b99ee1f388cfffd1bc93761
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Apr 10 19:45:50 2015 +0200
st/dri: implement the fence interface for CL events
commit 952b5e84db47be3adaf01f047efeedd26cf0d173
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Apr 10 18:42:42 2015 +0200
gallium,clover: add OpenCL interoperability support for CL events
v2: - move interop.cpp to clover/api
- change intptr_t to void* in the interface
- add a virtual function fence() to simplify some code
v3: - use bool in the interface
v4: - enclose the last two interop functions in try..catch
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 7070b0dd66d315b3106803580623df4fb5223473
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Apr 10 19:41:39 2015 +0200
st/dri: implement the fence interface
commit a2557b30d843d4f3dada6a022f27e8343adabca8
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Apr 10 23:35:39 2015 +0200
egl/dri2: return the latest sync status in eglGetSyncAttribKHR
commit 290a3eb7507f7f2949753a77c425ed2bb6fd0dd1
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Apr 10 13:16:30 2015 +0200
egl/dri2: implement EGL_KHR_cl_event2 (v2)
v2: fix the SYNC_CONDITION query
commit a8617cc0428dcc8340cb85776e122c6534a0fa11
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Apr 10 12:04:18 2015 +0200
egl/dri2: implement EGL_KHR_wait_sync
commit 9a0bda2430f10fbf43c64573412d97b6cc38e5d7
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Apr 10 10:56:02 2015 +0200
egl/dri2: implement EGL_KHR_fence_sync
commit 592ee249a139a46168cd8e3335039ce28e8a2c39
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Apr 9 23:26:14 2015 +0200
mesa: add GL_OES_EGL_sync
This is an empty extension whose presence means that EGL sync objects can be
used with ES contexts.
commit b02a5bf3ba04608d50916a4ca00261461280d548
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Apr 10 10:43:26 2015 +0200
dri_interface: add an interface for fences
commit 396cbabbefaae64deac6d33c79898bb07db8a621
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Apr 9 23:25:07 2015 +0200
egl/dri: don't expose configs with an accumulation buffer
commit 33f0d1138d6ffa4596d3deda68fa5ba9a3d7cf86
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Apr 30 02:01:22 2015 -0400
nvc0/ir: fix predicated PFETCH for real
Commit a9d08a250 accidentally didn't make use of the new src1 variable.
Use it.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org
commit db269ae495425849804fb1d05cfe42b0d3d304b3
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Apr 29 23:33:27 2015 -0400
nv50/ir: fix asFlow() const helper for OP_JOIN
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org
commit a9d08a250ada5fbd4e3f78f8e4119ec295d692cf
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Apr 29 23:05:44 2015 -0400
nvc0/ir: fix predicated PFETCH emission
src1 would contain the predicate, which would get emitted as a register
source by an undiscerning srcId helper. Work around this in the same way
as in emitTEX.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org
commit 515ac907e68ae1485bd9c65d7351dfb3c3d1e33f
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Apr 29 18:01:53 2015 -0400
gk110/ir: fix set with a register dest to not auto-set the abs flag
This was causing src0 to always have the absolute value flag set.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: mesa-stable at lists.freedesktop.org
commit 13670e8bade296c5c5846dc08615563ad51685e4
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Sun Mar 29 21:52:02 2015 +0300
i965/blorp: Prepare drawing rectangle for flipped coordinates
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit dfd896699d9f640518c0fbafb0352f454d5fc466
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Fri Mar 27 16:25:56 2015 +0200
i965/blorp: Add support for layered rendering
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 91daf9f09bac41c84c6868a56e0d538cc59cc334
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Thu Mar 26 16:43:31 2015 +0200
i965/blorp: Allow blend state to be set for multiple render targets
Original blorp writes only one buffer per shader invocation. Once
the launch mechanism is shared with glsl-based programs there will
be need for supporting multiple render targets.
Also drop the always constant color write disable settings.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 7fb0db4dd18e49d3ccdb872f7ed174740301f3a2
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Fri Feb 27 11:45:34 2015 +0200
i965/blorp: Prepare for attributes other than render position
Note that the magic number of one in gen7 logic is replaced by
BRW_SF_URB_ENTRY_READ_OFFSET ( == 1 also) for clarity.
On gen6 the change from zero to one (BRW_SF_URB_ENTRY_READ_OFFSET)
has no effect for native blorp as blorp doesn't use any
additional attributes. In fact, regular pipeline setup always
uses BRW_SF_URB_ENTRY_READ_OFFSET even when there are no additional
attributes. Hence the change makes the two (blorp and regular)
consistent.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 25ce6c6943576e22d8d00049578d0e6cc5feea07
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Fri Jan 30 11:37:54 2015 +0200
i965/blorp: Remove unused arguments
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit dce1972945a4568c181011880e0336a2a14909ec
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Fri Jan 30 11:30:34 2015 +0200
i965/gen7/blorp: Remove unused arguments
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 4de0bef7f438147091a7489728c4d187c6efbbc3
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Fri Feb 27 21:59:56 2015 +0200
i965/blorp: Allow caller to provide sampler settings
v2 (Ken): s/use_unorm_coords/non_normalized_coords/
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit bfdacac86cf82a1ae8d76e3282b8842f08a21c31
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Fri Feb 27 11:17:05 2015 +0200
i965/blorp: Refactor vertex buffer state setup
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit d271a13ba31168e0de75d7d4c1d4d7a2e2fb136c
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Sat Mar 14 10:21:33 2015 +0200
i965/blorp: Remove constant parameter
This was still needed when we had support for blorp clears but now
this is fixed to nop.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit d7e49fba9a48b5f90c0ce8b7d0c0588545090a7f
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Mon Mar 2 11:29:05 2015 +0200
i965/gen8: Expose state base address setup
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit fea168f49584333aeeabad2d2b0dc6aaee86f881
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Mon Mar 2 12:31:17 2015 +0200
i965/ps/gen8: Refactor state uploading
v2: Use SET_FIELD() for sampler count, and for that reason
added GEN7_PS_SAMPLER_COUNT_MASK.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 4047420ec47488f2cdd7511cbeea95201b620480
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Fri Feb 13 11:20:05 2015 +0200
i965/ps/gen7: Refactor state uploading
Now the uploading depends only on the input parameters instead
of consulting the current gl-state.
v2: Rebased on top of sampler count clamping
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 02dbc79297203a063b91e6b5a0b81bda8aa48c19
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Thu Apr 2 12:45:02 2015 +0300
i965: Refactor sampler state setup
v2 (Matt): Moved * to the name.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 47f32cb50d19145ed502e1fccd949d931c0cd392
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Sat Apr 4 20:28:45 2015 +0300
i965: Remove dependency to tex object in default color setup
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 21071afc431bb17419c353151544518be7daf05f
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Thu Mar 19 10:42:49 2015 +0200
i965: Refactor and expose brw_upload_binding_table()
Read and write parts of the state stage are also split into
explicit arguments allowing future patches to use constant
program data.
v2 (Ken): s/BRW_NEW_WM_PROG_DATA/BRW_NEW_FS_PROG_DATA/
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit c15e20d8f6f6d632ad55d444149c2a12d0dcc515
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Thu Mar 19 11:09:54 2015 +0200
i965: Expose and refactor brw_update_renderbuffer_surfaces()
Note that brw_update_renderbuffer_surfaces() already had a helper
variable which was used in parallel to direct access of the current
draw buffer of the context.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit c8b0d890c0b7e6aa5ed326b94ac30dcb7278e7ea
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Tue Mar 17 13:09:16 2015 +0200
i965: Refactor rb surface setup to allow caller to store offsets
Notice that in gen7_wm_surface_state.c there is also indentation
change in the surrounding code removing tabs.
v2 (Matt): Fixed whitespace: tabs -> spaces
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit d6c83c9d863f9f13e46584b93cbab6d3a3885aea
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Sun Mar 1 22:23:33 2015 +0200
i965/gen8: Use constant pointers for reading miptree details
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit f39846fb57c2b4d29b65a40019ba55219b062117
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Wed Apr 29 20:35:45 2015 +0300
i965/ps: Use SET_FIELD() for sampler count
The value is actually clamped to 0-16 as sample state pointer
can be used to support more than 16 samplers.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 2c7e289d8b1d3c63ab55b64ab3961067fd5a1985
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Apr 15 11:34:50 2015 -0700
glx: Massive update of comments in struct extension_info
In response to another patch, Emil asked for some clarification how this
stuff works. Rather than just reply to the e-mail, I decided to update
the exlanation in the code.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Cc: Emil Velikov <emil.l.velikov at gmail.com>
commit a582b22c6382f24d921e9fe8a24917100c1396f1
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Apr 16 22:53:04 2015 +0200
winsys/radeon: add a private interface for radeon_surface
commit dcfbc006b6b07d41338b87c64cdc01c36608087b
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Apr 16 22:50:33 2015 +0200
winsys/radeon: move radeon_winsys.h to drivers/radeon
commit d8f817ae7f4241a9ea23140805aaeb724a0ac851
Author: EdB <edb+mesa at sigluy.net>
Date: Thu Apr 23 20:13:51 2015 +0200
clover: remove util/compat
Acked-by: Francisco Jerez <currojerez at riseup.net>
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
commit 5d4f085a43ccd1122301421f2013e42a3f0a7604
Author: Neil Roberts <neil at linux.intel.com>
Date: Tue Apr 28 14:20:06 2015 +0100
i965: Don't try to apply the opt_sampler_eot extension for vs
The opt_sampler_eot optimisation of fs_visitor effectively assumes
that it is running on a fragment shader because it casts the program
key to a brw_wm_prog_key. However on Skylake fs_visitor can also be
used for vertex shaders. It looks like this usually works anyway
because the optimisation is skipped if key->nr_color_regions != 1.
However for a vertex shader the key is actually a brw_vs_prog_key so
the space for nr_color_regions is probably taken up by
key->base.program_string_id. This can end up making nr_color_regions
be 1 in which case the function will later assert when the last
instruction is not FS_OPCODE_FB_WRITE. This was making the DEQP test
suite assert. Presumably this only happens there because that compiles
a lot of shaders so it would end up with a high value for
program_string_id.
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit b124dc2b70a1ba546d1ce46578036d263a4287fe
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Apr 15 14:44:02 2015 +0100
r300: do not link against libdrm_intel
Accidentally added since the introduction of the file.
Cc: "10.4 10.5" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 2d112ed96152bc62e5417472270f29966c8feece
Author: EdB <edb+mesa at sigluy.net>
Date: Fri Apr 24 12:59:56 2015 +0200
clover: make module::symbol::name a string
Acked-by: Francisco Jerez <currojerez at riseup.net>
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
commit 5ca9b23319db66d9768d46c0a7504b7bb079164a
Author: EdB <edb+mesa at sigluy.net>
Date: Fri Apr 24 12:59:55 2015 +0200
clover: remove compat::string
Acked-by: Francisco Jerez <currojerez at riseup.net>
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
commit 1b4a1d0049646e574565bab38b8ae935c1c45fae
Author: EdB <edb+mesa at sigluy.net>
Date: Fri Apr 24 12:59:54 2015 +0200
clover: remove compat classes that match std one
Acked-by: Francisco Jerez <currojerez at riseup.net>
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
commit 3c61ff0d89da4a8cc921d131ce0c2480ddb111a0
Author: EdB <edb+mesa at sigluy.net>
Date: Tue Apr 21 15:49:09 2015 +0200
clover: compile all sources with c++11
Later we can remove the compat code
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
commit 231be57ee2515428e3de31f514effe9cf06bcda0
Author: Axel Davy <axel.davy at ens.fr>
Date: Fri Feb 20 12:59:45 2015 +0100
st/nine: Remove Managed texture hack.
Previously binding an unitialized managed texture
was causing a crash, and a workaround was added to
prevent the crash.
This patch removes this workaround and instead set the initial
state of managed textures as dirty, so that when the texture is bound
for the first time, it is always initialized.
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 58d295d41e30434c570248eeee73af2006b79eea
Author: Axel Davy <axel.davy at ens.fr>
Date: Fri Feb 20 12:34:47 2015 +0100
st/nine: Enforce LOD 0 for D3DUSAGE_AUTOGENMIPMAP
For D3DUSAGE_AUTOGENMIPMAP textures, applications can only
lock/copy from/get surface descriptor for/etc the first level.
Thus it makes sense to restrict the LOD to 0, and use only the first
level to generate the sublevels.
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 6f57e014365563c0dcc32451401a76212abf0a54
Author: Axel Davy <axel.davy at ens.fr>
Date: Fri Feb 20 12:11:56 2015 +0100
st/nine: Some D3DUSAGE_AUTOGENMIPMAP fixes
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 24eca6a30dea4cde0b0528b85e83d45a6430762e
Author: Axel Davy <axel.davy at ens.fr>
Date: Thu Feb 19 22:28:37 2015 +0100
st/nine: util_gen_mipmap doesn't need we reset states.
util_gen_mipmap uses pipe->blit, and thus doesn't need
we restore all states after using it.
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 7a7758c5525fa90bf7c546acc58a9ea41f7d320b
Author: Axel Davy <axel.davy at ens.fr>
Date: Thu Feb 19 20:55:42 2015 +0100
st/nine: D3DUSAGE_AUTOGENMIPMAP is forbidden for volumes
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit ec411d9b74f9aca941b27fafeae1416df0f9eaec
Author: Axel Davy <axel.davy at ens.fr>
Date: Thu Feb 19 20:23:06 2015 +0100
st/nine: Fix NineBaseTexture9_PreLoad
It wasn't uploading the texture when the lod
had changed.
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit b45fa97a22d091a5c9a3d9c9432ff880e79231d6
Author: Axel Davy <axel.davy at ens.fr>
Date: Thu Feb 19 19:34:02 2015 +0100
st/nine: Rewrite Managed texture uploads
That part of the code was quite obscure.
This new implementation tries to make it clearer
by separating the differents parts, and commenting more.
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 090ebc7638e64592716ac4ecd4c29609b2f35421
Author: Axel Davy <axel.davy at ens.fr>
Date: Thu Feb 19 17:44:43 2015 +0100
st/nine: Bound the dirty regions to resource size
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 520e36f89cb9048258d9c1ca42de68564ad876a9
Author: Axel Davy <axel.davy at ens.fr>
Date: Thu Feb 19 17:34:45 2015 +0100
st/nine: Simplify Surface9 Managed resources implementation
Remove the Surface9 code for dirty rects, used only for Managed
resources. Instead convey the information to the parent texture.
According to documentation, this seems to be the expected behaviour,
and if documentation is wrong there, that's not a problem since it can
only leads to more texture updates in corner cases.
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 4c2247ac60f426a6441f964f2204af9f8dc04dc5
Author: Axel Davy <axel.davy at ens.fr>
Date: Thu Feb 19 16:35:45 2015 +0100
st/nine: Remove impossible cases with Managed textures
Copying to/from a Managed texture is forbidden.
Rendering to a Managed texture is forbidden.
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit e558ce98f2b01e11ff79c29efaea2877121ae04a
Author: Axel Davy <axel.davy at ens.fr>
Date: Thu Feb 19 16:18:00 2015 +0100
st/nine: Encapsulate variables for MANAGED resource
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 35fe920e1ec877d487e5dd33c9aea7e1ec1dbe11
Author: Axel Davy <axel.davy at ens.fr>
Date: Thu Feb 19 11:21:12 2015 +0100
st/nine: Rework texture data allocation
Some applications assume the memory for multilevel
textures is allocated per continuous blocks.
This patch implements that behaviour.
v2: cache offsets
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 54f8e8a18da58c85a2f515d5fd0552fa4f5547bb
Author: Axel Davy <axel.davy at ens.fr>
Date: Mon Mar 23 23:31:18 2015 +0100
st/nine: Fix update_vertex_elements bad rebase
This code was supposed to be removed, but a rebase seems to have
made it stay.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 87868d38328a3875881fe1ca6861eb7816a5b0cf
Author: Axel Davy <axel.davy at ens.fr>
Date: Sun Mar 22 11:49:03 2015 +0100
st/nine: Add debug warning when application uses sw processing
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 4acbf420d1101bd32e8f23acadff5fe6c6fa9b26
Author: Axel Davy <axel.davy at ens.fr>
Date: Fri Feb 20 18:25:44 2015 +0100
st/nine: Rework update_vertex_buffers
Previous code was trying to optimise to call set_vertex_buffers on
big packets, and thus avoids as many calls as possible.
However in practice doing so won't be faster (drivers implement
set_vertex_buffers by a loop over the buffers we want to bind)
When we want to unbind a buffer, we were calling set_vertex_buffers
on a buffer with vtxbuf->buffer = NULL. It works on some drivers,
but not on all of them, because it isn't in Gallium spec.
This patch fixes that.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 5beb411bf753da4c86082c505929bcc9629c666c
Author: Xavier Bouchoux <xavierb at gmail.com>
Date: Mon Feb 16 09:43:23 2015 +0100
st/nine: Fix computation of const_used_size
Was sometimes too large for PS.
Reviewed-by: Axel Davy <axel.davy at ens.fr>
Signed-off-by: Xavier Bouchoux <xavierb at gmail.com>
commit 559342d01d4199e8fd475241a574a92c4ce63896
Author: Axel Davy <axel.davy at ens.fr>
Date: Sun Apr 26 23:19:03 2015 +0200
gallium/svga: Remove useless ARRAY_SIZE declaration
This is already declared in util/macros.h
Reviewed-by: Brian Paul <brianp at vmware.com>
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 64880d073ab21ae1abad0c049ea2d6a1169a3cfa
Author: Axel Davy <axel.davy at ens.fr>
Date: Sun Apr 26 23:17:45 2015 +0200
util/macros: Move DIV_ROUND_UP to util/macros.h
Move DIV_ROUND_UP to a shared location accessible everywhere
Reviewed-by: Brian Paul <brianp at vmware.com>
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 405c7d75114fadcf744f6bbd5556c86c66ac631b
Author: Xavier Bouchoux <xavierb at gmail.com>
Date: Sat Feb 21 19:58:38 2015 +0100
st/nine: Fix behaviour of D3DUSAGE_QUERY_POSTPIXELSHADER_BLENDING
Ignore D3DUSAGE_QUERY_POSTPIXELSHADER_BLENDING when
D3DUSAGE_RENDERTARGET is not specified.
This behaviour matches windows drivers.
Reviewed-by: Axel Davy <axel.davy at ens.fr>
Signed-off-by: Xavier Bouchoux <xavierb at gmail.com>
commit d838fe8243aa0e96b198c876c1b5d79c098d1c0d
Author: Xavier Bouchoux <xavierb at gmail.com>
Date: Sat Feb 21 19:56:40 2015 +0100
st/nine: Improve D3DQUERYTYPE_TIMESTAMP
Avoid blocking when retrieving D3DQUERYTYPE_TIMESTAMP result with
NineQuery9_GetData(), when D3DGETDATA_FLUSH is not specified.
This mimics Win behaviour and gives slightly better performance
for some games.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Axel Davy <axel.davy at ens.fr>
Signed-off-by: Xavier Bouchoux <xavierb at gmail.com>
commit 851abb91459b13d28303f54605b8da51c24efcb7
Author: Xavier Bouchoux <xavierb at gmail.com>
Date: Sun Feb 8 15:56:15 2015 +0100
st/nine: Fix D3DQUERYTYPE_TIMESTAMPFREQ query
D3DQUERYTYPE_TIMESTAMPFREQ is supposed to give the frequency
at which the clock of D3DQUERYTYPE_TIMESTAMP runs.
PIPE_QUERY_TIMESTAMP returns a value in ns, thus the corresponding
frequency is 1000000000.
PIPE_QUERY_TIMESTAMP_DISJOINT returns the frequency at which
PIPE_QUERY_TIMESTAMP value is updated. It isn't always
1000000000.
Reviewed-by: Axel Davy <axel.davy at ens.fr>
Signed-off-by: Xavier Bouchoux <xavierb at gmail.com>
commit 31bb4cd5c6e3d696b2f240c270a257abfcd8848f
Author: Tiziano Bacocco <tizbac2 at gmail.com>
Date: Sun Jan 25 12:15:39 2015 +0100
st/nine: Change x86 FPU Control word on device creation
As on wined3d and windows, when D3DCREATE_FPU_PRESERVE is not
specified, change the fpu control word to all exceptions masked,
single precision, round to nearest.
Signed-off-by: Axel Davy <axel.davy at ens.fr>
Signed-off-by: Tiziano Bacocco <tizbac2 at gmail.com>
commit e7b1a1e57cdfd8d019ba0ff4cdc2c7239066869f
Author: Axel Davy <axel.davy at ens.fr>
Date: Fri Feb 20 12:51:55 2015 +0100
st/nine: Do not advertise D3DDEVCAPS_TEXTURESYSTEMMEMORY
No major vendor advertises it, and we weren't supporting it.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 907f28f87e3858028bce4477f0b57f7e5d76060a
Author: Axel Davy <axel.davy at ens.fr>
Date: Thu Apr 23 21:46:24 2015 +0200
st/nine: Fix comment in update_viewport
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 6e825b69bd4fb163cba0a565616ed966fb1a8929
Author: Axel Davy <axel.davy at ens.fr>
Date: Thu Apr 23 21:46:09 2015 +0200
st/nine: Workaround barycentrics issue on some cards
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit f3fd06e94d29172a5de68594d3a6433f91a41362
Author: Xavier Bouchoux <xavierb at gmail.com>
Date: Mon Feb 16 10:02:42 2015 +0100
st/nine: Clear struct pipe_blit_info before use.
render_condition_enable was uninitialized.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Axel Davy <axel.davy at ens.fr>
Signed-off-by: Xavier Bouchoux <xavierb at gmail.com>
commit 77a38d2088678fa756aca61592777f12e245ac0c
Author: Patrick Rudolph <siro at das-labor.org>
Date: Fri Feb 20 15:48:57 2015 +0100
st/nine: NineDevice9_Clear skip fastpath for bigger depth-buffers
This adds an additional check to make sure the bound depth-buffer doesn't
exceed the rendertarget size when clearing depth and color buffer at once.
D3D9 clears only a rectangle with the same dimensions as the viewport, leaving
other parts of the depth-buffer intact.
This fixes failing WINE test visual.c:depth_buffer_test()
Signed-off-by: Patrick Rudolph <siro at das-labor.org>
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 716bef2643367d3696aa20ab7178cbe19bf78abc
Author: Axel Davy <axel.davy at ens.fr>
Date: Sat Mar 21 13:36:25 2015 +0100
st/nine: Fix wrong assert in nine_shader
The sampler src index was wrong for texldl and texldd
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 8d3e063e6851ca6c33c8bac1d8e9b9b344d27294
Author: Axel Davy <axel.davy at ens.fr>
Date: Tue Dec 23 15:15:10 2014 +0100
st/nine: Handle special LIT case
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Signed-off-by: Axel Davy <axel.davy at ens.fr>
commit 114ac39a888509b133f15ddae813fcf64adc72a7
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Tue Apr 28 21:49:36 2015 +0100
mesa: Fix glGetProgramiv(GL_ACTIVE_ATTRIBUTES).
It's returning random values, because RESOURCE_VAR() is casting
different objects into ir_variable pointers.
This updates _mesa_count_active_attribs to filter the resources with the
same logic used in _mesa_longest_attribute_name_length.
https://bugs.freedesktop.org/show_bug.cgi?id=90207
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
commit c66c158e59298fc4183148c466dd4eecb945f87c
Author: Marc-André Lureau <marcandre.lureau at gmail.com>
Date: Tue Apr 28 12:23:42 2015 +0200
egl: misc fixes for EGL_MESA_image_dma_buf_export
Fix define and a function argument name introduced in commit
8f7338f284cdb1fef64c85e3293d2200d0cc6387
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 6fe0d4f0354418c6e68dd352996e9891ddd4dfd6
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Tue Apr 28 03:30:08 2015 -0400
nvc0/ir: flush denorms to zero in non-compute shaders
This will set the FTZ flag (flush denorms to zero) on all opcodes that
can take it.
This resolves issues in Unigine Heaven 4.0 where there were solid-filled
boxes popping up.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89455
Cc: "10.4 10.5" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 66985d2a6de0afd9446c92dce999f00efa528d31
Author: Brian Paul <brianp at vmware.com>
Date: Fri Apr 24 20:12:50 2015 -0600
meta: remove unneeded #include colortab.h
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 7e8de8219fbde486364054cc2a75022ddcbe0c2c
Author: Brian Paul <brianp at vmware.com>
Date: Fri Apr 24 20:12:42 2015 -0600
mesa: remove unneeded #include colortab.h
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 7c1be009b7c34dce55be83ae2a955dd8a37e230a
Author: Brian Paul <brianp at vmware.com>
Date: Fri Apr 24 20:04:29 2015 -0600
mesa: remove unused options var in compile_shader()
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 3597a0de94fa721e86ef2b7a68855f44ed4e1973
Author: Brian Paul <brianp at vmware.com>
Date: Thu Apr 23 10:00:34 2015 -0600
docs: more details about Viewperf 12 medical-01 test issues
commit e312a6995850e78b3b9e2cbe4713928bc9cc386d
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Apr 26 16:15:02 2015 -0400
nvc0: expose GLSL version 410
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit b5947984cd7c90bf1409e15a2425fa1d4dc2be15
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Apr 26 16:14:36 2015 -0400
st/mesa: allow glsl version up to 410, enable ARB_shader_precision
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 2d4a890c0b763ae3feb7af9255d6d92baa9cfe57
Author: Leo Liu <leo.liu at amd.com>
Date: Thu Mar 12 14:29:21 2015 -0400
st/va: add h264 decoder level support
Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
commit b2596efeb767417f21ce45a411c56bb3ecc51620
Author: Leo Liu <leo.liu at amd.com>
Date: Fri Mar 13 12:39:26 2015 -0400
st/omx/dec: add h264 decoder level support
v2: use sps level idc as level to driver
Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
commit 1a5e2bb5ce254eb272960e5b50b803110f25c9b1
Author: Leo Liu <leo.liu at amd.com>
Date: Mon Mar 16 15:06:30 2015 -0400
vl: add level idc in sps
Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
commit ef1ae703a96fef72d2d8c22ef76bd1dfc41d1cee
Author: Leo Liu <leo.liu at amd.com>
Date: Fri Mar 13 12:25:42 2015 -0400
st/omx/dec: separate create_video_codec to different codecs
v2: get frame size from port info
Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
commit d043b51ba47688044b1a09a6023093a90ad62e6a
Author: Leo Liu <leo.liu at amd.com>
Date: Thu Mar 12 14:09:49 2015 -0400
st/vdpau: add h264 decoder level support
Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
commit 4509fc8b94a0dcf8a847e1f885685a4d2d660c5a
Author: Leo Liu <leo.liu at amd.com>
Date: Thu Mar 12 14:01:52 2015 -0400
gallium/util: get h264 level based on number of max references and resolution
v2: add commments for limitation of max references numbers,
and what the caculation is based
Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
commit 6d05396b0047c74d740c53156eda1a8574403498
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Feb 24 01:26:13 2015 +0100
r600g,radeonsi: add a driver query returning GPU load
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
commit 0b8e73a6ae2a77d0e9a7810cca5b181ba5f0893e
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Feb 24 00:50:20 2015 +0100
r600g,radeonsi: add driver queries for GPU temperature and shader+memory clocks
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
commit 9143940da2c4f0deb07d01c1b48d16bb16022997
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Tue Jul 22 23:45:13 2014 -0400
gm107/ir: add lane/vertex count sysvals
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 89e0b08794a56e2ef78e8573a8c11e0cc4589f9e
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Apr 27 12:54:43 2015 -0400
gk110/ir: add support for writing per-patch and shader outputs
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 52614f59b7a9c4ae5efeacba26fa811568818811
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Apr 25 15:37:24 2015 -0400
freedreno/a3xx: color masking works like a blend for some formats
When there is a colormask active that does not cover all the channels,
enable reading in the destination like with a combining blend
operation. This fixes fbo-blending-formats on a3xx.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 9fc3f472784b2ba53655b715d602268bef5bf12e
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Apr 22 14:35:00 2015 -0400
freedreno/a3xx: add support for S8 and Z32F_S8
Enables ARB_depth_buffer_float. There is no sampling support for
interleaved Z32F_S8, so we store the two textures separately, one as
Z32F, the other as S8. As a result, we need a lot of additional logic
for restores and transfers.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 1571da6ac31ade482f5e4adc82eb66d42a1bb389
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Apr 25 01:21:26 2015 -0400
freedreno/a3xx: add Z32F support
32-bit depth buffers are stored as unorm, and thus need special handling
when moving to and from gmem. They are copied into gmem by writing
depth, and resolved from gmem using a special resolve bit which
apparently float-ifies the data.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 0a4cb00c7765dbe26a4dbfad3bb87d6c6ce03919
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Apr 6 01:39:14 2015 -0400
freedreno: add fd_transfer to wrap around pipe_transfer
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit f5c110199675b7f4c50d4a7a64b6aac44c55d0a4
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Apr 24 21:44:05 2015 -0400
freedreno/a3xx: add support for disabling depth clipping
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit dffc1a0ae3a75d426f10c5d3ba021de977467929
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Apr 25 09:47:59 2015 -0700
i965/vs: Remove unnecessary NULL check on generate_code() result.
Code generation is not allowed to fail for any reason - in fact,
fs_generator has no mechanism for failing. The visitor is responsible
for that.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit d795cc6508cba209c66c658e39d5adbe2022f0fb
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Tue Apr 28 07:26:36 2015 +1000
glsl: fix packing support for arrays of doubles
Broke in commit f00c5f85b82efe9535b18dbf97c4591fb28aeae6 when
adding support for multidimensional arrays
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit ff6ee39c19adc59225d1f0664695c669cd7e5a94
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Apr 24 11:28:06 2015 -0700
i965: Enable ARB_gpu_shader5 on Gen8+.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 0c06d019bcf626b289ae94ca791dc25c216c1e5c
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Apr 24 11:28:05 2015 -0700
i965/fs: Fix code emission for imul_high in NIR.
Copy over from brw_fs_visitor.cpp.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit ecf428aa5945c5e1941b6bf496a381c7a09cdda2
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Apr 24 11:28:04 2015 -0700
i965/fs: Fix stride for multiply in macro.
We have to use W/UW type for src1 of the multiply in the MUL/MACH macro,
but in order to read the low 16-bits of each 32-bit integer, we need to
set the appropriate stride.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit b3e29a20225756c8db299088e0b6ead82139cabb
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Apr 24 11:28:03 2015 -0700
Revert "i965/fs: Allow SIMD16 borrow/carry/64-bit multiply on Gen > 7."
This reverts commit 9f5e5bd34d8ba48c851b442fb88f742b1ba6a571.
I have no idea what made me believe these didn't apply to Gen > 7. They
do, and without them we generate bad code that causes failures on Gen 8.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit b94a4e84987f6bdefabf45527ec434d8510da2b8
Author: Olivier Pena <opena at isagri.fr>
Date: Mon Apr 27 10:23:58 2015 +0000
scons: Support LLVM 3.5 and 3.6 on windows.
llvm/Config/llvm-config.h is parsed instead of llvm/Config/config.h for
detecting LLVM version
(http://lists.cs.uiuc.edu/pipermail/llvmdev/2014-June/073707.html).
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit dfb0b36e8ff93873920495647381b3faf30df028
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Apr 27 14:00:44 2015 -0400
mesa: fix up GLSL version when computing GL version
In some situations it is convenient for a driver to expose a higher GLSL
version while some extensions are still incomplete. However in that
situation, it would report a GLSL version that was higher than the GL
version. Avoid that situation by limiting the GLSL version to the GL
version.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 7c3d1c132eea83fb257cbc473a8a79638ddc3014
Author: Roland Scheidegger <sroland at vmware.com>
Date: Sat Apr 25 22:10:42 2015 +0200
softpipe: fix another stencil-as-float issue
Hopefully this is the last one now (for texture X32_S8X24_UINT views).
+4 piglits.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90167
Reviewed-by: Brian Paul <brianp at vmware.com>
commit dfb274af4c6e0991fa20af1606e45bea6f947fed
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Apr 24 19:33:05 2015 -0400
mesa: the function name appears to have a gl prefix already
Currently we're producing errors like
User error: GL_INVALID_OPERATION in glglDeleteProgramsARB(invalid call)
And noop_warn appears to be called with the full function name. Don't
prepend a gl prefix.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 05e7f7f4388bde882b7ce74124000a4d435affff
Author: Zoë Blade <zoe at bytenoise.co.uk>
Date: Wed Apr 22 11:33:17 2015 +0100
Fix a few typos
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit e17dc004fd96e589e92ee64deeb45339af4bf671
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Apr 13 21:38:06 2015 +0300
i965/gen8: Factor out texture surface state set-up from gen8_update_texture_surface().
This moves most of the surface state set-up logic that can be shared
between textures and shader images to a separate function.
commit 6f26ffaf66affb6563e548646fb6d6a049fe6bff
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Apr 13 21:37:02 2015 +0300
i965/gen7: Factor out texture surface state set-up from gen7_update_texture_surface().
This moves most of the surface state set-up logic that can be shared
between textures and shader images to a separate function.
commit e94c80c08b1744fb06dcdd083b92b97971e03892
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Apr 22 21:32:49 2015 +0300
i965: Add helper functions to calculate the slice pitch of an array or 3D miptree.
commit f9965347dc0cac8822c44faf7bade09093076c74
Author: Olivier Pena <opena at isagri.fr>
Date: Wed Apr 22 15:36:28 2015 +0000
scons: add target osmesa using gallium state tracker.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit db2415189a04fd64106a739c635b1433192ef969
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Apr 16 20:40:31 2015 +0200
radeonsi: set an optimal value for DB_Z_INFO.ZRANGE_PRECISION
Required because of a VI hw bug.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit bed98eef9a29af39520002e4ac1525ae0e3859cd
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Apr 16 20:37:45 2015 +0200
radeonsi: remove deprecated and useless registers
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 393b0e05319389ded24b40b81617cbe7e25ab678
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Apr 16 20:16:35 2015 +0200
radeonsi: remove useless includes
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit d8269be1ceed29d2e00829e1fd4a7bbac389d967
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Apr 16 20:15:16 2015 +0200
gallium/radeon: print winsys info with R600_DEBUG=info
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 96bbdc5188faf4c3b1df6d3a65aeb0daff61e384
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Apr 16 19:09:57 2015 +0200
winsys/radeon: make radeon_bo_vtbl static
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit ca9e280d897a307c485ef4dc7163e1f6900dc768
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Mon Aug 18 21:46:44 2014 -1000
glsl: replace while loop with without_array function
Signed-off-by: Timothy Arceri <t_arceri at yahoo.com.au>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit f00c5f85b82efe9535b18dbf97c4591fb28aeae6
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Fri Feb 27 22:43:39 2015 +1100
glsl: support packing of arrays of arrays
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit fda5f7bb2f23b4adb2f2684162dfb36fe0cb8641
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Mon Aug 18 21:40:50 2014 -1000
glsl: add arrays of arrays support to without_array function
Signed-off-by: Timothy Arceri <t_arceri at yahoo.com.au>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 9ea38ee96d483a1bc5b525f5452216f454f450ab
Author: Martin Peres <martin.peres at linux.intel.com>
Date: Mon Apr 27 10:13:49 2015 +0300
docs/GL3: started adding support for shader_image_size
Signed-off-by: Martin Peres <martin.peres at linux.intel.com>
commit 6fc0cd2f52ddc4a1e7026c9c46fd6da3968fa439
Author: Gediminas Jakutis <gediminas at varciai.lt>
Date: Sun Apr 12 02:58:33 2015 +0300
gallium/hud: add more options to customize HUD panes
Extends the syntax of GALLIUM_HUD environment variable to:
- Add options to set the size and exact location of each pane.
- Add an option to limit the maximum allowed value of the X axis on a
pane, clamping the graph down to not go above this value.
- Add an option to auto-adjust the value of the Y axis down to the
highest value still visible on the graph.
v2:
- Make the patch simpler and smaller.
- With dynamic auto-adjusting on, adjust the Y axis once per pane
update instead of updating once every several seconds.
- No longer mishandle pane height when having more than one graph per
pane.
commit 30c8d8a831edcdbac0bbaccab18cf3b53dbd08c1
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Apr 23 23:17:10 2015 -0700
i965: Fill out the rest of brw_debug_recompile_sampler_key().
This makes INTEL_DEBUG=perf report shader recompiles due to CMS vs.
UMS/IMS differences and Sandybridge textureGather workarounds.
Previously, we just flagged them as "Something else".
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 19165e3b6eff3a33379af127d27c6585ffbd1028
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Apr 23 22:56:25 2015 -0700
i965: Disassemble sampler message names on Gen5+.
Previously, sampler messages were decoded as
sampler (1, 0, 2, 2) mlen 6 rlen 8 { align1 1H };
I don't know how much time we've collectly wasted trying to read this
format. I can never recall which number is the surface index, sampler
index, message type, or...whatever that other number is. Figuring out
the message name from the numerical code is also painful.
Now they decode as:
sampler sample_l SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H };
This is easy to read at a glance, and matches the format I used for
render target formats.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit 7f5a8ac155283e78df2da5b172a65361a80d38b6
Author: Matt Turner <mattst88 at gmail.com>
Date: Sat Apr 25 01:50:04 2015 -0700
i965/fs: Disallow constant propagation into POW on Gen 6.
Fixes assertion failures in three piglit tests on Gen 6 since commit
0087cf23e.
commit 67ba388dc06456409762e66ed7ccdffebf956459
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Apr 23 10:48:47 2015 -0400
mesa: add support for exposing up to GL4.2
Add the 4.0/4.1/4.2 extensions lists to compute_version. A couple of
extensions aren't in mesa yet, so those are marked with 0 until they
become supported.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 11d2305d7fe2f8e8cd6a4f2ac5afe79718a4fa10
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Apr 24 16:23:46 2015 -0700
i965/fs: Add missing pixel_x/y to brw_instruction_name().
Forgotten in commit 529064f6.
commit 51c61fff8f46472820ac413ad22e9f3edf670396
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Apr 24 13:14:56 2015 -0700
i965/fs: Don't constant propagate into integer math instructions.
Constant combining won't promote non-floats, so this isn't safe.
Fixes regressions since commit 0087cf23e.
commit e17018589651d449bbef5f98a6c2f65cc3ca70e5
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Apr 24 22:58:23 2015 +0100
docs: add news item and link release notes for mesa 10.5.4
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 196cf8db6571b8cf7e44a4cf9d7e827e130a568d
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Apr 24 22:51:25 2015 +0100
docs: Add sha256 sums for the 10.5.4 release
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit adb47b5b279b6fd920151aa7926af6ffd2069339)
commit 5b39cb47366d1cfce206d4644983a4e5b2b76709
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Apr 24 22:27:09 2015 +0100
Add release notes for the 10.5.4 release
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit ea0d1f575c214c09ba3df12644a960e86e031766)
commit 13b2e6a520d1f8979fc4da1dd2c6811585b16203
Author: Brian Paul <brianp at vmware.com>
Date: Fri Apr 24 12:56:04 2015 -0600
mesa: put more info in glTexImage GL_OUT_OF_MEMORY error message
Give the user some idea about the size of the texture which caused
the GL_OUT_OF_MEMORY error.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 0087cf23e8e399778e93369d67dd543e767ab526
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Mar 16 17:53:34 2015 -0700
i965/fs: Allow 2-src math instructions to have immediate src1.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit f251ea393bf3d01d242e2eb56cd0f2b0e140f7b2
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Apr 24 11:37:30 2015 -0700
nir: Transform pow(x, 4) into (x*x)*(x*x).
commit 9b577d57029bb643f2b48b80648b4f901818e93b
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Mar 16 21:33:31 2015 -0700
glsl: Transform pow(x, 4) into (x*x)*(x*x).
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 18f44d303014c3c16084c1b15d1999833e0d55db
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Thu Apr 23 14:19:33 2015 +0300
mesa: fix glGetActiveUniformsiv regression
Commit 7519ddb caused regression to glGetActiveUniformsiv.
Patch adds back validation loop of all given uniforms before
writing any values, not touching params in case of errors
is tested by the conformance suite.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90149
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
commit a563689a408b7a28c710fb0e382272a0d823f38a
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Thu Apr 23 11:13:17 2015 +0300
mesa: refactor active attrib queries for glGetProgramiv
Main motivation here is to get rid of iterating IR and
encapsulate queries within program resources.
No functional changes.
Piglit tests calling the modified functionality:
- gl-get-active-attrib-returns-all-inputs
- glsl-1.50-get-active-attrib-array
- getactiveattrib
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
commit d5a15a89f081bdd23237b8ba5391a2ebea60468b
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Apr 23 11:49:27 2015 -0700
i965: Add an INTEL_DEBUG=spill option to test spilling
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit bf55096207898437a5f48ba28f98fe1b992f60e3
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Apr 23 13:59:32 2015 -0700
i965/debug: Use the ull specifier for DEBUG enum defines
The INTEL_DEBUG variable is a uint64_t and if we want a enum value higer
than 32 bits, you need to use ull. We might as well use it for all of them.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 5957da1edb9ad504d8af83878c10c3a24e41fc6c
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Apr 21 12:32:38 2015 -0700
i965: Disallow linear blits that are not cacheline aligned.
The BLT engine on Gen8+ requires linear surfaces to be cacheline
aligned. This restriction was added as part of converting the BLT to
use 48-bit addressing.
The main user, intel_emit_linear_blit, now handles this properly.
But we might also have linear miptrees; just refuse to blit those.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88521
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Cc: mesa-stable at lists.freedesktop.org
commit 8c17d53823c77ac1c56b0548e4e54f69a33285f1
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Apr 15 03:04:33 2015 -0700
i965: Make intel_emit_linear_blit handle Gen8+ alignment restrictions.
The BLT engine on Gen8+ requires linear surfaces to be cacheline
aligned. This restriction was added as part of converting the BLT to
use 48-bit addressing.
intel_emit_linear_blit needs to handle blits that are not cacheline
aligned, as we use it for arbitrary glBufferSubData calls and subrange
mappings.
Since intel_emit_linear_blit uses 1 byte per pixel, we can use the src/dst
pixel X offset field to represent the unaligned portion, and subtract
that from the address so it's cacheline aligned.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88521
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Cc: mesa-stable at lists.freedesktop.org
commit 29f0f976bd82c04c6c569658c260feaade7394cd
Author: Pali Rohár <pali.rohar at gmail.com>
Date: Thu Apr 23 22:02:07 2015 +0100
mapi: Adding missing string.h include.
File glapi_entrypoint.c calls memcpy() function, but does not include
string.h header. So compilation can fail at error: implicit declaration
of function 'memcpy'.
Signed-off-by: Jose Fonseca <jfonseca at vmware.com>
commit 525be9c0791e4a447335307b5f225273b9da0cca
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Wed Apr 22 20:23:59 2015 +0100
os/os_memory_aligned.h: Handle integer overflow.
This code is only used when our memory debugging wrappers are enabled,
as we use the C runtime functions directly elsewhere.
Tested llvmpipe on Windows w/ memory debugging enabled.
VMware PR894263.
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit f2a7fd9943fcb7d3de3bc2b21907e0a157b88e96
Author: Roland Scheidegger <sroland at vmware.com>
Date: Thu Apr 23 18:13:32 2015 +0200
draw: fix prim ids when there's no gs
We were resetting the prim id count for each run of the prim assembler,
hence this only worked when the draw calls were very small (the exact limit
depending on the vertex size), since larger draw calls get split up.
So, do the same as we do already if there's a gs, reset it to zero explicitly
for every new instance (this possibly could use the same variable but that
isn't doable without some heavy refactoring and I'm not sure it makes sense).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90130.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
CC: <mesa-stable at lists.freedesktop.org>
commit ecc7f2ed910345c4dd0d02ac9c72d69f10ac5572
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Mar 19 12:14:08 2015 +0100
gallium/radeon: don't crash when getting out-of-bounds TEMP references
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
commit 125574d1effcb3e3eda93f2b2975bc6cc606df3e
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Apr 13 14:13:16 2015 -0700
nir/lower_source_mods: Don't propagate register sources
The nir_lower_source_mods pass does a weak form of copy propagation to
clean up all of the mov-with-negate's that get generated. However, we
weren't properly checking that the sources were SSA and so we could end up
moving a register read which is not, in general, valid.
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 296131f4674ee979a8cffe56fc61bbd42110982e
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Apr 13 14:02:21 2015 -0700
nir: Rewrite instr_rewrite_src
The old code wasn't correctly handling the case where the new value of the
source contains an indirect.
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit d61bd972d861d9246fe7f9de71158aa79368bb79
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Apr 10 17:38:17 2015 -0700
nir/locals_to_regs: Hanadle indirect accesses of length-1 arrays
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 06f3c98b9da35b5f5c02bd30599fbde57a19520e
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Apr 10 15:39:34 2015 -0700
nir/locals_to_regs: Initialize registers with constant initializers
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 4e9b3765947f2c98d618082cd449db2e319bd887
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Apr 10 14:50:06 2015 -0700
nir/locals_to_regs: Pass around the nir_shader rather than a void * mem_ctx
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit f50f59d3d92061e69713b072aade66195dececd8
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Apr 10 17:06:05 2015 -0700
nir: Add a simple growing array data structure
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 8b900e74058dd48368511780a488ccb7a645c64f
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Apr 10 16:16:02 2015 -0700
nir/types: Make glsl_get_length smarter
Previously, this function returned the number of elements for structures
and arrays and 0 for everything else. In NIR, this is almost never what
you want because we also treat matricies as arrays so you have to
special-case constantly. This commit glsl_get_length treat matrices
as an array of columns by returning the number of columns instead of 0
This also fixes a bug in locals_to_regs caused by not checking for the
matrix case in one place.
v2: Only special-case for matrices and return a length of 0 for vectors as
we did before. This was needed to not break the TGSI-based drivers and
doesn't really affect NIR at the moment.
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Tested-by: Rob Clark <robclark at freedesktop.org>
commit 7e1d21edbff772f6dfc727e0e09788d87e00e0f5
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Apr 10 14:46:22 2015 -0700
nir: Move get_const_initializer_load from vars_to_ssa to NIR core
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit ba887602022340c596a09534e61b6554e3aeb533
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Apr 10 14:43:28 2015 -0700
nir/lower_vars_to_ssa: Pass around the nir_shader instead of a void mem_ctx
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit c68364ac341d5fbbc5b6dcf74812a776359c0168
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Apr 10 11:52:08 2015 -0700
i965/nir: Use the correct offsets when handling register indirects
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit e79120afdc17c04143ef4d7fb71394a5053114a5
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Apr 9 21:09:48 2015 -0700
nir/print: Print the closing paren on load_const instructions
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 02f03fc0f111c484bd26497a85cbca7245400f68
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Apr 9 21:04:21 2015 -0700
nir/tex: Use the correct return size for query_levels and lod
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 94669cb53483bd58f33e439411af3cb5c006da79
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Apr 9 21:03:02 2015 -0700
nir: Refactor tex_instr_dest_size to use a switch statement
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 73cc76362dd93a2b8b35583cc12cc3a61a61ea83
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Apr 9 20:45:45 2015 -0700
nir/lower_vars_to_ssa: Actually look for indirects when determining aliasing
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 734bceed8609a74d83032380e83488f3d2497012
Author: Dave Airlie <airlied at gmail.com>
Date: Sun Apr 5 14:46:11 2015 +1000
docs: mark off texture_stencil8 (v2.1)
copy drivers from the stencil_texturing list,
softpipe is definitely broken for stencil texturing
since it uses float, but I'll look at that later.
v2.1: update relnotes
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 6cc49c4ce1dcb06528bfa2d6e650c26721355ae1
Author: Dave Airlie <airlied at gmail.com>
Date: Sun Apr 5 14:45:25 2015 +1000
st/mesa: add ARB_texture_stencil8 support (v4)
if we support stencil texturing, enable texture_stencil8
there is no requirement to support native S8 for this,
the texture can be converted to x24s8 fine.
v2: fold fixes from Marek in:
a) put S8 last in the list
b) fix renderable to always test for d/s renderable
fixup the texture case to use a stencil only format
for picking the format for the texture view.
v3: hit fallback for getteximage
v4: put s8 back in front, it shouldn't get picked now (Ilia)
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 782e71cc078308dddd5d6f9505bff0cb8e67f455
Author: Dave Airlie <airlied at gmail.com>
Date: Sun Apr 5 13:19:18 2015 +1000
mesa: finish implementing ARB_texture_stencil8 (v5)
Parts of this were implemented previously, so finish it off.
v2: fix getteximage falling into the integer check
add fixes for the FBO paths, (fbo-stencil8 test).
v3: fix getteximage path harder.
v4: remove swapbytes from getteximage path (Ilia)
v5: brown paper bag the swapbytes removal. (Ilia)
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 1948880720a631f959c6fa7f5bc533f26619a31a
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Apr 22 09:30:30 2015 -0700
mesa: remove the gl_sl_pragmas structure
This code was added by Brian Paul in 2009 but, as far as Matt and I can
tell, it's been dead ever since the new GLSL compiler was added.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit ae3870df7043861632aa553e12cc9284a9aef827
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Apr 16 12:01:09 2015 -0700
i965: Add a brw_compiler structure and store the register sets in it
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit a85c4c9b3f75cac9ab133caa91a40eec2e4816ae
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Apr 16 11:06:57 2015 -0700
i965: Rename brw_compile to brw_codegen
This name better matches what it's actually used for. The patch was
generated with the following command:
for file in *; do
sed -i -e s/brw_compile/brw_codegen/g $file
done
Signed-off-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit cfc56fcee36912d5fb41262c71463292a737160e
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Apr 17 12:52:00 2015 -0700
i965: Use device_info instead of the context for computing vue maps
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 02ccb19495c5804f4ab798c00eeb786ee77aaacc
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Apr 17 12:15:58 2015 -0700
i965: Use device_info instead of the context in instruction scheduling
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 28e9601d0e681411b60a7de8be9f401b0df77d29
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Apr 15 18:00:05 2015 -0700
i965: Add a devinfo field to backend_visitor and use it for gen checks
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 73bf8f3d6b6b571175c5ce324b44fef26915875f
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Apr 15 17:39:25 2015 -0700
i965: Remove remaining uses of ctx->Const.UniformBooleanTrue in visitors
Since commit 2881b123, we have used 0/~0 for representing booleans on all
gens. However, we still had a bunch of places in the visitor code where we
were still referring to ctx->Const.UniformBooleanTrue. Since this is
always ~0, we can just remove them.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 2bf207b47347ec1c672448e3019029f899a5d3b5
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Apr 16 10:30:05 2015 -0700
i965/vec4: Add a devinfo field to the generator and use it for gen checks
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 5bda1ff1bec0e01300a4e8e3da38168958df9ebc
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Apr 14 17:45:40 2015 -0700
i965/fs: Add a devinfo field to the generator and use it for gen checks
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 38dc2ddab4a25398ebd07e1ecf52daa7466b6963
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Apr 16 17:52:03 2015 -0700
i965/device_info: Add a supports_simd16_3src flag
This also involves moving revision checking to screen creation time and
passing that into brw_get_device_info so that we can get the right
device_info for early versions of SKL. Since the only place we used
revision was to check for SIMD16 3-src instruction support, it's safe to
remove the revision field from brw_context.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 85db2aca52acd7f05e1d8cb3300c64f0307e39a9
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Apr 16 17:50:43 2015 -0700
i965/device_info: Add a HSW_FEATURES macro
It's basically just a copy of GEN7_FEATURES only with is_haswell set
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 9c89e47806ee0437a2617eb4b90a0b953869fea2
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Apr 15 15:01:25 2015 -0700
i965: Make the annotation code take a device_info instead of a context
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 5cb91db619e8689c8fd45a67b57b96fc36f4ca9b
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Apr 15 14:51:18 2015 -0700
i965/fs: Remove the GL context from the generator
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 61c4702489fa1694892c5ce90ccf65a5094df3e7
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Apr 15 14:13:58 2015 -0700
i965: Remove the context field from brw_compiler
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 639314d40e78b5b56c3fc840b2f416e7fc519a4d
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Apr 15 13:46:21 2015 -0700
i965: Make the disassembler take a device_info instead of a context
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit c3e5f32840fbc7b44a15b2c7c7d7299cbd6d332a
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Apr 15 13:19:21 2015 -0700
i965: Make instruction compaction take a device_info instead of a context
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 4e9c79c847c81701300b5b0d97d85dcfad32239a
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Apr 14 18:00:06 2015 -0700
i965: Make the brw_inst helpers take a device_info instead of a context
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 6219a8f098f4e18ff974db380e97a351c8e78906
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Apr 14 16:57:24 2015 -0700
i965/eu: Add a devinfo parameter to brw_compile
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit a921475c22fe88fb6921a1f628d3ea05d55ba43b
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Apr 17 15:23:18 2015 -0700
i965: Do better fake context setup in unit tests
In future tests, we will start relying on devinfo and not just brw in the
compiler. Changing this now keeps these tests from failing in the future.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit ceb6e5eebe13b85f57cf5a7a22371c10170943a3
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Apr 14 14:23:40 2015 -0700
i965: Remove the context parameter from brw_texture_offset
It wasn't really being used anyway. We used it to assert that gpu_shader5
is supported in the back-end but that should be caught by the front-end.
Signed-off-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 8a41cd2407c1d219cba98add69609ce3a65b5435
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Apr 22 17:13:06 2015 +1000
softpipe: fix stencil write to use an integer value
This fixes a number of regressions since
61393bdcdc3b63624bf6e9730444f5e9deeedfc8
u_tile: fix stencil texturing tests under softpipe
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89960
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 2c08e3b8ea6d3f689a138d19bc812551ca966415
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Wed Apr 22 11:23:49 2015 -0700
mesa: Fix typo in a comment
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit cb24d3b7ad2f6c03edd86d827db2b308670ae8a7
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Apr 22 13:11:33 2015 -0400
freedreno: misc minor cleanups
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 1b58d8c2bf6136af2a89178f9da4e5f0631d2909
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Apr 22 13:09:28 2015 -0400
freedreno/a4xx: (partial) gl_FragCoord.zw
The bit to enable .z is still commented out, as it is triggering gpu
hangs in 0ad. But at least gl_FragCoord.w works now, and we know what
bits we are *supposed* to set for .z (with that uncommented all piglit
fragcoord tests are passing).
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit a86918312320ccc2e6dafae25fd5800ef62b3710
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Apr 22 13:08:44 2015 -0400
freedreno/a4xx: primitive-restart
This was the missing bit to get dolphin-emu working on a4xx.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 632ea2a1139f4b228ca55331e411dbae9920c28d
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Apr 22 13:07:33 2015 -0400
freedreno/nir: sysval fixes
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 13527df143be1ca6e2f69bf4728f69efaebb3b13
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Apr 22 13:05:53 2015 -0400
freedreno/a4xx: wire up integer texture sampling
Similar to a3xx, the compiler needs to know the return type of the sam,
etc, instructions.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 48a651e98ce764a9dae3d4dfd6e18044414be18b
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Apr 22 13:00:03 2015 -0400
freedreno/a4xx: formats updates/fixes
Update formats table with new formats that Ilia has figured out, and fix
sampling from srgb texture and integer vbo's.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 21ceedfd8bd1b9e45ee12be24b328876bd7fa4eb
Author: Rob Clark <robclark at freedesktop.org>
Date: Sat Apr 18 12:08:53 2015 -0400
freedreno: update generated headers
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 9450bd56bee3ab99c33be2e08317990fa7563520
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Mar 20 21:20:10 2015 +0000
gallium/targets/d3dadapter9: drop the libdrm prefix for drm.h
The path is provided by libdrm.pc and already used appropriately by
the build system.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 02e93be55e81d5ff257f4717eb3fdb5a8f79b544
Author: Brian Paul <brianp at vmware.com>
Date: Tue Apr 21 08:10:22 2015 -0600
cso: minor comment fix
commit 31667e6237d30188d0b29e17f5b9892f10c0d83a
Author: Brian Paul <brianp at vmware.com>
Date: Thu Apr 16 15:29:18 2015 -0600
glsl: rewrite glsl_type::record_key_hash() to avoid buffer overflow
This should be more efficient than the previous snprintf() solution.
But more importantly, it avoids a buffer overflow bug that could result
in crashes or unpredictable results when processing very large interface
blocks.
For the app in question, key->length = 103 for some interfaces. The check
if size >= sizeof(hash_key) was insufficient to prevent overflows of the
hash_key[128] array because it didn't account for the terminating zero.
In this case, this caused the call to hash_table_string_hash() to return
different results for identical inputs, and then shader linking failed.
This new solution also takes all structure fields into account instead
of just the first 15 when sizeof(pointer)==8.
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit bd4dbdfa519362f74263a2c277a3b4be841acd06
Author: Brian Paul <brianp at vmware.com>
Date: Thu Apr 16 15:27:41 2015 -0600
mesa: add check for NV_texture_barrier in _mesa_TextureBarrierNV()
If an app called glTextureBarrierNV() without checking if the
extension was available, we'd crash with some gallium drivers
in st_TextureBarrier() because the pipe_context::texture_barrier()
pointer was NULL.
Generate GL_INVALID_OPERATION instead.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit b260d9d91f84f26676cf8baf42c6df88678be668
Author: Brian Paul <brianp at vmware.com>
Date: Thu Apr 16 15:27:20 2015 -0600
main: silence missing return value warning in array_index_of_resource()
v2: return -1 instead of 0, per Emil Velikov.
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 0b1823f5beeeb7a35e3addee071b31ac227734dc
Author: Chih-Wei Huang <cwhuang at android-x86.org>
Date: Sat Apr 4 05:01:26 2015 +0800
android: re-build all mesa binaries properly
The clean steps ensure both 32-bit and 64-bit objects are cleaned.
Signed-off-by: Chih-Wei Huang <cwhuang at linux.org.tw>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 36e59215bab203236602e0f5734dffe8339c58ba
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Apr 22 15:38:57 2015 +0100
android: xmlpool: cleanup the generation rules
- Do not attempt to create the save folder twice - both dir $@ and
PRIVATE_LOCALEDIR point to the same place.
- Use @ and $(hide), for mkdir and python, to avoid spamming the
output.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 98c8997fe5e4be1b158944d2bd58dba42afb4e1e
Author: Chih-Wei Huang <cwhuang at android-x86.org>
Date: Sat Apr 4 05:01:24 2015 +0800
android: xmlpool: Get rid of the last use of intermediates-dir-for
v2 [Emil Velikov]
- Keep the PRIVATE_LOCALEDIR variable.
- Do not use $(@D) but the more widespead $(dir $@)
Signed-off-by: Chih-Wei Huang <cwhuang at linux.org.tw>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 5b8d61b0ccf9c3228bef680b02c128734270a9d9
Author: Chih-Wei Huang <cwhuang at android-x86.org>
Date: Sat Apr 4 05:01:23 2015 +0800
android: export the path of the generated headers
The modules need the headers can get the path automatically.
Signed-off-by: Chih-Wei Huang <cwhuang at linux.org.tw>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit b0e33c2256a68d87c4f67b6e25a86e594649ab93
Author: Chih-Wei Huang <cwhuang at android-x86.org>
Date: Sat Apr 4 05:01:22 2015 +0800
android: fix the building rules for Android 5.0
Android 5.0 allows modules to generate source into $OUT/gen, which will
then be copied into $OUT/obj and $OUT/obj_$(TARGET_2ND_ARCH) as necessary.
Modules will need to change calls to local-intermediates-dir into
local-generated-sources-dir.
The patch changes local-intermediates-dir into local-generated-sources-dir.
If the Android version is less than 5.0, fallback to local-intermediates-dir.
The patch also fixes the 64-bit building issue of Android 5.0.
v2 [Emil Velikov]
- Keep the LOCAL_UNSTRIPPED_PATH variable.
Signed-off-by: Chih-Wei Huang <cwhuang at linux.org.tw>
commit 671a55084649f9e33018b1e5e1af4e28c639bf3b
Author: Chih-Wei Huang <cwhuang at android-x86.org>
Date: Sat Apr 4 05:01:21 2015 +0800
android: fix building issues of host binaries
Define _GNU_SOURCE to enable features (__USE_XOPEN2K and __USE_UNIX98)
required to build the host binaries.
Signed-off-by: Chih-Wei Huang <cwhuang at linux.org.tw>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 076edc6a036cb7601e010b7851eeaa7cfb1aa4e6
Author: Chih-Wei Huang <cwhuang at android-x86.org>
Date: Thu Apr 2 14:16:33 2015 +0800
android: fix a building error of libmesa_program
Add libmesa_glsl to LOCAL_STATIC_LIBRARIES to get
its exported include path (for nir_opcodes.h).
Signed-off-by: Chih-Wei Huang <cwhuang at linux.org.tw>
commit 8098bf8e7a975a18b271b44e760ff86feddb0472
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Apr 22 15:53:11 2015 +0100
android: mesa: fold the ARCH_X86_HAVE_SSE4_1 conditionals
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 669cfc267a1102ff903b3e562f9aa45a410e0312
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Mar 28 18:23:01 2015 +0000
android: mesa: fix the path of the SSE4_1 optimisations
Commit dd6f641303c(mesa: Build with subdir-objects.) removed the SRCDIR
variable, but forgot to update all references of it.
v2: Fix path - must be relative to LOCAL_PATH. (Chih-Wei)
Cc: "10.5" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Chih-Wei Huang <cwhuang at linux.org.tw>
commit 64171c2d24196801cbb5b549fdc90743c42e3257
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Mar 28 18:12:23 2015 +0000
android: build the Mesa IR -> NIR translator
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit c734261dcf91fef6f3f55096835608a600bddec4
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Apr 22 14:51:31 2015 +0100
android: nir: add build rules for nir_builder_opcodes.h
Missed out with commit 2a135c470e3(nir: Add an ALU op builder kind of
like ir_builder.h)
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 06619749a11651a50e353168c7c793082820585d
Author: Mauro Rossi <issor.oruam at gmail.com>
Date: Fri Mar 27 22:25:45 2015 +0000
android: add inital NIR build
Required by the i965 driver.
v2:
- Split out the nir_builder_opcodes.h rules.
- Do not unconditionally hide the python command - use $(hide)
- Use LOCAL_EXPORT_C_INCLUDE_DIRS to manage includes for the generated
sources.
Cc: "10.5" <mesa-stable at lists.freedesktop.org>
[Emil Velikov: Split from a larger commit, v2]
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Chih-Wei Huang <cwhuang at linux.org.tw>
commit 618885f71fcacb3d68bf37fa23be36830d4178d2
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Mar 27 21:39:15 2015 +0000
android: dri: link against libmesa_util
The dri modules depend on symbols provided by it.
Cc: "10.5" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Chih-Wei Huang <cwhuang at linux.org.tw>
commit 0afbd2df0485cd480979d9f4cdae00262d1a3c62
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Mar 28 01:11:54 2015 +0000
android: add $(mesa_top)/src/mesa/main to the includes list
Required by the format_{un,}pack rework. Otherwise the build will fail
to locate the respective headers - format_{un,}pack.h
Cc: "10.5" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Chih-Wei Huang <cwhuang at linux.org.tw>
commit 39a175e0c792f569dfe73de1b4d01b0caea43a01
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Mar 27 20:10:35 2015 +0000
android: add HAVE__BUILTIN_* and HAVE_FUNC_ATTRIBUTE_* defines
All of those are available on gcc 4.5 and later with the current android
build using gcc 4.7.
Cc: "10.4 10.5" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Chih-Wei Huang <cwhuang at linux.org.tw>
commit 94cab35ee93ed200013eddffa4c97828bd6aa82c
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Mar 28 01:10:52 2015 +0000
android: add gallium dirs to more places in the tree
Similar to e8c5cbfd921(mesa: Add gallium include dirs to more parts of
the tree.)
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Chih-Wei Huang <cwhuang at linux.org.tw>
commit 8d90bfb724f89b04d703f869362cf2fc2a3d7567
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Mar 27 18:57:46 2015 +0000
android: dri/common: conditionally include drm_cflags/set __NOT_HAVE_DRM_H
Otherwise we'll fail to find the drm.h header.
Cc: "10.4 10.5" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 2d06791f6f9e8ab37109be52e63d247bbbcb42d4
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Mar 27 18:36:10 2015 +0000
android: egl: add libsync_cflags to the build
... via local_shared_libraries. Otherwise the sync/sync.h header won't
be found.
Note: 10.5 and earlier will need similar change in st/egl.
v2: Append the library to the local_shared_libraries list. (Chih-Wei)
Cc: "10.4 10.5" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Chih-Wei Huang <cwhuang at linux.org.tw>
commit 5f7081eb90bc5a25f0740314fa22e04d189238ca
Author: Mauro Rossi <issor.oruam at gmail.com>
Date: Fri Mar 27 18:20:53 2015 +0000
android: mesa: generate the format_{un,}pack.[ch] sources
Missed out with commit e1fdcddafe9(mesa: Autogenerate format_unpack.c)
v2: Conditionaly print the python commands - s/@/$(hide) / (Chih-Wei)
Cc: "10.5" <mesa-stable at lists.freedesktop.org>
[Emil Velikov: Split our from a larger commit.]
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 6fb801786604c270fae99c3d665dcebaa0bff3a6
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Mar 27 16:13:50 2015 +0000
android: add $(mesa_top)/src include to the whole of mesa
Many parts of mesa already have the include with others depending on it
but it's missing. Add it once at the top makefile and be done with it.
Cc: "10.4 10.5" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Chih-Wei Huang <cwhuang at linux.org.tw>
commit ba3bc1eea2f41e06a6c4300d4bc2b3547dbcaaec
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Mar 27 14:18:24 2015 +0000
android: use := operator for assigning MESA_VERSION
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 6c2c5f74a2e8d94d22454bd19cf961a66bfc9103
Author: Chih-Wei Huang <cwhuang at linux.org.tw>
Date: Thu Jan 22 01:21:00 2015 +0800
util: android: optimize the rules to generate format_srgb.c
Signed-off-by: Chih-Wei Huang <cwhuang at linux.org.tw>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 63a76c15d8c259edc1a6bf8b696f109c86eace2e
Author: Chih-Wei Huang <cwhuang at linux.org.tw>
Date: Thu Jan 22 01:17:42 2015 +0800
android: simplify the subdirs including rules
Use the macro defined in the Android build system.
Signed-off-by: Chih-Wei Huang <cwhuang at linux.org.tw>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 86919352e3da1c80409fdcb67c36f29a9687b7a9
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Mar 27 11:40:42 2015 +0000
android: use LOCAL_SHARED_LIBRARIES over TARGET_OUT_HEADERS
... to manage the LIBDRM*_CFLAGS. The former is the recommended approach
by the Android build system developers while the latter has been
depreciated for quite some time.
Cc: "10.4 10.5" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 413bc0a618d39873336cbfaf8fb5e43217f66ccf
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Mar 27 11:13:21 2015 +0000
ilo: remove unused include from Android.mk
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Chih-Wei Huang <cwhuang at linux.org.tw>
commit 00bf7d2e9cd60dbd82d25b459c448e11c545a89a
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Apr 10 10:24:33 2015 -0700
drirc: Add "Second Life" quirk (allow_glsl_extension_directive_midshader).
Appears to fix shader compilation. Tested by starting the client,
dragging the "quality and speed" slider back and forth, and watching the
console output - instead of piles of "shader failed to compile", the CPU
seems to be busy compiling shaders. I haven't actually tried to play.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=69226
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71591
Cc: mesa-stable at lists.freedesktop.org
commit 44461e70985278464f5c2ce89bda2336c7299b0b
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Apr 17 14:08:14 2015 -0700
nir: Fix per-component negation in prog_to_nir's SWZ handling.
I missed the fact that the ARB_fragment_program SWZ instruction allows
per-component negation. To fix this, move Abs/Negate handling into both
the simple case and the SWZ case's per-component loop.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90000
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit ed10f9cfad1a01226725d542155a240bcf70e9cb
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Tue Apr 21 20:11:43 2015 +0300
glsl: correct indentation of comment, Trivial.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
commit 529064f6a80d72294cc865a46304110e0401296d
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Apr 14 13:17:38 2015 -0700
i965/fs: Combine pixel center calculation into one inst.
The X and Y values come interleaved in g1 (.4-.11 inclusive), so we can
calculate them together with a single add(32) instruction on some
platforms like Broadwell and newer or in SIMD8 elsewhere.
Note that I also moved the PIXEL_X/PIXEL_Y virtual opcodes from before
LINTERP to after it. That's because the writes_accumulator_implicitly()
function in backend_instruction tests for <= LINTERP for determining
whether the instruction indeed writes the accumulator implicitly. The
old FS_OPCODE_PIXEL_X/Y emitted ADD instructions, which did, but the new
opcodes just emit MOVs, which don't. It doesn't matter, since we don't
use these opcodes on Gen4/5 anymore, but in the case that we do...
On Broadwell:
total instructions in shared programs: 7192355 -> 7186224 (-0.09%)
instructions in affected programs: 1190700 -> 1184569 (-0.51%)
helped: 6131
On Haswell:
total instructions in shared programs: 6155979 -> 6152800 (-0.05%)
instructions in affected programs: 652362 -> 649183 (-0.49%)
helped: 3179
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 5af0604d528733af9113a6f8711c39796ce0ae40
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Apr 6 17:44:40 2015 -0700
i965/fs: Calculate delta_x and delta_y together.
This lets SIMD16 programs on G45 and Gen5 use the PLN instruction.
On Ironlake:
total instructions in shared programs: 5634757 -> 5518055 (-2.07%)
instructions in affected programs: 1745837 -> 1629135 (-6.68%)
helped: 11439
HURT: 4
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit fde3100fe65a175f034c77e7989601839c9983bb
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu Apr 2 16:15:53 2015 -0700
i965/fs: Emit ADDs for gl_FragCoord, not virtual opcodes.
These were used only on Gen4 and 5. emit_interpolation_setup_gen6() emits
ADDs directly. The virtual opcodes weren't providing anything useful.
I'm going to repurpose these opcodes, so deleting and readding them makes
it simpler to see what's going on.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit b14313e45295d91b5737775ec788c76d8f0c2f93
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Apr 6 21:46:54 2015 -0700
i965/fs: Manually set source regioning on PLN instructions.
Like LINE (commit 92346db0), src0 must have a scalar region. Setting
src1's region to <8,8,1> lets us pass a properly sized combined delta_xy
argument in a few commits without getting a bogus <16,16,1> region.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit a1dd2f0bb6f9bf61d4a40d033740140b86c060e0
Author: Matt Turner <mattst88 at gmail.com>
Date: Sat Apr 11 15:00:19 2015 -0700
i965/fs: Add LINTERP's src0 to fs_inst::regs_read().
LINTERP's src0 is PLN's src1, and PLN's src1 reads exec_size / 4
registers.
Having that information lets us drop the delta_x/y special case code in
split_virtual_grfs().
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 8bc49f9536058a8373d3057324e22fcbf79a7d89
Author: Matt Turner <mattst88 at gmail.com>
Date: Sat Apr 11 14:51:13 2015 -0700
i965/fs: Set compression only if writing two registers.
We don't want to set compression control on a SIMD16 instruction
operating on words or smaller.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit b5a5b63548e9b27a3d0b8ad1b399006c71dcc3c4
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Apr 3 17:44:06 2015 -0700
i965/fs: Allow an execution size of 32.
In a few commits, we'll start emitting an add(32) instruction on some
platforms.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 45a13486126fdf0cbb68b7a888cff642c32c1d12
Author: Matt Turner <mattst88 at gmail.com>
Date: Sat Apr 11 14:49:50 2015 -0700
i965: Make type_sz() return unsigned.
Avoids annoying warnings when comparing with sizeof(...).
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit dd5c8250537640f92dbc1ee63d516c6e3e2aaf77
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Apr 14 12:40:34 2015 -0700
i965: Replace guess_execution_size with something simpler.
guess_execution_size() does two things:
1. Cope with small destination registers.
2. Cope with SIMD8 vs SIMD16 mode.
This patch replaces the first with a simple if block in brw_set_dest: if
the destination register width is less than 8, you probably want the
execution size to match. (I didn't put this in the 3src block because
it doesn't seem to matter.)
Since only the FS compiler cares about SIMD16 mode, it's easy to just
set the default execution size there.
This pattern was already been proven in the Gen8+ generator, but we
didn't port it back to the existing generator when we combined the two.
This is based on a patch from Ken from about a year ago. I've rebased it
and and fixed a few bugs.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 3b4abdae041802183fa7d3792a21bf9ca10df96e
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu Apr 2 16:57:10 2015 -0700
i965/fs: Ensure delta_x/y are even-aligned registers on Gen6.
The BSpec says this applies to Gen6 as well.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 958b4965a23f69085dc04df165d6fccc2707d60e
Author: Marius Predut <marius.predut at intel.com>
Date: Thu Apr 16 13:36:07 2015 +0300
main: remove __FUNCTION__ defined because it is obsolete
Consistently just use C99's __func__ everywhere.
No functional changes.
Signed-off-by: Marius Predut <marius.predut at intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit d8b14a57a98f4bad6528eda8dd1406c15bdcce75
Author: Marius Predut <marius.predut at intel.com>
Date: Thu Apr 16 13:35:50 2015 +0300
radeon: replace __FUNCTION__ with __func__
Consistently just use C99's __func__ everywhere.
No functional changes.
Signed-off-by: Marius Predut <marius.predut at intel.com>
Acked-by: Michel Dänzer <michel.daenzer at amd.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit ad5ae271e7514e35e97c58f032b2949e3eee62c3
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Tue Apr 21 08:26:03 2015 +0300
mesa: add missing break in switch statement
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-By: Martin Peres <martin.peres at linux.intel.com>
commit 5917ca349ae88b35779179a6a0d949ec910bc680
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Tue Apr 21 08:25:16 2015 +0300
glsl: add fallthrough comment on switch
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-By: Martin Peres <martin.peres at linux.intel.com>
commit 054c7dc7eb091e631a01ade3e6a46d6cc77fc9f3
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Mon Apr 20 15:41:06 2015 +0300
mesa: fix UBO queries for active uniforms
Commit 34df5eb introduced regression to GetActiveUniformBlockiv
when querying one of the following properties:
GL_UNIFORM_BLOCK_ACTIVE_UNIFORMS
GL_UNIFORM_BLOCK_ACTIVE_UNIFORM_INDICES
Implementation counted all uniforms in ubo directly while query should
check first if the uniform in question is _active_.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90109
Reviewed-By: Martin Peres <martin.peres at linux.intel.com>
commit 7004632b28d8a31b16acc553a1fb31202767bd80
Author: Neil Roberts <neil at linux.intel.com>
Date: Wed Feb 18 18:41:58 2015 +0000
i965/skl: Fix the qpitch value
On Skylake the qpitch value is uploaded as part of the surface state
so we don't need to add the extra rows that are done for other
generations. However for 3D textures it needs to be aligned to the
tile height and for depth/stencil textures it needs to be a multiple
of 8. Unlike previous generations the qpitch is measured as a multiple
of the block size for compressed surfaces. When the horizontal mipmap
layout is used for 1D textures then the qpitch is measured in pixels
instead of rows.
v2: Align the depth/stencil textures to a multiple of 8
v3: Add an assert that ALL_SLICES_AT_EACH_LOD is not used. Ignore the
vertical alignment when picking the qpitch for 1D_ARRAY textures.
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 584f8e1ec56b45057b53e161233308f38e1c3b09
Author: Neil Roberts <neil at linux.intel.com>
Date: Fri Feb 20 19:11:46 2015 +0000
i965/skl: Don't use ALL_SLICES_AT_EACH_LOD
The render surface state command for Skylake doesn't have the surface
array spacing bit so it's not possible to select this layout. I think
it was only used in order to make it pick a tightly-packed qpitch
value that doesn't include space for the mipmaps. However this won't
be necessary after the next patch because it will automatically pick a
packed qpitch value whenever first_level==last_level. It is better to
remove this layout entirely on Gen8+ because although it can
effectively be implemented with a small qpitch value when there are no
mipmaps it isn't possible to support the case where there are mipmaps
because in that case the layout is very different.
It could be good to make a similar change for Gen8 if we also change
the layouting code to pick the qpitch value in a similar way.
v2: Make the commit message and comments more convincing
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
Tested-by: Ben Widawsky <ben at bwidawsk.net>
commit c1485f4b7d044724b3dbc1011f3c3a8a53132010
Author: EdB <edb+mesa at sigluy.net>
Date: Sun Apr 19 10:50:19 2015 +0200
clover: remove pre llvm 3.5.0 compatibility code
Acked-by: Francisco Jerez <currojerez at riseup.net>
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
commit f39cd716189f4b025f9c04cb3426c6b25b9eaf46
Author: EdB <edb+mesa at sigluy.net>
Date: Mon Apr 20 20:28:09 2015 +0200
clover: make llvm >= 3.5.0 and c++11 mandatory
Clover not longer compile with llvm <= 3.5.0 since e1d363b3.
e1d363b3 implies c++11 and llvm 3.5.0 CXXFLAGS provided it.
No one seems to have noticed it, it's now official.
Acked-by: Francisco Jerez <currojerez at riseup.net>
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
commit 3282e57bcfc44cce751afac94a421fc035d831f3
Author: Dave Airlie <airlied at gmail.com>
Date: Mon Apr 20 18:41:52 2015 +1000
docs/GL3.txt: update ARB_shader_subroutine status
Admit to having started working on this, I don't admit to ever finishing it
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 645f77fe50c1f04eb77d03b3feaaa5fd36d1d1a4
Author: Nick Sarnie <commendsarnex at gmail.com>
Date: Sun Apr 19 23:51:26 2015 -0400
gallivm: Fix build against LLVM 3.7 SVN r235265
LLVM removed JITEmitDebugInfo from TargetOptions since they weren't used
v2: Be consistent with the LLVM version check (Aaron Watry)
Signed-off-by: Nick Sarnie <commendsarnex at gmail.com>
Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer at amd.com>
commit c015008ee07745d29dde3502c1e2b34a1127d33e
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Thu Apr 16 12:17:19 2015 -0700
doc: Add GL_ARB_shader_image_size dependency for OpenGL ES 3.1
imageSize() is in the GLSL ES 3.1 spec. Trivial.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
commit b2e871bd484db229978cfe4b7efa12dfd79067a8
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Tue Apr 7 01:42:05 2015 -0400
indices: fix provoking vertex for quads/quadstrips
This allows drivers to provide consistent flat shading for quads.
Otherwise a driver that only supported tris would have to force last
provoking vertex when drawing quads (and would have to say that quads
don't follow the provoking vertex convention).
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Rob Clark <robclark at freedesktop.org>
commit 1cdb01d716cb8112c67f8538f7d71d0765153eb2
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Tue Apr 7 11:43:52 2015 -0400
primconvert: select pv convention only from flatshade_first
This should match to how drivers program hardware. flatshade relates to
whether color inputs are interpolated, not the provoking vertex
convention.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Rob Clark <robclark at freedesktop.org>
commit 0904774af1ff9202863e7c935ff9bc076d533fb3
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Tue Apr 7 00:57:34 2015 -0400
freedreno/a3xx: enable polymode setting with non-fill modes
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 63576016284e15e881fcd8bd6d3939b5d8b53572
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Apr 6 01:15:09 2015 -0400
freedreno/a3xx: fix integer and 32-bit float border colors
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 6895c3554eadaf187642a513bb95fef1a7e07f57
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Apr 5 21:38:57 2015 -0400
freedreno/a3xx: add support for float R/RG render targets
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 1eac3ae1a6ebecf353054d937dd603a11ea33fb3
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Fri Apr 17 12:53:53 2015 -0400
mesa: add .mesa-install-links files to gitignore
Signed-off-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 65f13352b901ba08c69d3e0a884f6029297f7fda
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Fri Apr 17 12:50:30 2015 -0400
mesa/main: add autogenerated format-info.c to gitignore
v2: move to right after format-info.h
Signed-off-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 1d6829813ef2b002fca488e6a8051e3090bf87bd
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Feb 24 21:34:30 2015 -0800
i965: Issue perf_debug messages for unsynchronized maps on !LLC systems.
We haven't implemented proper unsynchronized map support on !LLC systems
(pre-SNB, Atom). MapBufferRange with GL_MAP_UNSYNCHRONIZE_BIT will
actually do a synchronized map, probably killing performance.
Also warn on BufferSubData, when we should be doing an unsynchronized
upload, but instead have to do a synchronous map.
v2: Only complain if the buffer is actually busy - we use unsynchronized
maps internally for vertex upload and such, but expect those to not
be busy.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
Tested-by: Ben Widawsky <ben at bwidawsk.net>
commit cd9058fae3eddaa0e88cd3557684700852f86a5a
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Apr 15 02:16:47 2015 -0700
i965: Make shader_time store names/ids instead of referencing shaders.
Jason noticed that shader_time was bumping the reference count on the
gl_shader_program and gl_program structures, in code called during
compilation.
Not only were these never unreferenced, but it meant fragment shaders
might be referenced twice (SIMD8 and SIMD16)...or only once.
We don't actually need the programs. We just need their numeric ID and
their language (GLSL/ARB/FF) or KHR_debug label. If there's a label, we
have to strdup it since the underlying program could be deleted.
To be fair, we're not exactly cleaning that up either, but we at least
ralloc it out of the shader_time arrays, so if we ever bother cleaning
those up, they'll go away properly.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Acked-by: Anuj Phogat <anuj.phogat at gmail.com>
commit eb6e770889536e44da0947b64955e9a923ba98f6
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Apr 15 02:04:17 2015 -0700
i965: Delete some unnecessary code in brw_report_shader_time().
It is true that a gl_shader_program with ID 0 will be a fixed-function
fragment program; a gl_program with ID 0 but NULL gl_shader_program
means that it's a fixed-function vertex shader.
But that's not terribly interesting or relevant to what we're doing.
We just need to know that ID 0 means "fixed function".
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit e9efd667defe13c89881f138cb5719c72573ff73
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Apr 15 01:57:52 2015 -0700
i965: Make shader_time use 0 instead of -1 for "no meaningful ID".
0 is not a valid GLSL shader or ARB program ID. For some reason,
shader_time used -1 instead...so we had code to detect 0, then override
it to -1.
We can just delete that.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit cfab4ea9c654819c96272a62d7b1664e9038fe91
Author: Tobias Nygren <tnn at NetBSD.org>
Date: Fri Apr 17 20:27:55 2015 +0200
adjust a couple of ifdefs to handle NetBSD correctly
Acked-by: Matt Turner <mattst88 at gmail.com>
Signed-off-by: Tobias Nygren <tnn at NetBSD.org>
commit 52e4e4712f0da7e7e1d1164d9487f2d38f80c441
Author: Tobias Nygren <tnn at NetBSD.org>
Date: Fri Apr 17 20:18:48 2015 +0200
configure.ac: fix bashism
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Signed-off-by: Tobias Nygren <tnn at NetBSD.org>
commit 79010c9a531f45d2b6740ac26f4b04c169f5dc7a
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Fri Apr 10 04:35:24 2015 -0700
i965: Render R16G16B16X16 as R16G16B16A16
This enables using _mesa_meta_pbo_TexSubImage() to upload data
to R16G16B16X16 texture. Earlier it fell back to slower paths.
Jenkins run shows no piglit regressions.
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit c6b0922c31983c76f1b2b9df66ae50b25b966bee
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Mon Apr 13 10:20:29 2015 -0700
i965: Update the comment about platforms supporting blorp
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit 4dacb212fdcc82def02b8c9233f94caa5a8a3000
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu Apr 2 10:21:16 2015 -0700
nir: Allow abs/neg in select peephole pass.
total instructions in shared programs: 4314531 -> 4308949 (-0.13%)
instructions in affected programs: 429085 -> 423503 (-1.30%)
helped: 1680
HURT: 0
GAINED: 0
LOST: 111
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 472ef9a02f2e5c5d0caa2809cb736a0f4f0d4693
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Apr 3 11:07:47 2015 -0700
i965/fs: Change SEL and MOV types as needed to propagate source modifiers
SEL and MOV instructions, as long as they don't have source modifiers, are
just copying bits around. This commit adds support to copy propagation to
switch the type of a SEL or MOV instruction as needed so that it can
propagate source modifiers. This is needed because NIR generates integer
SEL and MOV instructions whenver it doesn't know what else to generate.
shader-db results with NIR:
total FS instructions in shared programs: 4360910 -> 4360186 (-0.02%)
FS instructions in affected programs: 59094 -> 58370 (-1.23%)
helped: 341
HURT: 0
GAINED: 2
LOST: 0
Signed-off-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit bb99a58e7710acd19463646c38cdddbd926e89c4
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Apr 3 12:15:48 2015 -0700
i965/fs: Use the source type when looking for UD negations in copy prop
There can be problems with floats and conditional modifiers when
copy-propagating a negated UD source. The problem arises when a source
modifier is applied to a UD value. In this case, a 33-bit representation
is internally used. If you do the following:
1: mov foo:UD 7U
2: mov bar:UD -foo:UD
3: mov out:F bar:UD
the out register will have the value (float)(unt32_t)-7 which is some very
large floating-point number. However, if we allow copy-propagation of the
second mov, we get
1: mov foo:UD 7U
3: mov out:f -bar:UD
and, since the negation is computed in 33-bits, we get a value of -7.0f
which is clearly not the same. This is a similar problem if the
instruction has a conditional modifier where the 33-bit value is used in
the comparison and not the 32-bit version.
Previously, we checked the source to be copied for the negate and then
checked the source being propagated to for the type. This isn't quite what
we want because we are really just looking for negated UD sources. A check
later in the file ensures that both ends of the propagate have the right
type so it works. However, if we relax the restriction that both ends of
the propagation have the same type, it ends up causing us to bail early in
cases we don't want.
Signed-off-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 95e68adcd9f2589ae6d998328c72b84ffc49edc7
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Apr 16 15:35:50 2015 -0400
freedreno/ir3/nir: few little fixes
isaml needs to scale up coords based on LoD. Also fix bogus bary.f
varying # when there are non-bary frag shader inputs. And use sub.s of
a positive immediate rather than add.s of negative (since CP is better
about figuring out that those can be collapsed into the cat2 instr).
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit efbf14e8936384ab1d243afbe3fa9bb0f40e3898
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Apr 15 10:16:31 2015 -0400
freedreno/ir3/nir: lower if/else
For now, completely flatten if/else blocks. That will almost certainly
change once we have flow control.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit e5e11b5baf26e175f802c8078db92fd8492aa29d
Author: Rob Clark <robclark at freedesktop.org>
Date: Sun Apr 12 12:58:52 2015 -0400
freedreno/a4xx: support for large shaders
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 20ea698c492ea04f52e50974ecf39e887d144e43
Author: Rob Clark <robclark at freedesktop.org>
Date: Sun Apr 12 14:25:29 2015 -0400
freedreno: update generated headers
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 57f0d3b3c6ae3b9f79a03517410b8dbfab0382c6
Author: Rob Clark <robclark at freedesktop.org>
Date: Sun Apr 12 09:47:40 2015 -0400
freedreno/ir3/nir: UBO support
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 87807e5cc50f404a8e3ec8864bf8b7427ab6d687
Author: Rob Clark <robclark at freedesktop.org>
Date: Sun Apr 12 09:46:34 2015 -0400
freedreno/ir3: move out helper
We'll also want it in NIR f/e for implementing UBO support.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 70b2f872ea6ae651b832a2b3dd975efd78289fad
Author: Rob Clark <robclark at freedesktop.org>
Date: Sat Apr 11 12:15:17 2015 -0400
freedreno/a4xx: sysvals and UBOs
Basically just sync up the cmdstream emit parts to match the changes
already done on a3xx.
Also, fix scheduling for mem instructions. This is needed on a4xx, and
I am a bit surprised it isn't needed for a3xx.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit e14af4c0672c974238bed4661ada383cf50501f6
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Apr 15 15:49:15 2015 -0400
nir/builder: add nir_builder_insert_after_instr()
For lowering if/else, I need a way to insert at the end of the previous
block.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 7a9063e7c735960d10f489314aa7623a3d262085
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Apr 16 15:16:12 2015 -0400
gallium/ttn: fix TXF
There is a level param stashed away in the .w component of the first
src.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit ef7c4f39bf26998f24999f03b313d2665e842d31
Author: Rob Clark <robclark at freedesktop.org>
Date: Sun Apr 12 08:15:33 2015 -0400
gallium/ttn: add UBO support
v2: move ishl into ttn (instead of driver backend) to keep the units
consistent between immediate and indirect offsets
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 8efe20467b2710cc502cbfec19c1e543e572f864
Author: Rob Clark <robclark at freedesktop.org>
Date: Sat Apr 11 15:25:58 2015 -0400
gallium/ttn: minor cleanup
v2: also use ttn_src_for_indirect() everywhere for addr access, rather
than open-coding it for INPUT/CONST srcs
v3: move ralloc out of ttn_src_for_indirect() into the one call site
that needs a ptr
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit a3cce7a38eb57b6845ee47c2aeeae7778c91be76
Author: Rob Clark <robclark at freedesktop.org>
Date: Sat Apr 11 11:37:12 2015 -0400
gallium/ttn: add support for TXL2
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit f44d836d7a26a7d7c4374cc9e1e8bdc96cd2db8e
Author: Rob Clark <robclark at freedesktop.org>
Date: Sat Apr 11 11:35:29 2015 -0400
gallium/ttn: add support for texture offsets
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit e050a19af895318aaf417919c6a8ecba2da53304
Author: Brian Paul <brianp at vmware.com>
Date: Fri Apr 17 15:14:23 2015 +0100
mesa/st: Free st_translate with FREE macro.
To match CALLOC_STRUCT macro.
Fixes memory corruption on Windows when u_memory's memory debugging is
enabled.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 8638e3ae1b33a887f24a6e50bdb722361ee9414c
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Thu Apr 16 13:08:56 2015 +0100
libgl-gdi: Prevent "pure virtual method called" error when.
When running piglit w/ llvmpipe on Windows several tests terminate
abnormally just when the test exits.
The problem was that LLVMContextDispose was being called
after LLVM global destructors.
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit 4fc645aed10f3470bba2237a7e7314c3e2b3c25b
Author: Ville Syrjälä <ville.syrjala at linux.intel.com>
Date: Thu Apr 16 19:21:07 2015 +0300
i965: Add marketing names for CHV
All CHV devices will be branded as "Intel(r) HD Graphics".
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
commit 94aab6cde696ab1cd1243f5c62444166efb1a2fa
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Apr 15 15:20:57 2015 -0700
nir: Convert the if-test for num_inputs == 2 to an assertion
Suggested by Jason on a different patch after some comments /
questions by Ilia.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Connor Abbott <cwabott0 at gmail.com>
commit 61293bfcedcab450e1a6f3301152bda5f6e348ed
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Apr 13 21:44:02 2015 +0200
configure.ac: print LLVM_LDFLAGS
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Emil Velikov <emil.l.velilkov at gmail.com>
commit 0d46440c3a31ee9bd35bb48de419332c65761205
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Apr 11 20:05:41 2015 +0200
glsl_to_tgsi: only associate the uniform storage once at link time
This hack is no longer needed. (see the previous commit)
Reviewed-by: Brian Paul <brianp at vmware.com>
commit bb5df7350b9ac780389bce9c7642cb88681a4b2d
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Apr 11 20:01:22 2015 +0200
glsl_to_tgsi: add STATE_FB_WPOS_Y_TRANSFORM at link time
This will allow removing the uniform storage re-association during
TGSI generation at draw time.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit e2066a4344e05ab66442e5de5a3caa19f7809323
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Apr 11 14:40:09 2015 +0200
glsl_to_tgsi: add assertions for detecting out-of-bounds immediates access
Reviewed-by: Brian Paul <brianp at vmware.com>
commit dcc74d47c40bf117f2dfaa359f9de7faef2c2200
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Apr 11 14:55:26 2015 +0200
glsl_to_tgsi: don't use a potentially-undefined immediate for ir_query_levels
Cc: 10.4 10.5 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 14c5bc3b9a6b03a8e42ef79da66d8b81b239cf96
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Apr 11 13:49:38 2015 +0200
glsl_to_tgsi: fix out-of-bounds constant access and crash for uniforms
This fixes piglit shaders at glsl-fs-uniform-array-loop-unroll with immediate
shader compilation - it's a compiler test, so it has never been translated
to TGSI before.
Cc: 10.4 10.5 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit d3045d391b0b06faf4fb6be0394ff64c415cf336
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Mar 18 12:38:19 2015 +0100
glsl_to_tgsi: cleanup includes
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 76c2d4498ddfcf127eecd2045d188a59b47b731b
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Apr 11 19:35:40 2015 +0200
mesa/program: remove dead code
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit b79c620663dc4eab1ad342a7961fa7aa16cff562
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Apr 10 23:58:34 2015 +0200
radeonsi: add a debug option to compile shaders when they're created
Tested-by: Tom Stellard <thomas.stellard at amd.com>
commit 99eef3b8b324d3be6f3b8f2a34c95006d8205599
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Apr 10 23:58:34 2015 +0200
st/mesa: add a debug option to compile shaders at link time
v2: fix crashes
Tested-by: Tom Stellard <thomas.stellard at amd.com>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit 993a6288f72fa98932df7cdb6f64d9dd645e670d
Author: Kristian Høgsberg <krh at bitplanet.net>
Date: Tue Apr 14 15:02:18 2015 +0000
i965: Rewrite ir_tex to ir_txl with lod 0 for vertex shaders
The ir_tex opcode turns into a sample or sample_c message, which will try to
compute derivatives to determine the lod. This produces garbage for
non-fragment shaders where the sample coordinates don't correspond to
subspans.
We fix this by rewriting the opcode from ir_tex to ir_txl and setting the
lod to 0.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89457
Cc: "10.5" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Kristian Høgsberg <kristian.h.kristensen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit a7d018accfd0161510a75ba685e056256de494c2
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Apr 8 19:27:02 2015 +0100
radeonsi: remove bogus r600-- triple
As mentioned by Michel Dänzer for LLVM >= 3.6 we create the
LLVMTargetMachine (with triple amdgcn--), as we setup the radeonsi
context. For older LLVM or hardware (r600) the triple is always r600--
and is created at a later stage - radeon_llvm_compile()
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 33f73e93ff6e14f72153d3df7e80763137fcb943
Author: Neil Roberts <neil at linux.intel.com>
Date: Tue Mar 24 15:52:20 2015 +0000
i965/skl: Add the header for constant loads outside of the generator
Commit 5a06ee738 added a step to the generator to set up the message
header when generating the VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
instruction. That pseudo opcode is implemented in terms of multiple
actual opcodes, one of which writes to one of the source registers in
order to set up the message header. This causes problems because the
scheduler isn't aware that the source register is written to and it
can end up reorganising the instructions incorrectly such that the
write to the source register overwrites a needed value from a previous
instruction. This problem was presenting itself as a rendering error
in the weapon in Enemy Territory: Quake Wars.
Since commit 588859e1 there is an additional problem that the double
register allocated to include the message header would end up being
split into two. This wasn't happening previously because the code to
split registers was explicitly avoided for instructions that are
sending from the GRF.
This patch fixes both problems by splitting the code to set up the
message header into a new pseudo opcode so that it will be done
outside of the generator. This new opcode has the header register as a
destination so the scheduler can recognise that the register is
written to. This has the additional benefit that the scheduler can
optimise the message header slightly better by moving the mov
instructions further away from the send instructions.
On Skylake it appears to fix the following three Piglit tests without
causing any regressions:
gs-float-array-variable-index
gs-mat3x4-row-major
gs-mat4x3-row-major
I think we actually may need to do something similar for the fs
backend and possibly for message headers from regular texture sampling
but I'm not entirely sure.
v2: Make sure the exec-size is retained as 8 for the mov instruction
to initialise the header from g0. This was accidentally lost
during a rebase on top of 07c571a39fa1.
Split the patch into two so that the helper function is a separate
change.
Fix emitting the MOV instruction on Gen7.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89058
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit a9e4cf5d323dbf11e42deda389ed03db571a7df7
Author: Neil Roberts <neil at linux.intel.com>
Date: Wed Apr 15 14:28:26 2015 +0100
i965/vec4: Add a helper function to emit VS_OPCODE_PULL_CONSTANT_LOAD
There were three places in the visitor that had a similar chunk of
code to emit the VS_OPCODE_PULL_CONSTANT_LOAD opcode using a register
for the offset. This patch combines the chunks into a helper function
to reduce the code duplication. It will also be useful in the next
patch to expand what happens on Gen9+. This shouldn't introduce any
functional changes.
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit 037e0e78abf0c312f737d33f3c33e37b22bf226d
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Thu Apr 16 10:19:57 2015 +0100
mesa,glsl: rename `interface` to `programInterface`.
`interface` is a define on Windows -- an alias for `struct` keyword,
used when declaring COM interfaces in C or C++.
So use instead `programInterface`, therefore matching the name used
in GL_ARB_program_interface_query spec/headers, which was renamed exactly
for the same reason:
"Revision 10, May 10, 2012 (pbrown)
- Rename the formal parameter <interface> used by the functions in this
extension to <programInterface>. Certain versions of the Microsoft
C/C++ compiler and/or its headers cause "interface" to be treated as a
reserved keyword."
Trivial.
commit f78b2c432f31a18794b9f62f0a0cfb8eca256151
Author: Flora Cui <flora.cui at amd.com>
Date: Tue Mar 24 18:34:29 2015 +0800
gbm: Add GBM_BO_USE_LINEAR flag
Signed-off-by: Flora Cui <flora.cui at amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou at amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
commit 7c154bbe6080ced9607bc3f3240d2f0866018aeb
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Fri Mar 13 08:53:23 2015 +0200
mesa: refactor GetUniformBlockIndex
Use _mesa_program_resource_index to get index.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
commit 1b256eb0ec1f919f23641f8d47d4b2ce126dd1a4
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Thu Mar 12 14:37:20 2015 +0200
mesa: refactor GetUniformIndices
Use _mesa_program_resource_index to get indices.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
commit 51313f567d59afd5491e03d1593030066df974eb
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Thu Mar 12 14:31:15 2015 +0200
mesa: refactor GetUniformLocation
Use _mesa_program_resource_location to get location.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
commit 45637e9c1f47df8cc8284b39b18f6b5f2e14aae9
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Thu Mar 12 13:33:25 2015 +0200
mesa: refactor GetActiveUniformBlockName
Use _mesa_get_program_resource_name to get name.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
commit 284003e1f1b84f165f2cffdcec47bee972b12a8d
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Thu Mar 12 13:53:07 2015 +0200
mesa: remove unused _mesa_get_uniform_name
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
commit 8d6fa52e33183942fe93e2fad27bf4881b0a1ce0
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Thu Mar 12 13:22:16 2015 +0200
mesa: refactor GetActiveUniformName
Use _mesa_get_program_resource_name to get name.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
commit 17dc939f756cfed23574ad84764f5e2a5a9b6751
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Thu Mar 12 12:55:18 2015 +0200
mesa: refactor GetActiveUniform
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
commit dc39d843d21898752ce5d79804ff9f638595d3a9
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Thu Mar 12 12:08:56 2015 +0200
mesa: refactor GetTransformFeedbackVarying
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
commit 7519ddb4d8192f992c4a8b3fff84465b52905958
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Thu Mar 12 10:17:09 2015 +0200
mesa: refactor GetActiveUniformsiv, use _mesa_program_resource_prop
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 34df5ebd778fd3027db0f380eab71a95cfa298c0
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Thu Mar 12 07:58:48 2015 +0200
mesa: mesa_bufferiv utility function for buffer objects
Patch adds new function 'mesa_bufferiv' and refactors existing
GetActiveUniformBlockiv and GetActiveAtomicCounterBufferiv to
use it.
corresponding Piglit tests:
arb_uniform_buffer_object*
arb_shader_atomic_counters*
(Many tests hit the corresponding queries.)
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
commit 4e7f134f89f52cf103e2b682faa72dac4cc2f840
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Thu Mar 12 15:14:31 2015 +0200
mesa: refactor GetFragDataIndex
Use _mesa_program_resource_location_index to fetch index.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
commit 62057c77f135ae7ebe5f10def714edb5492cb0be
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Thu Mar 12 15:13:30 2015 +0200
mesa: refactor GetFragDataLocation
Use program_resource_location to fetch location.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
commit 3d1544cc91cad4cca1deb67c82fc7390fe4196f9
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Thu Mar 12 15:11:04 2015 +0200
mesa: refactor GetAttribLocation
Use program_resource_location to fetch location.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
commit 26c0394a964f13d0266b1dcf7283bf21b7bca340
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Wed Mar 11 09:05:47 2015 +0200
mesa: refactor GetActiveAttrib
Instead of iterating IR, retrieve required information through
the new program resource functions.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 41c230cd983195e3989153f8d82ec95e298352d4
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Tue Apr 7 12:07:03 2015 +0300
mesa: enable GL_ARB_program_interface_query extension
(and mark it as DONE in docs/GL3.txt + 10.6.0 relnotes)
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
commit 2ab8de2181988870a95de23aeb906df5678e1e90
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Tue Mar 10 13:11:14 2015 +0200
mesa: implementation of glGetProgramResourceiv
Patch adds required helper functions to shaderapi.h and
the actual implementation.
The property query functionality can be tested with tests for
following functions that are refactored by later patches:
GetActiveAtomicCounterBufferiv
GetActiveUniformBlockiv
GetActiveUniformsiv
v2: code cleanup (Ilia Mirkin)
add bufSize < 0 check and error out
fix is_resource_referenced to return bool
check for propCount and bufSize, fixes in buffer_prop
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
commit 9367ade331e5d0a7724c595e7afb0322caaaddf7
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Thu Mar 12 14:08:38 2015 +0200
mesa: glGetProgramResourceLocationIndex
Patch adds required helper functions to shaderapi.h and
the actual implementation.
The added functionality can be tested by tests for following
functions that are refactored by later patches:
GetFragDataIndex
v2: return -1 if output not referenced by fragment stage
(Ilia Mirkin)
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
commit e0e4d77f0120865b3ca0a4055358fc87d38d1cfe
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Thu Mar 12 13:45:22 2015 +0200
mesa: glGetProgramResourceLocation
Patch adds required helper functions to shaderapi.h and
the actual implementation.
corresponding Piglit test:
arb_program_interface_query-resource-location
The added functionality can be tested by tests for following
functions that are refactored by later patches:
GetAttribLocation
GetUniformLocation
GetFragDataLocation
v2: code cleanup, changes to array element
syntax checking (Ilia Mirkin)
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
commit 2a5a0d19d67b2ccd7eee33a6f3bead66cc2d78ff
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Tue Mar 10 10:33:20 2015 +0200
mesa: glGetProgramResourceName
Patch adds required helper functions to shaderapi.h and
the actual implementation.
Name generation copied from '_mesa_get_uniform_name' which can
be removed later by refactoring functions to use resource list.
The added functionality can be tested by tests for following
functions that are refactored by later patches:
GetActiveUniformName
GetActiveUniformBlockName
v2: no index for geometry shader inputs (Ilia Mirkin)
add bufSize < 0 check and error out
validate enum
corresponding Piglit test:
arb_program_interface_query-getprogramresourcename
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Martin Peres <martin.peres at linux.intel.org>
commit 161f57f6103802de55d792bcc6a4370afa5c5173
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Tue Mar 10 09:30:30 2015 +0200
mesa: glGetProgramResourceIndex
Patch adds required helper functions to shaderapi.h and
the actual implementation.
v2: code cleanup (Ilia Mirkin)
corresponding Piglit test:
arb_program_interface_query-getprogramresourceindex
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Martin Peres <martin.peres at linux.intel.org>
commit 4d3b98bc5801df27a7f9f2e3df28d66d83f883d9
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Fri Mar 6 15:05:51 2015 +0200
mesa: glGetProgramInterfaceiv
Patch adds required helper functions to shaderapi.h and
the actual implementation.
v2: code cleanup (Ilia Mirkin)
fix array size fo xfb varyings
validate programInterface and throw error
v3: put GL_MAX_NUM_COMPATIBLE_SUBROUTINES where
it belongs
corresponding Piglit test:
arb_program_interface_query-getprograminterfaceiv
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
commit c796ce4108ccc4987c24df43606d04a0f3658d44
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Fri Mar 6 09:14:49 2015 +0200
mesa/glsl: build list of program resources during linking
Patch adds ProgramResourceList to gl_shader_program structure.
List contains references to active program resources and is
constructed during linking phase.
This list will be used by follow-up patches to implement hooks
for GL_ARB_program_interface_query. It can be also used to
implement any of the older shader program query APIs.
v2: code cleanups + note for SSBO and subroutines (Ilia Mirkin)
v3: code cleanups + assert(MESA_SHADER_STAGES < 8) (Martin Peres)
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
commit b297fc27aa93c4af4cf8ecf9702fd0b95d2c4f9a
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Mon Feb 16 14:15:36 2015 +0200
glapi: add GL_ARB_program_interface_query skeleton
v2: update dispatch_sanity test (Jason Ekstrand)
+ small code cleanups
v3: xml and Makefile fixes (Ilia Mirkin, Matt Turner)
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
commit 993b9b6adbd2c97ccb58b7cbc46382d1ae87b9ab
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Tue Mar 17 13:58:57 2015 +0200
linker: fix varying linking if SSO program has only gs and fs
Previously linker did not take in to account case where one would
have only gs and fs (with SSO), patch adds the case by refactoring
code around assign_varying_locations. This makes sure locations for
gs get populated correctly.
This was found with some of the SSO subtests of Martin's upcoming
GetProgramInterfaceiv Piglit test which passes with the patch, no
Piglit regressions.
v2: code cleanups (Martin Peres)
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
commit 17d69862a9232e2bcdfa032c5a65c27557dd9275
Author: Glenn Kennard <glenn.kennard at gmail.com>
Date: Wed Apr 8 11:30:37 2015 +0200
r600g/sb: Skip empty ALU clause while scheduling
Fixes assert triggered by
ext_transform_feedback-intervening-read output use_gs
piglit test.
Signed-off-by: Glenn Kennard <glenn.kennard at gmail.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 4cf5ca5ca5e70755723f7f0ced77c168d9e3a86f
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Apr 13 16:16:10 2015 -0700
nir: Try commutative sources in CSE
Shader-db results:
GM45 NIR:
total instructions in shared programs: 4082044 -> 4081919 (-0.00%)
instructions in affected programs: 27609 -> 27484 (-0.45%)
helped: 44
Iron Lake NIR:
total instructions in shared programs: 5678776 -> 5678646 (-0.00%)
instructions in affected programs: 27406 -> 27276 (-0.47%)
helped: 45
Sandy Bridge NIR:
total instructions in shared programs: 7329995 -> 7329096 (-0.01%)
instructions in affected programs: 142035 -> 141136 (-0.63%)
helped: 406
HURT: 19
Ivy Bridge NIR:
total instructions in shared programs: 6769314 -> 6768359 (-0.01%)
instructions in affected programs: 140820 -> 139865 (-0.68%)
helped: 423
HURT: 2
Haswell NIR:
total instructions in shared programs: 6183693 -> 6183298 (-0.01%)
instructions in affected programs: 96538 -> 96143 (-0.41%)
helped: 303
HURT: 4
Broadwell NIR:
total instructions in shared programs: 7501711 -> 7498170 (-0.05%)
instructions in affected programs: 266403 -> 262862 (-1.33%)
helped: 705
HURT: 5
GAINED: 4
v2: Rebase on top of Connor's fix.
v3: Convert the if-test for num_inputs == 2 to an assertion. Suggested
by Jason after some comments / questions by Ilia.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com> [v1]
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Cc: Connor Abbott <cwabbott0 at gmail.com>
commit 8957c9e448670e5aa78065619692cf285f9b0a30
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Apr 14 09:24:06 2015 -0700
glx: Create proper server dependency for GLX_EXT_create_context_es2_profile
Previously GLX_EXT_create_context_es2_profile was marked as "direct
only" so that it would not depend on server support. Since the
extension required functions that are part of
GLX_ARB_create_context_profile, support for the EXT was disabled if the
ARB was not supported.
This was complete rubbish. If the server supported the ARB but not the
EXT, sending a request with GLX_CONTEXT_ES2_PROFILE_BIT_EXT would result
in GLXBadProfileARB.
Instead of the misguided hack, make GLX_EXT_create_context_es2_profile
properly depend on server support by not marking it as "direct only."
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Acked-by: José Fonseca <jfonseca at vmware.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
Cc: Emil Velikov <emil.l.velikov at gmail.com>
commit b229e6c7dee2bb6b1736d6867790dfcd1c50f623
Author: Eric Anholt <eric at anholt.net>
Date: Tue Apr 14 22:01:55 2015 -0700
vc4: Don't try to use color load/stores to blit across format changes.
We could potentially support the right combination of 8888 to 565, but the
important thing for now is to not mix up our orderings of 8888. Fixes
fbo-copyteximage regressions.
commit cff2e08c4cb87b7c2e19100e24c336e50b9839cc
Author: Eric Anholt <eric at anholt.net>
Date: Tue Apr 14 21:59:46 2015 -0700
vc4: Don't try to use color load/stores to do depth/stencil blits.
Fixes regressions in fbo-generatemipmap-formats on depth/stencil (which
does blits to work around baselevel/lastlevel).
commit 3a728d4dfbd727c30f36116772803674beffcbb6
Author: Eric Anholt <eric at anholt.net>
Date: Tue Apr 14 11:31:11 2015 -0700
vc4: Update the shadow texture for public textures on every draw.
We don't know who else has written to it, so we'd better update it every
time. This makes the gears spin in X again.
commit bd957b1b79124c5061af1eddf16932793e806d87
Author: Eric Anholt <eric at anholt.net>
Date: Tue Apr 14 11:24:00 2015 -0700
vc4: Hook up VC4_DEBUG=perf to some useful printfs.
commit e1d095053b2b50109f77fd9eb524e8e1c7d025af
Author: Brian Paul <brianp at vmware.com>
Date: Tue Apr 14 10:54:34 2015 -0600
st/mesa: log shaders, GLSL info log with _mesa_log()
As with previous patch.
Reviewed-by: José Fonseca <jfonseca at vmware.com>
commit 011cad806a6e42caecfef0e9fc77c6db0333dcfe
Author: Brian Paul <brianp at vmware.com>
Date: Tue Apr 14 10:41:56 2015 -0600
mesa: log shaders, GLSL info log with _mesa_log()
Now, if we set MESA_LOG_FILE and MESA_GLSL=dump, all the shader info
will get logged to the named file instead of stderr.
Reviewed-by: José Fonseca <jfonseca at vmware.com>
commit 2926bbfb280b2eb195cc031991c956da38d89508
Author: Brian Paul <brianp at vmware.com>
Date: Tue Apr 14 10:24:22 2015 -0600
mesa: add _mesa_log(), _mesa_get_log_file() functions
_mesa_log() simply writes log information to stderr or MESA_LOG_FILE.
_mesa_get_log_file() returns the file handle to use for logging.
This will be used for shader dumping/logging instead of always printing
to stderr.
Reviewed-by: José Fonseca <jfonseca at vmware.com>
commit 11bfee4c3a9f285f4cd5467dac1af5f7f0dfa307
Author: Brian Paul <brianp at vmware.com>
Date: Thu Apr 9 13:45:18 2015 -0600
tgsi: also dump label for TGSI_OPCODE_BGNSUB opcode
So we can see the label associated with subroutines.
Reviewed-by: José Fonseca <jfonseca at vmware.com>
commit 1aa50339d816c5d5ad3107673c315569ce9b21d3
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Tue Apr 14 14:25:21 2015 +0100
st/wgl: Couple of fixes to opengl32.dll's wglCreateContext/wglDeleteContext dispatch.
- Use GetModuleHandle instead of LoadLibrary to avoid incrementing the
opengl32.dll reference count (otherwise the opengl32.dll will linger
in memory forever.)
- Ensure we use our fake wglCreateContext/wglDeleteContext when using
Mesa as a drop-in replacement for opengl32.dll
Untested. Just noticed by accident.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 6635fb6cae702b195e9912747b5a11c41970ab9e
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Tue Apr 14 14:25:06 2015 +0100
mesa: Enable _mesa_dlopen on MSVC too.
As pointed out by Shervin Sharifi.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 3cbefe3cf4c745c7c681cfc18a1e47461fec91db
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Thu Nov 27 09:39:05 2014 +0100
glsl: fix assignment of multiple scalar and vecs to matrices.
When a vec has more elements than row components in a matrix, the
code could end up failing an assert inside assign_to_matrix_column().
This patch makes sure that when there is still room in the matrix for
more elements (but in other columns of the matrix), the data is actually
assigned.
This patch fixes the following dEQP test:
dEQP-GLES3.functional.shaders.conversions.matrix_combine.float_bvec4_ivec2_bool_to_mat4x2_vertex
dEQP-GLES3.functional.shaders.conversions.matrix_combine.float_bvec4_ivec2_bool_to_mat4x2_fragment
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit bc672e261c5f7ff56cd2b8f6b518ebfdc0163bb7
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Apr 14 08:40:22 2015 -0700
nir: Fix typo in "ushr by 0" algebraic replacement
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Cc: "10.5" <mesa-stable at lists.freedestkop.org>
commit 67a8610caff15ba9f55ac5ee2404f19033b5bae6
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Apr 13 16:42:59 2015 -0700
nir: Silence unused parameter warnings
nir/nir.h: In function 'nir_validate_shader':
nir/nir.h:1567:56: warning: unused parameter 'shader' [-Wunused-parameter]
static inline void nir_validate_shader(nir_shader *shader) { }
^
nir/nir_opt_cse.c: In function 'src_is_ssa':
nir/nir_opt_cse.c:165:32: warning: unused parameter 'data' [-Wunused-parameter]
src_is_ssa(nir_src *src, void *data)
^
nir/nir_opt_cse.c: In function 'dest_is_ssa':
nir/nir_opt_cse.c:171:35: warning: unused parameter 'data' [-Wunused-parameter]
dest_is_ssa(nir_dest *dest, void *data)
^
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 47a1b4841d39fc358fc5ab67dc129a02419fba8d
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Tue Apr 14 15:44:24 2015 -0400
nir/cse: fix bug with comparing non-per-component sources
We weren't comparing the right number of components when checking
swizzles. Use nir_ssa_alu_instr_num_src_components() to do the right
thing.
No piglit regressions, and no fixes either.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Signed-off-by: Connor Abbott <cwabbott0 at gmail.com>
commit b069f9eafd945a86be633d8fff4e715fc6d7ec2d
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Sun Feb 8 13:59:57 2015 -0800
i965/fs: Combine tex/fb_write operations (opt)
Certain platforms support the ability to sample from a texture, and write it out
to the file RT - thus saving a costly send instructions (note that this is a
potnential win if one wanted to backport to a tag that didn't have the patch
from Topi which removed excess MOVs from LOAD_PAYLOAD - 97caf5fa04dbd2),
v2: Modify the algorithm. Instead of iterating in reverse through blocks and
insts, since the last block/inst is the only thing which can benefit. Rebased
on top of Ken's patching modifying is_last_send
v3: Rebased over almost 2 months, and Incorporated feedback from Matt:
Some comment typo fixes and rewordings.
Whitespace
Move the optimization pass outside of the optimize loop
v4: Some cosmetic changes requested from Ken. These changes ensured that the
optimization function always returned true when an optimization occurred, and
false when one did not. This behavior did not exist with the original patch. As
a result, having the separate helper function which Matt did not like no longer
made sense, and so now I believe everyone should be happy.
Benchmark (n=20) %diff
*OglBatch5 -1.4
*OglBatch7 -1.79
OglFillTexMulti 5.57
OglFillTexSingle 1.16
OglShMapPcf 0.05
OglTexFilterAniso 3.01
OglTexFilterTri 1.94
No piglit regressions:
(http://otc-gfxtest-01.jf.intel.com:8080/view/dev/job/bwidawsk/112/)
[*] I believe my measurements are incorrect for Batch5-7. If I add this new
optimization, but never emit the new instruction I see similar results.
v5: Remove declaration of combine_tex_header since v4 dropped that function
(Ben)
Remove check for impossible case of an empty block (Matt)
Set dest earlier to avoid extra special-casing in generate_tex (Matt)
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 6866378cf42c86d03f38616804e6714a932ab70b
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Fri Apr 10 10:04:55 2015 -0700
i965/fs: Only emit FS_OPCODE_PLACEHOLDER_HALT if there are discards
Based originally on a patch from Ken in May 2014 of the same title. Things
changed enough that I didn't feel comfortable leaving his authorship.
v2: Replace fp->UsesKill with wm_prog_data->uses_kill. Since Ken took the time
to also explain the difference to me, here is his explanation for posterity:
"fp->UsesKill indicates that a ARB_fragment_program shader uses the KIL
instruction, or that a GLSL shader uses the "discard" insntruction
(which are analogous).
On Gen4-5, we sometimes have to simulate OpenGL's "Alpha Test" feature
by emitting shader code that implicitly does a "discard" instruction.
In the key setup, we do:
/* key->alpha_test_func means simulating alpha testing via discards,
* so the shader definitely kills pixels.
*/
prog_data.uses_kill = fp->program.UsesKill || key->alpha_test_func;
Even though the shader may not technically contain a "discard", we need
to act as if it does.
I've also been trying to move the i965 state setup code to use
brw_wm_prog_key for everything, rather than poking at core Mesa's
gl_program/gl_fragment_program/gl_shader/gl_shader_program structures.
--Ken"
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 38707e1478a4b6f4687c583d06fbd68e22900735
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Tue Mar 31 15:49:42 2015 -0700
i965/fs: Create a has_side_effects for fs_inst
When an instruction has a side effect, it impacts the available options when
reordering an instruction. As the EOT flag is an implied write to the render
target in the FS, it can be considered a side effect.
This patch shouldn't actually have any impact on the current code since the EOT
flag implies that the opcode is already one with side effects,
FS_OPCODE_FB_WRITE. The next patch however will introduce an optimization
whereby the EOT flag can occur with an opcode SHADER_OPCODE_TEX, and as that
instruction will perform the same implied write to the render target, it cannot
be reordered.
v2: Remove extra whitespace (Matt)
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 28d9e90428282a5e0a6aa31ad858a5cf514d1264
Author: Marius Predut <marius.predut at intel.com>
Date: Tue Apr 7 22:05:28 2015 +0300
i965: replace __FUNCTION__ with __func__
Consistently just use C99's __func__ everywhere.
No functional changes.
Acked-by: Matt Turner <mattst88 at gmail.com>
Signed-off-by: Marius Predut <marius.predut at intel.com>
commit 139e6c7c4a9c59be5f4b3f431ac393cc097326ac
Author: Marius Predut <marius.predut at intel.com>
Date: Tue Apr 7 22:05:44 2015 +0300
i915: replace __FUNCTION__ with __func__
Consistently just use C99's __func__ everywhere.
No functional changes.
Acked-by: Matt Turner <mattst88 at gmail.com>
Signed-off-by: Marius Predut <marius.predut at intel.com>
commit fc57222f6097da737d578f081075a027377ba399
Author: Marius Predut <marius.predut at intel.com>
Date: Tue Apr 7 22:06:01 2015 +0300
glx: replace __FUNCTION__ with __func__
Consistently just use C99's __func__ everywhere.
No functional changes.
Acked-by: Matt Turner <mattst88 at gmail.com>
Signed-off-by: Marius Predut <marius.predut at intel.com>
commit 6f4d9418b41f650630e725e0a842de9bb1ad746f
Author: Marius Predut <marius.predut at intel.com>
Date: Tue Apr 7 22:04:58 2015 +0300
main: replace __FUNCTION__ with __func__
Consistently just use C99's __func__ everywhere.
The patch was verified with Microsoft Visual studio 2013
redistributable package(RTM version number: 18.0.21005.1)
Next MSVC versions intends to support __func__.
No functional changes.
Acked-by: Matt Turner <mattst88 at gmail.com>
Signed-off-by: Marius Predut <marius.predut at intel.com>
commit 50cb780f7f90ffc4018f41502a472604bf1677c3
Author: Marius Predut <marius.predut at intel.com>
Date: Tue Apr 7 22:04:38 2015 +0300
state_tracker: replace __FUNCTION__ with __func__
Consistently just use C99's __func__ everywhere.
The patch was verified with Microsoft Visual studio 2013
redistributable package(RTM version number: 18.0.21005.1)
Next MSVC versions intends to support __func__.
No functional changes.
Acked-by: Matt Turner <mattst88 at gmail.com>
Signed-off-by: Marius Predut <marius.predut at intel.com>
commit d02942cc779f97b499c80879db60aa469f651b49
Author: Marius Predut <marius.predut at intel.com>
Date: Tue Apr 7 22:03:52 2015 +0300
swrast: replace __FUNCTION__ with __func__
Consistently just use C99's __func__ everywhere.
The patch was verified with Microsoft Visual studio 2013
redistributable package(RTM version number: 18.0.21005.1)
Next MSVC versions intends to support __func__.
No functional changes.
Acked-by: Matt Turner <mattst88 at gmail.com>
Signed-off-by: Marius Predut <marius.predut at intel.com>
commit e1231159bcd0b0fc9aaebeda0745ee38d13a7282
Author: Marius Predut <marius.predut at intel.com>
Date: Fri Apr 3 15:02:33 2015 +0300
vbo: replace __FUNCTION__ with __func__
Consistently just use C99's __func__ everywhere.
The patch was verified with Microsoft Visual studio 2013
redistributable package(RTM version number: 18.0.21005.1)
Next MSVC versions intends to support __func__.
No functional changes.
Acked-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Signed-off-by: Marius Predut <marius.predut at intel.com>
commit f0e693efb393f1135702c80a64f8733adc922db1
Author: Marius Predut <marius.predut at intel.com>
Date: Fri Apr 3 16:11:57 2015 +0300
tnl: replace __FUNCTION__ with __func__
Consistently just use C99's __func__ everywhere.
The patch was verified with Microsoft Visual studio 2013
redistributable package(RTM version number: 18.0.21005.1)
Next MSVC versions intends to support __func__.
No functional changes.
Acked-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Signed-off-by: Marius Predut <marius.predut at intel.com>
commit 3ca17e75e4fe129511a4dcad47e139485beef880
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Apr 13 11:29:14 2015 -0700
i965/fs: Correct mistake in determining whether a MUL is negated.
a * b is equivalent to -a * -b, and the previous code was failing at
that.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89961
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 07c571a39fa12c3db1c638302de7aed67844609b
Author: Neil Roberts <neil at linux.intel.com>
Date: Fri Apr 10 17:20:21 2015 +0100
i965/skl: Use an exec size of 8 to initialise the message header
Commit e93566a15c61c33faa changed the message header code needed to
make Skylake use SIMD4x2 so that it uses a register with width 4
instead of 8 as the source register in the send message. However it
also changed the width for the dest in the MOV instruction which is
used to initialise the header register with the values from g0. The
width of the destination is used to determine the exec size in
brw_set_dest so this would end up making the MOV have an exec size of
4. I think this would end up leaving the top half of the register
uninitialised. The top half of the header has meaningful values so
this probably isn't a good idea.
This patch just casts the dest register for the MOV instruction back
to a vec8 to fix it. It doesn't cause any changes to a Piglit run.
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit 05a1d84491eabf56564488ba0b0b0b8e91fd4309
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Mar 23 12:03:56 2015 -0700
i965/fs: Always invert predicate of SEL with swapped arguments
Commit b616164 added an optimization of b2f generation of a comparison.
It also included an extra optimization of one of the comparison values
is a constant of zero. The trick was that some value was known to be
zero, so that value could be used in the SEL instruction instead of
potentially loading 0.0 into a register.
This change switched the order of the arguments to the SEL, and, for
some unknown reason, I thought that the predicate should therefore
only be inverted for the == case. Clearly, it should always be
inverted.
Fixes piglit fs-notEqual-of-expression.shader_test and
fs-equal-of-expression.shader_test.
v2: Don't do the "register already has zero" optimization for the '== 0'
case. In that case, the register does not have zero when we want to
produce a zero result.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89722
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org> [v1]
Tested-by: Lu Hua <huax.lu at intel.com>
commit e0994e0f97a2078735f0b5e86cbad9f74c565c05
Author: Tom Stellard <thomas.stellard at amd.com>
Date: Mon Apr 13 13:25:41 2015 +0000
radeon/llvm: Improve codegen for KILL_IF
Rather than emitting one kill instruction per component of KILL_IF's src
reg, we now or the components of the src register together and use the
result as a condition for just one kill instruction.
shader-db stats (bonaire):
979 shaders
Totals:
SGPRS: 34872 -> 34848 (-0.07 %)
VGPRS: 20696 -> 20676 (-0.10 %)
Code Size: 749032 -> 748452 (-0.08 %) bytes
LDS: 11 -> 11 (0.00 %) blocks
Scratch: 12288 -> 12288 (0.00 %) bytes per wave
Totals from affected shaders:
SGPRS: 1184 -> 1160 (-2.03 %)
VGPRS: 600 -> 580 (-3.33 %)
Code Size: 13200 -> 12620 (-4.39 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Scratch: 0 -> 0 (0.00 %) bytes per wave
Increases:
SGPRS: 2 (0.00 %)
VGPRS: 0 (0.00 %)
Code Size: 0 (0.00 %)
LDS: 0 (0.00 %)
Scratch: 0 (0.00 %)
Decreases:
SGPRS: 5 (0.01 %)
VGPRS: 5 (0.01 %)
Code Size: 25 (0.03 %)
LDS: 0 (0.00 %)
Scratch: 0 (0.00 %)
*** BY PERCENTAGE ***
Max Increase:
SGPRS: 32 -> 40 (25.00 %)
VGPRS: 0 -> 0 (0.00 %)
Code Size: 0 -> 0 (0.00 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Scratch: 0 -> 0 (0.00 %) bytes per wave
Max Decrease:
SGPRS: 32 -> 24 (-25.00 %)
VGPRS: 16 -> 12 (-25.00 %)
Code Size: 116 -> 96 (-17.24 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Scratch: 0 -> 0 (0.00 %) bytes per wave
*** BY UNIT ***
Max Increase:
SGPRS: 64 -> 72 (12.50 %)
VGPRS: 0 -> 0 (0.00 %)
Code Size: 0 -> 0 (0.00 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Scratch: 0 -> 0 (0.00 %) bytes per wave
Max Decrease:
SGPRS: 32 -> 24 (-25.00 %)
VGPRS: 16 -> 12 (-25.00 %)
Code Size: 424 -> 356 (-16.04 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Scratch: 0 -> 0 (0.00 %) bytes per wave
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit c6d79ed289a75f13c65f011be870f7e43a0fedc7
Author: Tom Stellard <thomas.stellard at amd.com>
Date: Fri Apr 10 17:07:16 2015 +0000
radeon/llvm: Run LLVM's instruction combining pass
This should improve code quality in general and will help with some
future changes to how we emit kill instructions.
shader-db shows a few regressions, but these don't seem to be the result
of deficiencies in instcombine. They're mostly caused by the scheduler
making different decisions than before.
shader-db stats (bonaire):
979 shaders
Totals:
SGPRS: 35056 -> 34872 (-0.52 %)
VGPRS: 20624 -> 20696 (0.35 %)
Code Size: 764372 -> 749032 (-2.01 %) bytes
LDS: 11 -> 11 (0.00 %) blocks
Scratch: 12288 -> 12288 (0.00 %) bytes per wave
Totals from affected shaders:
SGPRS: 13264 -> 13072 (-1.45 %)
VGPRS: 8248 -> 8316 (0.82 %)
Code Size: 486320 -> 470992 (-3.15 %) bytes
LDS: 11 -> 11 (0.00 %) blocks
Scratch: 11264 -> 11264 (0.00 %) bytes per wave
Increases:
SGPRS: 6 (0.01 %)
VGPRS: 20 (0.02 %)
Code Size: 14 (0.01 %)
LDS: 0 (0.00 %)
Scratch: 0 (0.00 %)
Decreases:
SGPRS: 32 (0.03 %)
VGPRS: 8 (0.01 %)
Code Size: 244 (0.25 %)
LDS: 0 (0.00 %)
Scratch: 0 (0.00 %)
*** BY PERCENTAGE ***
Max Increase:
SGPRS: 32 -> 48 (50.00 %)
VGPRS: 12 -> 20 (66.67 %)
Code Size: 216 -> 224 (3.70 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Scratch: 0 -> 0 (0.00 %) bytes per wave
Max Decrease:
SGPRS: 40 -> 32 (-20.00 %)
VGPRS: 16 -> 12 (-25.00 %)
Code Size: 368 -> 280 (-23.91 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Scratch: 0 -> 0 (0.00 %) bytes per wave
*** BY UNIT ***
Max Increase:
SGPRS: 32 -> 48 (50.00 %)
VGPRS: 28 -> 36 (28.57 %)
Code Size: 39320 -> 40132 (2.07 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Scratch: 0 -> 0 (0.00 %) bytes per wave
Max Decrease:
SGPRS: 72 -> 64 (-11.11 %)
VGPRS: 48 -> 40 (-16.67 %)
Code Size: 6272 -> 5852 (-6.70 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Scratch: 0 -> 0 (0.00 %) bytes per wave
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 2569c7109d466137ac2b9964db3427ccf2bbf49e
Author: Tom Stellard <thomas.stellard at amd.com>
Date: Mon Apr 13 12:56:37 2015 +0000
radeonsi: Add header and footer to shader stat dump
This makes it easier to parse.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 406df68736a213f17f21a38a7c2da4ea15acd053
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Apr 11 02:21:48 2015 -0700
i965: Fix software primitive restart with indirect draws.
new_prim was declared as a stack variable within a nested scope; we
tried to retain a pointer to that data beyond the scope, which is bogus.
GCC with -O1 eliminated most of the code that set new_prim's fields.
Move the declaration to fix the bug.
v2: Also fix new_ib (thanks to Matt Turner and Ben Widawsky).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=81025
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
Cc: mesa-stable at lists.freedesktop.org
commit f55ded764ce60f87463e33bfa3a32e2c44715581
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sun Apr 12 18:39:07 2015 -0700
i965: Implement proper workaround for Gen4 GPU CONSTANT_BUFFER hangs.
I finally managed to dig up some information on our mysterious GPU hangs.
A wiki page from the Crestline validation team mentions that they found
a GPU hang in "Serious Sam 2" (on Windows) with remarkably similar
conditions to the ones we've seen in Google Chrome and glmark2.
Apparently, if WM_STATE has "PS Use Source Depth" enabled, CC_STATE has
most depth state disabled, and you issue a CONSTANT_BUFFER command and
immediately draw, the depth interpolator makes a small mistake that
leads to hangs.
Most of the traces I looked at contained a CONSTANT_BUFFER packet
immediately followed by 3DPRIMITIVE, or at least very few packets.
It appears they also have "PS Use Source Depth" enabled - either at the
hang, or a little before it. So I think this is our bug.
The workaround is to emit a non-pipelined state packet after issuing a
CONSTANT_BUFFER packet. This is really similar to the workaround I
developed in commit c4fd0c9052dd391d6f2e9bb8e6da209dfc7ef35b.
v2: Fix word-wrapping issues.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 21d29124a719bdaf5794859a4a7441cc6be33df7
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sun Apr 12 03:52:39 2015 -0700
i965: Fix INTEL_DEBUG=shader_time for SIMD8 VS.
In commit 4ebeb71573ad44f7657810dc5dd2c9030e3e63db, I deleted the
emit_shader_time_end() call in emit_urb_writes(). But I failed to add
it to run_vs(), as I intended. So no data was recorded at all.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 1be329e64cd035e3ee088cff3a50d39e1ad66868
Author: Eric Anholt <eric at anholt.net>
Date: Mon Apr 6 15:12:58 2015 -0700
vc4: Add a blitter path using just the render thread.
This accelerates the path for generating the shadow tiled texture when
asked to sample from a raster texture (typical in glamor).
commit 76d56752ccff5bca3a0808705d5da76f186afb33
Author: Eric Anholt <eric at anholt.net>
Date: Thu Apr 9 13:35:57 2015 -0700
vc4: Allow submitting jobs with no bin CL in validation.
For blitting, we want to fire off an RCL-only job. This takes a bit of
tweaking in our validation and the simulator support (and corresponding
new code in the kernel).
commit 43b20795b742b9f1608dd6f2dc586337408760ad
Author: Eric Anholt <eric at anholt.net>
Date: Thu Apr 9 12:12:20 2015 -0700
vc4: Move the blit code to a separate file.
There will be other blit code showing up, and it seems like the place
you'd look.
commit e214a596352e67c89ce379a1e5a060dbc1ce31e1
Author: Eric Anholt <eric at anholt.net>
Date: Mon Apr 6 12:58:51 2015 -0700
vc4: Separate out a bit of code for submitting jobs to the kernel.
I want to be able to have multiple jobs being set up at the same time (for
example, a render job to do a little fixup blit in the course of doing a
render to the main FBO).
commit 44b63cf5c051f7eccfc1d7427247fd58dabb7761
Author: Eric Anholt <eric at anholt.net>
Date: Wed Apr 8 12:49:24 2015 -0700
vc4: When asked to sample from a raster texture, make a shadow tiled copy.
So, it turns out my simulator doesn't *quite* match the hardware. And the
errata about raster textures tells you most of what's wrong, but there's
still stuff wrong after that. Instead, if we're asked to sample from
raster, we'll just blit it to a tiled temporary.
Raster textures should only be screen scanout, and word is that it's
faster to copy to tiled using the tiling engine first than to texture from
an entire raster texture, anyway.
commit d04b07f8e2eb61bb389f2d6b8ed0a501952466ee
Author: Eric Anholt <eric at anholt.net>
Date: Thu Apr 9 13:43:55 2015 -0700
vc4: Fix off-by-one in branch target validation.
commit 7fa2f2e36660afe9f50f652baa6d65903d3a9dea
Author: Eric Anholt <eric at anholt.net>
Date: Mon Apr 13 14:12:59 2015 -0700
vc4: Use NIR-level lowering for idiv.
This fixes the idiv tests in piglit.
commit 84ebaff1b7f78cb47cd8eed5476f03c5c3d0e14b
Author: Eric Anholt <eric at anholt.net>
Date: Wed Apr 1 15:35:13 2015 -0700
vc4: Add a bunch of type conversions.
These are required to get piglit's idiv tests working. The
unsigned<->float conversions are wrong, but are good enough to get
piglit's small ranges of values working.
commit cc5860e40787b3afe36856674f028e830685271b
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Apr 8 10:00:27 2015 +1000
st/mesa: align cube map arrays layers
We create textures internally for texsubimage, and we use
the values from sub image to create a new texture, however
we don't align these to valid sizes, and cube map arrays
must have an array size aligned to 6.
This fixes texsubimage cube_map_array on CAYMAN at least,
(it was causing GPU hang and bad values), it probably
also fixes it on radeonsi and evergreen.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89957
Tested-by: Tom Stellard <thomas.stellard at amd.com>
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 5ed79312ed99f3b141c35569b9767f82f5ba0a93
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Apr 8 10:59:20 2015 +1000
st/mesa: convert sub image for cube map arrays to 2d arrays for upload
Since we can subimage upload a number of cube map array layers,
that aren't a complete cube map array, we should specify things
as a 2D array and blit from that.
Suggested by Ilia Mirkin as an alternate fix for texsubimage
cube map array issues.
seems to work just as well.
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 1e1d5456ba3dff82301ad4bbdde2fb6e2f562fe3
Author: Mathias Froehlich <Mathias.Froehlich at gmx.net>
Date: Sun Apr 12 18:23:58 2015 +0200
i965: Flush batchbuffer containing the query on glQueryCounter.
This change fixes a regression with timer queries introduced with
commit 3eb6258. There the pending batchbuffer is flushed
only if glEndQuery is executed. This present change adds such
a flush to glQueryCounter which also schedules a value query
just like glEndQuery does. The patch fixes GPU timer queries
going mad from within osgviewer.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Mathias Froehlich <Mathias.Froehlich at web.de>
Cc: mesa-stable at lists.freedesktop.org
commit adae027260bedc7af73e5cc7a74af3cafa4ab460
Author: Eric Anholt <eric at anholt.net>
Date: Wed Apr 8 13:11:01 2015 -0700
vc4: Use the blit interface for updating shadow textures.
This lets us plug in a better blit implementation and have it impact the
shadow update, too.
commit 39b6f7e76c909505df8590b6414e8f710121108a
Author: Eric Anholt <eric at anholt.net>
Date: Thu Apr 9 13:13:23 2015 -0700
vc4: Remove dead fields from vc4_surface.
commit 5100221ff705019334fcdc17da99d257224d2aff
Author: Eric Anholt <eric at anholt.net>
Date: Mon Apr 6 15:19:30 2015 -0700
vc4: Skip sending down the clear colors if not clearing.
commit 725620f21d19365d7a8a34d0c72694384c680afc
Author: Eric Anholt <eric at anholt.net>
Date: Thu Apr 9 13:41:29 2015 -0700
vc4: Sync with kernel changes to relax BCL versus RCL validation.
There was no reason to tie the two packets' values together.
commit cb88d2cfcb1f4444d1ec351277e8b662cda81a5e
Author: Eric Anholt <eric at anholt.net>
Date: Thu Apr 9 13:05:00 2015 -0700
vc4: Fix another space allocation mistake.
We're over-allocating our BCL in vc4_draw.c, so this never mattered.
However, new RCL-only blit support might end up here without having set up
any BCL contents.
commit 8eb9304ee74b7f4a3ef9f8ac9cb04f3031a61ded
Author: Eric Anholt <eric at anholt.net>
Date: Mon Apr 6 15:15:37 2015 -0700
vc4: Add missed accounting for the size of the semaphore.
This wouldn't have mattered except in the worst case scenario RCL setup.
commit 89b140dfaeacb8fb0a784c8dd7da26b0d14189e8
Author: Matt Turner <mattst88 at gmail.com>
Date: Sat Apr 11 10:14:00 2015 -0700
swrast: Mark MAX_GLUINT literal with u suffix.
Coverity is confused by the "float < int / 2" expression and suggests
casting MAX_GLUINT to unsigned, which I believe it was supposed to have
been already.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 1c9db39d54508608ea9518bc82eacbd8e27c410c
Author: Matt Turner <mattst88 at gmail.com>
Date: Sat Apr 11 10:05:31 2015 -0700
i965: Don't bother freeing NULL.
Commit e16c5c90 was replacing 'region' with 'mt', leaving this
nonsensical code.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit a76dc15b2b37db18151b42be63b49438588a92fe
Author: Chad Versace <chad.versace at intel.com>
Date: Thu Apr 9 20:29:59 2015 -0700
i965: Lift some restrictions on dma_buf EGLImages
Allow glEGLImageTargetRenderbufferStorageOES and
glEGLImageTargetTexture2DOES for dma_buf EGLImages if the image is
a single RGBA8 unorm plane. This is safe, despite fast color clears,
because i965 disables allocation of auxiliary buffers for EGLImages.
Chrome OS needs this, because its compositor uses dma_buf EGLImages for
its scanout buffers.
Testing:
- Tested on Ivybridge Chromebook Pixel with WebGL Aquarium and
YouTube.
- No Piglit regressions on Broadwell with `piglit run -p gbm
tests/quick.py`, with my Piglit patches that update the
EGL_EXT_image_dma_buf_import tests.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 2943b15ce7ce1bc29424949124a69538253008f7
Author: Chad Versace <chad.versace at intel.com>
Date: Mon Apr 6 08:07:27 2015 -0700
i965: Disable aux buffers for EGLImage-backed miptrees
EGL does not yet have extensions to manage the flushing and invalidating
of driver-internal aux buffers. So we must disable aux buffers of
dma_buf-backed EGLImages in order to safely render into them.
This patch is obviously needed for renderbufers. It's also needed for
textures because the user can attach the texture to a framebuffer and
because the driver sometimes renders to textures for internal reasons.
Testing:
- Tested on Ivybridge Chromebook Pixel with WebGL Aquarium and
YouTube.
- No Piglit regressions on Broadwell with `piglit run -p gbm
tests/quick.py`.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit bf504b61274123f09720c80569a8b4f2d3495630
Author: Chad Versace <chad.versace at intel.com>
Date: Mon Apr 6 08:11:43 2015 -0700
i965: Change intel_miptree_create_for_bo() signature
Add parameter 'bool disable_aux_buffers'.
This is a refactor patch. The patch changes no behavior because the new
parameter is false in every call.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit d3b042f359df5836d4a4f56664eb228fc80772c0
Author: Chad Versace <chad.versace at intel.com>
Date: Mon Apr 6 06:46:09 2015 -0700
i965: Add field intel_mipmap_tree::disable_aux_buffers
The new field disables allocation of auxiliary buffers, such as the HiZ
buffer and MCS buffer. This is useful for sharing the miptree bo with an
external client that doesn't understand auxiliary buffers.
We need this field to safely render to a buffer that was imported with
EGL_EXT_image_dma_buf_import, because EGL does not yet have extensions
to manage flushing and invalidating auxiliary buffers.
Nothing yet enables this field. That's left to follow-up patches.
Testing:
- Tested on Ivybridge Chromebook Pixel with WebGL Aquarium and
YouTube.
- No Piglit regressions on Broadwell with `piglit run -p gbm
tests/quick.py`.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit e1338f267fa5670fc02a450774fa89b42e990883
Author: Chad Versace <chad.versace at intel.com>
Date: Mon Apr 6 06:54:30 2015 -0700
i965: Refactor brw_is_hiz_depth_format()
Every caller of this function uses it to determine if the current
miptree needs a hiz buffer to be allocated. Strangely, the function
doesn't take a miptree argument. So, this function effectively decides
if and when a miptree's hiz buffer gets allocated without inspecting the
miptree itself. Luckily, the driver behaves correctly despite the
brw_is_hiz_depth_format's quirk.
I will soon make some changes to the miptree that will require
inspecting the miptree to determine if it needs a hiz buffer. So this
patch renames
brw_is_hiz_depth_format -> intel_miptree_wants_hiz_buffer
and gives it a miptree parameter.
This patch shouldn't change any behavior.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 5776d65114b553643eea74c58699910cbdb29b55
Author: Chad Versace <chad.versace at intel.com>
Date: Mon Apr 6 07:13:53 2015 -0700
i965: Declare intel_miptree_create_layout() as static
It's not used outside intel_mipmap_tree.c.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 1ef4bf71914c79b703fd9a75f047b24e0f16c59a
Author: Chad Versace <chad.versace at intel.com>
Date: Mon Apr 6 07:04:06 2015 -0700
i965: Declare intel_miptree_alloc_mcs() as static
It's not used outside of intel_mipmap_tree.c, nor should it ever be.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 36ceda4eced243c1fab487b878e20944d1238d50
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Mon Apr 13 13:08:13 2015 +0100
docs: Improve LLVM_USE_CRT_xxx instructions.
commit fa1b3e1501da3d24ec4205e0056d67ef9d2663ac
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Thu Apr 2 11:25:06 2015 +0100
glx: Include util/macros.h instead of redefining PRINTFLIKE.
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit 978753e84368ef3afa9288cbfbee1c85b3ab09d1
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Thu Apr 2 11:24:26 2015 +0100
util/ralloc: Fix `extern "C"` usage.
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 85dd46d90cd7d3d6898d28626063563c1aaba369
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Thu Apr 2 10:09:38 2015 +0100
mesa: Remove pointless USE_EXTERNAL_DXTN_LIB macro.
I'm not sure what was the original intention, but currently
USE_EXTERNAL_DXTN_LIB always ends up defined, one way or another.
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit 5ddeab8a069984f9ffc4e716528eeb43b3a8f77b
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sun Apr 12 23:16:42 2015 +0100
docs: add news item and link release notes for mesa 10.5.3
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit a94f8e712f97fec95e42643b0ad409814b7984f1
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sun Apr 12 23:10:42 2015 +0100
docs: Add 256 sums for the 10.5.3 release
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit 65776421fe59a0ffd5388c0968c9b0b1c1b230ed)
commit 794b9bf26af561f2a19a33df88bef1b96b1dd56b
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sun Apr 12 22:29:06 2015 +0100
Add release notes for the 10.5.3 release
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit c4b8bff6e24c6661a8a05ec05f8ed5762e95021b)
commit 61c6cc4a4aa23724bd51089b38741feed67617bc
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Apr 2 08:37:12 2015 +0000
docs: remove the --with-max-{width,height} note
Missed out with commit d99135b2e9b(configure: nuke
--with-max-{width,height})
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 0e742b1cb39c0df5846068d36c4f32c126b83fac
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Apr 1 17:46:09 2015 +0100
configure.ac: remove deprecated --with-libclc-path
The option was deprecated with commit 959e83d6507(clover: Adapt libclc's
INCLUDEDIR and LIBEXECDIR to make use of the new introduced libclc.pc.)
back in 2012 with mesa 9.2.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
commit b6354d9bb077815d2e388dc5d0e7411ea6d89748
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Jan 24 02:05:56 2015 -0800
i965/nir: Make INTEL_DEBUG=ann work with NIR.
Now that we store a copy of the NIR shader, and don't immediately free
it, we can use it in annotations as well.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 89c1feb78d010bc457f5d02be84c955eebf3549f
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Apr 7 15:15:09 2015 -0700
i965: Create NIR during LinkShader() and ProgramStringNotify().
Previously, we translated into NIR and did all the optimizations and
lowering as part of running fs_visitor. This meant that we did all of
that work twice for fragment shaders - once for SIMD8, and again for
SIMD16. We also had to redo it every time we hit a state based
recompile.
We now generate NIR once at link time. ARB programs don't have linking,
so we instead generate it at ProgramStringNotify time.
Mesa's fixed function vertex program handling doesn't bother to inform
the driver about new programs at all (which is rather mean), so we
generate NIR at the last minute, if it hasn't happened already.
shader-db runs ~9.4% faster on my i7-5600U, with a release build.
v2: Check NirOptions != NULL in ProgramStringNotify(). Don't bother
using _mesa_program_enum_to_shader_stage as we already know it.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit b3e286c4575bf6af343c1a03471fd876cdfb5c43
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Apr 7 17:13:45 2015 -0700
nir: Store num_direct_uniforms in the nir_shader.
Storing this here is pretty sketchy - I don't know if any driver other
than i965 will want to use it. But this will make it a lot easier to
generate NIR code at link time. We'll probably rework it anyway.
(Ian suggested making nir_assign_var_locations_scalar_direct_first
simply modify the nir_shader's fields, rather than passing pointers
to them. If this stays long term, we should do that. But Jason and
I suspect we'll be reworking this area again in the near future.)
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit f41f07f685e7f585e433b5fd1fadf602e74f0f1e
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Apr 7 15:05:12 2015 -0700
i965: Move lower_output_reads to brw_link_shader().
This makes it so emit_nir_code() doesn't modify the GLSL IR.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 8e414cbdec76ce33a16425631ac87cb4ba827409
Author: Matt Turner <mattst88 at gmail.com>
Date: Sat Apr 11 10:11:13 2015 -0700
glsl: Mark path as unreachable.
commit ea0c35faf88962e049c0a67ce714e03933383be1
Author: Matt Turner <mattst88 at gmail.com>
Date: Sat Apr 11 09:54:38 2015 -0700
i965: Remove useless null check.
If it were null, we'd have just derefernced it two lines above.
commit 024ecc783b763712d2896fd315d8b5222c27b1ec
Author: Matt Turner <mattst88 at gmail.com>
Date: Sat Apr 11 09:49:36 2015 -0700
i965/fs/nir: Mark fallthrough.
commit 1ac230975e2d3d9429e7a54f05d4fd803419fcd3
Author: Matt Turner <mattst88 at gmail.com>
Date: Sat Apr 11 09:47:39 2015 -0700
i965: Remove useless reg_offset >= 0 tests.
Commit eb9bd3a1 changed the type of this field to uint16_t.
commit b98c0262d1183d24a37272558c51678cd6a0e9ec
Author: Rob Clark <robclark at freedesktop.org>
Date: Sat Apr 11 10:04:50 2015 -0400
freedreno/ir3/nir: couple little fixes
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 1b936bb9f8da72baaef5c7454e8bebb63bbe067a
Author: Rob Clark <robclark at freedesktop.org>
Date: Fri Apr 10 15:57:29 2015 -0400
freedreno/ir3/nir: handle system values
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 715b2e0dbb88ef80880b8517f8fe822c26ef3be5
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Apr 9 20:32:14 2015 -0400
freedreno/ir3/nir: handle txs and query_levels tex ops
These correspond to the tgsi TXQ opcode
(plus sneak in a fix for two-sided color)
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 97e8fc3fdd8a5e7e9e5635cfde81c3cb297e9f1a
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Apr 9 16:44:38 2015 -0400
freedreno/ir3/nir: split out tex helpers
We'll need these in one or two other spots.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 6e8160d6e3ea7b000de112538dcbb0e29a6c3838
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Apr 9 12:55:49 2015 -0400
freedreno/ir3/nir: simplify emit_tex()
Just build up arrays for src0/src1, and use create_collect()..
Also add back missing .3d flag for 3d/cube textures.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit d5357c16cc0ccd84c3475778fcc08a025b8c24f7
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Apr 8 14:10:00 2015 -0400
freedreno/ir3/cp: handle indirect properly
I noticed some cases where we where trying to copy-propagate indirect
src's into places they cannot go, like 2nd src for cat3 (mad, etc).
Expand out valid_flags() to be aware of relativ flag, and fix up a few
related spots.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 49be76166b0b3c93bd2287fabc31d76d143d314c
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Apr 8 11:04:37 2015 -0400
freedreno/ir3/sched: avoid getting stuck on addr conflicts
When we get in a scenario where we cannot schedule any more instructions
due to address register conflict, clone the instruction that writes the
address register, and switch the remaining unscheduled users for the
current address register over to the new clone.
This is simpler and more robust than the previous attempt (which tried
and sometimes failed to ensure all other dependencies of users of the
address register were scheduled first).. hint it would try to schedule
instructions that were not actually needed for any output value.
We probably need to do the same with predicate register, although so far
it isn't so heavily used so we aren't running into problems with it
(yet).
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 4cf4006674bd7c507688316e2033d77066c45c90
Author: Rob Clark <robclark at freedesktop.org>
Date: Tue Apr 7 20:41:48 2015 -0400
freedreno/ir3/nir: add variable-indexing support
A bit fugly.. try and make this cleaner.. note if we hoist all the
get_addr() out of the loop we can drop the hashtable and just use
create_addr()..
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 972ce757d7f521f9f867594fe5661b8074130821
Author: Rob Clark <robclark at freedesktop.org>
Date: Mon Apr 6 11:42:57 2015 -0400
freedreno/ir3/asm: change assert to warning
It probably *should* be an assert, but for now TGSI f/e isn't very good
about dealing w/ CONST vs ABS/NEG. So for debug builds, print a warning
instead of crashing with an assert for now.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 09cbd97a47a81f5d4b014adb5bdb9a490b24db82
Author: Rob Clark <robclark at freedesktop.org>
Date: Mon Apr 6 10:54:30 2015 -0400
freedreno/ir3/nir: set first_driver_param
Without this, a3xx breaks.. a4xx would too if it had already implemented
support for passing driver params.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit f0e9a632a12798bd727799e396cde665bd960665
Author: Rob Clark <robclark at freedesktop.org>
Date: Mon Apr 6 10:48:11 2015 -0400
freedreno/ir3/cp: support to swap mad src's
For a normal MAD (ie. not MADSH), if first source is gpr and second
source is const, we can swap the first two sources to avoid needing a
mov instruction.
This gives back the biggest advantage TGSI f/e had over NIR f/e for
common shaders, since TGSI f/e had this logic in the f/e. Note that
doing this in copy-prop step has the advantage that it will also work
for cases like:
MOV TEMP[b], CONST[x]
MAD TEMP[d], TEMP[a], TEMP[b], TEMP[c]
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit f59613561694cc4a4b81db8a73f8afe893dbacac
Author: Rob Clark <robclark at freedesktop.org>
Date: Fri Apr 10 16:39:30 2015 -0400
nir: fix bit of cargo-culting in lower_idiv
I guess I was looking too much at how lower_system_values worked when
writing lower_idiv.
Since ttn wasn't emitting load_var for sysvals and the only drivers
using lower_idiv were using ttn, I think nothing was broken as a result.
But might as well fix this before it becomes a problem.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 58add76791459e023f82eab973719c71779dae9d
Author: Rob Clark <robclark at freedesktop.org>
Date: Sat Apr 4 08:13:44 2015 -0400
nir: split out lower_sub from lower_negate
Originally you had to have one or the other. But actually I don't want
either. (Or rather I want whatever is the minimum # of instructions.)
TODO: not sure where the best place to insert a check that driver hasn't
set *both* lower_negate and lower_sub?
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit fd65122a900a5779393faa0ede6737fafcb95a27
Author: Rob Clark <robclark at freedesktop.org>
Date: Fri Apr 10 15:01:16 2015 -0400
gallium/ttn: add support for system values
So far just the system values that freedreno supports, so we may add
more later.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 2faa878f13b414d3c6d1e4c3c7642f8db52d9550
Author: Rob Clark <robclark at freedesktop.org>
Date: Fri Apr 10 14:19:22 2015 -0400
gallium/ttn: fix TXD
With TXD we also have the ddx/ddy sources (before the sampler).
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit ca3ae90490d1df40d4a27c8a2d3171af528155b2
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Apr 9 15:41:31 2015 -0400
gallium/ttn: add TXQ support (v2)
Split out from ttn_tex() since it is kind of a weird instruction that
maps to two NIR opcodes, and it was cleaner this way.
v2: query_levels doesn't take any args
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 0b71451920e65c4dff049359cc6ebb6e9ce53773
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Apr 9 15:16:17 2015 -0400
gallium/ttn: split out helper to get texture info
We'll need this as well for TXQ. Split this out first to reduce noise
in the next patch.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 96c0f9328d315d6a5a0e83f920ad27791fd91b4f
Author: Rob Clark <robclark at freedesktop.org>
Date: Tue Apr 7 11:38:23 2015 -0400
gallium/ttn: add support for temp arrays
Since the rest of NIR really would rather have these as variables rather
than registers, create a nir_variable per array. But rather than
completely re-arrange ttn to be variable based rather than register
based, keep the registers. In the cases where there is a matching var
for the reg, ttn_emit_instruction will append the appropriate intrinsic
to get things back from the shadow reg into the variable.
NOTE: this doesn't quite handle TEMP[ADDR[]] when the DCL doesn't give
an array id. But those just kinda suck, and should really go away.
AFAICT we don't get those from glsl. Might be an issue for some other
state tracker.
v2: rework to use load_var/store_var with deref chains
v3: create new "burner" reg for temporarily holding the (potentially
writemask'd) dest after each instruction; add load_var to initialize
temporary dest in case not all components are overwritten
v4: review comments: asserts and use ttn_src_for_indirect() in
ttn_array_deref() so we can drop later patch converting to use vec1 for
addr reg (since ttn_src_for_indirect() handles the imov to vec1 from
tgsi addr component that we want)
v5: rebase: new requirements about parent mem ctx for derefs
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit b91d987140ce54969cbf9e0a10ad6b3ad5d5a75d
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Apr 8 13:17:30 2015 -0400
gallium/ttn: minor cleanup
Extract tgsi_dst->Index into a local.. split out from 'gallium/ttn: add
support for temp arrays' for noise reduction..
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit d47405eb707b9921f70454049677a9d504ee3fa6
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Apr 10 16:24:11 2015 -0700
i965: Use NIR by default for fragment shaders
GLSL IR vs. NIR shader-db results on i965:
total instructions in shared programs: 2889747 -> 2890782 (0.04%)
instructions in affected programs: 2425446 -> 2426481 (0.04%)
helped: 3698
HURT: 5341
GLSL IR vs. NIR shader-db results on g4x:
total instructions in shared programs: 2547252 -> 2550440 (0.13%)
instructions in affected programs: 1984482 -> 1987670 (0.16%)
helped: 2844
HURT: 4776
GLSL IR vs. NIR shader-db results on Iron Lake:
total instructions in shared programs: 4053381 -> 4063828 (0.26%)
instructions in affected programs: 3026601 -> 3037048 (0.35%)
helped: 4110
HURT: 8331
GAINED: 1287
LOST: 9
GLSL IR vs. NIR shader-db results on Sandy Bridge:
total instructions in shared programs: 5307041 -> 5236666 (-1.33%)
instructions in affected programs: 3442908 -> 3372533 (-2.04%)
helped: 11829
HURT: 5604
GAINED: 33
LOST: 18
GLSL IR vs. NIR shader-db results on Ivy Bridge:
total instructions in shared programs: 4926333 -> 4857017 (-1.41%)
instructions in affected programs: 3144042 -> 3074726 (-2.20%)
helped: 11559
HURT: 4774
GAINED: 46
LOST: 25
GLSL IR vs. NIR shader-db results on Bay Trail:
total instructions in shared programs: 4926333 -> 4857017 (-1.41%)
instructions in affected programs: 3144042 -> 3074726 (-2.20%)
helped: 11559
HURT: 4774
GAINED: 46
LOST: 25
GLSL IR vs. NIR shader-db results on Haswell:
total instructions in shared programs: 4392487 -> 4293476 (-2.25%)
instructions in affected programs: 2800180 -> 2701169 (-3.54%)
helped: 13073
HURT: 3383
GAINED: 46
LOST: 23
GLSL IR vs. NIR shader-db results on Broadwell (FS only):
total instructions in shared programs: 4378113 -> 4283025 (-2.17%)
instructions in affected programs: 2743209 -> 2648121 (-3.47%)
helped: 12470
HURT: 3609
GAINED: 64
LOST: 27
Signed-off-by: Jason Ekstrand <jason.ekstrand at intel.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
commit c2a0600d5b0645533ba442b5ab879b23c2564a4d
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Apr 9 23:26:49 2015 -0700
i965: Don't set NirOptions for stages that will use the vec4 backend.
We've started using NirOptions != NULL to mean "we're using NIR for this
stage." However, when INTEL_USE_NIR=1, we set it for a bunch of stages
that still use the vec4 backend, and thus definitely aren't using NIR.
For example, if INTEL_USE_NIR=1 we disable the GLSL IR cubemap
normalization pass, even for vertex shaders and geometry shaders. This
is wrong, but breaks a very uncommon case.
When I started deleting GLSL IR for stages where we claimed to be using
NIR, this bug quickly became apparent.
For now, only set it for fragment shaders, and vertex shaders if
brw->scalar_vs is set.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit f9048ee3c85ddaff0c44851b2523aaa2a554e059
Author: Nick Sarnie <commendsarnex at gmail.com>
Date: Fri Apr 10 12:45:57 2015 -0400
gallivm: Fix build since llvm-3.7.0svn r234495
Revert 50e9fa2ed69cb5f76f66231976ea789c0091a64d as LLVM reverted their
change.
Signed-off-by: Nick Sarnie <commendsarnex at gmail.com>
Reviewed-by: Jan Vesely <jan.vesely at rutgers.edu>
commit 50db8bd1b5942a6577ab5ee399cae460fde761d4
Author: Ville Syrjälä <ville.syrjala at linux.intel.com>
Date: Tue Mar 31 15:01:24 2015 +0300
i965/disasm: Print the type after the swizzle also for 3src src operands
The disassembly currently has the swizzle after the type for 3src source
operands, and the other way around for 2src. Flip the type and swizzle
around for 3src so that the output matches 2src.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
commit ae17f348502c0665fcead8daf8abaef8aa152b03
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Apr 7 16:28:10 2015 -0700
i965: Move brw_link_shader's GLSL IR transformations into a helper.
This function was getting a bit large and unwieldy.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 10d85ffc5a74bbce4decd7fe2aedd856ce7d39cb
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Apr 7 16:29:32 2015 -0700
i965: Change brw_shader to gl_shader in brw_link_shader().
Nothing actually wanted brw_shader fields - we just had to type
shader->base all over the place for no reason.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 500da98e0b96d211eab27629696ef50c47caaff9
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Apr 7 15:50:54 2015 -0700
nir: Constify nir_lower_sampler's gl_shader_program pointer.
Now that we're not generating linker errors, we don't actually modify
this.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 709b88ccd8009d98142616cb53c2ad66ddcd52a9
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Apr 7 15:46:56 2015 -0700
nir: Remove linker_error calls from nir_lower_samplers().
These should never happen. Plus, NIR passes really shouldn't be
reporting linker errors - this is past link time.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 99264b7f37dc92bcb3a9ae226e00c9300414431c
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Apr 7 15:14:16 2015 -0700
nir: Make nir_lower_samplers take a gl_shader_stage, not a gl_program *.
We don't actually need a gl_program struct. We only used it to
translate prog->Target (i.e. GL_VERTEX_PROGRAM) to the gl_shader_stage
(i.e. MESA_SHADER_VERTEX). We may as well just pass that.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 4b27391cadcc789a3befbd2b5a846012afa069b8
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Apr 7 15:18:43 2015 -0700
nir: Move gl_shader_stage enum from mtypes.h to shader_enums.h.
I want to use this in some code that doesn't currently include mtypes.h.
It seems like a better place for it anyway.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit feafe703998dd88ebea131741326eb229956656a
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Apr 7 15:16:51 2015 -0700
nir: Fix #include guards in shader_enums.h.
This header was originally going to be called pipeline.h, but it got
renamed at the last minute. Make the include guards match.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit d0f39a2fcd82da9b1e293ddfd2f5ea6e78d28df8
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Apr 7 15:07:33 2015 -0700
nir: Constify prog_to_nir's gl_program pointer.
prog_to_nir should not modify the incoming Mesa IR program - just
translate it.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 50e9fa2ed69cb5f76f66231976ea789c0091a64d
Author: Vinson Lee <vlee at freedesktop.org>
Date: Wed Apr 8 22:51:57 2015 -0700
gallivm: Fix build since llvm-3.7.0svn r234460.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89963
Signed-off-by: Vinson Lee <vlee at freedesktop.org>
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
commit a873b79fa5e3138196a3c1785f2a65308fa78286
Author: Roland Scheidegger <sroland at vmware.com>
Date: Sat Apr 4 16:49:08 2015 +0200
draw: (trivial) don't print the shader twice with GALLIVM_DEBUG=tgsi (or ir)
Neither the shader nor the key change when doing elts or linear variant, so
this was just annoying (probably mildly useful at some point when we printed
the IR per function too).
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 586536a4e1c34725b3b38c3425db569fac0c91e9
Author: Roland Scheidegger <sroland at vmware.com>
Date: Thu Apr 9 00:49:11 2015 +0200
gallivm: don't use control flow when doing indirect constant buffer lookups
llvm goes crazy when doing that, using way more memory and time, though there's
probably more to it - this points to a very much similar issue as fixed in
8a9f5ecdb116d0449d63f7b94efbfa8b205d826f. In any case I've seen a quite
plain looking vertex shader with just ~50 simple tgsi instructions (but with a
dozen or so such indirect constant buffer lookups) go from a terribly high
~440ms compile time (consuming 25MB of memory in the process) down to a still
awful ~230ms and 13MB with this fix (with llvm 3.3), so there's still obvious
improvements possible (but I have no clue why it's so slow...).
The resulting shader is most likely also faster (certainly seemed so though
I don't have any hard numbers as it may have been influenced by compile times)
since generally fetching constants outside the buffer range is most likely an
app error (that is we expect all indices to be valid).
It is possible this fixes some mysterious vertex shader slowdowns we've seen
ever since we are conforming to newer apis at least partially (the main draw
loop also has similar looking conditionals which we probably could do without -
if not for the fetch at least for the additional elts condition.)
v2: use static vars for the fake bufs, minor code cleanups
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 09e7e2016b702e2c4b79a2c01e8abc1365b4c422
Author: Brian Paul <brianp at vmware.com>
Date: Wed Apr 1 14:36:09 2015 -0600
glsl: check for forced_language_version in is_version()
This is a follow-on fix from the earlier "glsl: allow ForceGLSLVersion
to override #version directives" change. Since we're not changing
the language_version field, we have to check forced_language_version
here.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 4deca1274c25b80351dbec972b68ab6520a89b31
Author: Neil Roberts <neil at linux.intel.com>
Date: Fri Mar 6 19:11:19 2015 +0000
i965/skl: Fix the order of the arguments for the LD sampler message
In Skylake the order of the arguments for sample messages with the LD
type are u, v, lod, r whereas previously they were u, lod, v, r.
This fixes 144 Piglit tests including ones that directly use
texelFetch and also some using the meta stencil blit path which
appears to use texelFetch in its shader.
v2: Fix sampling 1D textures
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit eb51c6d55ff8b91497bd81f48f95e6bbe863a3e0
Author: Zhenyu Wang <zhenyuw at linux.intel.com>
Date: Tue Apr 7 13:48:38 2015 +0800
i965: Fix depth field setting in surface state for raw buffer on Gen7/8
On Gen7/8 for RAW surface format, the depth field (surf[3]) in surface
state means [30:21] bits of number of entries which is different from
other surface format which uses [26:21] bits field.
Signed-off-by: Zhenyu Wang <zhenyuw at linux.intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 6b722c390b484485b3be60057782ee19583a82d1
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Apr 8 10:31:14 2015 +1000
u_tile: fix warnings about incompatible casts.
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit f2947807c8c7eae4b98eb37263b8a1d9ebbcafb5
Author: Glenn Kennard <glenn.kennard at gmail.com>
Date: Tue Apr 7 03:00:20 2015 +0200
r600g/sb: Enable SB for geometry shaders
Add SV_GEOMETRY_EMIT special variable type to track the
implicit dependencies between CUT/EMIT_VERTEX/MEM_RING
instructions so GCM/scheduler doesn't reorder them.
Mark emit instructions as unkillable so DCE doesn't eat them.
Enable only for evergreen/cayman as there are a few
unexplained GS piglit regressions on R6xx/R7xx with SB
enabled otherwise.
Signed-off-by: Glenn Kennard <glenn.kennard at gmail.com>
Reviewed-by: Dave Airlie <airlied at redhat.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 06bb68da4a58403e678b51511e40a7f752dfc046
Author: Glenn Kennard <glenn.kennard at gmail.com>
Date: Thu Mar 26 02:56:50 2015 +0100
r600g/sb: Update last_cf for loops
CF_END could end up emitted in the middle of a shader on cayman
when there was a loop at the very end.
Fixes glsl-1.50-geometry-end-primitive and
ext_transform_feedback-geometry-shaders-basic piglit tests.
Signed-off-by: Glenn Kennard <glenn.kennard at gmail.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 61393bdcdc3b63624bf6e9730444f5e9deeedfc8
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Apr 7 09:52:41 2015 +1000
u_tile: fix stencil texturing tests under softpipe
arb_stencil_texturing-draw failed under softpipe because we got a float
back from the texturing function, and then tried to U2F it, stencil
texturing returns ints, so we should fix the tiling to retrieve
the stencil values as integers not floats.
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 11694737fc3b2d7f31367dbbbb8f5c02b40a1773
Author: Jason Ekstrand <jason at jlekstrand.net>
Date: Tue Apr 7 12:33:17 2015 -0700
nir: Make nir_*_instr_create take a nir_shader instead of a void * context
Signed-off-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit a10d493715cc3669a6e7647c5e514a386de886c0
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Mar 27 19:50:29 2015 -0700
nir: Implement a nir_sweep() pass.
This pass performs a mark and sweep pass over a nir_shader's associated
memory - anything still connected to the program will be kept, and any
dead memory we dropped on the floor will be freed.
The expectation is that this will be called when finished building and
optimizing the shader. However, it's also fine to call it earlier, and
many times, to free up memory earlier.
v2: (feedback from Jason Ekstrand)
- Skip sweeping impl->start_block, as it's already in the CF list.
- Don't sweep SSA defs (they're owned by their defining instruction)
- Don't steal phi sources (they're owned by nir_phi_instr).
- Don't steal tex->src (it's owned by the tex_inst itself)
- Don't sweep dereference chains (top-level dereferences are owned by
the instruction; sub-dereferences are owned by the parent deref).
- Don't sweep sources and destinations (SSA defs are handled as part of
the defining instruction, and registers are handled as part of
function implementations).
- Just steal instructions; don't walk them (no longer required).
v3: (feedback from Jason Ekstrand)
- Steal indirect sources from nir_src/nir_dest.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit de2014cf1e12826a53a1132f6d80c889f375b2e8
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Apr 2 21:24:38 2015 -0700
nir: Allocate dereferences out of their parent instruction or deref.
Jason pointed out that variable dereferences in NIR are really part of
their parent instruction, and should have the same lifetime.
Unlike in GLSL IR, they're not used very often - just for intrinsic
variables, call parameters & return, and indirect samplers for
texturing. Also, nir_deref_var is the top-level concept, and
nir_deref_array/nir_deref_record are child nodes.
This patch attempts to allocate nir_deref_vars out of their parent
instruction, and any sub-dereferences out of their parent deref.
It enforces these restrictions in the validator as well.
This means that freeing an instruction should free its associated
dereference chain as well. The memory sweeper pass can also happily
ignore them.
v2: Rename make_deref to evaluate_deref and make it take a nir_instr *
instead of void *. This involves adding &instr->instr everywhere.
(Requested by Jason Ekstrand.)
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 4f4b04b7c7ee1ce27da990190a740473db0f2ecb
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Mar 28 10:02:17 2015 -0700
nir: Allocate nir_ssa_def::uses/if_uses out of the instruction.
We can't allocate them out of the nir_ssa_def itself, because it may not
be ralloc'd (for example, nir_dest embeds a nir_ssa_def).
However, allocating them out of the instruction should work.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 900498bd111091dfda79d5ca6d84fffd427a866d
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Apr 2 16:15:11 2015 -0700
nir: Allocate nir_phi_src values out of the nir_phi_instr.
Phi sources are part of the phi instruction and should have the same
lifetime.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit b05d53404ccfe28b0011e93c388e5e5b8beaf6db
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Apr 7 00:32:55 2015 -0700
nir: Allocate nir_call_instr::params out of the nir_call itself.
The lifetime of the params array needs to be match the nir_call_instr
itself. So, allocate it using the instruction itself as the context.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 73d106822e3d0e851ef1308afff7490007b1af8c
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sun Mar 29 03:45:16 2015 -0700
i965: Add the ability to render to I8/L8 and I16/L16 UNORM formats.
This allows those formats to work with the meta PBO upload path.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 60dcd972574b11fa5f29ceb173d4b3ae430e618d
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Apr 6 16:09:35 2015 -0700
i965: Use SET_FIELD in 3DSTATE_STREAMOUT packets.
Suggested by Topi Pohjolainen.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 2e3b35a1cbe9e1c187b9a284c556821795ebaeea
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Apr 6 21:04:42 2015 -0700
nir/lower_tex_projector: Don't use designated initializers
These don't work in MSVC or in older versions of GCC
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89899
Reviewed-by: Mark Janes <mark.a.janes at intel.com>
commit 1aa5738e666a9534c7e5b46f077327e6d647c64f
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Thu Apr 2 12:59:55 2015 +0300
glsl: relax input->output validation for SSO programs
Commit 18004c3 introduced more restrictive validation to linker
between inputs and outputs. This patch skips the additional check
for programs that utilize GL_ARB_separate_shader_objects, there
inputs and outputs might not make exact match during linking but
only when constructing the final pipeline.
This made some of the GL_ARB_program_interface_query tests shaders
fail to link, these tests can be used to verify the change.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit ae720c66cb91c2640dfd6707446899694a24ab5b
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Apr 5 17:40:44 2015 -0400
nv50,nvc0: limit the y-tiling of 3d textures to the first level's tiling
We limit y-tiling to 0x20 when depth is involved. However the function is
run for each miplevel, and the hardware expects miplevel 0 to have the
highest tiling settings. Perform the y-tiling limit on all levels of a
3d texture, not just the ones that have depth.
Fixes:
texelFetch fs sampler3D 98x129x1-98x129x9
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Tested-by: Nick Tenney <nick.tenney at gmail.com> # GT216
Cc: "10.4 10.5" <mesa-stable at lists.freedesktop.org>
commit ad84689f737edefe549688f9b36d66027ca3fcb2
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Mar 31 15:18:47 2015 +1000
r600g: fix op3 abs issue
This code to handle absolute values on op3 srcs was a bit too simple,
it really needs a temp reg per src, not one per channel, make it
easier and let sb clean up the mess.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89831
Reviewed-by: Glenn Kennard <glenn.kennard at gmail.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 2042a2f961a07e04eaca0347e42859c249325531
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Mon Mar 9 15:17:03 2015 +0100
i965: Do not render primitives in non-zero streams then TF is disabled
Haswell hardware seems to ignore Render Stream Select bits from
3DSTATE_STREAMOUT packet when the SOL stage is disabled even if
the PRM says otherwise. Because of this, all primitives are sent
down the pipeline for rasterization, which is wrong. If SOL is
enabled, Render Stream Select is honored and primitives bound to
non-zero streams are discarded after stream output.
Since the only purpose of primives sent to non-zero streams is to
be recorded by transform feedback, we can simply discard all geometry
bound to non-zero streams then transform feedback is disabled
to prevent it from ever reaching the rasterization stage.
Notice that this patch introduces a small change in the behavior we
get when a geometry shader emits more vertices than the maximum declared:
before, a vertex that was emitted to a non-zero stream when TF was
disabled would still count for the purposes of checking that we don't
exceed the maximum number of output vertices declared by the shader. With
this change, these vertices are completely ignored and won't increase
the output vertex count, making more room for other (hopefully more
useful) vertices.
Fixes piglit test arb_gpu_shader5-emitstreamvertex_nodraw on Haswell
and Broadwell.
v2 (Ken): Drop is_haswell check in favor of doing this unconditionally.
Broadwell needs the workaround as well, and it doesn't hurt to do it in
general. Also tweak comments - the Haswell PRM does actually mention
this ("Command Reference: Instructions" page 797).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83962
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Cc: mesa-stable at lists.freedesktop.org
commit f368d0fa1fe37a58780ee555d4a9ccf15474782b
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Mar 26 17:21:10 2015 -0700
i965: Add forgotten multi-stream code to Gen8 SOL state.
Fixes Piglit's arb_gpu_shader5-xfb-streams-without-invocations.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
Cc: mesa-stable at lists.freedesktop.org
commit f9e5dc0a85df8dbfb8213ff772dfeb218972db12
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Apr 4 02:00:52 2015 -0700
i965: Fix instanced geometry shaders on Gen8+.
Jordan added this in commit 741782b5948bb3d01d699f062a37513c2e73b076 for
Gen7 platforms. I missed this when adding the Broadwell code.
Fixes Piglit's spec/arb_gpu_shader5/invocation-id-{basic,in-separate-gs}
with MESA_EXTENSION_OVERRIDE=GL_ARB_gpu_shader5 set.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
Cc: mesa-stable at lists.freedesktop.org
commit a09c5b8527c2b28d30c0b11111a66fc7d283c06f
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Apr 2 00:55:45 2015 -0700
i965: Free dead GLSL IR one last time.
While working on NIR's memory allocation model, I realized the GLSL IR
memory model was broken.
During glCompileShader, we allocate everything out of the
_mesa_glsl_parse_state context, and reparent it to gl_shader at the end.
During glLinkProgram, we allocate everything out of a temporary context,
then reparent it to the exec_list containing the linked IR.
But during brw_link_shader - the driver's final opportunity to do
lowering and optimization - we just allocated everything out of the
permanent context given to us by the linker. That memory stayed
forever.
Notably, passes like brw_fs_channel_expressions cause us to churn the
majority of the code, so we really want to free dead IR here.
Saves 125MB of memory when replaying a Dota 2 trace on Broadwell.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 797d606127c131a6ccff28150495d2b1f3f7e46e
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Feb 20 15:11:49 2015 -0800
i965: Implement SIMD16 texturing on Gen4.
This allows SIMD16 mode to work for a lot more programs. Texturing is
also more efficient in SIMD16 mode than SIMD8. Several messages don't
actually exist in SIMD8 mode, so we did SIMD16 messages and threw away
half of the data. Now we compute real data in both halves.
Also, the SIMD16 "sample" message doesn't require all three coordinate
components to exist (like the SIMD8 one), so we can shorten the message
lengths, cutting register usage a bit.
I chose to implement the visitor functionality in a separate function,
since mixing true SIMD16 with SIMD8 code that uses SIMD16 fallbacks
seemed like a mess. The new code bails on a few cases where we'd
have to do two SIMD8 messages - we just fall back to SIMD8 for now.
Improves performance in "Shadowrun: Dragonfall - Director's Cut" by
about 20% on GM45 (measured with LIBGL_SHOW_FPS=1 while standing around
in the first mission).
v2: Add ir_txf to the has_lod case (caught by Jordan Justen).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 8aee87fe4cce0a883867df3546db0e0a36908086
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Feb 20 14:09:17 2015 -0800
i965: Use SIMD16 instead of SIMD8 on Gen4 when possible.
Gen5+ systems allow you to specify multiple shader programs - both SIMD8
and SIMD16 - and the hardware will automatically dispatch to the most
appropriate one, given the number of subspans to be processed.
However, that is not the case on Gen4. Instead, you program a single
shader. If you enable multiple dispatch modes (SIMD8 and SIMD16), the
shader is supposed to contain a series of jump instructions at the
beginning. The hardware will launch the shader at a small offset,
hitting one of the jumps.
We've always thought that sounds like a pain, and weren't clear how it
affected performance - is it worth having multiple shader types? So,
we never bothered with SIMD16 until now.
This patch takes a simpler approach: try and compile a SIMD16 shader.
If possible, set the no_8 flag, telling the hardware to just use the
SIMD16 variant all the time.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 108b92b1e9f645e9d2ff33b24648f5d089cb89c9
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Jan 10 13:31:48 2015 -0800
i965: Respect the no_8 flag on Gen4-5.
This flag means to ignore the SIMD8 program and only use the SIMD16 one.
It was originally meant for repdata clear shaders, but I plan to use it
for other things on Gen4 as well.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 62050886c85b7b3b6c94e3c2363966b4f14df0bd
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Apr 3 18:30:57 2015 -0700
i965/fp: Set coord_components correctly for cube textures.
I've no idea why this was 4. It certainly seems wrong.
Prevents assertion failures in fp-incomplete-tex with some upcoming
patches of mine.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit dd7d0687848fb6c310debef4a6ff61b2159d2a4d
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Mar 25 17:23:40 2015 -0700
glsl/cse: Maintain a list of free ae_entry objects
The CSE algorithm will continuously allocate new ae_entry objects. As
each new basic block is exited, all of the previously allocated objects
are dumped. Instead, put them in a free list and re-use them in the
next basic block. Reduce, reuse, recycle!
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Thomas Helland <thomashelland90 at gmail.com>
commit d131630c0825f199768965c504b6fa1e593d03d5
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Apr 1 18:25:02 2015 -0700
nir: Remove fsin_reduced/fcos_reduced.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit c8d65dd7138ba5683be16e692882e41d6dae7bf8
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Apr 1 18:23:58 2015 -0700
st/mesa: Remove unused emit_scs().
Was only used by the sin_reduced/cos_reduced cases, which themselves
were impossible to reach.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 5fb735b75675bc4d6287f2a87c9baac65da5f405
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Apr 1 18:22:52 2015 -0700
program: Remove unused emit_scs().
Was only used by the sin_reduced/cos_reduced cases, which themselves
were impossible to reach.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit cdb1eb9a3fa096b0eeef239a602cd1c42cf27498
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Apr 1 18:21:41 2015 -0700
i965/vec4: Remove emit_scs() prototype.
This has never existed.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 5c71cf85315320fcb8b1cc2178f7f2d76b3beeef
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Apr 1 17:44:16 2015 -0700
glsl: Remove never used sin_reduced/cos_reduced.
These were added in commit f2616e56, presumably in preparation for
translating ARB vp/fp into GLSL IR. That never happened, and neither did
a lowering pass that actually generated these instructions.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 490621f0f2814ff1713c74f030acaff3f19cf8fb
Author: Antia Puentes <apuentes at igalia.com>
Date: Tue Mar 17 19:12:23 2015 +0100
glsl: Update the #line behaviour on GLSL 3.30+ and GLSL ES+
From GLSL 3.30 and GLSL ES 1.00 on, after processing the line
directive (including its new-line), the implementation should
behave as if it is compiling at the line number passed as
argument. In previous versions, it behaved as if compiling
at the passed line number + 1.
Partially fixes https://bugs.freedesktop.org/show_bug.cgi?id=88815
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit c0a7014601ca93d30ba9bf1ec3c6d04da904d503
Author: Antia Puentes <apuentes at igalia.com>
Date: Tue Mar 17 19:28:25 2015 +0100
glsl: respect the source number set by #line <line> <source>
From GLSL 1.30.10, section 3.3 (Preprocessor):
"#line line source-string-number ... After processing this directive
(including its new-line), the implementation will behave as if it is
compiling at ... source string number source-string-number. Subsequent
source strings will be numbered sequentially, until another #line
directive overrides that numbering."
In the previous implementation the source number was always zero.
Subsequent source strings are still not numbered sequentially, because
in the glShaderSource implementation we are concatenating the source code
strings into one long string.
Partially fixes https://bugs.freedesktop.org/show_bug.cgi?id=88815
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 47597f8f5cfe950093110d2b777923ef85c5d24f
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Tue Feb 3 12:34:29 2015 +0100
i965: Make sure we always mark array surfaces as such
Even if they only have one slice, otherwise textureSize() won't
produce correct results for the depth value.
Fixes 10 dEQP tests in this category:
dEQP-GLES3.functional.shaders.texture_functions.texturesize.sampler2darray*
Reviewed-by: Mark Janes <mark.a.janes at intel.com>
commit 8b0b81339b9c3806981ee2ec7c08501bbd8bb7a3
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Mar 12 17:18:33 2015 -0400
freedreno/ir3: add NIR compiler
The NIR compiler frontend is an alternative to the TGSI f/e, producing
the same ir3 IR and using the same backend passes for scheduling, etc.
It is not enabled by default yet, as there are still some regressions.
To enable, use 'FD_MESA_DEBUG=nir'. It is enough to use with, for
example, xonotic or supertuxkart.
With the NIR f/e, scalarizing and a number of other lowering steps
happen in NIR, so we don't have to do them in ir3. Which simplifies the
f/e and allows the lowered instructions to pass through other
optimization stages.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 700d949ea162a5036ffc3056adaa8eb3fecc9c2e
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Tue Mar 3 20:36:39 2015 -0500
freedreno/a3xx: don't decode srgb on mem2gmem
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit b060b56772cdb349478757382de036a20a2402ba
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Apr 4 02:53:52 2015 -0400
freedreno/a3xx: pass sprite coord mode through to program emit
Use the correct sprite replacement depending on the flip of the coord
mode, using either T or 1-T depending on whether we have an upper-left or
lower-left coordinate origin. This fixes all the point sprite piglits.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 1de72dfc8a2014069edd1b3d3d46dad478d0680a
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Tue Mar 31 11:51:00 2015 -0400
freedreno/a3xx: add UBO support
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit c7811f56c205b113dd820034a99ff3aaa20af636
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Apr 4 13:37:45 2015 -0400
freedreno/ir3: insert nop between sfu/mem operations
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 14dfd8cc4344a1bb15a63179b497d14eaec9cc0d
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Apr 3 22:29:44 2015 -0400
freedreno: dirty context when reallocating a bound bo
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit bde2045fa247b4d1de98a3bc7585d1b60f9b58b7
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Apr 3 02:15:17 2015 -0400
freedreno: keep track of buffer valid ranges
Copies nouveau_buffer and radeon_buffer. This allows a write to proceed
to an uninitialized part of a buffer even when the GPU is using the
previously-initialized portions.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit dacf22e0a34d4dc2595f3cb0dbee52318dc9d0d7
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Apr 2 20:48:44 2015 -0400
freedreno: mark resources as being read so that writes flush the queue
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 2e1445c8f3df7608ba4522f8d088170de4ec788c
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Apr 3 23:39:38 2015 -0400
freedreno: don't bother setting resource timestamps
Waiting on a bo being ready is handled in fd_bo_cpu_prep. No need to
keep separate timestamps around.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 1fee3061d531a9f4068952209926ad518aab07ee
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Apr 3 02:25:58 2015 -0400
freedreno: add a reading flag to indicate gpu is reading rsc
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit ea0952a9db1b5887f915d8f750f5fa9c45719976
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Apr 2 22:28:21 2015 -0400
freedreno: fix resource flushing confusion
A resource flush is an upload of a hypothetically-staging texture to the
GPU. For a UMA system, this will largely be a no-op or
cache-maintenance. Move the render flush logic into transfer_map where
it belongs, and clear out the transfer_flush function.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit bfb0a8eb6967065be92e40ba620fc6fededde51a
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Apr 2 22:26:03 2015 -0400
freedreno: remove tex_resource
pipe_sampler_view already contains a texture, remove the redundant
tex_resource member which pointed at the same thing.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 6cd9c94ce49a2c1a8826c1b1bf2fb73dc595131d
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Apr 1 12:31:46 2015 -0400
freedreno/ir3: handle FRAG IN's without interpolation specified
Fallback to picking based on semantic name.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit f513f006ceed825fa09e606d99190e490e559885
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Apr 1 10:52:29 2015 -0400
freedreno/ir3/cmdline: add @const headers for immediates
Since NIR f/e currently encodes immediates in instructions (rather than
passing via const), we need to ensure that when const's are used the get
initialized to the proper values. Otherwise comparing NIR to TGSI
compiler, it will use proper immediate values in one case, and randomly
initialize values in the other. Which confuses ir3test.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 6bc12bb5fd29a70967d467a19153bda9404653bd
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Apr 1 10:28:58 2015 -0400
freedreno/ir3/cmdline: remove hack for old compiler
Since we dropped the old compiler, we don't need this hack anymore.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit f370e95421f553ace931a02743c96be80fd62dc8
Author: Rob Clark <robclark at freedesktop.org>
Date: Sun Mar 29 11:24:57 2015 -0400
freedreno/ir3: handle const/immed/abs/neg in cp
Be smarter about propagating copies from const or immed, or with abs/neg
modifiers. Also, realize that absneg.s and absneg.f are really "fancy"
mov instructions.
This opens up the possibility to remove more copies. It helps the TGSI
frontend a bit, but will be really needed for the NIR f/e which builds
everything up in SSA form (ie. will *always* insert a mov from const or
immediate).
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 104713d9f2dced94a427004a25c54b2c7feee166
Author: Rob Clark <robclark at freedesktop.org>
Date: Sun Mar 29 11:18:29 2015 -0400
freedreno/ir3: split float/int abs/neg
Even though in the end, they map to the same bits, the backend will need
to be able to differentiate float abs/neg vs integer abs/neg. Rather
than making the backend figure it out based on instruction opcode (which
when combined with mov/absneg instructions, can be awkward), just split
out different flags for each so the frontend can signal it's intentions
more clearly. Also, since (neg) for bitwise op's is actually a bitwise-
not, split it out into bnot flag.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 203f37540a698a812f0a66e2f3f1fff954af22ab
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Mar 18 19:26:13 2015 -0400
freedreno/ir3: add ir3 builder helpers
Add helpers for constructing SSA forms of instructions.
Only partial cat5/cat6 coverage.. but we can add stuff as needed.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit b1c9fb9fcaf34923f69d671fdba0a35ea581b3a0
Author: Rob Clark <robclark at freedesktop.org>
Date: Mon Mar 30 14:14:31 2015 -0400
freedreno/ir3: fix sam argument order comment
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 101142c401038684ca971015d7576029b9dc5e63
Author: Rob Clark <robclark at freedesktop.org>
Date: Fri Apr 3 14:01:47 2015 -0400
xa: support for drivers which use NIR
We need to pull in libnir.la and it's dependency libglsl_util.la. Also,
_mesa_error_no_memory() must be defined.
Fortunately with libnir.la (vs pulling in all of libglsl.la) we don't
also need libstdc++.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 1c857727a12a45392b609949046b4abb25e3d7da
Author: Rob Clark <robclark at freedesktop.org>
Date: Fri Apr 3 13:57:46 2015 -0400
build: add libnir.la
If we want to use NIR from state trackers that don't already pull in the
whole of glsl (ie. anything other than mesa state tracker), we need a
separate more minimal libnir. Possibly NIR should be better split out
from glsl, but for now, generate a second smaller libnir.la for those
who just want NIR but not all of glsl.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 52282fa42d34051b042d20b52e84f32274691e36
Author: Rob Clark <robclark at freedesktop.org>
Date: Sat Apr 4 18:15:24 2015 -0400
gallium/ttn: MOD is an integer instruction
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Eric Anholt <eric at anholt.net
commit 7579ae422a0fcd8c36a6e873f5e47d0e8d158640
Author: Rob Clark <robclark at freedesktop.org>
Date: Sat Apr 4 18:15:00 2015 -0400
gallium/ttn: add UMAD
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit f2ecc95e44c5798a15cde4aa67887bc562756ccd
Author: Rob Clark <robclark at freedesktop.org>
Date: Tue Mar 31 17:03:39 2015 -0400
nir: add lowering for idiv/udiv/umod
Based on the algo from NV50LegalizeSSA::handleDIV() and handleMOD().
See also trans_idiv() in freedreno/ir3/ir3_compiler.c (which was an
adaptation of the nv50 code from Ilia Mirkin).
A python/numpy script which implements the same algorithm (and is
possibly useful for debugging or analysis) can be found here:
http://people.freedesktop.org/~robclark/div-lowering.py
I've tested this on i965 hacked up to insert the idiv lowering pass,
and on freedreno with NIR frontend.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Tested-by: Eric Anholt <eric at anholt.net> (vc4)
commit 7880bea2fb587871faead78f624920ad5e8b89f7
Author: Rob Clark <robclark at freedesktop.org>
Date: Tue Mar 31 15:13:00 2015 -0400
nir: fix typo for f2b/i2b/b2i expressions (v2)
v2: discovered that i2b/b2i are also confused
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 6829d76e0285f9ed8091990b908d2e7dc37c5218
Author: Rob Clark <robclark at freedesktop.org>
Date: Tue Mar 31 11:25:19 2015 -0400
nir: add option to lower slt/sge/seq/sne
In freedreno these get implemented as the matching f* instruction plus a
u2f to convert the result to float 1.0/0.0. But less lines of code to
just let nir_opt_algebraic handle this for us, plus opens up some small
window for other opt passes to improve (ie. if some shader ended up with
both a flt and slt with same src args, for example).
v2: use b2f rather than u2f
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 24b78fe54e1498dc3f66cb616561894039806642
Author: Mathias Froehlich <Mathias.Froehlich at gmx.net>
Date: Sun Apr 5 09:21:51 2015 +0200
mesa: Remove unused variables left over from 107ae27e57d.
Reviewed-by: Dave Airlie <airlied at redhat.com>
Signed-off-by: Mathias Froehlich <Mathias.Froehlich at web.de>
commit fdd90fcb15c109f3dcbf5e46fa8a1f8284b9c266
Author: Mathias Fröhlich <Mathias.Froehlich at gmx.net>
Date: Sun Mar 29 16:52:57 2015 +0200
i965: Implement support for ARB_clip_control.
Switch between the two clip space definitions already available
in hardware. Update winding order dependent state according
to the clip control state.
This change did not introduce new piglit quick.test regressions on
an Ivybridge Mobile and a GM45 Express chipset.
Also it enables and passes the clip-control and clip-control-depth-precision
tests on these two chipsets.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Mathias Froehlich <Mathias.Froehlich at web.de>
commit 107ae27e57dc2a1ddc6bbb7ea101c1c60794423f
Author: Mathias Froehlich <Mathias.Froehlich at web.de>
Date: Sun Mar 29 18:57:46 2015 +0200
mesa: Remove the _WindowMap from gl_viewport_attrib.
The _WindowMap can be dropped from gl_viewport_attrib now.
Simplify gl_viewport_attrib handling where possible.
Reviewed-by: Brian Paul <brianp at vmware.com>
Signed-off-by: Mathias Froehlich <Mathias.Froehlich at web.de>
commit 29e6c7dbc5bacf4f2b741333ac56469a00164e65
Author: Mathias Froehlich <Mathias.Froehlich at web.de>
Date: Sun Mar 29 18:57:45 2015 +0200
tnl: Maintain the _WindowMap matrix in TNLcontext v2.
This is the only real user of _WindowMap which has the depth
buffer scaling multiplied in. Maintain the _WindowMap of the
one and only viewport inside TNLcontext.
v2:
Remove unneeded parentheses.
Reviewed-by: Brian Paul <brianp at vmware.com>
Signed-off-by: Mathias Froehlich <Mathias.Froehlich at web.de>
commit 472913ea7563e136b9ad3d33111925147a044a39
Author: Mathias Froehlich <Mathias.Froehlich at web.de>
Date: Sun Mar 29 18:57:45 2015 +0200
radeon: Make use of _mesa_get_viewport_xform v2.
Instead of _WindowMap just use the translation and scale
of the viewport transform directly. Thereby avoid dividing by
_DepthMaxF again.
v2:
Change order of assignments.
Reviewed-by: Brian Paul <brianp at vmware.com>
Signed-off-by: Mathias Froehlich <Mathias.Froehlich at web.de>
commit a8ceb8e450354083b0b4141cd7fa0174a4d18f72
Author: Mathias Froehlich <Mathias.Froehlich at web.de>
Date: Sun Mar 29 18:57:45 2015 +0200
i965: Make use of _mesa_get_viewport_xform.
Instead of _WindowMap just use the translation and scale
of the viewport transform directly. Thereby avoid dividing by
_DepthMaxF again.
Reviewed-by: Brian Paul <brianp at vmware.com>
Signed-off-by: Mathias Froehlich <Mathias.Froehlich at web.de>
commit ba353935a392d2a43422f1d258456336b40b60ea
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Apr 3 23:57:43 2015 -0400
nv50: allocate more offset space for occlusion queries
Commit 1a170980a09 started writing to q->data[4]/[5] but kept the
per-query space at 16, which meant that in some cases we would write
past the end of the buffer. Rotate by 32, like nvc0 does. This ensures
that we always have 32 bytes in front of us, and the data writes will go
within the allocated space.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89679
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Tested-by: Nick Tenney <nick.tenney at gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de>
Cc: "10.4 10.5" <mesa-stable at lists.freedesktop.org>
commit 9c53e80b9b6a637a771328bac98d2292a00869ce
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Apr 3 15:23:20 2015 -0700
nir/lower_samplers: Use the right memory context for realloc'ing tex sources
As of da5ec2a, we allocate instruction sources out of the instruction
itself. When we realloc the texture sources we need to use the right
memory context or ralloc will get angry and assert-fail
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 1bd1fc248ce5ecc6882309ab64ec61835fea1eda
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Apr 2 17:04:28 2015 -0700
i965: Use brw_nir_cubemap_normalize for NIR shaders
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 52e718097fa7dc808b3e8b43a8fd14a5b2b64797
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Apr 2 16:38:30 2015 -0700
nir: Add a cubemap normalizing pass
This commit adds a pass to L1-normalize cube-map coordinates. Some hardware
such as i965 requires that largest cube-map coordinate is +-1. We had a
pass to perform this normalization in GLSL IR but we need it in NIR for
cube maps on ARB programs to work correctly.
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
v2 (Suggested by Eric):
- Do a vector fabs and split into components later
- Move to core NIR
Reviewed-by: Eric Anholt <eric at anholt.net>
commit bff421332661bfd0f82ab9eee9e4fec9d06ed1a1
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Apr 2 17:02:43 2015 -0700
i965: Check the INTEL_USE_NIR environment variable once at context creation
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit dccc57eaba5e5920a6c151e7abb386a636ebf861
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Apr 2 12:32:39 2015 -0700
nir/from_ssa: Don't set reg->parent_instr for ssa_undef instructions
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 7bdba4a24583f4cc2f9bca94f975cec9d384cddc
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Apr 2 11:07:48 2015 -0700
nir: Add a src_get_parent_instr function
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit cb966fb2bea77b1d7b1bdb6597b7b85d810f2d0a
Author: Eric Anholt <eric at anholt.net>
Date: Wed Apr 1 11:38:53 2015 -0700
i965: Use the tex projector lowering pass instead of hand-rolling it.
This only impacts the ARB_fp path. We can't quite disable the GLSL-level
lowering pass, because it needs to apply before
brw_do_lower_unnormalized_offset().
total instructions in shared programs: 5667857 -> 5667847 (-0.00%)
instructions in affected programs: 1114 -> 1104 (-0.90%)
helped: 16
HURT: 6
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit ea811b7868d4039499dddf53c109cf0b9da98967
Author: Eric Anholt <eric at anholt.net>
Date: Fri Mar 27 14:18:11 2015 -0700
nir: Add a lowering pass for texture projectors.
Not much hardware wants them these days, and it might give us a chance to
do CSE or algebraic at the NIR level.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 64bdfc698d6d9f543f82141330ae32de286b8417
Author: Eric Anholt <eric at anholt.net>
Date: Fri Mar 27 14:19:46 2015 -0700
nir: Add an interface to turn a nir_src into a nir_ssa_def.
We use nir_ssa_defs for nir_builder args, so this takes a nir_src and
makes one so it can be passed in.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit ec029702054ddc4e098ebb96e76c7451190d649f
Author: Eric Anholt <eric at anholt.net>
Date: Fri Mar 27 14:18:54 2015 -0700
nir: Add an interface for the builder to insert instructions before.
So far we'd only used nir_builder to build brand new programs. But if
we're doing modifications to instructions (like in a lowering pass), then
we want to generate new stuff before the instruction we're modifying.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 328375d2742a3394dc481fc5fae6c4a5d797b4e7
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Thu Apr 2 17:35:16 2015 +0200
gallium: fix gcc compile errors when using _XOPEN_SOURCE=600 but not std=c99
The fpclassify stuff either needs std=c99 or _XOPEN_SOURCE=600 passed
to gcc, but when using the latter the lrint family of function will be defined
too.
commit b9b66985c3d33fa0db2b49c0e0231aa6d341e183
Author: Carl Worth <cworth at cworth.org>
Date: Fri Mar 20 12:10:49 2015 -0700
i965: Rename do_<stage>_prog to brw_compile_<stage>_prog (and export)
This is in preparation for these functions to be called from other
files.
This commit is intended to have no functional change. It exists in
preparation for some upcoming code movement in preparation for the
shader cache.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit a57672f18deca3060eab129a77cf84f5e420bac8
Author: Carl Worth <cworth at cworth.org>
Date: Fri Mar 20 12:01:33 2015 -0700
i965: Split out per-stage dirty-bit checking into separate functions
The dirty-bit checking from each brw_upload_<stage>_prog function is
split out into its a new brw_<stage>_state_dirty function.
This commit is intended to have no functional change. It exists in
preparation for some upcoming code movement in preparation for the
shader cache.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 28510d69ff8fc03bc1693be2b7a02bc68791dd2f
Author: Carl Worth <cworth at cworth.org>
Date: Mon Feb 23 14:44:39 2015 -0800
i965: Split out brw_<stage>_populate_key into their own functions
This commit splits portions of the existing brw_upload_vs_prog and
brw_upload_gs_prog function into new brw_vs_populate_key and
brw_gs_populate_key functions. This follows the same style as is
already present for all other stages, (see brw_wm_populate_key, etc.).
This commit is intended to have no functional change. It exists in
preparation for some upcoming code movement in preparation for the
shader cache.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 01d3b750b3682f3774f1bd01fa07a6b3c8baf28e
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Apr 2 18:42:31 2015 -0400
nv50/ir: avoid folding immediates into imad operations
Commit 09ee907266 added logic to fold immediates into mad operations,
but the emission code is only there for fmad. Only allow it on float
types.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 603d28f32c1083921ea9d54a0a606dd832e44aaa
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Apr 2 18:33:55 2015 -0400
nv50/ir: fix imad emission when dst == src2
Commit fb63df22151f added 4-byte mad support, but only supported
emission for floats. Disable it for ints for now.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit da5ec2ac0bc20b52fefe59081efcdb9b3989f6a7
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Mar 28 00:02:37 2015 -0700
nir: Allocate nir_tex_instr::sources out of the instruction itself.
The lifetime of the sources array needs to be match the nir_tex_instr
itself. So, allocate it using the instruction itself as the context.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 7380c641b116a47d5729c553dcf3ed7143e877cc
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Mar 27 21:29:07 2015 -0700
nir: Allocate predecessor and dominance frontier sets from block itself.
These sets are part of the block, and their lifetime needs to match the
block itself. So, allocate them using the block itself as the context.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 131444e1c5e08cbac4694489110ab53c9c07816d
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Mar 27 20:21:59 2015 -0700
nir: Allocate register fields out of the register itself.
The lifetime of each register's use/def/if_use sets needs to match the
register itself. So, allocate them using the register itself as the
context.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 587b3a20a1d3201467adf90e66b53b9843b2cc0a
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Mar 27 19:23:36 2015 -0700
nir: Make nir_create_function() strdup the function name.
glsl_to_nir passes in the ir_function's name field; we were copying the
pointer, but not duplicating the memory.
We want to be able to free the linked GLSL IR program after translating
to NIR, so we'll need to create a copy of the function name that the NIR
shader actually owns.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit f61b6c3e48071991c098aa588ee86473f419d5c0
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Mar 27 16:19:27 2015 -0700
nir: Free dead variables when removing them.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit f4e449108060dcaea1b4e1e445b76a8ef43d3a05
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Mar 27 16:17:20 2015 -0700
nir: Combine remove_dead_local_vars() and remove_dead_global_vars().
We can just pass a pointer to the list of variables, and reuse the code.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 33f0f68d590a460f84a0df0de10f29c4a582d7e7
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Mar 27 19:24:33 2015 -0700
ralloc: Implement a new ralloc_adopt() API.
ralloc_adopt() reparents all children from one context to another.
Conceptually, ralloc_adopt(new_ctx, old_ctx) behaves like this
pseudocode:
foreach child of old_ctx:
ralloc_steal(new_ctx, child)
However, ralloc provides no way to iterate over a memory context's
children, and ralloc_adopt does this task more efficiently anyway.
One potential use of this is to implement a memory-sweeper pass: first,
steal all of a context's memory to a temporary context. Then, walk over
anything that should be kept, and ralloc_steal it back to the original
context. Finally, free the temporary context. This works when the
context is something that can't be freed (i.e. an important structure).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit ca3b4d6d17a0f95b287e87888c9d893be94f0301
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Apr 2 10:42:12 2015 -0700
nir/opt_peephole_ffma: Fix a couple typos in a comment
Acked-by: Matt Turner <mattst88 at gmail.com>
commit 4609ba6ea3487dd3440596c460062f03526d335c
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Apr 1 16:19:09 2015 -0400
mesa: add ARB_depth_buffer_float to ES3.0 required extension list
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit a9152376b49d8c56debb8023cc6e93d9c071d293
Author: Eric Anholt <eric at anholt.net>
Date: Wed Apr 1 15:19:38 2015 -0700
vc4: Add support for nir_iabs.
Tested using the GLSL 1.30 tests for integer abs(). Not currently used,
but it was one of the new opcodes used by robclark's idiv lowering.
commit e50cf5faa5709eaeea1da8759f13b140b4b3cea1
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Apr 1 16:18:31 2015 -0700
i965/generator: Get rid of the ! in the unreachable statement
Reviewed-by: Mark Janes <mark.a.janes at intel.com>
commit 0573d0e4845803969634c975355bbf55651dde19
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Apr 1 16:16:52 2015 -0700
nir/print: Correctly print swizzles for explicitly sized alu sources
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 4a3c0e995063320693782b934962969e11dab29d
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Feb 15 03:39:43 2015 -0500
freedreno/a3xx: add MRT support
The hardware only supports 4 MRTs. It should be possible to emulate
support for 8, but doesn't seem worth the trouble.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 6f4c1976f4e5ecdebfe5b9ac16b6d13a5e60eed1
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Apr 1 01:14:39 2015 -0400
freedreno: convert blit program to array for each number of rts
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit d9992ab35a51c574dcfa8049859c0887956ecdf6
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Mar 29 20:54:42 2015 -0400
freedreno: add support for laying out MRTs in gmem
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 602bc6c88dbfa34083aa9d229fb6396b008e23eb
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Mar 29 20:39:48 2015 -0400
freedreno: add core infrastructure support for MRTs
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit d13803c76fd7429df64c1aa3631dcc451e7f1a29
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Mar 29 20:24:57 2015 -0400
freedreno/ir3: add support for FS_COLOR0_WRITES_ALL_CBUFS property
This will enable the driver to tell which regids to link up to which
MRT outputs.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit f27ec5908416e6a3ea3d770026cd6a1c6ded188f
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Mar 29 20:04:38 2015 -0400
freedreno/a3xx: add independent blend function support
This is needed for MRT support
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 8efa3e340d13a9f373e7b2834f12d9fae43e6867
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Mar 29 19:59:38 2015 -0400
freedreno: remove alpha key from ir3_shader
This complication is unnecessary and makes MRTs more complicated and
likely to generate tons of variants.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 70eed78cacd711e663068e78a8430372cc5fabf1
Author: Stéphane Marchesin <marcheu at chromium.org>
Date: Wed Apr 1 20:00:08 2015 -0700
i915g: Implement EGL_EXT_image_dma_buf_import
This adds all the plumbing to get EGL_EXT_image_dma_buf_import in
i915g.
Signed-off-by: Stéphane Marchesin <marcheu at chromium.org>
commit a03d0ba78f33e43df2ca7a9e4c58fdc9fbc9876a
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu Mar 26 10:09:54 2015 -0700
i965/fs: Relax type check in cmod propagation.
The thing we want to avoid is int/float comparisons, but int/unsigned
comparisons with 0 are equivalent.
total instructions in shared programs: 6194829 -> 6193996 (-0.01%)
instructions in affected programs: 117192 -> 116359 (-0.71%)
helped: 471
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 781badee7a46c7eb778fb2755d799151d8b748bf
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu Mar 26 10:09:42 2015 -0700
nir: Remove useless ftrunc inside f2i/f2u.
No shader-db changes, probably because they're all removed by the GLSL
compiler optimization added in commit 69ad5fd4.
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 97e6c1b9579573444487d0ac6d9a6b73c067b495
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu Mar 26 10:09:21 2015 -0700
nir: Recognize (a < b || a < c) as a < max(b, c).
Doesn't work for analogous && cases, because of NaNs.
total instructions in shared programs: 6195712 -> 6194829 (-0.01%)
instructions in affected programs: 42000 -> 41117 (-2.10%)
helped: 403
Reviewed-by: Eric Anholt <eric at anholt.net>
commit a2b6e908cfa1b85bc3eed9d31869ec3768b3daa2
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu Mar 26 11:08:01 2015 -0700
nir: Add addition/multiplication identities of exp/log.
instructions in affected programs: 2858 -> 2808 (-1.75%)
helped: 12
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 099c729b4cb6863e8ddbdb9afe7fd7bd53c11ee1
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu Mar 26 10:07:58 2015 -0700
nir: Add identities for the log function.
The rcp(log(x)) pattern affects instruction counts.
instructions in affected programs: 144 -> 138 (-4.17%)
helped: 6
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 8a6ae384b2ae95f047e9d48a5a4c11002ffdd814
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu Mar 26 10:16:24 2015 -0700
nir: Add identities for the exponential function.
No changes in shader-db.
Reviewed-by: Eric Anholt <eric at anholt.net>
commit e26783d4459583790e50e1f59eb2507f618695c6
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu Mar 26 10:36:42 2015 -0700
nir: Recognize another open coded lrp.
total instructions in shared programs: 6195924 -> 6195768 (-0.00%)
instructions in affected programs: 4876 -> 4720 (-3.20%)
helped: 58
HURT: 10
Reviewed-by: Eric Anholt <eric at anholt.net>
commit e82437e14153af212006deee4a6b808091314482
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Mar 25 15:03:52 2015 -0700
nir: Recognize open coded lrp.
total instructions in shared programs: 6197614 -> 6195924 (-0.03%)
instructions in affected programs: 34773 -> 33083 (-4.86%)
helped: 147
HURT: 6
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 25e214db0094306835a03225e1a37164c7c98bf7
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Mar 30 16:09:51 2015 -0700
nir: Use _mesa_flsll(InputsRead) in prog->nir.
InputsRead is a 64-bit bitfield. Using _mesa_fls would silently
truncate off the high bits, claiming inputs 32..56 (VARYING_SLOT_MAX)
were never read.
Using <= here was a hack I threw in at the last minute to fix programs
which happened to use input slot 32. Switch back to using < now that
the underlying problem is fixed.
Fixes crashes in "Euro Truck Simulator 2" when using prog->nir, which
uses input slot 33.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 3d166b313db14523c2e618e0ebf22b83c86d6334
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Mar 30 16:08:26 2015 -0700
mesa: Implement _mesa_flsll().
This is _mesa_fls() for 64-bit values.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 4b38c5c783e8858f362bb1ff6cf651875bd0bbc5
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Mar 30 05:17:56 2015 -0700
nir: In prog->nir, don't wrap dot products with ptn_channel(..., X).
ptn_move_dest and nir_fadd already take care of replicating the last
channel out, so we can just use a scalar and skip splatting it.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 218e45e2f7b2d6c20bbba837f6e5cbe15610771e
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Mar 23 15:58:34 2015 -0700
i965: Use the same nir options for all gens
If we tell NIR to split ffma's, then we don't need seperate options
anymore.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit b9d7454571029ab330f28164fe6869f5e455ca90
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Apr 1 12:37:43 2015 -0700
i965/nir: Run DCE again before going out of SSA
We run lowering and optimization passes that might leave garbage lying
around. This keeps the FS cse from having to clean it up.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 37703040a142da6bc7c458479a70e35118e10e6b
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Mar 23 15:08:31 2015 -0700
i965/nir: Run the ffma peephole after the rest of the optimizations
The idea here is that fusing multiply-add combinations too early can reduce
our ability to perform CSE and value-numbering. Instead, we split ffma
opcodes up-front, hope CSE cleans up, and then fuse after-the-fact.
Unless an algebraic pass does something silly where it inserts something
between the multiply and the add, splitting and re-fusing should never
cause a problem. We run the late algebraic optimizations after this so
that things like compare-with-zero don't hurt our ability to fuse things.
shader-db results for fragment shaders on Haswell:
total instructions in shared programs: 4390538 -> 4379236 (-0.26%)
instructions in affected programs: 989359 -> 978057 (-1.14%)
helped: 5308
HURT: 97
GAINED: 78
LOST: 5
This does, unfortunately, cause some substantial hurt to a shader in Kerbal
Space Program. However, the damage is caused by changing a single
instruction from a ffma to an add. This, in turn, *decreases* register
pressure in one part of the program causing it to fail to register allocate
and spill. Given the overwhelmingly positive results in other shaders and
the fact that the NIR for the Kerbal shaders is actually better, this
should be considered a positive.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 7f344721b1a94a6166b53f959ff6b159af3b5f9a
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Mar 23 14:55:20 2015 -0700
nir/peephole_ffma: Be less agressive about fusing multiply-adds
shader-db results for fragment shaders on Haswell:
total instructions in shared programs: 4395688 -> 4389623 (-0.14%)
instructions in affected programs: 355876 -> 349811 (-1.70%)
helped: 1455
HURT: 14
GAINED: 5
LOST: 0
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit a8c8b3b8720bb7ce8ac1cb94815ed36d8c881f66
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Sat Mar 21 12:21:21 2015 -0700
nir: Add a dedicated ffma peephole optimization
i965/nir: Use the dedicated ffma peephole
total instructions in shared programs: 4418748 -> 4394618 (-0.55%)
instructions in affected programs: 1292790 -> 1268660 (-1.87%)
helped: 5999
HURT: 457
GAINED: 4
LOST: 9
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit e06a3d0282ef018ae4a28b091a632c6a2e8c7c52
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Mar 23 17:36:22 2015 -0700
nir: Move the compare-with-zero optimizations to the late section
total instructions in shared programs: 4422307 -> 4422363 (0.00%)
instructions in affected programs: 4230 -> 4286 (1.32%)
helped: 0
HURT: 12
While this does hurt some things, the losses are minor and it prevents the
compare-with-zero optimization from fighting with ffma which is much more
important.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit da294f9b2f666f487001b2a25627c867c40eb3d9
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Mar 23 17:11:49 2015 -0700
nir/algebraic: Add a seperate section for "late" optimizations
i965/nir: Use the late optimizations
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 1779dc060fa8d55d979f887e41f1ec2c793859b7
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Apr 1 12:24:37 2015 -0700
nir/algebraic: Remove a duplicate optimization
This optimization is repeated verbatim above
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 22ee7eeb4e08ffdd8d53aa68e4d2b2c09f1721d0
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Mar 23 17:22:44 2015 -0700
nir/algebraic: #define around structure definitions
Previously, we couldn't generate two algebraic passes in the same file
because of multiple structure definitions. To solve this, we play the
age-old header file trick and just #define around it.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 793a94d6b5fc589ca8d7475347def4e222cd3d7c
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Mar 23 18:20:21 2015 -0700
nir/print: Don't print extra swizzzle components
Previously, NIR would just print 4 swizzle components if the swizzle was
anything other than foo.xyzw. This creates lots of noise if, for example,
you have a one-component element with a swizzle of foo.xxxx.
Reviewed-by: Kenneth Grunke <kenneth at whitecape.org>
commit d99135b2e9b7599ee57ac90952c605b725239908
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Apr 1 15:51:59 2015 +0100
configure: nuke --with-max-{width,height}
Unused as of commit 630ab0d27ba(mesa: remove last of MAX_WIDTH,
MAX_HEIGHT). Update all the remaining references to the defines.
v2: Use the correct variable name in the comments
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit bd4925c6ac468e80f6106f3d684119498b606a0d
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Apr 1 19:09:00 2015 +0000
gallium: ship tgsi_to_nir.h in the tarball
Acked-by: Matt Turner <mattst88 at gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 4008975e6f4b2e15fceed4f07d8ec763dd0949d1
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Mar 23 17:49:24 2015 +0000
configure.ac: error out if python/mako is not found when required
In case of using a distribution tarball (or a dirty git tree) one can
have the generated sources locally. Make configure.ac error out
otherwise, to alert that about the unmet requirement(s) of python/mako.
v2: Check only for a single file for each dependency.
Suggested-by: Matt Turner <mattst88 at gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 3384179faab0456f93f4a5c62ce05305ff20fe5c
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Apr 1 10:24:26 2015 -0700
glsl: Make sure not to dereference NULL.
Found by Coverity.
commit 142909f19ddeae7237acbb98b47e9228533e58f0
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Wed Apr 1 11:18:32 2015 -0700
main: create_buffers unlocks mutex when throwing OUT_OF_MEMORY.
Ilia Mirkin found that I had forgotten to free the mutex in the error case.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 3321724c10e2c9c5cd8f84bafb26678c6d1108b5
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Wed Apr 1 19:49:09 2015 +0100
automake,scons: Put NIR source files in a separate var to fix SCons build.
SCons does not build NIR yet.
Trivial.
commit 7f0682cebf8b100922d45a423df1e2fbd036bc3e
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Wed Apr 1 19:48:09 2015 +0100
automake: Fix out-of-source builds.
Add include path for generated nir_opcodes.h.
Trivial.
commit 1625d7a87ae66eb50653d9194e8f9e67b6957c05
Author: Brian Paul <brianp at vmware.com>
Date: Wed Apr 1 10:31:26 2015 -0600
mesa: don't include colormac.h in format code
Acked-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Mark Janes <mark.a.janes at intel.com>
commit 2768a0b1b42f3c1531ab9c3647a93f0504002280
Author: Brian Paul <brianp at vmware.com>
Date: Wed Apr 1 09:45:57 2015 -0600
mesa: remove unneeded #include of colormac.h
Acked-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Mark Janes <mark.a.janes at intel.com>
commit f1d55017d7cb0e8fd9314ca29849304eb067960f
Author: Brian Paul <brianp at vmware.com>
Date: Wed Apr 1 09:45:38 2015 -0600
tnl: remove unneeded #include of colormac.h
Acked-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Mark Janes <mark.a.janes at intel.com>
commit 8ac9407a835ee892d96f326b0c56967046cbb982
Author: Brian Paul <brianp at vmware.com>
Date: Wed Apr 1 09:45:31 2015 -0600
swrast: remove unneeded #include of colormac.h
Acked-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Mark Janes <mark.a.janes at intel.com>
commit 2ad8af1a0c319c83e4a8e00db3a9b9cb0ae029eb
Author: Brian Paul <brianp at vmware.com>
Date: Wed Apr 1 09:45:12 2015 -0600
mesa: remove unused macros from colormac.h
Acked-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Mark Janes <mark.a.janes at intel.com>
commit 15b03b7964fc2c3c52e9f384815b76957f557878
Author: Eric Anholt <eric at anholt.net>
Date: Sun Mar 29 23:04:21 2015 -0700
nir: Recognize a pattern of bool frobbing from TGSI KILL_IF.
TGSI's conditional discards take float arg and negate it, so GLSL to TGSI
generates a b2f and negates that value. Only, in NIR we want a proper
bool once again, so we compare with 0. This is a lot of pointless extra
instructions.
total instructions in shared programs: 39735 -> 39702 (-0.08%)
instructions in affected programs: 1342 -> 1309 (-2.46%)
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 6e8d4a2f8043a3a7a28175326e63770aa9511ee7
Author: Eric Anholt <eric at anholt.net>
Date: Sun Mar 29 22:59:39 2015 -0700
nir: Recognize a pattern for doing b2f without the opcode.
Since we have patterns based on b2f, generate them if we see the b2f
equivalent using an iand. This is common when generating NIR from TGSI.
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 26261bca2137eb1ca57e53f4efb95bcb3f1419df
Author: Eric Anholt <eric at anholt.net>
Date: Fri Feb 20 00:31:51 2015 -0800
vc4: Add shader-db dumping of NIR instruction count.
I was previously using temporary disables of VC4 optimization to show the
benefits of improved NIR optimization, but this can get me quick and dirty
numbers for NIR-only improvements without having to add hacks to disable
VC4's code (disabling of which might hide ways that the NIR changes would
hurt actual VC4 codegen).
commit 73e2d4837d7e4611f31532ab0ccc14369341e0cb
Author: Eric Anholt <eric at anholt.net>
Date: Thu Oct 30 12:51:47 2014 -0700
vc4: Convert to consuming NIR.
NIR brings us better optimization than I would have bothered to write
within the driver, developers sharing future optimization work, and the
ability to share device-specific lowering code that we and other
GLES2-level drivers need.
total uniforms in shared programs: 13421 -> 13422 (0.01%)
uniforms in affected programs: 62 -> 63 (1.61%)
total instructions in shared programs: 39961 -> 39707 (-0.64%)
instructions in affected programs: 15494 -> 15240 (-1.64%)
v2: Add missing imov support, and assert that there are no dest saturates.
v3: Rebase on the target-specific algebraic series.
v4: Rebase on gallium-includes-from-NIR changes in mater.
v5: Rebase on variables being in lists instead of hash tables.
v6: Squash in intermediate changes that used the NIR-to-TGSI pass (which
I'm not committing)
commit 783ad697d25e754ab719ab6c715969c35dbe867b
Author: Eric Anholt <eric at anholt.net>
Date: Wed Oct 29 14:32:16 2014 -0700
gallium: Add tgsi_to_nir to get a nir_shader for a TGSI shader.
This will be used by the VC4 driver for doing device-independent
optimization, and hopefully eventually replacing its whole IR. It also
may be useful to other drivers for the same reason.
v2: Add all of the instructions I was relying on tgsi_lowering to remove,
and more.
v3: Rebase on SSA rework of the builder.
v4: Use the NIR ineg operation instead of doing a src modifier.
v5: Don't use ineg for fnegs. (infer_src_type on MOV doesn't do what I
expect, again).
v6: Fix handling of multi-channel KILL_IF sources.
v7: Make ttn_get_f() return a swizzle of a scalar load_const, rather than
a vector load_const. CSE doesn't recognize that srcs out of those
channels are actually all the same.
v8: Rebase on nir_builder auto-sizing, make the scalar arguments to
non-ALU instructions actually be scalars.
v9: Add support for if/loop instructions, additional texture targets, and
untested support for indirect addressing on temps.
v10: Rebase on master, drop bad comment about control flow and just choose
the X channel, use int comparison opcodes in LIT for now, drop unused
pipe_context argument..
v11: Fix translation of LRP (previously missed because I mis-translated
back out), use nir_builder init helpers.
v12: Rebase on master, adding explicit include of mtypes.h to get
INTERP_QUALIFIER_*
v13: Rebase on variables being in lists instead of hash tables, drop use
of mtypes.h in favor of util/pipeline.h. Use Ken's nir_builder
swizzle and fmov/imov_alu helpers, drop "struct" in front of
nir_builder, use nir_builder directly as the function arg in a lot of
cases, drop redundant members of ttn_compile that are also in
nir_builder, drop some half-baked malloc failure handling.
v14: The indirect uniform src0 should be scalar, not vector (noticed as
odd by robclark, confirmed by cwabbott). Apply Ken's review to
initialize s->num_uniforms and friends, skip ttn_channel for dot
products, and use the simpler discard_if intrinsic.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org> (v13)
Acked-by: Rob Clark <robclark at freedesktop.org>
commit 486dcfbbd955e01ff1d254cc533c3cc4692ad54b
Author: Eric Anholt <eric at anholt.net>
Date: Tue Mar 31 11:39:45 2015 -0700
vc4: Tell shader-db how big our UBOs are, if present.
I had regressed them for a while with the NIR work.
commit a3a07d46d1a8e89136669dd4bb242c7bd5d10015
Author: Eric Anholt <eric at anholt.net>
Date: Wed Mar 25 12:58:51 2015 -0700
mesa: Make a shared header for 3D pipeline enum / #defines.
NIR uses these enums/#defines in nir_variables and associated intrinsics,
but I want to be able to use them from TGSI->NIR and NIR->TGSI.
Otherwise, we had to pull in all of mtypes.h.
This doesn't cover all of the enums we might want from a shared compiler
core (like varying slots or vert attribs), but it at least covers what I
need at the moment (system values and interp qualifiers).
v2: Move to src/glsl since util/ is really vague. Include in Makefile.am
list. Use plain bitshifts and stdint types instead of undefined
BITFIELD64_BIT.
v3: Rename to shader_enums.h. Move it into Makefile.sources.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org> (v2, with
recommendation to rename)
commit 5604d7675ed40227df9fc6a500eb4f0d2421f4ca
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Tue Mar 31 10:54:34 2015 +0100
nir: add nir_builder.h to the tarball
The header was added with commit 2a135c470e3(nir: Add an ALU op builder
kind of like ir_builder.h) but did not made it into to the sources list.
Fortunately it remained unused until a recent commit faf6106c6f6(nir:
Implement a Mesa IR -> NIR translator.)
v2: Remove the bogus dependency. Tweak commit message.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 4984cb7ef866572c56981dab3e10b0ad62dc9782
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sun Mar 29 13:46:32 2015 +0100
xmlpool: remove the clean target
... by folding it into CLEANFILES. Don't worry about $(LANG) as it is
essentially the first folder of $(POS). With the latter already handled.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit a665b9b3c89095923cf2251895afc69c9f79aafe
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sun Mar 29 13:46:31 2015 +0100
xmlpool: don't forget to ship the MOS
This will allow us to finally remove python from the build time
dependencies list. Considering that you're building from a release
tarball of course :-)
Cc: Bernd Kuhls <bernd.kuhls at t-online.de>
Reported-by: Bernd Kuhls <bernd.kuhls at t-online.de>
Cc: "10.5" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit c07df0f2014636b601cdbaff63214296599b1ad5
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sun Mar 29 00:56:09 2015 +0000
osmesa: don't try to bundle osmesa.def SConscript
Both of which were removed with commit 69db422218b(scons: Don't build
osmesa.)
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 1d36c52f5db1e7ed651d6cea24fe87e80c7c1565
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Mar 25 20:12:02 2015 +0000
docs: note that classic osmesa/libEGL no longer builds with scons
Plus nuke the final reference to osmesa from README.WIN32.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 3818dfcf3c2d03809774bba613d7dd92752b36db
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Tue Mar 17 10:48:04 2015 +0100
i965: Handle scratch accesses where reladdr also points to scratch space
This is a problem when we have IR like this:
(array_ref (var_ref temps) (swiz x (expression ivec4 bitcast_f2i
(swiz xxxx (array_ref (var_ref temps) (constant int (2)) ) )) )) ) )
where we are indexing an array with the result of an expression that
accesses the same array.
In this scenario, temps will be moved to scratch space and we will need
to add scratch reads/writes for all accesses to temps, however, the
current implementation does not consider the case where a reladdr pointer
(obtained by indexing into temps trough a expression) points to a register
that is also stored in scratch space (as in this case, where the expression
used to index temps access temps[2]), and thus, requires a scratch read
before it is accessed.
v2 (Francisco Jerez):
- Handle also recursive reladdr addressing.
- Do not memcpy dst_reg into src_reg when rewriting reladdr.
v3 (Francisco Jerez):
- Reduce complexity by moving recursive reladdr scratch access handling
to a separate recursive function.
- Do not skip demoting reladdr index registers to scratch space if the
top level GRF has already been visited.
v4 (Francisco Jerez)
- Remove redundant checks.
- Simplify code by making emit_resolve_reladdr return a register with
the original src data except for reg, reg_offset and reladdr.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89508
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit e3252defd2eabb6bcc8eb14f16d534e964fd8884
Author: Roland Scheidegger <sroland at vmware.com>
Date: Wed Apr 1 13:25:56 2015 +0200
gallivm: (trivial) fix the logic deciding if function call should be used...
Copy and paste bug with the img filter decision. Since there's only 2 different
filters anyway just drop this bit.
commit 59af7ed28cd1b44b525a7d6a324c4e00092104b6
Author: Martin Peres <martin.peres at linux.intel.com>
Date: Mon Mar 30 10:34:20 2015 +0300
mesa/fbo: lock ctx->Shared->Mutex when allocating renderbuffers
This mutex is used to make sure the shared context does not change
while some shared code is looking into it.
Calling BindRenderbufferEXT BindRenderbuffer with a gles context
would not take the mutex before allocating an entry. Commit a34669b
then moved out the allocation out of bind_renderbuffer into
allocate_renderbuffer before using it for the CreateRenderBuffer
entry point. This thus also made this entry point unsafe.
The issue has been hinted by Ilia Mirkin.
Reviewed-by: Brian Paul <brianp at vmware.com>
Signed-off-by: Martin Peres <martin.peres at linux.intel.com>
commit fa3832155100850da8346faa64c3cb30c4e86e39
Author: Martin Peres <martin.peres at linux.intel.com>
Date: Wed Mar 25 16:28:03 2015 +0200
mesa/fbo: do not assign a value that is never read later on
The issue has been detected by coverty.
v2:
- move the declaration of obj to the else clause (Brian Paul)
v3: Review by Brian Paul
- get rid of the obj declaration in favor of a direct reference
Reviewed-by: Brian Paul <brianp at vmware.com>
Signed-off-by: Martin Peres <martin.peres at linux.intel.com>
commit 8f7338f284cdb1fef64c85e3293d2200d0cc6387
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Mar 3 13:57:16 2014 +1000
egl: add initial EGL_MESA_image_dma_buf_export v2.4
At the moment to get an EGL image to a dma-buf file descriptor,
you have to use EGL_MESA_drm_image, and then use libdrm to
convert this to a file descriptor.
This extension just provides an API modelled on EGL_MESA_drm_image,
to return a dma-buf file descriptor.
v2: update spec for new API proposal
add internal queries to get the fourcc back from intel driver.
v2.1: add gallium pieces.
v2.2: add offsets to spec and API, rename fd->fds, stride->strides
in API. rewrite spec a bit more, add some q/a
v2.3:
add modifiers to query interface and 64-bit type for that (Daniel Stone)
specifiy what happens to num fds vs num planes differences. (Chad Versace)
v2.4:
fix grammar (Daniel Stone)
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 22ccdf12dd7b5db6eb0c8f2b03c3516f8376fdad
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Fri Mar 20 00:46:03 2015 -0700
i965/state: Remove brw->state.dirty
We now use brw->NewGLState and brw->ctx.NewDriverState instead.
Suggested-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 7ecf3530d87e88971fd77d35ac23c5383630d35b
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Thu Mar 19 22:33:16 2015 -0700
i965/state: Don't use brw->state.dirty.mesa
Now, we only use brw->NewGLState.
I used this bash & sed command in the i965 directory:
for file in *.[ch] *.[ch]pp; do
sed -i -e 's/brw->state\.dirty\.mesa/brw->NewGLState/g' $file
done
Followed by manual changes to brw_state_upload.c.
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 4e56a9ad46ff7fe85308ce12e21719ff2b476516
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Thu Mar 19 18:57:34 2015 -0700
i965/state: Don't use brw->state.dirty.brw
Now, we only use ctx->NewDriverState.
I used this bash & sed command in the i965 directory:
for file in *.[ch] *.[ch]pp; do
sed -i -e 's/state\.dirty\.brw/ctx.NewDriverState/g' $file
done
Followed by manual changes to brw_state_upload.c.
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 20ef23b22721961c93b73700f619179d33747554
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Sun Mar 8 00:08:18 2015 -0800
i965/state: Add compute pipeline with empty atom lists
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit a8e39e19032d077a4adf7e451c608f3f139a05e2
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Fri Mar 20 12:36:21 2015 -0700
i965/state: Only upload render programs for render state uploads
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit d70f4e6daf4a548eb6debaa2a1646fea21e5fbf3
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Sat Mar 7 23:21:46 2015 -0800
i965/state: Create separate dirty state bits for each pipeline
When clearing the state for a pipeline, we will save changed state for
the other pipelines.
v3:
* Adjust brw_upload_pipeline_state
* Don't pull pipeline state bits into common state bits
* Don't clear pipeline state bits
* Adjust 'clear' phase
* brw_clear_dirty_bits is now brw_render_state_finished
* Move cross-pipeline state flagging to brw_pipeline_state_finished
* Move pipeline clears to brw_pipeline_state_finished
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit db119550725d438c928c50382a2a675b37c24a66
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Sat Mar 7 22:44:39 2015 -0800
i965/state: Support multiple pipelines in brw->num_atoms
brw->num_atoms is converted to an array, but currently just an array
of length 1.
Adds brw_copy_pipeline_atoms which copies the atoms for a pipeline,
and sets brw->num_atoms[p] for pipeline p.
v2:
* Rename brw->atoms[] to render_atoms
* Rename brw_add_pipeline_atoms to brw_copy_pipeline_atoms
* Rename brw_pipeline_first_atom to brw_get_pipeline_atoms
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 736a31d46252187a04a7b5c0119e3ba9be2418cb
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Wed Mar 18 15:43:34 2015 -0700
i965/state: Rename brw_clear_dirty_bits to brw_render_state_finished
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 2c02baa4870cf08592ac64a576fd6a73262892fb
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Sat Mar 7 20:20:03 2015 -0800
i965/state: Rename brw_upload_state to brw_upload_render_state
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 611bd80f3b4972622a9f2c155c95d3241668e4d9
Author: Roland Scheidegger <sroland at vmware.com>
Date: Wed Apr 1 00:56:12 2015 +0200
gallivm: do some hack heuristic to disable texture functions
We've seen some cases where performance can hurt quite a bit.
Technically, the more simple the function the more overhead there is
for using a function for this (and the less benefits this provides).
Hence don't do this if we expect the generated code to be simple.
There's an even more important reason why this hurts performance,
which is shaders reusing the same unit with some of the same inputs,
as llvm cannot figure out the calculations are the same if they
are performned in the function (even just reusing the same unit without
any input being the same provides such optimization opportunities though
not very much). This is something which would need to be handled by IPO
passes however.
commit 47c4b3854076adfe5a27b537f36262ac4ec4530d
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Jan 27 19:18:46 2015 -0800
i965/fs: Allow CSE to handle MULs with negated arguments.
mul x, -y is equivalent to mul -x, y; and mul x, y is the negation of
mul x, -y.
With NIR:
total instructions in shared programs: 6167779 -> 6161193 (-0.11%)
instructions in affected programs: 983511 -> 976925 (-0.67%)
helped: 4106
HURT: 16
GAINED: 18
LOST: 7
Without NIR:
total instructions in shared programs: 6192323 -> 6185299 (-0.11%)
instructions in affected programs: 987875 -> 980851 (-0.71%)
helped: 4146
HURT: 16
GAINED: 16
LOST: 0
commit 438c1c0080a00b073706a8708c5fd79dc42a7a15
Author: Matt Turner <mattst88 at gmail.com>
Date: Sat Mar 28 11:01:29 2015 -0700
i965: Mark brw_inst_bits' brw_inst* parameter const.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit ac6102bcc5dc85bf5bd1e25e0d94a91441673681
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Mar 31 14:06:56 2015 -0700
glsl: Remove bogus Makefile dependency.
commit 2c38f891ad82881cd3cc6e4323bfca7bdb13d13a
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Mar 27 17:13:51 2015 -0700
glsl: Reassociate multiplication of mat*mat*vec.
The typical case of mat4*mat4*vec4 is 80 scalar multiplications, but
mat4*(mat4*vec4) is only 32.
On HSW (with vec4 vertex shaders):
instructions in affected programs: 4420 -> 3194 (-27.74%)
On BDW (with scalar vertex shaders):
instructions in affected programs: 12756 -> 6726 (-47.27%)
Implementing a general matrix chain ordering is harder (or at least
tedious) because of having to walk the GLSL IR to create a list of
multiplicands. I'm guessing that this patch handles 90+% of cases, but
of course to tell definitively you'd have to implement the general
thing.
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit cf2dc1624fe711ad0aa89322a1142eae46bbfc30
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Mar 27 10:45:07 2015 -0700
glsl: Implement type inferencing of matrix types.
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit 73f6f9b9be1aedf85cfe15b87e3c543e5cc399d2
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Mar 27 10:43:05 2015 -0700
glsl: Factor out a get_mul_type() function.
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit f9e2295560f9b4869fa2a94933c1881ec7970af4
Author: Marcin Åšlusarz <marcin.slusarz at gmail.com>
Date: Tue Mar 31 22:04:31 2015 +0200
nouveau: synchronize "scratch runout" destruction with the command stream
When nvc0_push_vbo calls nouveau_scratch_done it does not mean
scratch buffers can be freed immediately. It means "when hardware
advances to this place in the command stream the scratch buffers
can be freed".
To fix it, just postpone scratch runout destruction after current
fence is signalled.
The bug existed for a very long time. Nobody noticed, because
"scratch runout" code path is rarely executed.
Fixes hang at the very beginning of first mission in "Serious Sam 3"
on nve7/gk107. It manifested as:
nouveau E[ PFIFO][0000:01:00.0] read fault at 0x000a9e0000 [PTE] from GR/GPC0/PE_2 on channel 0x007f853000 [Sam3[17056]]
Cc: "10.4 10.5" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 3db0317351e02be4498c7833262ac919d597b396
Author: Brian Paul <brianp at vmware.com>
Date: Tue Mar 31 11:30:32 2015 -0600
docs: document Viewperf 12 issues
Signed-off-by: Brian Paul <brianp at vmware.com>
commit fe026d7ce5c59535c5296004b94138bdf8ef613c
Author: Neil Roberts <neil at linux.intel.com>
Date: Tue Mar 31 14:58:28 2015 +0100
i965/skl: Avoid using the 1D stencil layout for stencil-only images
Commit cf67ca9ffa9 made the layouting code pick a special layout for
1D images on Skylake. This should not be used for depth and stencil
buffers because these need to be treated as 2D tiled images. However
the patch was missing a check for images with a base format of
GL_STENCIL_INDEX. In practice I don't think it's currently possible to
hit this because Mesa doesn't support GL_ARB_texture_stencil8 and it's
not possible to create a 1D renderbuffer, but it'll be good to be
ready for when the extension is supported.
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit fda7558057a301a5a0ee1cb4d68f09ea39b03bb3
Author: Tom Stellard <thomas.stellard at amd.com>
Date: Tue Mar 24 17:17:22 2015 +0000
clover: Return CL_BUILD_ERROR for CL_PROGRAM_BUILD_STATUS when compilation fails v2
v2:
- Don't use _errs map
Cc: 10.5 10.4 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 4c53d2acbb8b6fa48e91d7edaa81d95e19c2c40d
Author: Tom Stellard <thomas.stellard at amd.com>
Date: Sat Mar 21 00:27:16 2015 +0000
radeonsi/compute: Default to the same PIPE_SHADER_CAP values as other shader types v2
v2:
- Fix typo
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit a714fbacf7bc5dcbc316bbfcb6bd9cb38fb4f858
Author: Leo Liu <leo.liu at amd.com>
Date: Mon Mar 30 13:33:19 2015 -0400
radeon/vce: implement video usability information support
This will help encoding VUI into the bitstream
v2: make backward compatible
Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
commit 8e3668a7c0c725285d1d23cf5f2bc32c69114650
Author: Leo Liu <leo.liu at amd.com>
Date: Mon Mar 30 13:25:15 2015 -0400
st/omx/enc: export framerate to vce driver
The framerate will be used for video usability info support by VCE driver
Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
commit 489866938f8bf85625f0f452006a3422a2585950
Author: Roland Scheidegger <sroland at vmware.com>
Date: Tue Mar 31 17:23:17 2015 +0200
llvmpipe: enable ARB_texture_gather
Just announce support for 4 components.
While here also increase the max/min texel offsets (the limit is completely
artificial, was chosen because that's what other hardware did, however there's
other drivers using larger limits).
Over a thousand little piglits skip->pass.
v2: update docs/GL3.txt
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 0753b135f6e83b171d8a1b08aea967374f3542bc
Author: Roland Scheidegger <sroland at vmware.com>
Date: Sun Mar 29 23:40:31 2015 +0200
gallivm: implement TG4 for ARB_texture_gather
This is quite trivial, essentially just follow all the same code you'd
use with linear min/mag (and no mip) filter, then just skip the filtering
after looking up the texels in favor of direct assignment of the right channel
to the result. (This is though not true for the multi-offset version if we'd
want to support it - for this would probably need to do something along the
lines of 4x nearest sampling due to the necessity of doing coord wrapping
individually per texel.)
Supports multi-channel formats.
From the SM5 gather cap bit, should support non-constant offsets, plus shadow
comparisons (the former untested), but not component selection (should be
easy to implement but all this stuff is not really exposable anyway for now).
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 73c6914195bd3cc81f52192d4ec8e23fc6239c41
Author: Roland Scheidegger <sroland at vmware.com>
Date: Sun Mar 29 23:21:56 2015 +0200
gallivm: add gather support to sampler interface
Luckily thanks to the revamped interface this is a lot less work now...
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 1863ed21ffbb3ab7fd9875dc25e32ececea79d50
Author: Roland Scheidegger <sroland at vmware.com>
Date: Sat Mar 28 20:51:23 2015 +0100
gallivm: simplify sampler interface
This has got a bit out of control with more and more parameters added.
Worse, whenever something in there changes all callees have to be updated
for that, even though they don't really do much with any parameter in there
except pass it on to the actual sampling function.
Hence simply put almost everything into a struct. Also instead of relying
on some arguments being NULL, be explicit and set this in a key (which is
just reused for function generation for simplicity). (The code still relies
on them being NULL in the end for now.)
Technically there is a minimal functional change here for shadow sampling:
if shadow sampling is done is now determined explicitly by the texture
function (either sample_c or the gl-style tex func inherit this from target)
instead of the static texture state. These two should always match, however.
Otherwise, it should generate all the same code.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 0fc5b80e7abae061dd5b0a17a0e775619a5245be
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Wed Mar 18 22:06:44 2015 +0000
util/debug: Update MgwHelp link, drop BfdHelp link.
commit b8797a78752daf9e1d4c06d5555a81efea4bb85a
Author: Michel Dänzer <michel.daenzer at amd.com>
Date: Tue Mar 31 15:05:01 2015 +0900
gallivm: Fix build against LLVM 3.7 SVN r233648
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 1dcc1ee314a6907213e2abd5337ec0bbba3bd1bf
Author: Eric Anholt <eric at anholt.net>
Date: Mon Mar 30 10:44:28 2015 -0700
vc4: Drop integer multiplies with 0 to moves of 0.
This cleans up more instructions generated by uniform array indexing
multiplies.
total instructions in shared programs: 39989 -> 39961 (-0.07%)
instructions in affected programs: 896 -> 868 (-3.12%)
commit 8c5dcdbccb68b73d2856d9c1faafadc536e682e3
Author: Eric Anholt <eric at anholt.net>
Date: Mon Mar 30 10:38:21 2015 -0700
vc4: Add a constant folding pass.
This cleans up some pointless operations generated by the in-driver mul24
lowering (commonly generated by making a vec4 index for a matrix in a
uniform array).
I could fill in other operations, but pretty much anything else ought to
be getting handled at the NIR level, I think.
total uniforms in shared programs: 13423 -> 13421 (-0.01%)
uniforms in affected programs: 346 -> 344 (-0.58%)
commit dbe67d76e0487b04a7b6081d9d46666db3c3ee3e
Author: Brian Paul <brianp at vmware.com>
Date: Fri Mar 27 10:54:10 2015 -0600
glsl: allow ForceGLSLVersion to override #version directives
Previously, the ctx->Const.ForceGLSLVersion setting only worked if
the shader lacked a #version directive. Now, the ForceGLSLVersion
setting will override the #version directive too.
This change should be safe since it should be rare to have an app
that has a mix of shader versions and we only wanted to override
the #version for shaders which lacked the #version directive.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit c519c4d85e7b4f9cad4e51dc08e8ae99bf3c810d
Author: Eric Anholt <eric at anholt.net>
Date: Sun Mar 29 21:26:16 2015 -0700
vc4: Don't bother masking out the low 24 bits for integer multiplies
The hardware just uses the low 24 lines, saving us an AND to drop the high
bits.
total uniforms in shared programs: 13433 -> 13423 (-0.07%)
uniforms in affected programs: 356 -> 346 (-2.81%)
total instructions in shared programs: 40003 -> 39989 (-0.03%)
instructions in affected programs: 910 -> 896 (-1.54%)
commit 5df8bf86fe40ae95ad3888cb167ce80c710af227
Author: Eric Anholt <eric at anholt.net>
Date: Sun Mar 29 21:21:10 2015 -0700
vc4: Make integer multiply use 24 bits for the low parts.
The hardware uses the low 24 bits in integer multiplies, so we can have
fewer high bits (and so probably drop them more frequently).
commit 18004c338f6be8af2e36d2f54972c60136229aeb
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Fri Nov 28 11:23:20 2014 +0100
glsl: fail when a shader's input var has not an equivalent out var in previous
GLSL ES 3.00 spec, 4.3.10 (Linking of Vertex Outputs and Fragment Inputs),
page 45 says the following:
"The type of vertex outputs and fragment input with the same name must match,
otherwise the link command will fail. The precision does not need to match.
Only those fragment inputs statically used (i.e. read) in the fragment shader
must be declared as outputs in the vertex shader; declaring superfluous vertex
shader outputs is permissible."
[...]
"The term static use means that after preprocessing the shader includes at
least one statement that accesses the input or output, even if that statement
is never actually executed."
And it includes a table with all the possibilities.
Similar table or content is present in other GLSL specs: GLSL 4.40, GLSL 1.50,
etc but for more stages (vertex and geometry shaders, etc).
This patch detects that case and returns a link error. It fixes the following
dEQP test:
dEQP-GLES3.functional.shaders.linkage.varying.rules.illegal_usage_1
However, it adds a new regression in piglit because the test hasn't a
vertex shader and it checks the link status.
bin/glslparsertest \
tests/spec/glsl-1.50/compiler/gs-also-uses-smooth-flat-noperspective.geom pass \
1.50 --check-link
This piglit test is wrong according to the spec wording above, so if this patch
is merged it should be updated.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit d64adc3a79e419062432cfa8d1cbc437676a3fbd
Author: Michel Dänzer <michel.daenzer at amd.com>
Date: Thu Mar 26 11:32:59 2015 +0900
radeonsi: Cache LLVMTargetMachineRef in context instead of in screen
Fixes a crash in genymotion with several threads compiling shaders
concurrently.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89746
Cc: 10.5 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
commit ce83a6ec8142894531cfad8cd677cd3dc47eced7
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Mon Mar 30 07:59:53 2015 +0300
glsl: fix unreachable(!"") to unreachable("")
Correct error with commit 151fb1e where assert was renamed
to unreachable without removing ! from string argument.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 938b17940fe0f9823665c1450c1254936651e9d9
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Mar 28 19:01:15 2015 +0000
docs: add news item and link release notes for mesa 10.5.2
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit dc8d8a29515cc7dc96b9c0820e31de0bbe20ed38
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Mar 28 18:50:31 2015 +0000
docs: Add sha256 sums for the 10.5.2 release
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit ff87ae1e003be7104d3550250af3343c01cea882)
commit 6e19f6b4d0073ff863bb76cffd9e4dd637e3b628
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Mar 28 18:42:51 2015 +0000
Add release notes for the 10.5.2 release
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit 5e59f895c468c1ac497ad925b8bddd7f227c89a2)
commit ee670c9efa471aa78563b14f47bcd89220b608dc
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Tue Mar 17 01:34:33 2015 -0400
freedreno/a3xx: add support for point sprite coordinate replacement
This does not (yet) support different coordinate origins, so the tests
still fail due to fbo flipping.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 995f55a6cedfd47a2aed75178a1b0caed7059f20
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Tue Mar 17 01:02:32 2015 -0400
freedreno/a3xx: make vs-set point size work
This appears to need the A2XX version of the point list, so select it at
draw time if necessary.
Experimentally, always using the A2XX version causes hangs when PSIZE
isn't actually emitted.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 7fc5da8b9392042b5f8a989d2afa49ea1944f9a9
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Tue Mar 17 01:00:38 2015 -0400
freedreno/a3xx: point size should not be divided by 2
The division is probably a holdover from the days when the fixed point
inline functions generated by headergen were broken.
Also reduce the maximum point size to 4092 (vs 4096), which is what the
blob does.
Cc: "10.4 10.5" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 738c8319ac85b175994b35d1fdc4860e18184b93
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Mar 15 16:38:42 2015 -0400
freedreno/a3xx: fix 3d texture layout
The SZ2 field contains the layer size of a lower miplevel. It only
contains 4 bits, which limits the maximum layer size it can describe. In
situations where the next miplevel would be too big, the hardware
appears to keep minifying the size until it hits one of that size.
Unfortunately the hardware's ideas about sizes can differ from
freedreno's which can still lead to issues. Minimize those by stopping
to minify as soon as possible.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.4 10.5" <mesa-stable at lists.freedesktop.org>
commit 3735643df3fc29d7ce84b2156c53f23a3092765c
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Mar 13 18:01:11 2015 -0400
freedreno/a3xx: LAYERSZ2 appears to have no effect on arrays
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 72b06fb08e40907cdf94d4f390f53f42240a4345
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Mar 27 18:22:20 2015 -0700
nir: Fix copy and pasted error message in nir_validate.
These are nir_cf_nodes, not ALU instructions.
Also, use unreachable() to preempt said review feedback.
v2: Do it right (thanks Ilia).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 31dc63d5ca090fed3f1adcd4fd0db2f1f7aa19f7
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Mar 25 15:16:30 2015 -0700
i965/nir: Use NIR for ARB_vertex_program support on Gen8+.
Everything is already in place; we simply have to take the scalar code
generation path. This gives us SIMD8 VS programs, instead of SIMD4x2.
v2: Rebase on the patch that drops brw->gen >= 8.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit ac69ab7302dffa1350c64a9c69abd7721d0f0127
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Mar 27 13:48:44 2015 -0700
i965: Move env_var_as_boolean to intel_debug.c.
I need to use this in brw_vec4.cpp, so it can't be static anymore.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 826d3afb8f421a62020308813397e541e672381e
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Jan 30 01:16:49 2015 -0800
i965/fs: Add ARB_fragment_program support to the NIR backend.
Use prog_to_nir where we would normally call glsl_to_nir, handle program
parameter lists, and skip a few things that don't exist.
Using NIR generates much better shader code than Mesa IR, since we get
real optimizations, as opposed to prog_optimize:
total instructions in shared programs: 314007 -> 279892 (-10.86%)
instructions in affected programs: 285173 -> 251058 (-11.96%)
helped: 2001
HURT: 67
GAINED: 4
LOST: 7
v2: Change early return in nir_setup_uniforms to if/else (Jordan).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit bf2c3bc316cbfcc19d1bb65ab7410784ed7a3dac
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Mar 25 15:22:12 2015 -0700
nir: Lower subtraction to add with negation when !lower_negate.
prog->nir will generate fsub opcodes, but i965 doesn't implement them.
We may as well lower them at the NIR level, since it's trivial to do.
Suggested by Connor Abbott.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit faf6106c6f6fa2ba90ec175baaa8b54bec9f5125
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Jan 29 23:22:08 2015 -0800
nir: Implement a Mesa IR -> NIR translator.
Shamelessly ripped off from Eric Anholt's tgsi_to_nir pass.
This is not built on SCons, like the rest of NIR.
v2:
- Delete redundant c->s, c->impl, and c->cf_node_list pointers (Ken)
- Use nir_builder directly instead of ptn_compile in more places (Ken)
- Drop 'struct' keyword in front of nir_builder (ken)
- Add a file level Doxygen comment (Ken)
- Use scalar constants instead of splatting (Eric)
- Use nir_builder helpers for constants, moves, and swizzles (Connor)
v3: Minor indentation improvements.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 06f7bea96ab62e7de1523de837f5b69c1bac6513
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Mar 25 14:51:02 2015 -0700
nir: Add builder helpers for MOVs with ALU sources and swizzling MOVs.
These will be useful for prog->nir and tgsi->nir.
v2: Don't forget to mark nir_swizzle as inline (Eric).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 75c922e0fed41acf28318b082f7f915c752ffe74
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Mar 25 02:11:52 2015 -0700
nir: Add nir_builder helpers for creating load_const intrinsics.
Both prog->nir and tgsi->nir will want to use these.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 74fd226e34d0cf5e9ff43174ae69b4a66f5de1ab
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Wed Mar 25 16:52:46 2015 -0700
i965/skl: Don't use the PMA depth stall workaround
The PMA depth stall must be enabled (optimization turned off) under certain
circumstances on gen8. This was supposedly fixed for Gen9, which means we do not
need to check, or toggle the state. The hardware is supposed to enable the
hardware optimization by default, unlike BDW, so we also don't need to set it at
init. For whatever reason this improves stability on ETQW with the bug mentioned
below.
References: https://bugs.freedesktop.org/show_bug.cgi?id=89039 (doesn't fix)
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Tested-by: Anuj Phogat <anuj.phogat at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 9d32d358500733249d3c0264c7458c2e5a65f515
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Thu Feb 26 18:14:17 2015 -0800
i965/skl: Disable partial resolve in VC
Recomendation [sic] is to set this field to 1 always. Programming it to default
value of 0, may have -ve impact on performance for MSAA WLs.
Another don't suck bit which needs to get set.
The patch wasn't as well tested as I would have liked, primarily I don't have
perf numbers for it, but it's getting to a point where it is in danger of being
lost.
v2: v1 was a mix of two patches. Since 0x7004 is masked, we only need to set it
once at initialization and make sure the pma workaround doesn't set the mask bit
(which it doesn't).
Move LRI to init gpu state (Ken)
Add a comment.
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit b2424fb0304cf4afd363b35c1dab49fb7edddb08
Author: Roland Scheidegger <sroland at vmware.com>
Date: Fri Mar 27 16:49:54 2015 +0100
llvmpipe: simplify address calculation for 4x4 blocks
These functions looked quite complicated, even though what they actually did
was trivial (ever since we dropped swizzled rendering). Also drop lookup of
format block per bytes done for each block, and do it once per scene instead.
This improves everybody's favorite "benchmark" by 3% or so, though
lp_rast_shade_quads_all() which calls this shows up still quite high for a
function which does little more than call the jit function.
(This would most likely be much better handled by the jit function itself,
the strides are passed through anyway already, though for being able to
handle layers it would definitely add some complexity.)
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 764fc2be5ab61c86baaab746e7ea7702328c4f9f
Author: Roland Scheidegger <sroland at vmware.com>
Date: Sat Mar 28 02:57:13 2015 +0100
gallivm: fix texture function name (key) when using txf/ld
When using the texel fetch functions rather than ordinary texturing,
the arguments are all int vecs instead of float vecs, not to mention
the actual function would look completely different. Hence this must
be included in the texture function name (which serves as the key)
otherwise things crash badly when a shader accesses the same texture
and sampler unit with both txf/ld and ordinary texturing instructions
with otherwise matching keys.
commit 2cb149c2894679c5c7af81b40277f77cc0fb099d
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Fri Mar 27 23:03:40 2015 +1100
glsl: mark uniform and input interface blocks as read only
Reviewed-by: Mark Janes <mark.a.janes at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 58030a8f99d94d6c1bab02ef113d93c6c2636216
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Mar 27 18:38:24 2015 -0400
nv50/ir/gk110: fix offset flag position for TXD opcode
Cc: "10.4 10.5" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 49b86007aa2bb599ada6cdbed7ff56246917f12e
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Mar 25 18:00:00 2015 -0400
nv50/ir: take postFactor into account when doing peephole optimizations
Multiply operations can have a post-factor on them, which other ops
don't support. Only perform the peephole optimizations when there is no
post-factor involved.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89758
Cc: "10.4 10.5" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit a99a16a0cffbb79e1f9a2d2844c549e6ff91afdb
Author: Jan Vesely <jan.vesely at rutgers.edu>
Date: Fri Mar 27 18:45:23 2015 -0400
gallivm: Fix build since llvm r233411
Signed-off-by: Jan Vesely <jan.vesely at rutgers.edu>
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
commit afa9fc15613c3ebdc59245c9d4d8c1280b2a2a37
Author: Eric Anholt <eric at anholt.net>
Date: Wed Feb 18 12:24:38 2015 -0800
nir: Add optional lowering of flrp.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 56076be2ac60f005770516a9ac305e60e6285497
Author: Roland Scheidegger <sroland at vmware.com>
Date: Fri Mar 27 02:39:59 2015 +0100
gallivm: use llvm function calls for texturing instead of inlining
There are issues with inlining everything, most notably llvm will use much
more memory (and be slower) when compiling. Ideally we'd probably use
functions for shader functions too but texture sampling usually is responsible
for quite some IR (it can easily reach 80% of total IR instructions) so this
seems like a good start.
This still generates a different function for all different combinations just
like before, however it is possible llvm is missing some optimization
opportunities - it is believed though such opportunities should be somewhat
rare, but at least for now it can still be switched off (at compile time only).
It should probably make compiled code also smaller because the same function
should be used for different variants in the same module (so for the
opaque/partial or linear/elts variants).
No piglit change (though it does indeed speed up unrealistic tests like
fp-indirections2 by a factor of 30 or so).
Has a small negative performance impact in openarena - I suspect this could
be fixed by running some IPO passes (despite the private linkage, llvm right
now does NO optimization at all wrt anything going past the call, even if
there's just one caller - so things like values stored before the call and then
always written by the function etc. will not be optimized away, nor will dead
arguments (which we mostly shouldn't have) be eliminated, always constant
arguments promoted etc.).
v2: use proper return values instead of pointer function arguments.
llvm supports aggregate return values, which do wonders here eliminating
unnecessary stack variables - everything in fact will be returned in registers
even without any IPO optimizations. It makes the code simpler too.
With this I could not measure a peformance impact in openarena any longer
(though since there's still no constant value propagation etc. into the tex
functions this does not mean it couldn't have a negative impact elsewhere).
v3: fix some minor issues suggested by Jose, and do disassembly (and the
profiling) without hacks.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 8dad9455ff748c543635b24908566c3b94cb93a9
Author: Roland Scheidegger <sroland at vmware.com>
Date: Wed Mar 25 03:10:10 2015 +0100
gallivm: pass jit_context pointer through to sampling
The callbacks used for getting the dynamic texture/sampler state were using
the jit_context from the generated jit function. This works just fine, however
that way it's impossible to generate separate functions for texture sampling,
as will be done in the next commit. Hence, pass this pointer through all
interfaces so it can be passed to a separate function (technically, it would
probably be possible to extract this pointer from the current function instead,
but this feels hacky and would probably require some more hacks if we'd use
real functions instead of inlining all shader functions at some point).
There should be no difference in the generated code for now.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 787aa26cb7b48504f7770cacfc321324ecafa29a
Author: Christian König <christian.koenig at amd.com>
Date: Thu Mar 26 14:49:18 2015 +0100
gallium/vl: partially revert "Use util_cpu_to_le{16,32} in many more places."
The data in memory is in big endian format and needs to be converted
into CPU byte order. So the patch actually reversed what needs to be done.
Signed-off-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 626434893a048f3ba89a751998fcb3789a3dbb96
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Mar 26 19:06:37 2015 -0400
tgsi: fix out-of-bounds access for cube arrays
The CUBE_ARRAY case uses r[4]. Make sure that the stack variable is
there.
Noticed by Coverity.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit f95a6b2ff4237181fd7e9622e19e9aa0719a1f21
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Mar 26 19:33:01 2015 -0400
st/mesa: initialize have_fma in constructor
Spotted by Coverity.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 1b87d73a9f93fd0ce2c943964de9eae44affb991
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Mar 26 19:26:38 2015 -0400
gallium/util: remove u_linkage
Does not appear to be used in tree. Coverity spotted some errors in the
bitmask stuff, but the whole thing appears to be unused.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 2e34faaf06f50741164209cc5743ab4d8579c94c
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Mar 26 19:37:50 2015 -0400
gallium/hud: avoid overflowing hud graph name size
Spotted by Coverity.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 9d1b5febb62d74c9fc564635d4e0fa5207928c46
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Mar 26 15:14:22 2015 -0400
st/mesa: update arrays when the current attrib has been updated
Fixes the recently-sent gl-2.0-vertex-const-attr piglit test. Makes sure
to revalidate arrays when only the current attribute has been updated
via glVertexAttrib*.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89754
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Cc: "10.4 10.5" <mesa-stable at lists.freedesktop.org>
commit 91e3533481d6921c4b46109742d6f67b7f897f86
Author: Dave Airlie <airlied at redhat.com>
Date: Thu Mar 26 09:17:39 2015 +1000
st_glsl_to_tgsi: only do mov copy propagation on temps (v2)
Don't propagate ARRAYs
This should fix:
https://bugs.freedesktop.org/show_bug.cgi?id=89759
v2: just specify arrays so we get input propagation
Signed-off-by: Dave Airlie <airlied at redhat.com>
Cc: mesa-stable at lists.freedesktop.org
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit ef09cfb51e0c1cc9e3c6f370813a843a6ecaa4e2
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Mar 25 15:15:43 2015 -0700
i965: Drop unnecessary brw->gen >= 8 check from scalar VS code.
brw->scalar_vs already implies that brw->gen >= 8.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 649173b473ded2d7b1aded91cd4aab42eaeb5766
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Jan 31 23:36:52 2015 -0800
i965/fs: Implement texture projection support.
Our fragment program backend implements support for TXP directly, and
there's no NIR lowering pass to remove the projection. When we switch
fragment program support over to NIR, we need to support it somehow.
It's easy enough to support directly.
v2: Split out offset/tex_offset rename (requested by Jordan).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 0a9bcf9e39409ea5acfdfbcf0c388e41e0f9ea45
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Mar 25 13:12:20 2015 -0700
i965/fs: Rename offset to tex_offset to avoid shadowing offset().
fs_visitor::nir_emit_texture() created an fs_reg variable called offset,
which shadowed the offset() helper function in brw_ir_fs.h.
Rename the variable to tex_offset so we can still call offset().
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 3120345f407695e9fef96e4fa98f7ff3af8c38ce
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Feb 23 19:56:00 2015 -0800
nir: Add glsl_float_type() wrapper.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 871f1080d0f7b7444458de40b67de7938c220922
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Jan 12 22:35:53 2015 -0800
glsl: Use INFINITY instead of std::numeric_limits<float>::infinity().
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 5dc573e5de0eb49bc8622558789ebc4adf03926c
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Mar 21 20:45:22 2015 +0000
automake: add missing egl files to the tarball
Namely the Haiku EGL driver backend and the SConscript for the dri2 EGL
driver backend.
Cc: Alexander von Gluck IV <kallisti5 at unixzen.com>
Cc: mesa-stable at lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 60757802471ba5a13e31cac7786eed3f369b6927
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Mar 18 19:00:48 2015 -0700
glsl: Constify ir_instruction::equals
v2: Don't be lazy. Constify the as_foo functions and use those instead
of ugly casts. Suggested by Curro.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit dec9664e35a35b447f21ea15631ae5a5404e9624
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Mar 24 09:14:35 2015 -0700
glsl: Constify the as_foo functions
Now that they're all implemented using macros, this is trivial.
v2: Remove redundant parenthesis. Suggested by Curro.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 0c4ee62045ed184a5b9662f940b8a9e9bd454734
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Mar 24 09:02:24 2015 -0700
glsl: Implement remaining as_foo functions with macros
The downcast functions for non-leaf classes were previously implemented
"by hand." Now they are implemented using macros based on the is_foo
functions added in the previous patch.
v2: Remove redundant parenthesis. Suggested by Curro (on the next
patch).
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit a284c6300665d4388dae14363807a57bb82e4cb5
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Mar 24 08:55:15 2015 -0700
glsl: Add is_rvalue, is_dereference, and is_jump methods
These functions deteremine when an IR node is one of the non-leaf
classes.
v2: Adjust indentation to line up. Suggested by Matt.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 25d6cdd2ff1f00e0eab532956c0ae17d4ffa42da
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Tue Mar 24 19:56:21 2015 +0000
util/u_atomic: Ignore warnings interlocked accesses.
These are due how we implemented the atomic tests, not the atomic
implementation itself. It's also difficult to refactor the code to
avoid the warnings due to the use of macros -- the code would be quite
hairy.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 28c54400af1ee04306342f67e56dc9e37933c538
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Tue Mar 24 19:50:48 2015 +0000
scons: Disable MSVC warnings about inconsistent function annotation.
Somehow, merely including any of the *intrin.h headers causes dozens of
this warnings (when compiling pretty much every source file). MSVC does
not always complain the same -- so it's possible we're doing something
weird --, but silence these warnings in the meanwhile.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit cb88edbd4e9cb198013129a360cb3d4163ac3837
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Tue Mar 24 19:01:46 2015 +0000
mesa: Avoid MSVC C6334 warning in /analyze mode.
MSVC's implementation of signbit(x) uses sizeof(x) with expressions to
dispatch to an internal function based on the argument's type (float,
double, etc), but that raises a flag with MSVC's own static analyzer,
and because this is an inline function in a header it causes substantial
warning spam.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit fdb507e3d6a9a78f8a42bc8d6f7e60816627403e
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Tue Mar 24 13:16:24 2015 +0000
c99_math: Don't reimplement lrint and friends on MSVC 2013.
MSVC 2013 declares these functions, both for C and C++ source files.
This was caught with MSVC in analyze mode.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 69db422218b0264b5b8eef45bd003a2544e9cbd6
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Tue Mar 24 20:30:03 2015 +0000
scons: Don't build osmesa.
There doesn't seem much interest on osmesa on Windows, particularly classic osmesa.
If there is indeed interest in osmesa on Windows, we should instead
integrate src/gallium/targets/osmesa into SCons.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 47870d658b777722d48d6b9084d66e270a04e52e
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Tue Mar 24 20:26:21 2015 +0000
scons: Don't build loader on Windows.
EGL was the last user.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit f9b8c9299d10542c9806927018a488f84adcb036
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Tue Mar 24 20:11:36 2015 +0000
scons: Don't build egl on Windows.
Useless, as there are no drivers for it.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 5db57b8a55bb1961f1ada029f63c1f07511d60aa
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Mon Mar 23 10:48:31 2015 +0000
scons: Fix git_sha1.h generation fallback.
I didn't meant to remove the 'if not os.path.exists(filename)' statement.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 31a30fb342624658f9ab3f9febd06c59b3a3d2c8
Author: Martin Peres <martin.peres at linux.intel.com>
Date: Thu Mar 19 19:44:56 2015 +0200
docs: Update progress on ARB_direct_state_access.
v2:
- Fix the state of the Program pipelines and Query objects (Laura)
Signed-off-by: Martin Peres <martin.peres at linux.intel.com>
commit bf11c195a59a3d545d91917f503dcee81d48ab09
Author: Martin Peres <martin.peres at linux.intel.com>
Date: Fri Feb 13 15:35:48 2015 +0200
main: Added entry points for NamedRenderbufferStorage/Multisample
v2: Review from Laura Ekstrand
- get rid of a change that should not have happened in this patch
- improve the error messages
- fix alignments
- fix a capitalization in a function name in an error message
v3: Review from Laura Ekstrand
- move the test for the validity of the renderbuffer to less generic
functions
- get rid of some changes that accidentally landed in the wrong commit
- revert some alignment fixes
v3: Review from Laura Ekstrand
- check that the lookup returns a valid renderbuffer
- cosmetic changes to some error messages
Reviewed-by: Laura Ekstrand <laura at jlekstrand.net>
Signed-off-by: Martin Peres <martin.peres at linux.intel.com>
commit 245e5c4813eb30e32bd61a08ae32ee278b09d1cf
Author: Martin Peres <martin.peres at linux.intel.com>
Date: Fri Feb 13 15:46:55 2015 +0200
main: Added entry point for glGetNamedRenderbufferParameteriv
v2:
- improve an error message
v3:
- move a test to less generic functions
- fix an alignment
v4:
- take the caller as a parameter instead of bool dsa
- check that the lookup returns a valid renderbuffer
Reviewed-by: Laura Ekstrand <laura at jlekstrand.net>
Signed-off-by: Martin Peres <martin.peres at linux.intel.com>
commit a34669b96166ffe839168bc8effc60aba9aa4178
Author: Martin Peres <martin.peres at linux.intel.com>
Date: Thu Feb 12 18:52:10 2015 +0200
main: Added entry point for glCreateRenderbuffers
v2:
- refactor bindRenderBuffer and create_render_buffers to fix an assertion
Reviewed-by: Laura Ekstrand <laura at jlekstrand.net>
Signed-off-by: Martin Peres <martin.peres at linux.intel.com>
commit 73a9d0fbe5a6d2d9e8ef98531bf662343dcc1abe
Author: Martin Peres <martin.peres at linux.intel.com>
Date: Thu Feb 12 13:12:19 2015 +0200
main: Added entry point for glCreateSamplers
Because of the current way the code is architectured, there is no
functional difference between the DSA and the non-DSA path.
Reviewed-by: Laura Ekstrand <laura at jlekstrand.net>
Signed-off-by: Martin Peres <martin.peres at linux.intel.com>
commit b09f2ee8f7b76f30a75eec61ea8225a434365d49
Author: Martin Peres <martin.peres at linux.intel.com>
Date: Wed Feb 11 18:12:21 2015 +0200
main: Added entry point for glCreateProgramPipelines
v2:
- add spaces in an error message (Laura)
Reviewed-by: Laura Ekstrand <laura at jlekstrand.net>
Signed-off-by: Martin Peres <martin.peres at linux.intel.com>
commit 19e6efc0ad0e937bd89c00967d06f54d987810bc
Author: Martin Peres <martin.peres at linux.intel.com>
Date: Mon Feb 16 12:20:19 2015 +0200
main: Added entry points for glGetQueryBufferObject*
These entry points will be fleshed out when the GL_ARB_query_buffer_object
extension gets implemented. In the meantime, return GL_INVALID_OPERATION as
suggested by Ian.
Reviewed-by: Laura Ekstrand <laura at jlekstrand.net>
Signed-off-by: Martin Peres <martin.peres at linux.intel.com>
commit c3c1ed874e57b439e856a3eec735181b3221730e
Author: Martin Peres <martin.peres at linux.intel.com>
Date: Tue Feb 10 17:13:06 2015 +0200
main: Added entry point for glCreateQueries
v2:
- display the name of the target instead of its id (Laura)
Reviewed-by: Laura Ekstrand <laura at jlekstrand.net>
Signed-off-by: Martin Peres <martin.peres at linux.intel.com>
commit 6ead10d08f0a4e0ccc699437ed424a0019c07ef8
Author: Martin Peres <martin.peres at linux.intel.com>
Date: Thu Jan 22 16:55:29 2015 +0200
main: Added entry point for glGetTransformFeedbacki64_v
v2: Review from Laura Ekstrand
- use the transform feedback object lookup wrapper
v3:
- use the new name of _mesa_lookup_transform_feedback_object_err
v4: Review from Laura Ekstrand
- fix some alignement problems
Reviewed-by: Laura Ekstrand <laura at jlekstrand.net>
Signed-off-by: Martin Peres <martin.peres at linux.intel.com>
commit 8799ecddb680f908b719df531dfe740e056ccb77
Author: Martin Peres <martin.peres at linux.intel.com>
Date: Mon Feb 16 16:13:59 2015 +0200
main: Added entry point for glGetTransformFeedbacki_v
v2: Review from Laura Ekstrand
- use the transform feedback object lookup wrapper
v3:
- use the new name of _mesa_lookup_transform_feedback_object_err
Reviewed-by: Laura Ekstrand <laura at jlekstrand.net>
Signed-off-by: Martin Peres <martin.peres at linux.intel.com>
commit e59d2434a075176ebc94438f81d742e222da3e82
Author: Martin Peres <martin.peres at linux.intel.com>
Date: Mon Feb 16 16:13:58 2015 +0200
main: Added entry point for glGetTransformFeedbackiv
v2: Review from Laura Ekstrand
- use the transform feedback object lookup wrapper
Reviewed-by: Laura Ekstrand <laura at jlekstrand.net>
Signed-off-by: Martin Peres <martin.peres at linux.intel.com>
commit 296d82376e5d31961c02f6669f2012eb7bf4439d
Author: Martin Peres <martin.peres at linux.intel.com>
Date: Wed Jan 21 12:22:11 2015 +0200
main: Added entry point for glTransformFeedbackBufferRange
v2: review from Laura Ekstrand
- use the refactored code to lookup the objects
- improve some error messages
- factor out the gl method name computation
- better handle the spec differences between the DSA and non-DSA cases
- quote the spec a little more
v3: review from Laura Ekstrand
- use the new name of _mesa_lookup_bufferobj_err
- swap the comments around the offset and size checks
v4: review from Laura Ekstrand
- add more spec quotes
- properly fix the comments around the offset and size checks
v5: review from Laura Ekstrand
- add quotes on the spec citations
- revert some changes in the printf format
v6: review from Laura Ekstrand
- remove a redondant "gl" in a method name
Signed-off-by: Martin Peres <martin.peres at linux.intel.com>
Reviewed-by: Laura Ekstrand <laura at jlekstrand.net>
commit a5d165afed8dae34f0b4f281fc1c390d019e9b97
Author: Martin Peres <martin.peres at linux.intel.com>
Date: Tue Jan 20 16:30:32 2015 +0200
main: Added entry point for glTransformFeedbackBufferBase
v2: Review from Laura Ekstrand
- give more helpful error messages
- factor the lookup code for the xfb and objBuf
- replace some already-existing tabs with spaces
- add comments to explain the cases where xfb == 0 or buffer == 0
- fix the condition for binding the transform buffer or not
v3: Review from Laura Ekstrand
- rename _mesa_lookup_bufferobj_err to
_mesa_lookup_transform_feedback_bufferobj_err and make it static to avoid a
future conflict
- make _mesa_lookup_transform_feedback_object_err static
v4: Review from Laura Ekstrand
- add the pdf page number when quoting the spec
- rename some of the symbols to follow the public/private conventions
v5: Review from Laura Ekstrand
- properly rename some of the symbols to follow the public/private conventions
- fix some alignments
- add quotes around a spec citation
- add back a newline I accidentally deleted
- add spaces around the ternary operator usages
Signed-off-by: Martin Peres <martin.peres at linux.intel.com>
Reviewed-by: Laura Ekstrand <laura at jlekstrand.net>
commit c86cb2da255216524974eb1c92caa1ecb378e32e
Author: Martin Peres <martin.peres at linux.intel.com>
Date: Wed Jan 14 18:17:21 2015 +0200
main: Added entry point for glCreateTransformFeedbacks
v2: Review from Laura Ekstrand
- generate the name of the gl method once
- shorten some lines to stay in the 78 chars limit
v3: Review from Fredrik Höglund <fredrik at kde.org>
- rename gl_mthd_name to func
- set EverBound in _mesa_create_transform_feedbacks in the dsa case
v4:
- rename _mesa_create_transform_feedbacks to create_transform_feedbacks and
make it static
Reviewed-by: Laura Ekstrand <laura at jlekstrand.net>
Signed-off-by: Martin Peres <martin.peres at linux.intel.com>
commit fc76fac4199f06e26d6c9b4fbb87b85f802b06f3
Author: Martin Peres <martin.peres at linux.intel.com>
Date: Fri Feb 13 18:14:15 2015 +0200
main: fix the validation of the number of samples
Maybe this should be the job of the dispatch layer.
v2:
- add the section name and pdf page number of the quote (Laura)
- OpenGL 3.0 core does not exist, get rid of "core"
Signed-off-by: Martin Peres <martin.peres at linux.intel.com>
commit 7bd8b48084971b1e0d852136e5436776e8ffb044
Author: Martin Peres <martin.peres at linux.intel.com>
Date: Thu Feb 12 17:54:43 2015 +0200
main: replace tabs by 8 spaces in fbobject.c
Reviewed-by: Laura Ekstrand <laura at jlekstrand.net>
Signed-off-by: Martin Peres <martin.peres at linux.intel.com>
commit cd0763b78f041167ba7c33f3c766f8082d3343e1
Author: Martin Peres <martin.peres at linux.intel.com>
Date: Wed Feb 11 11:21:56 2015 +0200
main: replace tabs by 8 spaces in bufferobj.c
Reviewed-by: Laura Ekstrand <laura at jlekstrand.net>
Signed-off-by: Martin Peres <martin.peres at linux.intel.com>
commit 169b389a34966b921fe4b75baff5503c3a31a98a
Author: Kristian Høgsberg <krh at bitplanet.net>
Date: Tue Mar 24 09:41:08 2015 -0700
mesa: Apply visibility flags to src/Makefile.am targets
We were building libglsl_util.la without our visibility flags and
leaking hash_table_* symbols.
Signed-off-by: Kristian Høgsberg <kristian.h.kristensen at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit babd0fa3e28ae673128aaab55bd59fc3b7135be3
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Mar 24 19:14:18 2015 -0700
nir: Fix typo.
commit 3fb56805f0dbfe929cd733e15566197bc0733290
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Mar 17 23:30:43 2015 -0700
nir: Recognize sat(add(b2f(a), b2f(b))) as a logical OR.
Transform this into b2f(or(a, b)).
instructions in affected programs: 432 -> 430 (-0.46%)
helped: 2
Acked-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit c31158d2cb06a864cf44d6d4f2c539e359990d3d
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Mar 17 23:30:32 2015 -0700
nir: Recognize mul(b2f(a), b2f(b)) as a logical AND.
Transform this into b2f(and(a, b)).
total instructions in shared programs: 6205448 -> 6204391 (-0.02%)
instructions in affected programs: 284030 -> 282973 (-0.37%)
helped: 903
HURT: 6
Acked-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit b481ebbe399fdc6386fd52f890ba7c310d333ed5
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Mar 18 10:39:38 2015 -0700
glsl: Recognize sat(add(b2f(a), b2f(b))) as a logical OR.
Transform this into b2f(or(a, b)).
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit c8e8f660365515560af029651e593f7ee700401c
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Mar 17 23:28:27 2015 -0700
glsl: Recognize mul(b2f(a), b2f(b)) as a logical AND.
Transform this into b2f(and(a, b)).
total instructions in shared programs: 6190291 -> 6189225 (-0.02%)
instructions in affected programs: 267247 -> 266181 (-0.40%)
helped: 866
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 95729d2458515788ed84c81698033b8ef170bd4e
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Mar 23 16:04:41 2015 -0700
nir: Handle mixed scalar/vector arguments to logical and/or/xor.
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit c8acbd1bfdafa892e6c5e9a6d9100aa2e69b9096
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Mar 17 23:27:38 2015 -0700
glsl: Allow vector logic ops to be generated.
They're not accessible from the source language, but optimizations are
allowed to generate them.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 248eb54eb6117cc5a863ba2deaa14c3bee0b5d41
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Mar 23 17:49:23 2015 +0000
configure.ac: move AC_MSG_RESULT reporting back into the m4 macro
The one who does AC_MSG_CHECKING should provide the AC_MSG_RESULT.
Fixes: ced9425327b (configure: Introduce new output variable to
ax_check_python_mako_module.m4"
Cc: "10.5" <mesa-stable at lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89328
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
commit 726d99b19740dca6787ab819ab99bc9d942d80a6
Author: Jonathan Gray <jsg at jsg.id.au>
Date: Tue Mar 17 12:49:39 2015 +1100
gallium/util: Use HAVE___BUILTIN_FFS* macros.
Make use of the builtin ffs macros and split out ffsll
to a seperate block. Needed for at least OpenBSD which
does not have ffsll in libc.
Signed-off-by: Jonathan Gray <jsg at jsg.id.au>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 8cce7b05f19207d331a1abe294c201e0c3ee6ec1
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Mar 23 16:17:36 2015 +0000
i965: add the remaining files to the tarball
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 9950eec173d056e324332c12fa269c852cc931aa
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Mar 23 16:17:35 2015 +0000
glsl: add the remaining files to the tarball
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit b2439602bef14387ccb1ea63ea452af4f15e8889
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Mar 23 16:17:34 2015 +0000
makefile: add all headers to the tarball
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 113d59fb557c377316904010ce88b9a87b4cc4d7
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Mar 21 17:45:26 2015 +0000
gbm: remove gbm_gallium_drm from the loader
No longer used as of commit 48c7461d5a0(st/gbm: remove state-tracker)
v2: Add commit message.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net> (v1)
commit d8208312a3a200b4e6d71ce533d835b2d705234a
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Thu Mar 5 11:07:52 2015 -0800
glsl: Generate link error for non-matching gl_FragCoord redeclarations
in different fragment shaders. This also applies to a case when gl_FragCoord
is redeclared with no layout qualifiers in one fragment shader and not
declared but used in other fragment shader.
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Khronos Bug#12957
Cc: "10.5" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit 7bc39c8418ee5de49e3d38aaf5f9e478ff78874c
Author: Eric Anholt <eric at anholt.net>
Date: Wed Jan 14 09:58:35 2015 +1300
vc4: Add a dump-the-surface-contents routine.
This has been useful once again while trying to debug stride issues
between render targets and texturing.
commit 4df13f55b6c2cdda82b7909e1b089cc72f4c1151
Author: Eric Anholt <eric at anholt.net>
Date: Mon Mar 23 16:15:11 2015 -0700
vc4: Allow DRI3 on simulation, as well.
The problem I'd seen before seems to be gone.
commit 7f797e3d173c7a84aa5d231a1c173b00e84ea44f
Author: Eric Anholt <eric at anholt.net>
Date: Mon Mar 16 14:48:26 2015 -0700
vc4: Fix pitch alignment of linear textures.
Fixes some non-power-of-two texture rendering when I force ARGB8888 to
raster.
commit b3ea377f8629ada57c67632a89f0d2e9d2faf23c
Author: Eric Anholt <eric at anholt.net>
Date: Mon Mar 23 16:34:24 2015 -0700
vc4: Write the alignment of level width consistently in validation.
16 / cpp happens to be the same as utile_w on the only raster format
supported (4 bytes per pixel), but simulator/hw source code generally
talks in terms of utiles.
commit 8975a09494cb6ee7b010fddb0ca5a7a74d46b0c7
Author: Eric Anholt <eric at anholt.net>
Date: Mon Mar 16 14:14:22 2015 -0700
vc4: Fix use of a bool as an enum.
The enum compared to was 0, so it worked out, but it sure looked wrong.
commit 04605c21f65bfbc78018c5bafa8cbf49e96a33b5
Author: Eric Anholt <eric at anholt.net>
Date: Mon Mar 23 16:21:25 2015 -0700
vc4: Decide the HW's format before laying out the miptree.
I'm experimenting with a workaround for raster texture misrendering on
hardware, and this lets me look at the format chosen when computing
strides.
commit 25d60763d9c2767c279f28ac2a7eddcd245f4259
Author: Eric Anholt <eric at anholt.net>
Date: Mon Mar 23 17:17:17 2015 -0700
vc4: Use our device-specific ioctls for create/mmap.
They don't do anything special for us, but I've been told by kernel
maintainers that relying on dumb for my acceleration-capable buffers
is not OK.
commit af3d7471943d54e692f2dd7448321a4f96e56ed2
Author: Eric Anholt <eric at anholt.net>
Date: Mon Mar 23 17:26:40 2015 -0700
vc4: Make a new #define for making code conditional on the simulator.
I'd like to compile as much of the device-specific code as possible
when building for simulator, and using if (using_simulator) instead of
ifdefs helps.
commit 9bafcf630ab009b3b39bbe3c0f4370386bc5a6b2
Author: Eric Anholt <eric at anholt.net>
Date: Mon Mar 23 17:38:29 2015 -0700
vc4: Add some useful debug printfs for miptrees.
I keep rewriting these.
commit baa22c8825133a69fd0657f09d2a027236233eb1
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Mar 23 06:32:08 2015 -0400
glsl: avoid calling base_alignment when samplers are involved
Earlier commit 53bf7c8fd2e changed the logic to always call
base_alignment on structs. 1ec715ce8b12 hacked the function to return 0
for sampler fields, but didn't handle sampler arrays. Instead of
extending the hack, avoid calling base_alignment in the first place on
non-UBO uniforms.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89726
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Tapani Palli <tapani.palli at intel.com>
commit 43277fcd59b163a8bdd00d7875557bb71ecf48ff
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Mar 23 20:53:19 2015 -0400
Revert "nv50,nvc0: remove bogus 64_FLOAT formats"
This reverts commit 20346808cf4f1ee4f320afaf18f94043fb146f2e.
The conversion is actually done since these are the *B macro variants
and no vtx format is supplied, which makes them go through the translate
module.
This restores the following piglit tests to passing:
draw-vertices user
gl-2.0-vertexattribpointer
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 1110113a7f0b6f9b21dd26dee8e95a021041c71c
Author: Mario Kleiner <mario.kleiner.de at gmail.com>
Date: Thu Mar 12 23:34:12 2015 +0100
mapi: Make private copies of name strings provided by client.
glXGetProcAddress("glFoo") ends up in stub_add_dynamic() to
create dynamic stubs for dynamic functions. stub_add_dynamic()
doesn't store the caller provided name string "Foo" in a mesa
private copy, but just stores a pointer to the "glFoo" string
passed to glXGetProcAddress - a pointer into arbitrary memory
outside mesa's control.
If the caller passes some dynamically allocated/changing
memory buffer to glXGetProcAddress(), or the caller gets unmapped
from memory, e.g., some dynamically loaded application
plugin which uses OpenGL, this ends badly - with a dangling
pointer.
strdup() the name string provided by the client to avoid
this problem.
Cc: "10.3 10.4 10.5" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Mario Kleiner <mario.kleiner.de at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit dfb1ae9d914b7723ef50fdd2efe811feebc045ad
Author: Tom Stellard <thomas.stellard at amd.com>
Date: Fri Mar 20 22:19:43 2015 +0000
clover: Return 0 as storage size for local kernel args that are not set v2
The storage size for local kernel args can be queried before the
arguments are set by using the CL_KERNEL_LOCAL_MEM_SIZE param
of clGetKernelWorkGroupInfo().
The spec says that if local kernel arguments have not been specified,
then we should assume their size is 0.
v2:
- Implement using c++11 member initialization.
Reviewed-by: Jan Vesely <jan.vesely at rutgers.edu>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
Cc: 10.5 10.4 <mesa-stable at lists.freedesktop.org>
commit 769b366b83dcc12bfe06935f816023cdcfbdf578
Author: Tom Stellard <thomas.stellard at amd.com>
Date: Mon Mar 23 14:37:24 2015 +0000
gallivm: Use MCInstrInfo in the disassembler for querying instruction info
This fixes the build since llvm r232885 and also simplifies the code.
commit 7932b30892ef898ec4c74ac1f972cb462f19962b
Author: Giuseppe Bilotta <giuseppe.bilotta at gmail.com>
Date: Sun Mar 22 07:21:02 2015 +0100
clover: use get_device_vendor instead of get_vendor
The pipe's get_vendor method returns something more akin to a driver
vendor string in most cases, instead of the actual device vendor. Use
get_device_vendor instead, which was introduced specifically for this
purpose.
Signed-off-by: Giuseppe Bilotta <giuseppe.bilotta at gmail.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 76039b38f0ef54ca61cbe72b899dfcf0f0c724e4
Author: Giuseppe Bilotta <giuseppe.bilotta at gmail.com>
Date: Sun Mar 22 07:21:01 2015 +0100
gallium: implement get_device_vendor() for existing drivers
The only hackish ones are llvmpipe and softpipe, which currently return
the same string as for get_vendor(), while ideally they should return
the CPU vendor.
Signed-off-by: Giuseppe Bilotta <giuseppe.bilotta at gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
commit 31d4e6fbffb0c5bcaf92e2c2953f58dc072295d6
Author: Giuseppe Bilotta <giuseppe.bilotta at gmail.com>
Date: Sun Mar 22 07:21:00 2015 +0100
gallium: introduce get_device_vendor() entrypoint for pipes
This will be needed by Clover to return the correct information
to CL_DEVICE_VENDOR info queries.
Signed-off-by: Giuseppe Bilotta <giuseppe.bilotta at gmail.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 9280f17e823cbdbddf30a4ae5e2de9f2d327d33c
Author: Giuseppe Bilotta <giuseppe.bilotta at gmail.com>
Date: Sun Mar 22 07:20:59 2015 +0100
gallium: remove trailing whitespace in p_screen.h
Signed-off-by: Giuseppe Bilotta <giuseppe.bilotta at gmail.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 6e17936bf84c286c3540fe559838bc2a4d975539
Author: Tom Stellard <thomas.stellard at amd.com>
Date: Sat Mar 21 00:44:47 2015 +0000
clover: The unit for CL_DEVICE_MEM_BASE_ADDR_ALIGN is bits not bytes
Reviewed-by: Jan Vesely <jan.vesely at rutgers.edu>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 2b12b1752ae18c468cb01e94c78544ca5783dc44
Author: Tom Stellard <thomas.stellard at amd.com>
Date: Sat Mar 21 00:25:34 2015 +0000
clover: Add all the mandatory 1.1 extensions to the extension string
Reviewed-by: Jan Vesely <jan.vesely at rutgers.edu>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 96f9cc9181403a93208cb44786c485ce44492eda
Author: Tom Stellard <thomas.stellard at amd.com>
Date: Fri Mar 20 23:55:58 2015 +0000
clover: Add a space at the end of CL_DEVICE_OPENCL_C_VERSION
This is required by the spec.
Reviewed-by: Jan Vesely <jan.vesely at rutgers.edu>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 3d1bba7c9be856ed4e7611ef92796430556a2f6d
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Mar 18 21:06:28 2015 +0200
i965/vec4: Fix handling of multiple register reads and writes in dead_code_eliminate().
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 2babde35b9a38a0561a87dc2d7cb431e9aabbd5a
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Mar 23 14:08:49 2015 +0200
i965/vec4: Calculate live intervals with subregister granularity.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit e6e655ef76bb22193b31af2841cb50fda0c39461
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Mar 18 20:49:43 2015 +0200
i965/vec4: Define helpers to calculate the common live interval of a range of variables.
These will be especially useful when we start keeping track of
liveness information for each subregister.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit eddb87402ea7ce68357a3d93b0dbb41857be27f6
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Mar 18 20:17:23 2015 +0200
i965/vec4: Define helper functions to convert a register to a variable index.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit ce030a63993f7192c6aa4c5b9180f9543a6a76bc
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Mar 19 15:08:16 2015 +0200
i965/vec4: Don't lose the force_writemask_all flag during CSE.
And set it in the MOV instructions that copy the temporary to the
original destination if the generator instruction had it set.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 1db9c0cd0c0f4a1a0a4409e4c90cd0f0d0bce68d
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Mar 18 19:51:01 2015 +0200
i965/vec4: Fix handling of multiple register reads and writes in opt_cse().
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit d041a43c0f3e01c9d6f81244cbf1c85d4f3a17d5
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Mar 18 19:46:54 2015 +0200
i965/vec4: Fix handling of multiple register reads and writes during copy propagation.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 588859e18cb597612e56980a65a762ef069363e4
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Mar 18 19:45:40 2015 +0200
i965/vec4: Fix handling of multiple register reads and writes in split_virtual_grfs().
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 9304f60cbe7c348a4771a7746606730bea3ae45f
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Mar 18 19:43:44 2015 +0200
i965/vec4: Fix handling of multiple register reads and writes in opt_register_coalesce().
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 74c7e5d35181d31e4448c614f6aa62c1e1f60694
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Mar 18 19:35:31 2015 +0200
i965: Define method to check whether a backend_reg is inside a given range.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit bf6eb37e0b62fa61c01a32dc5ccb6a7ab00be5f4
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Mar 18 16:03:30 2015 +0200
i965/vec4: Remove dependency of vec4_live_variables on the visitor.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 2e7622a48714934411c84cdd8b6576b2b8ce311d
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Mar 19 15:30:06 2015 +0200
i965/vec4: Trivial copy propagate clean-up.
Fix typo and punctuation in a comment, break long line and add space
before curly bracket.
Reviewed-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
commit 7526ee36bcb89c867f4ec94f4585952195429841
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Mar 18 15:51:45 2015 +0200
i965/vec4: Add argument index and type checks to SEL saturate propagation.
SEL saturate propagation already implicitly relies on these
assumptions.
Reviewed-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
commit 24073b2cd7c15d989a40c1b7bc30e8be200ff328
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Mar 19 18:25:30 2015 +0200
i965/vec4: Fix broken saturate mask check in copy propagation.
try_copy_propagate() was checking the bit of the saturate mask for the
arg-th component of the source to decide whether the whole source
should be saturated (WTF?). We need to swizzle the original saturate
mask and check that for all enabled channels the saturate flag is
either set or unset, as we cannot saturate a subset of destination
components only.
Reviewed-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
commit 18dc59c21295a2a4acf4b69cb7e7ea502c8dd8c8
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Mar 18 15:45:16 2015 +0200
i965/vec4: Don't lose copy propagation saturate bits for not written components.
Reviewed-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
commit a3733defbe4f87acd1b6dca716b861f2dfaea05a
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Mar 18 15:39:03 2015 +0200
Revert "i965/vec4: Don't lose the saturate modifier in copy propagation."
This reverts commit 0dfec59a2785cf7a87ee5128889ecebe810b611b. The
change prevented propagation of copies with the saturate flag set,
making the whole saturate mask tracking completely useless. A proper
fix follows.
Reviewed-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
commit 21c829e5cc6fefa5a42550e9043fade3e9e54e64
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Mar 18 15:40:25 2015 +0200
i965/vec4: Remove unused method definition.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 516d45f78a3bbab0288c49c0f876ebdf4ad05bff
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Mar 18 21:19:28 2015 +0200
i965/vec4: Some more trivial swizzle clean-up.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 430c6bf70e48c08ba4dc9e00f2b88e2230793010
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Mar 18 15:27:58 2015 +0200
i965/vec4: Improve src_reg/dst_reg conversion constructors.
This simplifies the src_reg/dst_reg conversion constructors using the
swizzle utils introduced in a previous patch. It also makes them more
useful by changing their semantics slightly: dst_reg(src_reg) used to
set the writemask to XYZW if the src_reg swizzle was anything other
than XXXX, which was almost certainly not what the caller intended if
the swizzle was non-trivial. After this patch the same components
that are present in the swizzle will be enabled in the resulting
writemask.
src_reg(dst_reg) used to set the first components of the swizzle to
the enabled components of the writemask and then replicate the last
enabled component to fill the swizzle, which, in cases where the
writemask didn't have exactly the first n components set, would in
general not be compatible with the original dst_reg. E.g.:
| ADD(tmp, src_reg(tmp), src_reg(1));
would *not* do what one would expect (add one to each of the enabled
components of tmp) if tmp didn't have a writemask of the described
form (e.g. YZ, YW, XZW would all fail). This pattern actually occurs
in many different places in the VEC4 back-end, it's a wonder that it
hasn't caused piglit failures until now. After this patch
src_reg(dst_reg) will construct a swizzle with each enabled component
at its natural position (e.g. Y at the second position, Z at the
third, and so on). The resulting swizzle will behave like the
identity when used in any instruction with the original writemask.
I've manually verified that *none* of the callers of both conversion
constructors were relying on the previous broken semantics. There are
no piglit regressions on any generation.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 62fd3353387547504966d77f3350afc9b688ef93
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Mar 18 15:21:20 2015 +0200
i965/vec4: Pass argument by reference to src_reg/dst_reg conversion constructors.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 23bda945f570b4f566ed39b4c1de89a957247df7
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Mar 18 21:18:08 2015 +0200
i965/vec4: Remove swizzle_for_size() in favour of brw_swizzle_for_size().
It could be objected that swizzle_for_size() is "faster" than
brw_swizzle_for_size(). It's not measurably better in any reasonable
CPU-bound benchmark on VLV according to the Finnish benchmarking
system (including the SynMark2 DrvShComp shader compilation
benchmark).
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 5bcca9f8dc34a13e34270d284bcf8a49b52bb58e
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Mar 18 15:26:10 2015 +0200
i965/vec4: Remove broken vector size deduction in setup_builtin_uniform_values().
This seemed to be trying to deduce the number of uniform vector
components from the parameter swizzle, but the algorithm would always
give 4 as result. Instead grab the correct number of components from
the GLSL type.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 132cdcc468d0e40f422dd96303a61ee231be1a92
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Mar 18 21:15:05 2015 +0200
i965/vec4: Simplify visitor handling of swizzles using the swizzle utils.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 9a17e4e900256b5be73d935fa5f35c98b3b0d7fe
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Mar 18 21:11:20 2015 +0200
i965/vec4: Simplify opt_register_coalesce() using the swizzle utils.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 05ec72d8ecdba04a81745fbc3ca0df40c7fb8828
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Mar 18 21:09:51 2015 +0200
i965/vec4: Simplify reswizzle() using the swizzle utils.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 7b30493dc4f0b1346fe4c1fe52211f0c0d7ed229
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Mar 18 21:08:52 2015 +0200
i965/vec4: Simplify opt_reduce_swizzle() using the swizzle utils.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit eb9bd3a1b0d6c518f9a38d81c0729feb38474f5a
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Mar 19 16:03:57 2015 +0200
i965: Fix signedness of backend_reg::reg_offset.
And make it 16-bit so it packs nicely with the previous field.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 7e816c7feb8cffa878546eee363240b1b66d5c42
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Mar 18 15:24:06 2015 +0200
i965/vec4: Fix signedness of dst_reg::writemask.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 7678fb9c639f25313f3ae2e2b539e424370d3ec6
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Mar 18 15:22:52 2015 +0200
i965/vec4: Don't use GL types in the IR data structures.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 7bc02c786df437024e2a8582192a66ddb5e40624
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Mar 18 14:32:37 2015 +0200
i965/vec4: Fix signedness of brw_is_single_value_swizzle() argument.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit cff670b009ee8c8a60d1551148bf02038824507b
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Mar 18 14:34:51 2015 +0200
i965: Define some useful swizzle helper functions.
This defines helper functions implementing some common swizzle
transformations that are usually open-coded in the compiler back-end,
causing a lot of clutter. Some optimization passes will become almost
trivial implemented in terms of these functions (e.g.
vec4_visitor::opt_reduce_swizzle()).
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 3cf99701ba6c9e56c9126fdbb74107a31ffcbcfb
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Mon Mar 23 09:12:35 2015 +0200
glsl: fix names in lower_constant_arrays_to_uniforms
Patch changes lowering pass to use unique name for each uniform
so that arrays from different stages cannot end up having same
name.
v2: instead of global counter, use pointer to achieve
unique name (Kenneth Graunke)
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89590
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
Cc: 10.5 10.4 <mesa-stable at lists.freedesktop.org>
commit a6d4a108d27f2b635748c583fe0507f04b3b493e
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Mar 17 19:57:59 2015 -0700
i965/nir: Use signed integer type for booleans
FS instructions with NIR on i965:
total instructions in shared programs: 2663561 -> 2619051 (-1.67%)
instructions in affected programs: 1612965 -> 1568455 (-2.76%)
helped: 5455
HURT: 12
FS instructions with NIR on g4x:
total instructions in shared programs: 2352633 -> 2307908 (-1.90%)
instructions in affected programs: 1441842 -> 1397117 (-3.10%)
helped: 5463
HURT: 11
FS instructions with NIR on ilk:
total instructions in shared programs: 3997305 -> 3934278 (-1.58%)
instructions in affected programs: 2189409 -> 2126382 (-2.88%)
helped: 8969
HURT: 22
FS instructions with NIR on hsw (snb and ivb were similar):
total instructions in shared programs: 4109389 -> 4109242 (-0.00%)
instructions in affected programs: 109869 -> 109722 (-0.13%)
helped: 339
HURT: 190
No SIMD16 programs were gained or lost on any platform
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 41d64fa184671d372f6630deaf2401b00d4e984a
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Mar 17 11:49:04 2015 -0700
i965/nir: Do boolean resolves on GEN <= 5
v2: A couple comment clean-ups from Matt
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit a55af2699feb8f64d6f480b223204da071606721
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Mar 17 11:29:01 2015 -0700
i965: Add a NIR analysis pass for determining when a boolean resolve is needed
v2: Fix the spelling of analyze and re-arrange code for better readability
as per Connor's comments.
v3: Make the naming of things more consistent and add a pile of comments
v4: Stop trying to avoid vectors
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 2612e569e04e29500f81ed233bd86b45ef583495
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Mar 17 13:43:10 2015 -0700
i965/nir: Properly set the predicate on the SEL used in min/max
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 80390f91a0e200ae29a678bda495b91f6452023a
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Mar 17 13:10:19 2015 -0700
i965/nir: Use NIR lowering for ffma for gen < 6
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 235c728020af352ee0f4b7d598c951f4a4e83232
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Mar 17 11:37:09 2015 -0700
i965/nir: Use emit_lrp for emitting flrp
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit a3e05898e9915566ca3cfbfe40a0c9ea92b0d0d9
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Mar 17 11:36:10 2015 -0700
i965/fs: Make emit_lrp return an fs_inst
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 484f9f4fcd53fcaa768e63934a5f74346bfb46a9
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Mar 23 09:54:52 2015 +1000
i965: define I915_PARAM_REVISION
we are broken against the libdrm 2.4.60 minimum specified,
so fix it for now.
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 397b491173f0d2df4deb44d21c170bf16840d507
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Fri Mar 20 12:02:42 2015 +0000
gallivm: Silence unused variable warnings on release builds.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 06ac7178108ff8eb6e3eae103a302d79f0972d1a
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Fri Mar 20 12:01:23 2015 +0000
scons: Silence conversion from 'size_t' to 'type', possible loss of data on MSVC.
Most cases seem harmless, though that might not always be the case. Maybe
one day we can get gcc to complain about these and fix them throughout
the code, but until then let's silence them.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 15c5595bb144d8018ebd922c6914772958cbf2b2
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Fri Mar 20 06:53:09 2015 +0000
scons: Ensure inttypes.h is always pre-included on MSVC.
It's a bit hackish couldn't find another solution. See code comment
for details. The warning is useful, so universally disabling doesn't
sound a good idea.
Fixes
warning C4005: 'xxx' : macro redefinition
Reviewed-by: Brian Paul <brianp at vmware.com>
commit e4d95982ee36097a86c4afec3f34924964978c21
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Thu Mar 19 22:22:26 2015 +0000
scons: Silence MSVC C4351 warning.
It warns about change in MSVC behavior -- array initialisation used to
be non-standard, but is standard now, assuming I understand correctly
http://en.cppreference.com/w/cpp/language/zero_initialization .
Reviewed-by: Brian Paul <brianp at vmware.com>
commit e518d97d7e8136384d5310235e2dd295170bfdcd
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Thu Mar 19 22:09:20 2015 +0000
scons: Match some of LLVM warning options.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 31e47a59ad542c72a56f1eee1b402b23d42e4475
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Thu Mar 19 13:35:18 2015 +0000
scons: Cleanup flex/bison settings specification.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 9c1c657e19ff373315b517ca58f87227b336f3b7
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Thu Mar 19 13:30:19 2015 +0000
scons: Prefer winflexbison, and use --wincompat when available.
This avoids MSVC the warning
warning C4013: 'isatty' undefined; assuming extern returning int
with certain versions of flex.
Reviewed-by: Brian Paul <brianp at vmware.com>
v2: Add win flex-bison link to docs/install.html.
commit 015e8b6384bbdba8421c5dafd4783dba4d3a9182
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Thu Mar 19 11:53:36 2015 +0000
scons: Define YY_USE_CONST on MSVC.
This prevents the MSVC from
warning C4090: 'function' : different 'const' qualifiers
when compiling flex generated lexers.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 357d1fc81aceec6dda866ea74962ee2ddf3aa350
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Fri Mar 20 06:27:59 2015 +0000
scons: Tell MSVC STL library to not use exceptions.
MSVC defaults to no exceptions unless /EH option is passed (which we don't), while
MSVC's STL defaults to use exceptions unless _HAS_EXCEPTIONS=0 is defined,
which we didn't.
This fixes
warning C4530: C++ exception handler used, but unwind semantics are not enabled. Specify /EHsc
Reviewed-by: Brian Paul <brianp at vmware.com>
commit e6330f9f56d6df2c59191513630d837ef3a7b1a9
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Thu Mar 19 13:31:37 2015 +0000
scons: Ensure git_sha1.h's directory exists.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 8f0274c6c645f65a59cb54e14c299cbe131b162d
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Thu Mar 19 13:38:52 2015 +0000
configure: Bail out with MinGW targets.
We only support native Windows builds with SCons.
Tested with:
./configure --host=i686-w64-mingw32
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 8d5c303ab965c928eef684755c2db9cd441e37ad
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Thu Mar 19 11:51:08 2015 +0000
include: Ensure float.h is included for DBL_MAX.
I didn't actually hit the issue in practice, but just happen to notice
while looking at the code.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 60eff442772865bc98f05fe4c18bf468fff39e20
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Thu Mar 19 13:14:41 2015 +0000
st/vdpau: Avoid constness cast warnings.
Fixes MSVC
warning C4090: '=' : different 'const' qualifiers
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
commit fb78cccd7b5c29f9ecd2c86b530449e903dcc093
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Thu Mar 19 22:24:20 2015 +0000
glsl: Disable MSVC switch warning on a per-file basis.
This addresses
...\glsl_parser.cpp(...) : warning C4065: switch statement contains 'default' but no 'case' labels
This is on code generated by bison, which we have little control.
It seems useful to have this warning otherwise enabled.
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit d01a7cdae576162791813c131027a6e675a4e6c7
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Wed Mar 18 14:21:15 2015 +0000
glsl: Avoid GLboolean vs bool arithmetic MSVC warnings.
Note that GLboolean is an alias for unsigned char, which lacks the
implicit true/false semantics that C++/C99 bool have.
Reviewed-by: Brian Paul <brianp at vmware.com>
v2: Change gl_shader::IsES and gl_shader_program::IsES to be bool as
recommended by Ian Romanick.
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 7c7954b09dd28502aedb3eed312672620b9e6b7a
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Mar 21 22:30:52 2015 +0000
galahad: actually remove the driver
Should have been part of 429a4355259(galahad: remove driver). Seems like
I've erroneously committed the trimmed patch.
Reported-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit bbaf22a998f89eb720a3995fa2216512deed5f76
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Mar 19 01:36:08 2015 +0000
egl: cut down static storage size for {Version,ClientAPI}String
Both seems to be excessively long, namely:
ClientAPIString can get up-to 47 based on current code, while the name
of the driver can dictate the length of the VersionString, currently it
is around 11. Let's pad each to 100, rather than the current 1000.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 0bff196b225be13f91ec34da06093a13a9ed425b
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Mar 21 17:21:21 2015 +0000
docs: note the removal of gbm_gallium, galahad and identity
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 429a4355259b3c4fe80838b499a8d8afa41f290a
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Mar 14 22:36:31 2015 +0000
galahad: remove driver
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit 84041bab3f3673c92861d31321a25158831a74fa
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Mar 14 22:36:30 2015 +0000
gallium/docs: remove information about identity driver
Removed from tree.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit 55029b2bab707616eb8a296e1d67cbedde0985b3
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Mar 14 22:36:29 2015 +0000
docs: update the egl_platforms list
Add the missing wayland, null, android and haiku platforms.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit 0d6e7620f35331be301ec3177c0d9236838a845b
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Mar 14 22:36:28 2015 +0000
egl/main: drop platform fbdev specific code
st/egl was the only one which had support for this platform.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit 65a8d4d6ddbed8fd47cd4efc38d4a344add5ec5a
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Mar 14 22:36:27 2015 +0000
winsys/sw/fbdev: remove unused software winsys
st/egl was its only user.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit 1081ed9dc38e7f84b3a7a6e4461a188ae30bd9a2
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Mar 14 22:36:26 2015 +0000
winsys/sw/wayland: remove unused winsys
st/egl was its only user.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit 48c7461d5a0d5cb0f3df5025d7849d27e73a80b3
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Mar 14 22:36:25 2015 +0000
st/gbm: remove state-tracker
st/egl was its only user.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Acked-by: Matt Turner <mattst88 at gmail.com>
commit e8039208c4a771b0c1fb8a44623bcf0261508f87
Author: Roland Scheidegger <sroland at vmware.com>
Date: Sat Mar 21 01:13:54 2015 +0100
llvmpipe: use global llvm context for PIPE_SUBSYSTEM_EMBEDDED
There's 2 reasons why we'd want to use the global context:
1) There still seems to be one memory "leak" left when using multiple llvm
contexts (it is not a true leak as the memory disappears into some still
addressable pool but nevertheless the memory consumption grows). See
http://cgit.freedesktop.org/~jrfonseca/llvm-jitstress/
2) These contexts get kinda big - even when disposing modules etc. after
compiling a shader the LLVMContext can easily be over 100kB. So when there's
lots of llvm contexts arounds it adds up.
The downside is that at least right now this is absolutely not thread safe,
so this only works safely in environments where multiple pipe contexts are not
used concurrently.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit b2dccfd17eb045ce240cda232d40edb5dc1c7c31
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Mar 21 00:54:14 2015 +0000
docs: add news item and link release notes for mesa 10.4.7
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 0030eef62b7090fe790a8e7f0e6ab801a36a8b05
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Mar 21 00:50:13 2015 +0000
docs: Add sha256 sums for the 10.4.7 release
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit cb154bb22116910c462f7a83f4401bd01e15c34d)
commit befb5d1c94a13fddb1ce508714c909479aeb49c3
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Mar 21 00:26:27 2015 +0000
Add release notes for the 10.4.7 release
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit d26f3c1f860e267964d2bd74a86235ae702af3f4)
commit ad6ede260f7b2b7356217c4a0d196edba9ebd5e9
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Mar 20 17:25:15 2015 +1000
mesa: reorder gl_light_attrib
reduces from 2664->2656.
Acked-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Alex Deucher alexander.deucher at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit b99c7defaca2bd89d02c40b0c42dac105b46293c
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Mar 20 17:21:57 2015 +1000
mesa: reorder gl_framebuffer
this reduces it from 1088 -> 1080 bytes
Acked-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Alex Deucher alexander.deucher at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 727eb4c4e7edc3eeb8126000379d9e2bab985773
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Mar 20 17:13:03 2015 +1000
mesa: fix hole in vertex_array_object
this just removes 4 bytes from this object.
Acked-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Alex Deucher alexander.deucher at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 974e4783a5c7ee9d378124f6dcfc6a0ffd9727db
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Mar 20 17:10:57 2015 +1000
mesa: repack gl_texture_attrib.
This removes a hole, and puts the large allocation at the end,
Acked-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Alex Deucher alexander.deucher at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 2dbd8284e72c8b3fe412a7e1c7734e9685fedd7d
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Mar 20 17:05:40 2015 +1000
mesa: reduce gl_colorbuffer_attrib and gl_fog_attrib
These 392->388 and 72->68.
Acked-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Alex Deucher alexander.deucher at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 2c016ed35fff36e39a457db8efbc82ec90d4f5da
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Mar 20 17:01:55 2015 +1000
mesa: reorder gl_image_unit
reduces 40->32
but reduces use in context from 7680->6144.
Acked-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Alex Deucher alexander.deucher at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 0ff4726a0632b9c15d349cd05070b57fd61f1f98
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Mar 20 16:54:40 2015 +1000
mesa: reorder gl_program, gl_shader, gl_shader_program
gl_program : 1344->1336
gl_shader: 488->472
gl_shader_program: 352->344.
Acked-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Alex Deucher alexander.deucher at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 7b634fed5918bb55b7335170a57b297830d0817f
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Mar 20 16:52:44 2015 +1000
mesa: reorder gl_transform_feedback_object
Reduces size from 184 to 176 bytes.
Acked-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Alex Deucher alexander.deucher at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit e17b0435c54bf14d9d1c9a9815814eb11fc66636
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Mar 20 16:26:59 2015 +1000
mesa: reorder prog_instruction
reduces size from 64 to 56 bytes.
Acked-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Alex Deucher alexander.deucher at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 401b11843b91112e2f5957c2b174b564cd1825b3
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Mar 20 16:07:24 2015 +1000
mesa: reorder gl_array_attrib
drops 80 bytes to 72.
Acked-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Alex Deucher alexander.deucher at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit b3f6e0bb587457cbfab3c04cae9d062843369eb9
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Mar 20 16:02:46 2015 +1000
mesa: reorder gl_client_array
drops from 56 to 48 bytes,
drops gl_vertex_array_object from 4584 to 4320 bytes
Acked-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Alex Deucher alexander.deucher at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit cbaff50828205188d738f5727261b8a95861ef38
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Mar 20 16:00:10 2015 +1000
mesa: reorder gl_texture_unit
drops size from 520 -> 512 bytes,
which then makes gl_texture_attrib go from 99984 to 98440.
Acked-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Alex Deucher alexander.deucher at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 83606b490491adbe9f3b8af9413f2a23b7896ff1
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Mar 20 15:59:01 2015 +1000
mesa: reorder gl_point_attrib
this drops the size from 52 bytes to 48 bytes.
Acked-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Alex Deucher alexander.deucher at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 684c91401472a3bf60c219901dbc2727aab8c351
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Mar 20 15:58:09 2015 +1000
mesa: reorder gl_multisample_attrib
drops size from 28 bytes to 20.
Acked-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Alex Deucher alexander.deucher at amd.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit a04b520890c669ce012b4b18165392dcabe0b27b
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Thu Mar 19 16:44:14 2015 -0700
i965/fs: Use correct null destination register in cmod tests
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89670
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Cc: Vinson Lee <vlee at freedesktop.org>
commit ccb9cbc849af50c435ec69498281cd3cef52d02e
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Thu Mar 19 20:58:58 2015 -0400
i965/fs: bail on move-to-flag in sel peephole
Fixes a piglit regression
(shaders/glsl-fs-vec4-indexing-temp-dst-in-nested-loop-combined) with
my series for GVN.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Signed-off-by: Connor Abbott <cwabbott0 at gmail.com>
commit 1cc00f1875e7b830db27945090ad78be41157dc9
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Feb 26 13:58:21 2015 +0200
i965: Mask out unused Align16 components in brw_untyped_atomic.
This is currently not a problem because the vec4 visitor happens to
mask out unused components from the destination, but it might become
an issue when we start using atomics without writeback message. In
any case it seems sensible to set it again here because the
consequences of setting the wrong writemask (random graphics memory
corruption) are difficult to debug and can easily go unnoticed.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
commit 959d16e38e007b29349d7371fb390a5449c88341
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Feb 26 12:56:19 2015 +0200
i965: Pass number of components explicitly to brw_untyped_atomic and _surface_read.
And calculate the message response size based on the number of
components rather than the other way around. This simplifies their
interface somewhat and allows the caller to request a writeback
message with more than one vector component in SIMD4x2 mode.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
commit a815cd8449c207956176020e752cd0051ed842ec
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Feb 26 17:24:03 2015 +0200
i965: Don't disable exec masking for sampler message sends.
This was telling the sampler to do texture fetches for *all* channels
in the non-constant surface index case, what could have reduced
throughput unnecessarily when some of the channels were disabled by
control flow.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
commit a902a5d6ba921ab006496aeecab0f68bca7ffb09
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Mar 19 15:44:24 2015 +0200
i965: Factor out logic to build a send message instruction with indirect descriptor.
This is going to be useful because the Gen7+ uniform and varying pull
constant, texturing, typed and untyped surface read, write, and atomic
generation code on the vec4 and fs back-end all require the same logic
to handle conditionally indirect surface indices. In pseudocode:
| if (surface.file == BRW_IMMEDIATE_VALUE) {
| inst = brw_SEND(p, dst, payload);
| set_descriptor_control_bits(inst, surface, ...);
| } else {
| inst = brw_OR(p, addr, surface, 0);
| set_descriptor_control_bits(inst, ...);
| inst = brw_SEND(p, dst, payload);
| set_indirect_send_descriptor(inst, addr);
| }
This patch abstracts out this frequently recurring pattern so we can
now write:
| inst = brw_send_indirect_message(p, sfid, dst, payload, surface)
| set_descriptor_control_bits(inst, ...);
without worrying about handling the immediate and indirect surface
index cases explicitly.
v2: Rebase. Improve documentatation and commit message. (Topi)
Preserve UW destination type cargo-cult. (Topi, Ken, Matt)
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Acked-by: Kenneth Graunke <kenneth at whitecape.org>
commit fd149628e142af769c1c0ec037bc297d8a3e871f
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Jan 22 17:08:23 2015 +0200
i965: Set nr_params to the number of uniform components in the VS/GS path.
Both do_vs_prog and do_gs_prog initialize brw_stage_prog_data::nr_params to
the number of uniform *vectors* required by the shader rather than the number
of uniform components, contradicting the comment. This is inconsistent with
what the state upload code and scalar path expect but it happens to work until
Gen8 because vec4_visitor interprets it as a number of vectors on construction
and later on overwrites its original value with the number of uniform
components referenced by the shader.
Also there's no need to add the number of samplers, they're not actually
passed in as uniforms.
Fixes a memory corruption issue on BDW with SIMD8 VS.
Cc: "10.5" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 706b916960c898cfc24110f14fa4def84caaba93
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Mar 4 12:53:45 2015 -0800
i965/skl: Break down SIMD16 3-source instructions when required.
Several steppings of Skylake fail when using SIMD16 with 3-source
instructions (such as MAD).
This implements WaDisableSIMD16On3SrcInstr and fixes ~190 Piglit
tests.
Based on a patch by Neil Roberts.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Neil Roberts <neil at linux.intel.com>
commit bc4b18d2977a94a6fb513bf5955236a0e92298ca
Author: Neil Roberts <neil at linux.intel.com>
Date: Thu Mar 19 18:18:49 2015 +0000
i965: Refactor SIMD16-to-2xSIMD8 checks.
The places that were checking whether 3-source instructions are
supported have now been combined into a small helper function. This
will be used in the next patch to add an additonal restriction.
Based on a patch by Kenneth Graunke.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit c02c4b567ce001f6605c46e71e089692b837bf26
Author: Neil Roberts <neil at linux.intel.com>
Date: Wed Mar 4 14:13:40 2015 +0000
i965: Store the GPU revision number in brw_context
brwContextInit now queries the GPU revision number via a new parameter
for DRM_I915_GETPARAM. This new parameter requires a kernel patch and
a patch to libdrm. If the kernel doesn't support it then it will
continue but set the revision number to -1. The intention is to use
this to implement workarounds that are only needed on certain
steppings of the GPU.
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 2fd21d8a84bd28461c964e2ab350389a55b7f001
Author: Fredrik Höglund <fredrik at kde.org>
Date: Thu Mar 19 19:44:57 2015 +0100
mesa: Make sure the buffer exists in _mesa_lookup_bufferobj_err
Generate GL_INVALID_OPERATION and return NULL when the buffer object
hasn't been created. All callers expect this.
v2: Use a more concise error message.
Cc: Laura Ekstrand <laura at jlekstrand.net>
Reviewed-by: Laura Ekstrand <laura at jlekstrand.net>
commit 9d97cd2e3e993658ebe038f4652dc59c3ae56031
Author: Dave Airlie <airlied at gmail.com>
Date: Wed Mar 18 11:46:45 2015 +1000
u_primconvert: add primitive restart support
This add primitive restart support to the prim conversion.
This involves changing the API for the translate functions
as we need to pass the prim restart index and the original
number of indices into the translate functions.
primitive restart is support for quads, quad strips
and polygons.
This deal with the case where the actual number of output
primitives is less than the initially calculated number,
by filling the rest of the output primitives with the restart
index, the other option is to reduce the output prim number,
but that will make the generator code a bit messier.
Reviewed-by: Brian Paul <brianp at vmware.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 201aef9d1370ff524f856b725d2328c4f48199e8
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Feb 24 12:48:56 2015 -0800
i965/fp: Emit discard jumps.
This should improve the performance of any shaders using the KIL
instruction. I'm a bit surprised we missed this.
Unfortunately, I have not been able to measure any performance
improvements from this patch. It does make ARB_fragment_program
behave similarly to GLSL code.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 8a0946f3b1522e5f91afe14c8c3b22ba6009ed04
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Mar 5 15:48:39 2015 -0800
i965/fs: Make an emit_discard_jump() function to reduce duplication.
This is already copied in two places, and I want to copy it to a third
place.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Carl Worth <cworth at cworth.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 09bfa326a90a0ec1ddce0dc971d7d4b429884266
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Tue Mar 17 12:55:41 2015 -0700
main: Add TEXTURE_CUBE_MAP support in CopyTextureSubImage3D.
So it turns out that this doesn't actually fix any bugs or add any features,
stictly speaking. However, it does avoid a lot of kludginess. Previously, if
you called
glCopyTextureSubImage3D(texcube, 0, 0, 0, zoffset = 3, ...
it would grab the texture image object for face = 0 in teximage.c instead of
the desired face = 3. But Line 274 of brw_blorp_blit.cpp would correct for
this by updating the slice to 3.
This commit does the correct thing before calling any drivers,
which should make the functionality much more robust and uniform across all
drivers.
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 037e36a8aad623b0e16e4d69774dbeb5bcf456d1
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Thu Mar 19 10:43:17 2015 -0700
main: Simplify debug messages for CopyTex*SubImage*D.
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit a44b95cd574ecab4a4c41c6380c82db6029ad114
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Mar 16 12:14:10 2015 -0700
glsl: Annotate as_foo functions that the this pointer cannot be NULL
We use the idiom
ir_foo *x = y->as_foo();
if (x == NULL)
return;
all over the place. GCC generates some quite lovely code for this.
One such example:
340a5b: 83 7d 18 04 cmpl $0x4,0x18(%rbp)
340a5f: 0f 85 06 04 00 00 jne 340e6b
340a65: 48 85 ed test %rbp,%rbp
340a68: 0f 84 fd 03 00 00 je 340e6b
This case used as_expression() (ir_type_expression is 4). Note that it
checks the ir_type, then checks that the pointer isn't NULL. There is
some disconnect in GCC around the condition in the as_foo functions.
return ir_type == ir_type_##TYPE ? (ir_##TYPE *) this : NULL; \
It believes "this" could be NULL, so it emits check outside the function
just for fun.
This patch uses assume() to tell GCC that it need not bother with extra
NULL checking of the pointer returned by the as_foo functions.
text data bss dec hex filename
4836430 158688 26248 5021366 4c9eb6 i965_dri-before.so
4836173 158688 26248 5021109 4c9db5 i965_dri-after.so
v2: Replace 'if (this == NULL) unreachable("this cannot be NULL")' with
assume(this != NULL). Suggested by Ilia Mirkin.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit bf9d921936305e1514d4ce7a162c4f81eba3e9f5
Author: Paul Berry <stereotype441 at gmail.com>
Date: Fri Jan 10 06:48:11 2014 -0800
main: Change the type argument of use_shader_program() to gl_shader_stage.
This allows it to be called from a loop.
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 57b2652322c833f9007203488526571023279cfc
Author: Paul Berry <stereotype441 at gmail.com>
Date: Fri Jan 10 06:35:09 2014 -0800
main: Clean up a strange construction in use_shader_program().
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 46c35c61e9c5c1b56fdd9fcd4eb45591dd16d21d
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Mar 18 15:18:54 2015 -0700
i965/nir: Sort uniforms direct-first and use two different uniform registers
Previously, we put all the uniforms into one big array. The problem with
this approach is that, as soon as there was one indirect array acces, the
backend would decide that the entire large array should be pull constants.
This commit splits the array in half: first direct-only uniforms and then
potentially-indirect uniforms. This may not be optimal, but it does let
the backend promote things to push constants.
Shader-db results on HSW:
total instructions in shared programs: 4114840 -> 4112172 (-0.06%)
instructions in affected programs: 43316 -> 40648 (-6.16%)
helped: 116
HURT: 0
v2: Set param_size[num_direct_uniforms] only if we have indirect uniforms.
This caused a bug that, strangely enough, only showed up on Broadwell
vertex shaders.
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 8a33f95b7a1128b5e46bd30306961bac72f5f12e
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Mar 18 15:05:28 2015 -0700
nir/lower_io: Add a assign_locations function that sorts by [in]direct use
v2: Delete the set of indirectly accessed variables when we're done with it
v3: Rename from _packed to _scalar
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 25db44a84597960a6aea6b252bcf2c3d7e17fc74
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Mar 18 15:04:15 2015 -0700
nir/lower_io: Make variable location assignment a manual operation
Previously, we just assigned variable locations in nir_lower_io. Now, we
force the user to assign variable locations for us. This gives the backend
a bit more control over where variables are placed.
v2: Rename from _packed to _scalar
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 639115123efe7f71d432e24b1719adda7d23e97e
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Mar 18 12:34:09 2015 -0700
nir: Use a list instead of a hash_table for inputs, outputs, and uniforms
We never did a single hash table lookup in the entire NIR code base that I
found so there was no real benifit to doing it that way. I suppose that
for linking, we'll probably want to be able to lookup by name but we can
leave building that hash table to the linker. In the mean time this was
causing problems with GLSL IR -> NIR because GLSL IR doesn't guarantee us
unique names of uniforms, etc. This was causing massive rendering isues in
the unreal4 Sun Temple demo.
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 8f255f948bd5c7b8fd56c8f72f6a9a7f626fca29
Author: Brian Paul <brianp at vmware.com>
Date: Thu Mar 19 08:48:56 2015 -0600
gallivm: remove unused 'builder' variable
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 1cd37459110402f8a5c07fe0aa0f1198b4bb1da1
Author: Brian Paul <brianp at vmware.com>
Date: Thu Mar 19 08:10:19 2015 -0600
mesa: use more descriptive error messages for glUniform errors
Different errors for type mismatches, size mismatches and matrix/
non-matrix mismatches. Use a common format of "uniformName"@location
in the messags.
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
commit b0d422cd2a99d2fd26ab11880d5d8410ebfc64b2
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Mar 16 12:18:31 2015 -0700
i965/fs: Print spills:fills and number of promoted constants.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit b616164c95cb495ce43f6b61dc805ed911a85e89
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Fri Jan 23 17:31:12 2015 -0800
i965/fs: Emit better b2f of an expression on GEN4 and GEN5
On platforms that do not natively generate 0u and ~0u for Boolean
results, b2f expressions that look like
f = b2f(expr cmp 0)
will generate better code by pretending the expression is
f = ir_triop_sel(0.0, 1.0, expr cmp 0)
This is because the last instruction of "expr" can generate the
condition code for the "cmp 0". This avoids having to do the "-(b & 1)"
trick to generate 0u or ~0u for the Boolean result. This means code like
mov(16) g16<1>F 1F
mul.ge.f0(16) null g6<8,8,1>F g14<8,8,1>F
(+f0) sel(16) m6<1>F g16<8,8,1>F 0F
will be generated instead of
mul(16) g2<1>F g12<8,8,1>F g4<8,8,1>F
cmp.ge.f0(16) g2<1>D g4<8,8,1>F 0F
and(16) g4<1>D g2<8,8,1>D 1D
and(16) m6<1>D -g4<8,8,1>D 0x3f800000UD
v2: When the comparison is either == 0.0 or != 0.0 use the knowledge
that the true (or false) case already results in zero would allow better
code generation by possibly avoiding a load-immediate instruction.
v3: Apply the optimization even when neither comparitor is zero.
Shader-db results:
GM45 (0x2A42):
total instructions in shared programs: 3551002 -> 3550829 (-0.00%)
instructions in affected programs: 33269 -> 33096 (-0.52%)
helped: 121
Iron Lake (0x0046):
total instructions in shared programs: 4993327 -> 4993146 (-0.00%)
instructions in affected programs: 34199 -> 34018 (-0.53%)
helped: 129
No change on other platforms.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Tapani Palli <tapani.palli at intel.com>
commit 036e347f3c129bb547137aed955e75062fca09b8
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Mar 18 14:23:41 2015 -0700
util: Optimize _mesa_roundeven with SSE 4.1.
The SSE 4.1 ROUND instructions let us implement roundeven directly.
Otherwise we assume that the rounding mode has not been modified (as we
do in the rest of Mesa) and use rint().
glibc uses the ROUND instruction in rint() after a cpuid check. This
patch just lets us inline it directly when we're already building for
SSE 4.1.
Reviewed-by: Carl Worth <cworth at cworth.org>
commit 5de86102f917d9f3a229daec8f107afb77246feb
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu Mar 12 11:34:05 2015 -0700
util: Add a roundeven test.
Reviewed-by: Carl Worth <cworth at cworth.org>
commit dd0d3a2c0fb388745519c8a3be800720541eccfe
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Mar 10 17:55:21 2015 -0700
mesa: Replace _mesa_round_to_even() with _mesa_roundeven().
Eric's initial patch adding constant expression evaluation for
ir_unop_round_even used nearbyint. The open-coded _mesa_round_to_even
implementation came about without much explanation after a reviewer
asked whether nearbyint depended on the application not modifying the
rounding mode. Of course (as Eric commented) we rely on the application
not changing the rounding mode from its default (round-to-nearest) in
many other places, including the IROUND function used by
_mesa_round_to_even!
Worse, IROUND() is implemented using the trunc(x + 0.5) trick which
fails for x = nextafterf(0.5, 0.0).
Still worse, _mesa_round_to_even unexpectedly returns an int. I suspect
that could cause problems when rounding large integral values not
representable as an int in ir_constant_expression.cpp's
ir_unop_round_even evaluation. Its use of _mesa_round_to_even is clearly
broken for doubles (as noted during review).
The constant expression evaluation code for the packing built-in
functions also mistakenly assumed that _mesa_round_to_even returned a
float, as can be seen by the cast through a signed integer type to an
unsigned (since negative float -> unsigned conversions are undefined).
rint() and nearbyint() implement the round-half-to-even behavior we want
when the rounding mode is set to the default round-to-nearest. The only
difference between them is that nearbyint() raises the inexact
exception.
This patch implements _mesa_roundeven{f,}, a function similar to the
roundeven function added by a yet unimplemented technical specification
(ISO/IEC TS 18661-1:2014), with a small difference in behavior -- we
don't bother raising the inexact exception, which I don't think we care
about anyway.
At least recent Intel CPUs can quickly change a subset of the bits in
the x87 floating-point control register, but the exception mask bits are
not included. rint() does not need to change these bits, but nearbyint()
does (twice: save old, set new, and restore old) in order to raise the
inexact exception, which would incur some penalty.
Reviewed-by: Carl Worth <cworth at cworth.org>
commit bb22aa08e4b08c9688c5d5c6558ac01663d0163a
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Mar 17 19:17:15 2015 -0700
i965/fs: Ignore type in cmod prop if scan_inst is CMP.
total instructions in shared programs: 6263270 -> 6203091 (-0.96%)
instructions in affected programs: 2606529 -> 2546350 (-2.31%)
helped: 14301
GAINED: 5
LOST: 3
Revewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit e1f3ddef8c9928d9b8e845b811dc08983c541f99
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Mar 17 12:10:58 2015 -0700
i965/nir: Make our environment variable checking smarter
Before, we enabled NIR if you set INTEL_USE_NIR to anything which mean that
INTEL_USE_NIR=false would actually turn on NIR. In preparation for turning
NIR on by default, this commit makes it smarter by allowing the
INTEL_USE_NIR variable to work as either a force-enable or a force-disable.
Reviewed-by: Mark Janes <mark.a.janes at intel.com>
commit 37e3a116f8ae09d0fa894d126d081a1af24ec14f
Author: Dave Airlie <airlied at gmail.com>
Date: Mon Mar 16 15:21:55 2015 +1000
egl: don't fill client apis string forever.
We never reset the string on eglTerminate, so it grows
for ever on multiple eglInitialise.
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit cebc62f1060c815e3b5a1bd3728c3d909db3d2b8
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Wed Mar 18 14:25:19 2015 +0000
swrast: Use BITFIELD64_BIT for arrayAttribs.
As VARYING_SLOT_MAX can be bigger than 32.
I'll probably stop building swrast with MSVC in the near future, but this
seems a real bug regardless.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit d3e9aa8d88e6684235bb0be549551d1402ef8881
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Wed Mar 18 14:22:41 2015 +0000
scons: Don't link program_lexer.l/y twice.
program/lex.yy.c and program/program_parse.tab.c is already included in
the PROGRAM_FILES variable.
We still need to specify the dependency relationship though.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit a56f1a8b32a2cafdd4e46c0d48a1a252d0e3c0ae
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Wed Mar 18 14:19:10 2015 +0000
gallivm: Use INFINITY directly.
Already done below.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 1d30fd85dd2a240d4ccafc9a9eca55a129306cf5
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Wed Mar 18 14:18:28 2015 +0000
scons: Silence MSVC warnings about overflows in constant arithmetic.
These get triggered even when using the standard C99 INFINITY/NAN
constants.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit bbac03ecca51fdbedf3c569c68322043c8e93fae
Author: José Fonseca <jfonseca at vmware.com>
Date: Tue Nov 25 22:27:04 2014 +0000
scons: Disable MSVC signed/unsigned mismatch warnings.
By default gcc ignores the issue, and as result code that mixes
signed/unsigned is so widespread through the code base that it ends up
being little more than noise, potentially obscuring more pertinent
warnings.
Maybe one day we enable the corresponding gcc warnings and cleanup, but
until then, this change disables them.
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit 2ccfce3f4ce72e1ae3e85c44193b3343e23572d8
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Wed Mar 18 13:26:31 2015 -0700
docs: Update progress on ARB_direct_state_access.
Acked-by: Matt Turner <mattst88 at gmail.com>
commit 627991dbf74ce5aee9ce75155fc27a429bdd0548
Author: Brian Paul <brianp at vmware.com>
Date: Wed Mar 18 12:25:03 2015 -0600
dri: add _glapi_set_nop_handler(), _glapi_new_nop_table() to dri_test.c
I wasn't aware of these _glapi_ stub functions when I committed
4bdbb588a9d385509f9168e38bfdb76952ba469c. Fixes "make check"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89662
Reviewed-by: Mark Janes <mark.a.janes at intel.com>
commit 9263986401c90a309d167121bc98c47b24c39d3d
Author: Brian Paul <brianp at vmware.com>
Date: Tue Mar 17 11:57:34 2015 -0600
mesa: remove MSVC warning pragmas
Removing this block of pragmas doesn't seem to increase the number of
warning generated by MSVC. Other than signed/unsigned comparison warnings
there's very few other warnings nowadays.
Acked-by: Matt Turner <mattst88 at gmail.com>
commit ea1b066a34dccd3bf1fe8bba52a586fff4158601
Author: Brian Paul <brianp at vmware.com>
Date: Tue Mar 17 11:50:35 2015 -0600
mesa: add void to format_array_format_table_init() declaration
Silences an MSVC warning where it's called from call_once().
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 9fbbd60c1da4467683d93540c64164ad337ce454
Author: Brian Paul <brianp at vmware.com>
Date: Fri Mar 13 13:12:12 2015 -0600
mapi: move some #includes from .h file to .c files
Just include things where they're needed.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 4009d22b61e76850b1b725f4e491da05c2406fa4
Author: Brian Paul <brianp at vmware.com>
Date: Fri Mar 13 12:05:01 2015 -0600
mesa: make _mesa_alloc_dispatch_table() static
Never called from outside of context.c
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 4bdbb588a9d385509f9168e38bfdb76952ba469c
Author: Brian Paul <brianp at vmware.com>
Date: Fri Mar 13 11:43:44 2015 -0600
mesa: reimplement dispatch table no-op function handling
Use the new _glapi_new_nop_table() and _glapi_set_nop_handler() to
improve how we handle calling no-op GL functions.
If there's a current context for the calling thread, generate a
GL_INVALID_OPERATION error. This will happen if the app calls an
unimplemented extension function or it calls an illegal function
between glBegin/glEnd.
If there's no current context, print an error to stdout if it's a debug
build.
The dispatch_sanity.cpp file has some previous checks removed since
the _mesa_generic_nop() function no longer exists.
This fixes the piglit gl-1.0-dlist-begin-end and gl-1.0-beginend-coverage
tests on Windows.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 201e36e77d6ca616f75f14d5f1c31f0062ae4366
Author: Brian Paul <brianp at vmware.com>
Date: Fri Mar 13 10:20:29 2015 -0600
mapi: add new _glapi_new_nop_table() and _glapi_set_nop_handler()
_glapi_new_nop_table() creates a new dispatch table populated with
pointers to no-op functions.
_glapi_set_nop_handler() is used to register a callback function which
will be called from each of the no-op functions.
Now we always generate a separate no-op function for each GL entrypoint.
This allows us to do proper stack clean-up for Windows __stdcall and
lets us report the actual function name in error messages. Before this
change, for non-Windows release builds we used a single no-op function
for all entrypoints.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit aee26d292f165438577426f5e62a62ec2a1514c9
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Mar 18 09:51:57 2015 -0400
freedreno/ir3: fix infinite recursion in sched
One more case we need to handle. One of the src instructions for the
indirect could also end up being ourself.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 62cc003b7d2031c2321f4698bd5b97cc97261c07
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Mar 18 09:51:27 2015 -0400
freedreno: fix spelling
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 42715ad7932cdcfaffd8e514a200a461d6133927
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Mar 18 01:50:03 2015 +0100
docs/GL3: don't list nv30
Suggested by Ilia Mirkin.
commit 4e46af0195f7f9000ee0633685756d26f745499a
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Mar 16 23:19:17 2015 +0100
docs/GL3: don't list swrast
Let's face it: This driver is unlikely to get more love.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 2b5379651f0b4dca9c1187b53b8466ff265ceb80
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Mar 16 23:15:22 2015 +0100
docs/GL3: don't list r300
r300g already supports everything it can. There's no point in listing
the driver here.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit a984abdad39df2d8ceb4c46e11f4ce1344c36c86
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Mar 17 17:47:17 2015 +0100
radeonsi: increase coords array size for radeon_llvm_emit_prepare_cube_coords
radeon_llvm_emit_prepare_cube_coords uses coords[4] in some cases (TXB2 etc.)
Discovered by Coverity. Reported by Ilia Mirkin.
Cc: 10.5 10.4 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 8475526a3842580f00a043bca8f821e14e9f5eb7
Author: Jonathan Gray <jsg at jsg.id.au>
Date: Tue Mar 17 13:16:05 2015 +1100
configure: check if compiler supports -Werror=vla.
Check if the compiler supports -Werror=vla before using it.
-Wvla was introduced with GCC 4.3 and is not present in 4.2.
Fixes the build on OpenBSD.
v2: Fix statement order, and quote $save_CFLAGS.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89433
Signed-off-by: Jonathan Gray <jsg at jsg.id.au>
Signed-off-by: Jose Fonseca <jfonseca at vmware.com>
commit eeb504e0ae7796e7ba475f6e9d6c26daa6b06608
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Wed Mar 11 12:21:29 2015 +0000
i965: Defer the throttle until we submit new commands
Currently, we throttle before the user begins preparing commands for the
next frame when we acquire the draw/read buffers. However, construction
of the command buffer can itself take significant time relative to the
frame time. If we move the throttle from the buffer acquire to the
command submit phase we can allow the user to improve concurrency
between the CPU and GPU (i.e. reduce the amount of time we waste inside
the throttle).
v2: Whitespace + delay throttling until after the next submission for
greater parallelism
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter at ffwll.ch>
Cc: Kenneth Graunke <kenneth at whitecape.org>
Cc: Ben Widawsky <ben at bwidawsk.net>
Cc: Kristian Høgsberg <krh at bitplanet.net>
Cc: Chad Versace <chad.versace at linux.intel.com>
Cc: Ian Romanick <idr at freedesktop.org>
Reviewed-by: Chad Versace <chad.versace at linux.intel.com> [v1]
commit 64788b2e8dc2ddedc2712ed02b7e9096638b7bae
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Fri Sep 19 10:10:13 2014 +0100
i965: Throttle to the previous frame
In order to facilitate the concurrency offered by triple buffering and to
offset the latency induced by swapping via an external process, which
may incur extra rendering itself, only throttle to the previous frame
and not the last. The second issue that mostly affects swap benchmarks,
but also can incur jitter in the throttling, is that the throttle bo is
closer to the next SwapBuffers rather than immediately after the previous
SwapBuffers. Throttling to the previous frame doubles the maximum possible
latency at the benefit of improving throughput and reducing jitter.
v2: Rename "first_post_swapbuffer" batches array to a plain
throttle_batch[] as the pluralisation was contorting the name and not
making it clear as to whether it was the first batch or first_post_swap
batch. Not least of which was that not all throttle points are SwapBuffers.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter at ffwll.ch>
Cc: Kenneth Graunke <kenneth at whitecape.org>
Cc: Ben Widawsky <ben at bwidawsk.net>
Cc: Kristian Høgsberg <krh at bitplanet.net>
Cc: Chad Versace <chad.versace at linux.intel.com>
Cc: Ian Romanick <idr at freedesktop.org>
Reviewed-by: Chad Versace <chad.versace at linux.intel.com>
commit 8b9bd19021c0efef33d66ae24f8871b826d66e8a
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Thu Feb 26 11:25:18 2015 +0000
i965: Throttle rendering to an fbo
When rendering to an fbo, even though it may be acting as a winsys
frontbuffer or just generally, we never throttle. However, when rendering
to an fbo, there is no natural frame boundary. Conventionally we use
SwapBuffers and glFinish, but potential callers avoid often glFinish for
being too heavy handed (waiting on all outstanding rendering to complete).
The kernel provides a soft-throttling option for this case that waits for
rendering older than 20ms to be complete (that's a little too lax to be
used for swapbuffers, but is here a useful safety net). The remaining
choice is then either never to throttle, throttle after every draw call,
or at after intermediate user defined point such as glFlush and thus all the
implied flushes. This patch opts for the latter as that is the current
method used for flushing to front buffers.
v2: Defer the throttling from inside the flush to the next
intel_prepare_render() and switch non-fbo frontbuffer throttling over to
use the same lax method. The issuing being that
glFlush()/intel_prepare_read() is just as likely to be called inside a
tight loop and not at "frame" boundaries.
v3: Rename from need_front_throttle to need_flush_throttle to avoid any
ambiguity between front buffer rendering and fbo rendering. (Chad)
v4: Whitespace
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter at ffwll.ch>
Cc: Kenneth Graunke <kenneth at whitecape.org>
Cc: Ben Widawsky <ben at bwidawsk.net>
Cc: Kristian Høgsberg <krh at bitplanet.net>
Cc: Chad Versace <chad.versace at linux.intel.com>
Cc: Ian Romanick <idr at freedesktop.org>
Reviewed-by: Chad Versace <chad.versace at linux.intel.com>
commit 27bf37ba05b69ebf6f373d1637a26b4839265921
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Mar 16 15:08:04 2015 -0700
nir/peephole_select: Allow uniform/input loads and load_const
Shader-db results on HSW:
total instructions in shared programs: 4174156 -> 4157291 (-0.40%)
instructions in affected programs: 145397 -> 128532 (-11.60%)
helped: 383
HURT: 0
GAINED: 20
LOST: 22
There are two more tests lost than gained. However, comparing this with
GLSL IR vs. NIR results, the overall delta is reduced from 85/44
gained/lost on current master to 71/32 with this commit. Therefore, I
think it's probably a boon since we are getting "closer" to where we were
before.
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 1be862c0c4965a0184908df736a30d354498ba3d
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Mar 16 14:55:00 2015 -0700
nir/peephole_select: Copy instructions into the block before the if
Previously we tried to do poor-man's copy propagation as we created the
select instructions. Instead, this commit just moves the instructions from
the blocks inside the if into the block before. Copy propagation will take
care of making sure we don't have any extra mov's in there for us.
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 8cf40ed05dbd3a62ee817e7ebc9409cf327c10ce
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Mar 16 14:45:54 2015 -0700
nir/peephole_select: Rename are_all_move_to_phi and use a switch
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit cc5ddd584d17abd422ae4d8e83805969485740d9
Author: Mario Kleiner <mario.kleiner.de at gmail.com>
Date: Thu Mar 12 20:34:06 2015 +0100
glx: Handle out-of-sequence swap completion events correctly. (v2)
The code for emitting INTEL_swap_events swap completion
events needs to translate from 32-Bit sbc on the wire to
64-Bit sbc for the events and handle wraparound accordingly.
It assumed that events would be sent by the server in the
order their corresponding swap requests were emitted from
the client, iow. sbc count should be always increasing. This
was correct for DRI2.
This is not always the case under the DRI3/Present backend,
where the Present extension can execute presents and send out
completion events in a different order than the submission
order of the present requests, due to client code specifying
targetMSC target vblank counts which are not strictly
monotonically increasing. This confused the wraparound
handling. This patch fixes the problem by handling 32-Bit
wraparound in both directions. As long as successive swap
completion events real 64-Bit sbc's don't differ by more
than 2^30, this should be able to do the right thing.
How this is supposed to work:
awire->sbc contains the low 32-Bits of the true 64-Bit sbc
of the current swap event, transmitted over the wire.
glxDraw->lastEventSbc contains the low 32-Bits of the 64-Bit
sbc of the most recently processed swap event.
glxDraw->eventSbcWrap is a 64-Bit offset which tracks the upper
32-Bits of the current sbc. The final 64-Bit output sbc
aevent->sbc is computed from the sum of awire->sbc and
glxDraw->eventSbcWrap.
Under DRI3/Present, swap completion events can be received
slightly out of order due to non-monotic targetMsc specified
by client code, e.g., present request submission:
Submission sbc: 1 2 3
targetMsc: 10 11 9
Reception of completion events:
Completion sbc: 3 1 2
The completion sequence 3, 1, 2 would confuse the old wraparound
handling made for DRI2 as 1 < 3 --> Assumes a 32-Bit wraparound
has happened when it hasn't.
The client can queue multiple present requests, in the case of
Mesa up to n requests for n-buffered rendering, e.g., n = 2-4 in
the current Mesa GLX DRI3/Present implementation. In the case of
direct Pixmap presents via xcb_present_pixmap() the number n is
limited by the amount of memory available.
We reasonably assume that the number of outstanding requests n is
much less than 2 billion due to memory contraints and common sense.
Therefore while the order of received sbc's can be a bit scrambled,
successive 64-Bit sbc's won't deviate by much, a given sbc may be
a few counts lower or higher than the previous received sbc.
Therefore any large difference between the incoming awire->sbc and
the last recorded glxDraw->lastEventSbc will be due to 32-Bit
wraparound and we need to adapt glxDraw->eventSbcWrap accordingly
to adjust the upper 32-Bits of the sbc.
Two cases, correponding to the two if-statements in the patch:
a) Previous sbc event was below the last 2^32 boundary, in the previous
glxDraw->eventSbcWrap epoch, the new sbc event is in the next 2^32
epoch, therefore the low 32-Bit awire->sbc wrapped around to zero,
or close to zero --> awire->sbc is apparently much lower than the
glxDraw->lastEventSbc recorded for the previous epoch
--> We need to increment glxDraw->eventSbcWrap by 2^32 to adjust
the current epoch to be one higher than the previous one.
--> Case a) also handles the old DRI2 behaviour.
b) Previous sbc event was above closest 2^32 boundary, but now a
late event from the previous 2^32 epoch arrives, with a true sbc
that belongs to the previous 2^32 segment, so the awire->sbc of
this late event has a high count close to 2^32, whereas
glxDraw->lastEventSbc is closer to zero --> awire->sbc is much
greater than glXDraw->lastEventSbc.
--> We need to decrement glxDraw->eventSbcWrap by 2^32 to adjust
the current epoch back to the previous lower epoch of this late
completion event.
We assume such a wraparound to a higher (a) epoch or lower (b)
epoch has happened if awire->sbc and glxDraw->lastEventSbc differ
by more than 2^30 counts, as such a difference can only happen
on wraparound, or if somehow 2^30 present requests would be pending
for a given drawable inside the server, which is rather unlikely.
v2: Explain the reason for this patch and the new wraparound handling
much more extensive in commit message, no code change wrt. initial
version.
Cc: "10.3 10.4 10.5" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Mario Kleiner <mario.kleiner.de at gmail.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 3f94a5afcbab5ebcc4229cb3c65140ad5b5dafca
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Mar 16 14:47:09 2015 +0000
r600g: constify r600_shader_tgsi_instruction lists.
Massive list of constant data. Annotate it as such.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 63cf2b4448f96c8b69c11dac14d8c55742dc6918
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Mar 16 14:47:08 2015 +0000
r600g: kill off r600_shader_tgsi_instruction::{tgsi_opcode,is_op3}
Both of which are no longer used. Use designated initializer to make
things obvious as people add/remove TGSI_OPCODEs.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 5e68c6b32284a5d8d65cf87359f321fc135bdc1c
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Mar 16 14:47:07 2015 +0000
r600g: use the tgsi opcode from parse.FullToken.FullInstruction
... rather than the local one in inst_info->tgsi_opcode.
This will allow us to simplify struct r600_shader_tgsi_instruction.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 6db5e134b627d24e3d6d42a6835e6595652c5aab
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Sat Feb 28 08:32:57 2015 -0800
i965/fs: Apply gl_FrontFacing ? -1 : 1 optimization only for floats
At the very least, unreal4/sun-temple/102.shader_test uses this pattern
for a signed integer result. However, that shader did not hit the
optimization in the first place because it uses !gl_FrontFacing. I
changed the shader to use remove the logical-not and reverse the other
operands. I verified that incorrect code is generated before this
change and correct code is generated after.
Fixes fs-frontfacing-ternary-1-neg-1.shader_test.
No shader-db changes.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 4a53445b0d199489b2d1ae7d8654791e42b16804
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Sat Feb 28 08:26:37 2015 -0800
i965/fs: Change try_opt_frontfacing_ternary to eliminate asserts
If we check for the case that is actually necessary, the asserts
become superfluous.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit ce3f46397d77141156f81dd7fcf06fb936e2b0ef
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Feb 3 21:12:28 2015 +0200
i965/fs: Handle CMP.nz ... 0 and AND.nz ... 1 similarly in cmod propagation
Espically on platforms that do not natively generate 0u and ~0u for
Boolean results, we generate a lot of sequences where a CMP is
followed by an AND with 1. emit_bool_to_cond_code does this, for
example. On ILK, this results in a sequence like:
add(8) g3<1>F g8<8,8,1>F -g4<0,1,0>F
cmp.l.f0(8) g3<1>D g3<8,8,1>F 0F
and.nz.f0(8) null g3<8,8,1>D 1D
(+f0) iff(8) Jump: 6
The AND.nz is obviously redundant. By propagating the cmod, we can
instead generate
add.l.f0(8) null g8<8,8,1>F -g4<0,1,0>F
(+f0) iff(8) Jump: 6
Existing code already handles the propagation from the CMP to the ADD.
Shader-db results:
GM45 (0x2A42):
total instructions in shared programs: 3550829 -> 3550788 (-0.00%)
instructions in affected programs: 10028 -> 9987 (-0.41%)
helped: 24
Iron Lake (0x0046):
total instructions in shared programs: 4993146 -> 4993105 (-0.00%)
instructions in affected programs: 9675 -> 9634 (-0.42%)
helped: 24
Ivy Bridge (0x0166):
total instructions in shared programs: 6291870 -> 6291794 (-0.00%)
instructions in affected programs: 17914 -> 17838 (-0.42%)
helped: 48
Haswell (0x0426):
total instructions in shared programs: 5779256 -> 5779180 (-0.00%)
instructions in affected programs: 16694 -> 16618 (-0.46%)
helped: 48
Broadwell (0x162E):
total instructions in shared programs: 6823088 -> 6823014 (-0.00%)
instructions in affected programs: 15824 -> 15750 (-0.47%)
helped: 46
No chage on Sandy Bridge or on any platform when NIR is used.
v2: Add unit tests suggested by Matt. Remove spurious writes_flag()
check on scan_inst when scan_inst is known to be BRW_OPCODE_CMP (also
suggested by Matt).
v3: Fix some comments and remove some explicit int() casts in fs_reg
constructors in the unit tests. Both suggested by Matt.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit d35720da9b9824d104532028775e497491f433ad
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Mar 4 17:27:21 2015 -0800
i965: Mark paths in linear <-> tiled functions as unreachable().
text data bss dec hex filename
9663 0 0 9663 25bf intel_tiled_memcpy.o before
8215 0 0 8215 2017 intel_tiled_memcpy.o after
Reviewed-by: Carl Worth <cworth at cworth.org>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
commit 6c6e2a15aa7e8c0fd9a1180a901389c1692992c3
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Mar 13 17:00:26 2015 -0700
egl: Remove eglQueryString virtual dispatch.
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit 827da841a1b3dbd4252c39be99965710c5085f5a
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Tue Mar 17 13:27:31 2015 -0700
main: Correct _mesa_error with no format in bufferobj.c.
This fixes Bug 89616, a build failure due to line 1639 of bufferobj.c:
_mesa_error(ctx, GL_INVALID_OPERATION, func);
Trivial.
commit 579297c8bdffd92f47a8cc02100b9535822d2ae7
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Wed Feb 11 16:53:46 2015 -0800
main: Cosmetic changes to GetBufferSubData.
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
commit 23eab47bbe998b95d5da889b85b7b0ca6e14385b
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Tue Jan 20 15:24:53 2015 -0800
main: Add entry point for GetNamedBufferSubData.
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
commit 3706ace2446825b9544e45800c0ce1df261a1c30
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Mon Mar 16 16:08:36 2015 -0700
main: Cosmetic updates to GetBufferPointerv.
v3: Review from Fredrik Hoglund
-Split cosmetic refactor of GetBufferPointerv out into a separate commit
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
commit 105ddc6aea397bd5d39b8ffcd25278ed12102e3c
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Tue Jan 20 14:32:35 2015 -0800
main: Add entry point for GetNamedBufferPointerv.
v3: Review from Fredrik Hoglund
-Split cosmetic refactor of GetBufferPointerv out into a separate commit
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
commit 1e45752aaf4ac7d2324d71bda4d2ac34f3abf8bd
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Wed Feb 11 16:10:20 2015 -0800
main: Add entry points for GetNamedBufferParameteri[64]v.
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
commit efcb830d49d601140a62a096a4ff4c215e68d89c
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Wed Feb 11 16:07:45 2015 -0800
main: Refactor GetBufferParameteri[64]v.
v2: Split into a refactor commit and an entry point commit.
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
commit 1cfc18da8d3220fd6b123b6e269b3b440988027b
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Wed Feb 11 16:06:52 2015 -0800
main: Add entry point for FlushMappedNamedBufferRange.
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
commit ee5fae6e897a38f5104859851eb8fba84180cfa8
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Wed Jan 14 17:01:20 2015 -0800
main: Refactor FlushMappedBufferRange.
v2:-Remove "_mesa" from in front of static software fallback.
-Split out the refactor from the addition of the DSA entry points.
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
commit f7f5df99542d6492fffd803d77d5f7d2f44d08c9
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Wed Jan 14 14:52:01 2015 -0800
main: Add entry point for UnmapNamedBuffer.
v2: review from Ian Romanick
- Restore VBO_DEBUG and BOUNDS_CHECK
- Remove _mesa from static software fallback unmap_buffer.
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
commit a0cc03929e754692ae593df5072d144460434297
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Wed Feb 11 14:09:52 2015 -0800
main: Add entry points for MapNamedBuffer[Range].
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
commit 4f513bc330393c4615b4bad98e3e634408123960
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Wed Jan 14 12:44:39 2015 -0800
main: Refactor MapBuffer[Range].
v2: review from Jason Ekstrand
- Split refactor from addition of DSA entry points.
review from Ian Romanick
- Remove "_mesa" from static software fallback map_buffer_range
- Restore VBO_DEBUG and BOUNDS_CHECK
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
commit 16244525fbe09ff41074eb36a435875892e316a9
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Wed Feb 11 11:45:57 2015 -0800
main: Minor whitespace fixes in ClearNamedBuffer[Sub]Data.
Reviewed-by: Fredrik Höglund <fredrik at kde.org>
commit 5030d0a4f79c3309bad04cc257beb97f74f84f61
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Wed Feb 11 12:17:38 2015 -0800
main: Add entry points for ClearNamedBuffer[Sub]Data.
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
commit 9fa6c3637a53603bc92db8a97b71cf35d88e5176
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Tue Jan 13 15:20:19 2015 -0800
main: Refactor ClearBuffer[Sub]Data.
v2: review by Jason Ekstrand
- Split refactor of clear buffer sub data from addition of DSA entry
points.
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
commit 4adaad5fcc7fc959f24f807e783b6be2903e08a3
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Tue Jan 13 13:28:08 2015 -0800
main: Add entry point for CopyNamedBufferSubData.
v2: remove _mesa in front of static software fallback.
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
commit 9cb732b8e9fad4a603f38ce896cd84300e2743a3
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Wed Feb 11 11:06:42 2015 -0800
main: Improve errors and style in BufferSubData.
- More explicit error reporting.
- Removed legacy style.
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
commit 566ccdf11b37363255bf5d20d7ab6639ddaf1b30
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Tue Jan 13 11:28:17 2015 -0800
main: Add entry point for NamedBufferSubData.
v2: review by Ian Romanick
- Remove "_mesa" from name of static software fallback buffer_sub_data.
- Remove mappedRange from _mesa_buffer_sub_data.
- Removed some cosmetic changes to a separate commit.
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
commit cb56835f870de01ed9c638d1470af38775bb6f72
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Mon Feb 9 17:57:46 2015 -0800
main: Add entry point for NamedBufferData.
v2: review from Ian Romanick
- Fix space in ARB_direct_state_access.xml.
- Remove "_mesa" from the name of buffer_data static fallback.
- Restore VBO_DEBUG and BOUNDS_CHECK.
- Fix beginning of comment to start on same line as /*
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
commit a76808dc19580855eb39c0904f3254edd765aa50
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Fri Jan 9 16:17:10 2015 -0800
main: Add entry point for NamedBufferStorage.
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
commit 2cf48c37c1e2946f7c0648e0a5927a90209f59a4
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Thu Dec 18 17:10:06 2014 -0800
main: Add entry point for CreateBuffers.
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
commit 44ecf0793d872e771edc448436f7a2fd7c3390f5
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Tue Mar 17 09:43:52 2015 -0700
Revert "main: _mesa_cube_level_complete checks NumLayers."
This reverts commit 1ee000a0b6737d6c140d4f07b6044908b8ebfdc7.
Failures with the GLES3 conformance suite and Synmark2 OGLHdrBloom revealed
that this commit was in error.
Extensive testing with Piglit prior to patch review and upstreaming did not
reveal this problem because, in the few Piglit tests that test for cube
completeness, NumLayers = 6. This is because all of the existing tests use
TextureStorage to initialize the texture, which sets NumLayers.
A new Piglit test has been sent to the mailing list that reproduces the bug
related to this patch ("texturing: Testing
glGenerateMipmap(GL_TEXTURE_CUBE_MAP) without glTexStorage2D").
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 5a06ee7384934f8b5177b2f01bb7dff08b370145
Author: Neil Roberts <neil at linux.intel.com>
Date: Thu Mar 12 17:41:07 2015 +0000
i965/skl: Send a message header when doing constant loads SIMD4x2
Commit 0ac4c272755c7 made it add a header for the send message when
using SIMD4x2 on Skylake because without this it will end up using
SIMD8D. However the patch missed the case when a sampler is being used
to implement constant loads from a buffer surface in a SIMD4x2 vertex
shader.
This fixes 29 Piglit tests, mostly related to the ARL instruction in
vertex programs.
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Tested-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 627c68308683abbd6e563a09af6013a33938a790
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Mon Mar 16 10:08:08 2015 +0200
i965/fs: in MAD optimizations, switch last argument to be immediate
Commit bb33a31 introduced optimizations that transform cases of MAD
in to simpler forms but it did not take in to account that src[0]
can not be immediate and did not report progress. Patch switches
src[0] and src[1] if src[0] is immediate and adds progress
reporting. If both sources are immediates, this is taken care of by
the same opt_algebraic pass on later run.
v2: Fix for all cases, use temporary fs_reg (Matt, Kenneth)
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89569
Reviewed-by: Francisco Jerez <currojerez at riseup.net> (v1)
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Cc: "10.5" <mesa-stable at lists.freedesktop.org>
commit 60f77b22b1e3bbef7e4d1f10012acf830d81ed7b
Author: Vinson Lee <vlee at freedesktop.org>
Date: Sat Mar 14 01:45:03 2015 -0700
common.py: Fix PEP 8 issues.
Signed-off-by: Vinson Lee <vlee at freedesktop.org>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 2372275d2fc9e4d3785b34a5aeb7b6126e8cc402
Author: Roland Scheidegger <sroland at vmware.com>
Date: Fri Mar 13 23:45:20 2015 +0100
gallivm: abort properly when running out of buffer space in lp_disassembly
Before this actually ran into an infinite loop printing out "invalid"...
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 9d1682d619426d0a5b90a12df82390cdfa098107
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Mar 16 23:24:15 2015 +0100
docs/GL3: also mark GLES3/GS5 for radeonsi as done
commit c066669b8df9fa5a5e87354b613988944c9a0e5c
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Mar 16 15:00:19 2015 +0000
st/dri: remove unused include from the automake/scons build
st/dri/common hasn't been around for a while.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 55f0c0a29f788c5df4820e81c0cf93613ccedf5e
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Mar 16 15:00:18 2015 +0000
auxiliary/os: fix the android build - s/drm_munmap/os_munmap/
Squash this silly typo introduced with commit c63eb5dd5ec(auxiliary/os: get
the mmap/munmap wrappers working with android)
Cc: "10.4 10.5" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 5664f57df3b7dfc5def189d1ee7a1b3df7d92bd6
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Mar 16 11:50:47 2015 +0000
gallium/sw/kms: trivial cleanups
Remove the forward declaration and make use of the DEBUG_PRINT macro for
debug builds.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 771cd266b9d00bdcf2cf7acaa3c8363c358d7478
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Wed Mar 11 19:12:35 2015 +0000
loader: include <sys/stat.h> for non-sysfs builds
Required by fstat(), otherwise we'll error out due to implicit function
declaration.
Cc: "10.4 10.5" <mesa-stable at lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89530
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reported-by: Vadim Rutkovsky <vrutkovs at redhat.com>
Tested-by: Vadim Rutkovsky <vrutkovs at redhat.com>
commit aead7fe2e2b6c89258f80a25299f4ec0fece2d95
Author: Felix Janda <felix.janda at posteo.de>
Date: Mon Feb 2 20:04:16 2015 +0100
c11/threads: Use PTHREAD_MUTEX_RECURSIVE by default
Previously PTHREAD_MUTEX_RECURSIVE_NP had been used on linux for
compatibility with old glibc. Since mesa defines __GNU_SOURCE__
on linux PTHREAD_MUTEX_RECURSIVE is also available since at least
1998. So we can unconditionally use the portable version
PTHREAD_MUTEX_RECURSIVE.
Cc: "10.5" <mesa-stable at lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88534
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit b5f19db9766ac54d78b8087b0433011f908ebd2c
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Feb 28 14:31:45 2015 +0100
radeonsi: implement TGSI_OPCODE_BFI (v2)
v2: Don't use the intrinsics, the shader backend can recognize these
patterns and generates optimal code automatically.
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
commit d3723c614fb42c22e4e87fe8151bbb36462b425a
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Feb 27 19:09:30 2015 +0100
radeonsi: add a helper for extracting bitfields from parameters (v2)
This will be used a lot (especially by tessellation).
v2: don't use the bfe intrinsic
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
commit 9735a62a2c6007e7ee7baa5a769575a0adb5fda3
Author: Antia Puentes <apuentes at igalia.com>
Date: Thu Mar 12 13:59:17 2015 +0100
i965: Emit IF/ELSE/ENDIF/WHILE JIP with type W on Gen7
IvyBridge and Haswell PRM say that the JIP should be emitted
with type W but we were using UD. The previous implementation
did not show adverse effects, but IMHO it is safer to follow
the specification thoroughly.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Signed-off-by: Antia Puentes <apuentes at igalia.com>
commit dc394136404eafec689874934db0198be6182c59
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Mar 15 20:13:52 2015 +0100
radeonsi: move scratch reloc state setup
- move it to its own function
- do it after all states are emitted
- bump SI_MAX_DRAW_CS_DWORDS
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 567c8d73008a672cb71a84a4724829d34e1652b2
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Mar 15 19:24:13 2015 +0100
radeonsi: don't emit PA_SC_LINE_STIPPLE if not rendering lines
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 1f4bb3826464e2ce1d3f47183c96e6e7fde9a1d7
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Mar 15 19:21:31 2015 +0100
radeonsi: don't emit PA_SC_LINE_STIPPLE after every rasterizer state change
Do it only when the line stipple state is changed.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit f5832f3f9dd0ac0b401d351acab19425fe3c1187
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Mar 15 18:53:50 2015 +0100
radeonsi: move PA_SU_SC_MODE_CNTL to rasterizer state
This requires enabling the optional GL provoking vertex behavior for quads.
+ some cosmetic changes, so that the register is set exactly the same as
on r600.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 98a23982227dce29b015dcb5a867d05f2bee4388
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Mar 15 18:20:19 2015 +0100
radeonsi: implement line and polygon smoothing
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 303d23e10d2caad69b2d122f45c78fee2906fc09
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Mar 15 18:11:19 2015 +0100
radeonsi: add shader code for smoothing
The fragment shader multiplies the alpha channel with gl_SampleMaskIn.
If blending is enabled, it looks like MSAA.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 4f20a8f278aa92fb0dc6abc6998171b3ddea7dc1
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Mar 15 17:54:29 2015 +0100
radeonsi: split sample locations into its own state atom
Sample locations are not updated as often as framebuffers.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit f7796a966d20b04c00025bdc170883f4179a5697
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Mar 15 17:14:53 2015 +0100
radeonsi: add basic code for overrasterization
This will be used for line and polygon smoothing.
This is GCN-only even though it's in shared code.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 1921fa430452304e42059e36b654d9d446371526
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Feb 28 17:22:54 2015 +0100
radeonsi: small cleanup in si_shader_selector_key
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 52ff1edc5161dd7090fa55a11969c79dd4baad7d
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Feb 28 17:16:57 2015 +0100
radeonsi: simplify accessing alpha pointer in si_llvm_emit_fs_epilogue
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 955ebf2890f18973a128ef3a6a6cfe4416fabaef
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Mar 13 16:21:11 2015 +0100
radeonsi: add support for easy opcodes from ARB_gpu_shader5
I have to use the BFE instrinsics, because BFE is one of the most complex
instructions that can't be matched easily. BFE has 3 conditional branches
and one of them is quite big.
In the isel DAG, lowered BFE has 27 nodes (including leafs).
commit 755a2907a3e7f896f86861254554543d815bfad3
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Feb 28 14:01:43 2015 +0100
radeonsi: implement bit-finding opcodes from ARB_gpu_shader5
Reviewed-by: Glenn Kennard <glenn.kennard at gmail.com>
commit ca90cde81eb48a50286193c6bbef9ef47c70a0c6
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Feb 28 00:30:26 2015 +0100
radeonsi: implement gl_SampleMaskIn
Reviewed-by: Glenn Kennard <glenn.kennard at gmail.com>
commit f9fd0c4a55afd97fd34d0e846000c75f5f6ecac2
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Mar 2 02:40:57 2015 +0100
radeonsi: add support for SQRT
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
Reviewed-by: Glenn Kennard <glenn.kennard at gmail.com>
commit d73c1c1304a205c8bf6d1cad1dd1d9a421ce2f32
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Feb 28 00:44:19 2015 +0100
radeonsi: add support for FMA
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
Reviewed-by: Glenn Kennard <glenn.kennard at gmail.com>
commit dfea35666e8031e9565a51eda1ee98837dbd044f
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Feb 27 18:39:40 2015 +0100
gallium/radeon: don't use LLVMReadOnlyAttribute for ALU
None of the instructions use a pointer argument.
(+ small cosmetic changes)
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
commit 9da9c8e3f4f8f06c32efa8344b0a995d34c3b592
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Feb 28 00:34:53 2015 +0100
tgsi: handle bitwise opcodes in tgsi_opcode_infer_type (v2)
v2: set the same types as the destination type in tgsi_exec
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 216543ea547dd0572d9f2f0364f7a239a5aeafe1
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Feb 28 00:26:31 2015 +0100
gallium: add FMA and DFMA opcodes (v3)
Needed by ARB_gpu_shader5.
v2: select DMAD for FMA with double precision
v3: add and select DFMA
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit e92bc6b38e90339a394e95a562bcce35c3ee9696
Author: Rob Clark <robclark at freedesktop.org>
Date: Sun Mar 15 17:59:01 2015 -0400
freedreno: update generated headers
Fix a3xx texture layer-size.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
Cc: "10.4 10.5" <mesa-stable at lists.freedesktop.org>
commit d3fb949c039b80385d35c11ca86e8e7c5a84ae44
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Mar 11 15:10:25 2015 -0400
freedreno/ir3: remove old compiler
Now that piglit is no longer falling back to old compiler for any tests,
we can remove it. Hurray \o/
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit feb858b788cf27b31d12ad8a00805f015d4063cc
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Mar 11 13:21:42 2015 -0400
freedreno/ir3: avoid scheduler deadlock
Deadlock can occur if we schedule an address register write, yet some
instructions which depend on that address register value also depend on
other unscheduled instructions that depend on a different address
register value. To solve this, before scheduling an address register
write, ensure that all the other dependencies of the instructions which
consume this address register are already scheduled.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 7208e96bb810a7a6c92fd11bb7f4df8c9b7f1a2d
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Mar 11 12:36:26 2015 -0400
freedreno/ir3: bit of cleanup
Add an array_insert() macro to simplify inserting into dynamically sized
arrays, add a comment, and remove unused prototype inherited from the
original freedreno.git/fdre-a3xx test code, etc.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit db095eb43bd02414e71f93e72ff61b463bef0ece
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Mar 13 14:34:06 2015 -0700
i965: De-duplicate is_expression_commutative() functions.
Create a backend_inst::is_commutative() method to replace two static
functions that did the exact same thing.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit f68a973dfb8926ac872b0b0e3b4b5c2163389d06
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Mon Dec 8 20:37:00 2014 +1300
i965/gen4-5: Cope with immutable-format texture revalidation
This is unfortunately sometimes necessary due to rebasing levels when
rendering into them.
16 piglits crash -> pass, when building mesa with debug enabled.
Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 8ed1b65b62665810291562b59f1e983f7a78a0fc
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Mar 13 23:36:33 2015 +0000
docs: add news item and link release notes for mesa 10.5.1
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 5f72847a885518eacafc05d10e1cb52b978ba061
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Mar 13 23:32:12 2015 +0000
docs: Add sha256 sums for the 10.5.1 release
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit 2abba086ca84f200fae940129c0a5342c3748f00)
commit 6c966089374d7cb7a7778e91de182f54fc70e07c
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Mar 13 22:32:57 2015 +0000
Add release notes for the 10.5.1 release
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit 11c0ff60ef19cca84452aa989fb8bb25127473e0)
commit 620e29b74821fd75b24495ab2bfddea53fc75350
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Mar 13 01:36:57 2015 -0400
freedreno: fix slice pitch calculations
For example if width were 65, the first slice would get 96 while the
second would get 32. However the hardware appears to expect the second
pitch to be 64, based on halving the 96 (and aligning up to 32).
This fixes texelFetch piglit tests on a3xx below a certain size. Going
higher they break again, but most likely due to unrelated reasons.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.4 10.5" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Rob Clark <robclark at freedesktop.org>
commit 89b26d5a360ebde11a69f2cdefa66e4d6a2a13fd
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Mar 13 00:53:49 2015 -0400
freedreno/a3xx: use the same layer size for all slices
We only program in one layer size per texture, so that means that all
levels must share one size. This makes the piglit test
bin/texelFetch fs sampler2DArray
have the same breakage as its non-array version instead of being
completely off, and makes
bin/ext_texture_array-gen-mipmap
start passing.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.4 10.5" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Rob Clark <robclark at freedesktop.org>
commit e76a8dc8ed8af9ea9c99ff4f84948fa834317ee9
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Feb 24 20:57:18 2015 -0500
i965/vs: Add missing resolve_bool_comparison calls on GEN4 and GEN5
The ir_unop_any problem was discovered by some later optimization passes
that generate ir_triop_csel. I was also able to reproduce it by
modifying the gl-2.0-vertexattribpointer vertex shader to generate its
result using
color = mix(vec4(0, 1, 0, 0),
vec4(1, 0, 0, 0),
bvec4(any(greaterThan(diff, vec4(tolerance)))));
instead of an if-statement. This also required using #version 130 and
MESA_GLSL_VERSION_OVERRIDE=130.
I have not nominated this for stable releases because I don't think
there's any way to trigger the problem without GLSL 1.30 or
optimizations that don't exist in stable.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Abdiel Janulgue <abdiel.janulgue at intel.com>
commit 21ff9bfe1cea8c0a51e9f607cc580df62baa3445
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Sat Mar 14 07:10:11 2015 +1300
i965/disasm: Fix format strings
Most of the brw_inst_* api returns 64bit values. This fixes disassembly
of sampler messages, etc.
Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 7c3095d6b71c410fd625ead797c78a0f5376904d
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Sat Mar 14 07:10:10 2015 +1300
i965/disasm: Mark format() as being printf-style.
This allows us to get warnings from GCC when we mess up the format
strings.
Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 97399fc751a0f9750c4f9585dfed14b662ebec2e
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Mar 11 18:43:56 2015 -0700
docs: List ARB_shading_language_packing/EXT_shader_integer_mix.
Reviewed-by: Carl Worth <cworth at cworth.org>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 8d3aa5926b73c67c7dbd4477b7177aaa00c533e5
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Mar 11 18:14:28 2015 -0700
glsl: Expose built-in packing functions under GLSL 4.2.
ARB_shading_language_packing is part of GLSL 4.2, not 4.0 as I
mistakenly believed. The following functions are available only with
ARB_shading_language_packing, GLSL 4.2 (not GLSL 4.0), or ES 3.0:
- packSnorm2x16
- unpackSnorm2x16
- packHalf2x16
- unpackHalf2x16
Reviewed-by: Carl Worth <cworth at cworth.org>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit dac2e7deaae2540645a6b485c7d1f47195689116
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Mar 10 11:41:57 2015 -0700
egl: Create queryable strings in eglInitialize().
Creating/recreating the strings in eglQueryString() is extra work and
isn't thread-safe, as exhibited by shader-db's run.c using libepoxy.
Multiple threads in run.c call eglReleaseThread() around the same time.
libepoxy calls eglQueryString() to determine whether eglReleaseThread()
exists, and our EGL implementation passes a pointer to the version
string to libepoxy while simultaneously overwriting the string, leading
to a failure in libepoxy.
Moreover, the EGL spec says (emphasis mine):
"eglQueryString returns a pointer to a *static*, zero-terminated string"
This patch moves some auxiliary functions from eglmisc.c to eglapi.c so
that they may be used to create the extension, API, and version strings
once during eglInitialize(). The auxiliary functions are renamed from
_eglUpdate* to _eglCreate*, and some checks made unnecessary by calling
the functions from eglInitialize() are removed.
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit b43bbfa90ace596c8b2e0b3954a5f69924726c59
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Tue Feb 24 19:02:57 2015 +0100
glsl: optimize (0 cmp x + y) into (-x cmp y).
The optimization done by commit 34ec1a24d did not take it into account.
Fixes:
dEQP-GLES3.functional.shaders.random.all_features.fragment.20
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Cc: "10.4 10.5" <mesa-stable at lists.freedesktop.org>
commit cf6f33ee68ca56df1650762634fa9c038359c3ec
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Thu Mar 12 08:16:09 2015 +0100
mesa: Check for valid PBO access in gl(Compressed)Tex(Sub)Image calls
This patch adds two types of checks to the gl(Compressed)Tex(Sub)Imgage family
of functions when a pixel buffer object is bound to GL_PIXEL_UNPACK_BUFFER:
- That the buffer is not mapped.
- The total data size is within the boundaries of the buffer size.
It does so by calling auxiliary validations functions from PBO API:
_mesa_validate_pbo_source() for non-compressed texture calls, and
_mesa_validate_pbo_source_compressed() for compressed texture calls.
The first check is defined in Section 6.3.2 'Effects of Mapping Buffers
on Other GL Commands' of the GLES 3.1 spec, page 57:
"Any GL command which attempts to read from, write to, or change the
state of a buffer object may generate an INVALID_OPERATION error if all
or part of the buffer object is mapped. However, only commands which
explicitly describe this error are required to do so. If an error is not
generated, using such commands to perform invalid reads, writes, or
state changes will have undefined results and may result in GL
interruption or termination."
Similar wording exists in GL 4.5 spec, page 76.
In the case of gl(Compressed)Tex(Sub)Image(2,3)D, the specification doesn't force
implemtations to throw an error. However since Mesa don't currently implement
checks to determine when it is safe to read/write from/to a mapped PBO, we
should always return the error if all or parts of it are mapped.
The 2nd check is defined in Section 8.5 'Texture Image Specification' of the
OpenGL 4.5 spec, page 203:
"An INVALID_OPERATION error is generated if a pixel unpack buffer object
is bound and storing texture data would access memory beyond the end of
the pixel unpack buffer."
Fixes 4 dEQP tests:
* dEQP-GLES3.functional.negative_api.texture.compressedteximage2d_invalid_buffer_target
* dEQP-GLES3.functional.negative_api.texture.compressedtexsubimage2d_invalid_buffer_target
* dEQP-GLES3.functional.negative_api.texture.compressedteximage3d_invalid_buffer_target
* dEQP-GLES3.functional.negative_api.texture.compressedtexsubimage3d_invalid_buffer_target
Reviewed-by: Laura Ekstrand <laura at jlekstrand.net>
commit 7c084752c612c1763212830618ee0a86f4edf8f6
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Thu Mar 12 08:14:03 2015 +0100
mesa: Separate PBO validation checks from buffer mapping, to allow reuse
Internal PBO functions such as _mesa_map_validate_pbo_source() and
_mesa_validate_pbo_compressed_teximage() perform validation and buffer mapping
within the same call.
This patch takes out the validation into separate functions to allow reuse
of functionality by other code (i.e, gl(Compressed)Tex(Sub)Image).
Reviewed-by: Laura Ekstrand <laura at jlekstrand.net>
commit 7b5bb97cefbf1d0cfef28bc974ee9a68024e3b45
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Thu Mar 5 09:20:11 2015 +0100
mesa: Set the correct image size in _mesa_validate_pbo_access()
_mesa_validate_pbo_access() provides a generic way to check that a
requested pixel transfer operation on a PBO falls within the
boundaries of the buffer. It is used in various other places, and
depending on the caller, some arguments are used or not.
In particular, the 'clientMemSize' argument is used only by calls
that are knowledgeable of the total size of the user data involved
in a pixel transfer, such as the case of compressed texture image
calls. Other calls don't provide 'clientMemSize' directly since it
is made implicit from the size and format of the texture, and its
data type. In these cases, a sufficiently big value is passed to
'clientMemSize' (INT_MAX) to avoid an incorrect constrain.
The problem is that _mesa_validate_pbo_access() use uint
pointers to make the calculations, which are 64 bits long in 64
bits platforms, meanwhile the dummy INT_MAX passed in 'clientMemSize'
is just 32 bits. This causes a constrain that is not desired.
This patch fixes that by checking that if 'clientMemSize' is MAX_INT,
then UINTPTR_MAX is assumed instead.
This is an ugly workaround to the fact that _mesa_validate_pbo_access()
intends to be a one function fits all. The clean solution here would
be to break it into different functions that provide the adequate API
for each of the possible code paths and validation needs.
Since there are callers relying on passing INT_MAX to 'clientMemSize',
this patch is necessary to deal with the problem above while a cleaner
implementation of the PBO API is not implemented.
Reviewed-by: Laura Ekstrand <laura at jlekstrand.net>
commit f6f7bfb5e1308593df9642aa8f46a17e8ce340a2
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Tue Mar 10 19:33:30 2015 +0100
meta: Remove error checks for texture <-> pixel-buffer transfers that don't belong in driver code
The implementation of texture <-> pixel-buffer transfers in drivers common layer
includes certain error checks and argument validation that don't belong there,
considering how the Mesa codebase is laid out. These are higher level
validations that, if necessary, should be performed earlier (i.e, in GL API
entry points).
This patch simply removes these error checks from driver code.
For more information, see discussion at
http://lists.freedesktop.org/archives/mesa-dev/2015-February/077417.html.
Reviewed-by: Laura Ekstrand <laura at jlekstrand.net>
commit 558dcd877095a27ce5de8198744f2f95ddf66b2a
Author: Brian Paul <brianp at vmware.com>
Date: Thu Mar 12 15:50:20 2015 -0600
util: convert slab macros to inline functions
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit d24a20e967303e1172928937fb7f96f010d4a99c
Author: Brian Paul <brianp at vmware.com>
Date: Thu Mar 12 08:35:38 2015 -0600
egl: fix cast to silence compiler warning
eglcurrent.c: In function '_eglSetTSD':
eglcurrent.c:57:4: warning: passing argument 2 of 'tss_set' discards
'const' qualifier from pointer target type [enabled by default]
tss_set(_egl_TSD, (const void *) t);
^
In file included from ../../../include/c11/threads.h:72:0,
from eglcurrent.c:32:
../../../include/c11/threads_posix.h:357:1: note: expected 'void *'
but argument is of type 'const void *'
tss_set(tss_t key, void *val)
^
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit a38e6c4fbd6a941ec9ffb98bdf9f040cccda0247
Author: Alexandre Demers <alexandre.f.demers at gmail.com>
Date: Thu Mar 12 20:50:08 2015 -0400
gallivm: (trivial) Fix typo in comment introduced by 70dc8a
Fix typo in comment introduced by 70dc8a
Signed-off-by: Alexandre Demers <alexandre.f.demers at gmail.com>
Signed-off-by: Jose Fonseca <jfonseca at vmware.com>
commit 1a469a34d517d4c24c60a613c7d1a56f77778c8e
Author: Seán de Búrca <leftmostcat at gmail.com>
Date: Sat Mar 7 02:23:53 2015 -0700
mesa: improve ARB_copy_image internal format compat check
The memory layout of compatible internal formats may differ in bytes per
block, so TexFormat is not a reliable measure of compatibility. For example,
GL_RGB8 and GL_RGB8UI are compatible formats, but GL_RGB8 may be laid out in
memory as B8G8R8X8. If GL_RGB8UI has a 3 byte-per-block memory layout, the
existing compatibility check will fail.
Additionally, the current check allows any two compressed textures which share
block size to be used, whereas the spec gives an explicit table of compatible
formats.
v2: Use a switch instead of array iteration for block class and show the
correct GL error when internal formats are mismatched.
v3: Include spec citations for new compatibility checks, rearrange check
order to ensure that compressed, view-compatible formats return the
correct result, and make style fixes. Original commit message amended
for clarity.
v4: Reformatted spec citations.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit f3e4b2c9d2087c7f655d323cc6b4150313fc0128
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Mar 9 18:36:31 2015 -0700
nir: Fix non-determinism in nir_lower_vars_to_ssa().
Previously, we stored derefs in a hash table, using the malloc'd pointer
as the key. Then, we walked through the hash table and generated code,
based on the order of the hash table's elements.
Memory addresses returned by malloc are pretty much random, which meant
that the hash was random, and the hash table's elements would be walked
in some random order. This led to successive compiles of the same
shader using different variable names and slightly different orderings
of phi-nodes. Code could not be diff'd, and the final assembly would
sometimes change slightly too.
It turns out the only point of the hash table was to avoid inserting
the same node multiple times for different dereferences. We never
actually searched the hash table! This patch uses an intrusive
linked list instead. Since exec_list uses head and tail sentinels,
checking prev or next against NULL will tell us whether the node is
already in the list.
Pair programming with Jason Ekstrand.
Signed-off-by: Jason Ekstrand <jason.ekstrand at intel.com>
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 67388c1ef27e9ff4d7f60a496dbaea4b290dc741
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Mar 9 18:36:30 2015 -0700
util: Fix foreach_list_typed_safe when exec_node is not at offset 0.
__next and __prev are pointers to the structure containing the exec_node
link, not the embedded exec_node. NULL checks would fail unless the
embedded exec_node happened to be at offset 0 in the parent struct.
v2: Jason Ekstrand <jason.ekstrand at intel.com>:
Use "(__node)->__field.next != NULL" to check for the end of the list
instead of the "&__next->__field != NULL". The former is far more
obviously correct as it matches what the non-safe versions do. The
original code tried to avoid any use of __next as the client code may
delete it during its execution. However, since the looping condition is
checked after the iteration clause but before the client code is
executed, we know that __node is valid during the looping condition.
Signed-off-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 547c760964bcad23a056e5156e4fefd7487c0192
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Mar 9 01:58:59 2015 -0700
i965: Use NIR for scalar VS when INTEL_USE_NIR is set.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 7ef0b6b367f73e24e6dd47a15d439775d3dd1297
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Mar 9 01:58:58 2015 -0700
i965/fs: Add VS output support to nir_setup_outputs().
Adapted from fs_visitor::visit(ir_variable *).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit eb137117b7db6c78d6a1662730524d622301c708
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Mar 9 01:58:57 2015 -0700
i965/fs: Handle VS inputs in the NIR backend.
(Jason noted that this is not a good long term solution, and we should
instead improve nir_lower_io so that this extra set of MOVs is
unnecessary. I tend to agree, but decided we could do that as a
follow-up improvement.)
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit a5c4e7fcf52c048c02e4ee14413a574b4ff3695e
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Mar 9 01:58:56 2015 -0700
i965/fs: Refactor fs_visitor::nir_setup_inputs().
No functional change. In preparation for supporting vertex shaders,
this adds a switch statement on shader stage (since vertex attributes
and fragment shader varyings will need different handling). It also
renames "varying" to "input", to be more general.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 34628a838aa96643be02cd23eb55af50025dd422
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Mar 9 01:58:55 2015 -0700
i965: Implement NIR intrinsics for loading VS system values.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 2c79f6f9c339448b5361f080e8f373cea5de3179
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Mar 9 01:58:54 2015 -0700
nir: Add intrinsics for SYSTEM_VALUE_BASE_VERTEX and VERTEX_ID_ZERO_BASE
Ian and I added these around the time Connor was developing NIR. Now
that both exist, we should make them work together!
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit b9dea9bc45299f19c445170a4cac27810547de00
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Mar 9 01:58:53 2015 -0700
i965/nir: Lower to registers a bit later.
We can't safely call nir_optimize() with register present, since several
passes called in the loop can't handle registers, and will fail asserts.
Notably, nir_lower_vec_alus() and nir_opt_algebraic() really don't want
registers.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 1f0067811c059fb3b284a2169e94fbdec7a4b909
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Mar 9 01:58:52 2015 -0700
i965/nir: Optimize after nir_lower_var_copies().
Array variable copy splitting generates a bunch of stuff we want to
clean up before proceeding.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 1d8ef6ba606a88239de633e5abcc19471c9d3cf4
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Mar 9 01:58:51 2015 -0700
i965/fs: Store a pointer to brw_sampler_prog_key_data in the visitor.
The NIR backend hardcodes brw_wm_prog_key at the moment, which won't
work when we support scalar VS. We could use get_tex(), but it's a
static method. I was going to promote it to fs_visitor, but then
realized that both parameters (stage and key) are already members.
It then occured to me that we could just set up a pointer in the
constructor, and skip having a function altogether.
This patch also converts all existing users to use key_tex.
v2: Make key_tex a "const brw_sampler_prog_key_data *" instead of
non-const; word-wrap some lines. (Review comments from Topi.)
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 48b0a3c1c9d829a9b1d401afb2796b35df94a5d7
Author: Brian Paul <brianp at vmware.com>
Date: Wed Mar 11 17:10:53 2015 -0600
tnl: HAVE_LE32_VERTS is never defined, remove associated code
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 6d3b86c3afe4ee1bfb29c322b3d36131139cbab9
Author: Brian Paul <brianp at vmware.com>
Date: Wed Mar 11 16:54:15 2015 -0600
mesa: move LONGSTRING into generated enums.c
enums.c is the only place this directive is needed.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit f8ed0bbfef7b8e8098cb3263a196689dbd280758
Author: Brian Paul <brianp at vmware.com>
Date: Wed Mar 11 08:38:09 2015 -0600
mesa: remove _ASMAPI, ASMAPIP
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 09ffa04cd9c560b7a8c6d8ac80e3d59c49c5ef70
Author: Brian Paul <brianp at vmware.com>
Date: Wed Mar 11 08:33:21 2015 -0600
mesa: remove _XFORMAPI
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 10035361b5c23483f236c59fe13c23153455e5c9
Author: Brian Paul <brianp at vmware.com>
Date: Wed Mar 11 08:29:56 2015 -0600
swrast: remove _BLENDAPI
_BLENDAPI boils down to __cdecl on Windows, but __cdecl is the default
calling convention so this serves no purpose.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 6ca5eaf49ce184009571f58fb94865cf788e8907
Author: Brian Paul <brianp at vmware.com>
Date: Sat Mar 7 13:15:22 2015 -0700
mesa: use ARRAY_SIZE in _mesa_QueryMatrixxOES()
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit c3984c1155bc78b45001f90ed1333bbacfc32151
Author: Brian Paul <brianp at vmware.com>
Date: Sat Mar 7 13:15:22 2015 -0700
mesa: remove register keyword, add const in _mesa_QueryMatrixxOES()
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 97f6d50f7247c40eeef33219e5cf5ccb7bf6d4ea
Author: Brian Paul <brianp at vmware.com>
Date: Sat Mar 7 13:15:22 2015 -0700
mesa: reindent querymatrix.c
Use 3-space indents, not 4. Move some comments after the case statements.
Acked-by: Matt Turner <mattst88 at gmail.com>
commit be4e198be00c03e88315058eb81187a9547e3e87
Author: Brian Paul <brianp at vmware.com>
Date: Sat Mar 7 13:15:22 2015 -0700
mesa: move fpclassify work-arounds into c99_math.h
v2: Use #error in the #else clause, per Jose.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 70dc8a9930f561d7ce6db7e58b5bc9b4d940e37b
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Thu Mar 12 09:57:43 2015 +0000
gallivm: Prevent double delete on LLVM 3.6
std::unique_ptr takes ownership of MM, and a double delete could ensure
in case of an error, as pointed out by Chris Vine in
https://bugs.freedesktop.org/show_bug.cgi?id=89387
Reviewed-by: Chris Vine <chris at cvine.freeserve.co.uk>
commit 30916a5ef008a84e53d9821ccc11a0dee50fe77b
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Mar 9 11:46:07 2015 +0000
autogen.sh: pass --force to autoreconf, quote ORIGDIR
By passing --force autoreconf will update all the aux files, which would
otherwise be ignored if one updates autoconf/automake.
Quote the ORIGDIR variable to prevent fall-outs, when its name contains
space.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit a385d18598b28bf935e4460b86ce3f9e095a8015
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Mar 6 16:54:59 2015 +0000
glx: remove support for non-multithreaded platforms
Implicitly required for a while, although commit 9385c592c68 (mapi:
remove u_thread.h) was the one that put the final nail on the
coffin.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 42144170d189d2539a4fb2243200e760114af9f7
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Mar 6 16:54:58 2015 +0000
glx: remove final reference to THREADS
Left over from commit 18db13f5865(mapi: THREADS was always defined,
remove it)
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 39f90e6b9bb0c9c8b40abae2afde07587cd49010
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Mar 6 16:54:57 2015 +0000
configure: require pthreads for POSIX builds
This has been an implicit rule for building mesa for a long time. Let's
make it official and just bail out at configure time. This way we can
cleaning up some of our glx code.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit a806df3f23cd5fadffbfe818f8c5af7e17205426
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Mar 6 16:54:56 2015 +0000
egl/main: convert thread management to use c11 threads
Convert the code to use the C11 threads implementation, and nuke the
Windows non-pthreads code-path. The c11/threads_win32.h abstraction
should be better than the current code.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit efe87f1a801c61d087cd2b29a2c150453241c3d4
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Mar 6 16:54:55 2015 +0000
egl/main: use c11/threads' mutex directly
Remove the inline wrappers/abstraction layer.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 90e50908d7f080d91f41d889cfe0dc67134971eb
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Mar 2 17:59:38 2015 -0800
nir/worklist: Don't change the start index when computing the tail index
Reviewed-by: Mark Janes <mark.a.janes at intel.com>
commit 8fb8fe46fa565dceedacd95287c836004b0fade2
Author: Thomas Helland <thomashelland90 at gmail.com>
Date: Sat Feb 28 20:32:32 2015 +0100
nir: Optimize a + neg(a)
Shader-db i965 instructions:
total instructions in shared programs: 1711180 -> 1711159 (-0.00%)
instructions in affected programs: 825 -> 804 (-2.55%)
helped: 9
HURT: 0
GAINED: 3
LOST: 3
Shader-db NIR instructions:
total instructions in shared programs: 606187 -> 606179 (-0.00%)
instructions in affected programs: 298 -> 290 (-2.68%)
helped: 4
HURT: 0
GAINED: 0
LOST: 0
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Signed-off-by: Thomas Helland <thomashelland90 at gmail.com>
commit 0525f2e851f5f6f53b5f83c8dcdfa48f9838133b
Author: Thomas Helland <thomashelland90 at gmail.com>
Date: Sat Feb 28 20:32:31 2015 +0100
nir: Optimize (a*b)+(a*c) -> a*(b+c)
Shader-db i965 instructions:
total instructions in shared programs: 1715894 -> 1710802 (-0.30%)
instructions in affected programs: 443080 -> 437988 (-1.15%)
helped: 1502
HURT: 13
GAINED: 4
LOST: 4
Shader-db NIR instructions:
total instructions in shared programs: 607710 -> 606187 (-0.25%)
instructions in affected programs: 208285 -> 206762 (-0.73%)
helped: 769
HURT: 8
GAINED: 0
LOST: 0
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Signed-off-by: Thomas Helland <thomashelland90 at gmail.com>
commit 09b03254091d054800834ddee604885a1093673f
Author: Marius Predut <marius.predut at intel.com>
Date: Wed Mar 11 03:25:00 2015 -0600
vbo: improve the code style by adjust the preprocessing c code directives
Brian Paul review suggestion: there's more macro use here than necessary.
Removed and redefine some #define preprocessing directives.
Removed the directive input parameter 'T' .
No functional changes.
Signed-off-by: Marius Predut <marius.predut at intel.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 9816acff2ca570e248652fe05ac4ee3ce02bd2ab
Author: Brian Paul <brianp at vmware.com>
Date: Sun Mar 8 16:46:39 2015 -0600
mesa: remove CPU_TO_LE32() for AIX
This is the only remnant of AIX-specific code in Mesa. Probably long
unused.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 3158b3abb34abc9f61e4b5161411e5e83640d42d
Author: Brian Paul <brianp at vmware.com>
Date: Sun Mar 8 16:44:28 2015 -0600
mesa: remove #define __volatile
Not actually used anwhere in Mesa.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit d7193ce42cedc4cc7839fc4522edf5724e954c80
Author: Brian Paul <brianp at vmware.com>
Date: Sat Mar 7 13:15:22 2015 -0700
mesa: use strdup() instead of _mesa_strdup()
We were already using strdup() in various places in Mesa. Get rid
of the _mesa_strdup() wrapper. All the callers pass a non-NULL
argument so the NULL check isn't needed either.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 5376bc74ccfac0d1a4df6c5652e075d99e3f4fe4
Author: Brian Paul <brianp at vmware.com>
Date: Sat Mar 7 13:15:22 2015 -0700
st/glx: use strdup() instead of _mesa_strdup()
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 279c5965aa501e6b8f8432b1213f917298154d6c
Author: Brian Paul <brianp at vmware.com>
Date: Sat Mar 7 13:15:22 2015 -0700
xlib: use strdup() instead of _mesa_strdup()
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 14ba6c9325229270d3f04c13253ca547f9a216ff
Author: Brian Paul <brianp at vmware.com>
Date: Tue Mar 10 08:18:27 2015 -0600
i915: add parens to silence operator precedence warning
Signed-off-by: Brian Paul <brianp at vmware.com>
commit 6ac1bc90c4a7a6f32901a9782e14b090f6fe5270
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Tue Mar 10 11:36:43 2015 +0100
i965: Fix out-of-bounds accesses into pull_constant_loc array
The piglit test glsl-fs-uniform-array-loop-unroll.shader_test was designed
to do an out of bounds access into an uniform array to make sure that we
handle that situation gracefully inside the driver, however, as Ken describes
in bug 79202, Valgrind reports that this is leading to an out-of-bounds access
in fs_visitor::demote_pull_constants().
Before accessing the pull_constant_loc array we should make sure that
the uniform we are trying to access is valid.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79202
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 5750595ca97b2f8f18d22af35b431a6c66dd899a
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Sat Feb 21 15:05:22 2015 -0800
i965/gen6 gs: Convert brw_imm_ud/brw_imm_d to src_reg
Same idea as this patch, only for gen6_gs_visitor:
commit 49a938a265f5959c9b558995cc658f80acb6eb18
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Fri Feb 20 12:12:25 2015 -0800
i965/fs: Use fs_reg for CS/VS atomics pixel mask immediate data
Suggested-by: Matt Turner <mattst88 at gmail.com>
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit e5269ca28e4c44fb49890b33af8b3058377d35c8
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Sat Feb 21 15:00:28 2015 -0800
i965/fs: Use unsigned for CS/VS atomics pixel mask immediate data
brw_imm_ud(0xffff) should have been converted to fs_reg(0xffffu) to
make sure the uint32_t fs_reg constructor was matched.
commit 49a938a265f5959c9b558995cc658f80acb6eb18
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Fri Feb 20 12:12:25 2015 -0800
i965/fs: Use fs_reg for CS/VS atomics pixel mask immediate data
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 6626e3548b5365dcb284504ea863d2ccdba2c7a5
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Sun Jun 29 12:06:33 2014 -0700
i965/gen8: Don't allocate hiz miptree structure
We now skip allocating a hiz miptree for gen8. Instead, we calculate
the required hiz buffer parameters and allocate a bo directly.
v2:
* Update hz_height calculation as suggested by Topi
v3:
* Bail if we failed to create the bo (Ben)
v4:
* CEILING => DIV_ROUND_UP
* Make sure mt->logical_depth0 being 0 would not cause trouble
* Fail if Y tiling is not returned
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=67564
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit 81124aefe8a2f61d5af4257e5b9989019bfed518
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Sun Jun 29 12:06:33 2014 -0700
i965/gen7: Don't allocate hiz miptree structure
We now skip allocating a hiz miptree for gen7. Instead, we calculate
the required hiz buffer parameters and allocate a bo directly.
v2:
* Update hz_height calculation as suggested by Topi
v3:
* Bail if we failed to create the bo (Ben)
v4:
* CEILING => DIV_ROUND_UP
* Make sure mt->logical_depth0 being 0 would not cause trouble
* Fail if Y tiling is not returned
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=67564
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit 31b851dccb606090989c0400fc1899cbfe44bcf1
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Sun Jun 29 12:06:33 2014 -0700
i965/gen8: Don't rely directly on the hiz miptree structure
We are still allocating a miptree for hiz, but we only use fields from
intel_miptree_aux_buffer. This will allow us to switch over to not
allocating a miptree.
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit 26eabd189d9dd1e1e1c711ee4bcc8ff73c076d11
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Sun Jun 29 12:06:33 2014 -0700
i965/gen7: Don't rely directly on the hiz miptree structure
We are still allocating a miptree for hiz, but we only use fields from
intel_miptree_aux_buffer. This will allow us to switch over to not
allocating a miptree.
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit aedcd466bb9d899e892f9d47f96fbca5e5647133
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Sun Jun 29 11:55:26 2014 -0700
i965/hiz: Start to separate miptree out from hiz buffers
Today we allocate a miptree's for the hiz buffer. We needed this in
the past because we would point the hardware at offsets of the hiz
buffer. Since the hiz format is not documented, this is not a good
idea.
Since moving to support layered rendering on Gen7+, we no longer point
at an offset into the buffer on Gen7+.
Therefore, to support hiz on Gen7+, we don't need a full miptree
structure allocated.
This patch starts to create a new auxiliary buffer structure
(intel_miptree_aux_buffer) that can be a more simplistic miptree
side-band buffer associated with a miptree. (For example, to serve the
needs of the hiz buffer.)
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit 4d318b61fc14c7ed550007cb568ff27dbeab1662
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Mar 10 16:45:18 2015 +1000
mesa/scissor: fix typos in debug names
Just noticed this when working on virgl.
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit e5cd42ed9abadac8be085eea67049dc1e19ade09
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Sun Mar 8 17:18:07 2015 +0100
nvc0: fix wrong max value for driver queries
The maximum value of a Gallium HUD's panel is automatically adjusted
when the current value is greater than the max. If we set the
pipe_query_driver_info::max_value to UINT64_MAX, the maximum value is
never adjusted and this results in a flat line instead of a pretty curve
which is correctly scaled.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 13f4963ed2de90680841658af4561ef7ab238406
Author: Vinson Lee <vlee at freedesktop.org>
Date: Fri Mar 6 22:08:00 2015 -0800
i965: Silence GCC maybe-uninitialized warning.
brw_shader.cpp: In function ‘bool brw_saturate_immediate(brw_reg_type, brw_reg*)’:
brw_shader.cpp:618:31: warning: ‘sat_imm.brw_saturate_immediate(brw_reg_type, brw_reg*)::<anonymous union>::ud’ may be used uninitialized in this function [-Wmaybe-uninitialized]
reg->dw1.ud = sat_imm.ud;
^
Signed-off-by: Vinson Lee <vlee at freedesktop.org>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 282f67becd072068147c95f26d9c705acf1bbe1b
Author: Vinson Lee <vlee at freedesktop.org>
Date: Fri Mar 6 21:52:31 2015 -0800
i915: Fix GCC unused-but-set-variable warning in release build.
i915_fragprog.c: In function ‘i915ValidateFragmentProgram’:
i915_fragprog.c:1453:11: warning: variable ‘k’ set but not used [-Wunused-but-set-variable]
int k;
^
Signed-off-by: Vinson Lee <vlee at freedesktop.org>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 5f759836ad75360a2f4581083043a86f7a8c1e09
Author: Vinson Lee <vlee at freedesktop.org>
Date: Sat Mar 7 14:07:10 2015 -0800
Add macro for unused function attribute.
Suggested-by: Emil Velikov <emil.l.velikov at gmail.com>
Signed-off-by: Vinson Lee <vlee at freedesktop.org>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 7aba4ab1f355ea1a5870b3deb4b295565132dfc5
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Fri Mar 6 17:31:00 2015 -0800
meta: Plug memory leak
It looks like this has existed since
commit f5a477ab76b6e0b268387699cd2253a43db0dfae
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Mon Dec 16 11:54:08 2013 -0800
meta: Refactor shader generation code out of mipmap generation path
Valgrind was complaining on fbo-generatemipmap-formats
v2: Instead, do the allocation after the early return block (v2)
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit e95969cd9548033250ba12f2adf11740319b41e7
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Feb 26 17:45:49 2015 -0800
i965/fs: Don't issue FB writes for bound but unwritten color targets.
We used to loop over all color attachments, and emit FB writes for each
one, even if the shader didn't write to a corresponding output variable.
Those color attachments would be filled with garbage (undefined values).
Football Manager binds a framebuffer with 4 color attachments, but draws
to it using a shader that only writes to gl_FragData[0..2]. This meant
that color attachment 3 would be filled with garbage, resulting in
rendering artifacts. Now we skip writing to it, fixing rendering.
Writes to gl_FragColor initialize outputs[0..nr_color_regions-1] to
GRFs, while writes to gl_FragData[i] initialize outputs[i].
Thanks to Jason Ekstrand for tracking this down.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86747
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Cc: mesa-stable at lists.freedesktop.org
commit 4ebeb71573ad44f7657810dc5dd2c9030e3e63db
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Feb 26 22:55:54 2015 -0800
i965/fs: Make emit_shader_time_end() insert before EOT.
Previously, we emitted the shader-time epilogue from emit_fb_writes(),
during the middle of looping through color regions (or emit_urb_writes
for the VS). This is duplicated several times and rather awkward.
I need to fix a bug in our FB write handling, and it will be a lot
easier if we move emit_shader_time_end() out of there.
Now, we simply emit FB writes/URB writes, and subsequently have
emit_shader_time_end() insert instructions before the final SEND with
EOT. Not only is this simpler, it's actually a slight improvement:
we now include the MOVs to set up the final FB write payload in our
shader-time measurements.
Note that INTEL_DEBUG=shader_time only exists on Gen7+, and uses
send-from-GRF. (In the past, we might have hit trouble where both
attempt to use MRFs for messages; that's not a problem now.)
v2: Rebase on v3 of the previous patch and other shader_time fixes.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com> [v1]
Acked-by: Matt Turner <mattst88 at gmail.com>
Cc: mesa-stable at lists.freedesktop.org
commit e43af8d09f919d02b5ac0810c1c0f1783cbef6ef
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Feb 26 23:51:27 2015 -0800
i965/fs: Make get_timestamp() pass back the MOV rather than emitting it.
This makes another part of the INTEL_DEBUG=shader_time code emittable
at arbitrary locations, rather than just at the end of the instruction
stream.
v2: Don't lose smear! Caught by Topi Pohjolainen.
v3: Don't set smear on the destination of the MOV. Thanks Topi!
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Cc: mesa-stable at lists.freedesktop.org
commit bea854c7f33cc10b8292f931f114afc4f88a8dd4
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Feb 26 22:49:04 2015 -0800
i965/fs: Make emit_shader_time_write return rather than emit.
Instead of emit_shader_time_write, we now do emit(SHADER_TIME_ADD(...)).
The advantage is that we can also insert a shader time write at an
arbitrary location in the instruction stream, rather than being
restricted to emitting at the end.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Cc: mesa-stable at lists.freedesktop.org
commit f1adc45dbe649cdd4538fb96f6d2a27328bbfba1
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sun Mar 8 00:13:41 2015 -0800
i965/fs: Set smear on shader_time diff register.
The ADD(diff, diff, fs_reg(-2u)) instruction reads diff, which is a
width 1 register. We need to read it as <0,1,0> with a subreg of 0,
which is what smear accomplishes.
Fixes assertion:
brw_eu_emit.c:285: validate_reg: Assertion `hstride == 0' failed.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86974
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Cc: mesa-stable at lists.freedesktop.org
commit ef9cc7d0c176669c03130abf576f2b700be39514
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Mar 7 23:01:07 2015 -0800
i965/fs: Set force_writemask_all on shader_time instructions.
These computations don't have anything to do with the currently
executing channels, so they should use force_writemask_all.
This fixes assert failures.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86974
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Cc: mesa-stable at lists.freedesktop.org
commit 7a37d5c3a48c4adec5b5db589b0cb99dc9296f0c
Author: Alexandre Demers <alexandre.f.demers at gmail.com>
Date: Wed Feb 25 01:50:49 2015 -0500
r600g: Use R600_MAX_VIEWPORTS instead of 16
Lets define R600_MAX_VIEWPORTS instead of using 16 here and there
in the code when looping through viewports and scissors. It is
easier to understand what this number represents.
v2: Missed a case where R600_MAX_VIEWPORTS should have been used.
Signed-off-by: Alexandre Demers <alexandre.f.demers at gmail.com>
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit 85df48b45a3bdc8c25b37b243a9f2a2398fc9e24
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Thu Mar 5 11:26:53 2015 -0800
i915: Remove unused IS_GEN2 macro
Inspired by Damien's recent libdrm changes.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau at intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 07a062997a3e1c12ad0e07a7d3f07340689612b8
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Thu Mar 5 10:55:32 2015 -0800
i915: Remove (mostly) unused IS_915 macro
Inspired by Damien's recent libdrm changes.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau at intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 117288dbf305064cd57333bb05442fad0539d0fa
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Thu Mar 5 10:47:56 2015 -0800
i915: Remove (mostly) unused IS_PNV, IS_PNVG, and IS_PNVGM macros
Inspired by Damien's recent libdrm changes.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau at intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 19fda9fc8336795b9898d3773b05549238b72bd0
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Thu Mar 5 10:27:04 2015 -0800
i915: Remove IS_9XX macro
Since the i915 / i965 split, IS_9XX just means IS_GEN3. Inspired by
Damien's recent libdrm changes.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau at intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 6d41316b79cf6d67bcbd155dfb6556e2977080d5
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Thu Mar 5 10:24:57 2015 -0800
i915: Remove unused IS_MOBILE macro
Inspired by Damien's recent libdrm changes.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau at intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit e7d94be1ec9c87063a21731a982ae4677cd43bdf
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Fri Feb 27 18:43:00 2015 -0800
i965: Don't write past the end of the application supplied buffer
Both the AMD and Intel APIs provide a dataSize parameter, and this
function would merrily ignore it. Neither API specifies what to do when
the buffer isn't big enough. I take the easy route of writing all the
complete bits of data that will fit. With more complete specs, we could
probably do something different.
I noticed this while looking into an unused parameter warning. The
warning was actually useful!
brw_performance_monitor.c: In function 'brw_get_perf_monitor_result':
brw_performance_monitor.c:1261:37: warning: unused parameter 'data_size' [-Wunused-parameter]
GLsizei data_size,
^
v2: Fix checks to include offset in the calculation. Noticed by Jan.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jan Vesely <jan.vesely at rutgers.edu>
commit 78a211cee5f3f5fc101e3e68b5b1c8258837a6c3
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Fri Feb 27 18:42:03 2015 -0800
i965: Silence unused parameter warning
All dd functions take a gl_context as the first parameter. Instead of
removing it, just silence the warning.
brw_performance_monitor.c: In function 'brw_new_perf_monitor':
brw_performance_monitor.c:1354:41: warning: unused parameter 'ctx' [-Wunused-parameter]
brw_new_perf_monitor(struct gl_context *ctx)
^
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Carl Worth <cworth at cworth.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 3a6a732c43e6ba6d48575796907f1ed144c7722c
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Fri Feb 27 18:26:11 2015 -0800
i965: Silence many 'static' is not at beginning of declaration warnings
What a useful warning. #ThanksGCC
brw_performance_monitor.c:153:1: warning: 'static' is not at beginning of declaration [-Wold-style-declaration]
const static struct gl_perf_monitor_counter gen5_raw_chaps_counters[] = {
^
brw_performance_monitor.c:185:1: warning: 'static' is not at beginning of declaration [-Wold-style-declaration]
const static int gen5_oa_snapshot_layout[] =
^
brw_performance_monitor.c:221:1: warning: 'static' is not at beginning of declaration [-Wold-style-declaration]
const static struct gl_perf_monitor_group gen5_groups[] = {
^
brw_performance_monitor.c:240:1: warning: 'static' is not at beginning of declaration [-Wold-style-declaration]
const static struct gl_perf_monitor_counter gen6_raw_oa_counters[] = {
^
brw_performance_monitor.c:281:1: warning: 'static' is not at beginning of declaration [-Wold-style-declaration]
const static int gen6_oa_snapshot_layout[] =
^
brw_performance_monitor.c:317:1: warning: 'static' is not at beginning of declaration [-Wold-style-declaration]
const static struct gl_perf_monitor_counter gen6_statistics_counters[] = {
^
brw_performance_monitor.c:332:1: warning: 'static' is not at beginning of declaration [-Wold-style-declaration]
const static int gen6_statistics_register_addresses[] = {
^
brw_performance_monitor.c:346:1: warning: 'static' is not at beginning of declaration [-Wold-style-declaration]
const static struct gl_perf_monitor_group gen6_groups[] = {
^
brw_performance_monitor.c:356:1: warning: 'static' is not at beginning of declaration [-Wold-style-declaration]
const static struct gl_perf_monitor_counter gen7_raw_oa_counters[] = {
^
brw_performance_monitor.c:402:1: warning: 'static' is not at beginning of declaration [-Wold-style-declaration]
const static int gen7_oa_snapshot_layout[] =
^
brw_performance_monitor.c:470:1: warning: 'static' is not at beginning of declaration [-Wold-style-declaration]
const static struct gl_perf_monitor_counter gen7_statistics_counters[] = {
^
brw_performance_monitor.c:493:1: warning: 'static' is not at beginning of declaration [-Wold-style-declaration]
const static int gen7_statistics_register_addresses[] = {
^
brw_performance_monitor.c:515:1: warning: 'static' is not at beginning of declaration [-Wold-style-declaration]
const static struct gl_perf_monitor_group gen7_groups[] = {
^
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Carl Worth <cworth at cworth.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit c82c8b220192bcdc6e39afd42576965b523a9ed5
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Fri Feb 27 18:19:33 2015 -0800
i965/fs: Silence unused parameter warning
I don't this opt_cmod_propagation_local ever used the fs_visitor.
brw_fs_cmod_propagation.cpp:52:40: warning: unused parameter 'v' [-Wunused-parameter]
opt_cmod_propagation_local(fs_visitor *v, bblock_t *block)
^
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit f9779e4a8f2ca67423cded0203adac6ad3d5c448
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Fri Feb 27 18:06:25 2015 -0800
i965/fs: Silence unused parameter warning
Unused since b18fd23.
brw_fs.cpp:2878:44: warning: unused parameter 'dispatch_width' [-Wunused-parameter]
clear_deps_for_inst_src(fs_inst *inst, int dispatch_width, bool *deps,
^
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit e4f26acc08a3d852e60a27d0f0da7001944cb607
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Fri Feb 27 16:43:13 2015 -0800
i965/fs: Silence unused parameter warning
brw_fs_visitor.cpp:2162:56: warning: unused parameter 'offset_components' [-Wunused-parameter]
fs_reg offset_value, unsigned offset_components,
^
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 1e552db5228e4e0acdef1d4bec4503f7116a2622
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Fri Feb 27 14:54:00 2015 -0800
main: Add entry point for TextureBufferRange.
v2: Review by Martin Peres
- Get rid of difficult-to-follow code copied and pasted from
the original TexBufferRange
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 311b3686fe7433b1624384f7d344cc23d6363df2
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Wed Mar 4 14:46:02 2015 -0800
main: Add check_texture_buffer_target.
Creates a shared function to ensure that texture buffer target is
GL_TEXTURE_BUFFER. Helps to clean up the Tex[ture]Buffer[Range] functions.
v2: Review from Anuj Phogat
- Split rebase of Tex[ture]Buffer[Range]
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 5f8c6eabbeb698b6dc653eda9dcf01704e53ae58
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Wed Mar 4 14:45:40 2015 -0800
main: Add check_texture_buffer_range.
Creates a shared function that TexBufferRange and TextureBufferRange can use
to check the buffer range. This cleans up TexBufferRange considerably.
v2: Review from Anuj Phogat
- Split rebase of Tex[ture]Buffer[Range]
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 0f6372946b8bf52658140508d6501fe1bfd180d0
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Wed Mar 4 14:34:27 2015 -0800
main: Cosmetic changes for Texture Buffers.
Adds a useful comment and some whitespace. Fixes an error message.
v2: Review from Anuj Phogat
- Split rebase of Tex[ture]Buffer[Range]
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 6b78a1fb89670fd050747c79a20ecb1b2cd2dc2e
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Wed Mar 4 14:31:29 2015 -0800
main: Refactor _mesa_texture_buffer_range.
Changes how the caller is identified in error messages, moves a check for
ARB_texture_buffer_object from the entry points to the shared code in
_mesa_texture_buffer_range, and removes an unused argument (GLenum target).
v2: Review from Anuj Phogat
- Split rebase of Tex[ture]Buffer[Range]
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit d03337306a59ec7a9c1b4bd37856a95c40c1c801
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Wed Mar 4 14:07:50 2015 -0800
main: Use _mesa_lookup_bufferobj_err to simplify Tex[ture]Buffer[Range].
v2: Review from Anuj Phogat
- Split rebase of Tex[ture]Buffer[Range]
- Closing curly brace on the same line as else
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 768ca8b83e45b1d23c0d3af0b79cc19c1b3b6988
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Fri Jan 9 16:16:48 2015 -0800
main: Add utility function _mesa_lookup_bufferobj_err.
This function is exposed to mesa driver internals so that texture buffer
objects and array objects can use it.
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit ff011340a499d9fe5c3ead6b46b917578bfeb533
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Tue Jan 6 14:05:41 2015 -0800
main: Checking for cube completeness in GetCompressedTextureImage.
v2: Review from Anuj Phogat
- Remove redundant copies of the cube map block comment
- Replace redundant "if (!texImage) return;" statements with
assert(texImage)
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 4080c330fa2868017c99b059b8e5ccf8d4eaa938
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Tue Jan 6 15:27:32 2015 -0800
main: Add TEXTURE_CUBE_MAP support for glCompressedTextureSubImage3D.
v2: Review from Anuj Phogat
- Remove redundant copies of the cube map block comment
- Replace redundant "if (!texImage) return;" statements with
assert(texImage)
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 70eab80f802b26ac87fe9c3e1fa819affe903afd
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Wed Mar 4 11:14:48 2015 -0800
main: assert(texImage) in ARB_DSA texture cube map functions.
ARB_direct_state_access functions that deal with texture cube
maps need to make sure that texture images are not NULL before operating on
them. In the following cases, the error check functions already throw an
error if texImage == NULL, so an assert can be raised instead.
v2: Review from Anuj Phogat
- Replace redundant "if (!texImage) return;" statements with
assert(texImage)
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit c3e92faeb4875de47f0c83ab807b4ea298bfa079
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Wed Mar 4 11:09:17 2015 -0800
main: Remove redundant copy of cube map block comment in GetTextureImage.
The comment describing why ARB_direct_state_access texture cube map functions
use _mesa_cube_level_complete is very long. To save room in the files,
readers are now referred to one central comment on texturesubimage in
teximage.c.
v2: Review from Anuj Phogat
- Remove redundant copies of the cube map block comment
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 8979368f12b96c28774119aff955e7f66a57b3fc
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Wed Mar 4 11:03:18 2015 -0800
main: Remove redundant NumLayers checks.
ARB_direct_state_access texture functions that operate on cube maps no longer
need to verify that cube map texture objects contain six texture images
because _mesa_cube_level_complete now does that for them.
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 1ee000a0b6737d6c140d4f07b6044908b8ebfdc7
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Wed Mar 4 10:49:55 2015 -0800
main: _mesa_cube_level_complete checks NumLayers.
_mesa_cube_level_complete now verifies that a cube map texture object actually
has six texture images before proceeding.
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit c939231e7223510408a446400ad23b8b5ce2922e
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Mar 9 21:20:03 2015 +0100
r300g: fix sRGB->sRGB blits
Cc: 10.5 10.4 <mesa-stable at lists.freedesktop.org>
commit 9953586af2254f83a610d4cd284f52f37fa18b98
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Feb 24 23:15:59 2015 +0100
r300g: fix a crash when resolving into an sRGB texture
Cc: 10.5 10.4 <mesa-stable at lists.freedesktop.org>
commit 113601086d336b4ba8b378c4df6b557461a26ad6
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Mar 9 20:01:26 2015 +0100
r300g: use memset for clearing the shader key
commit 4815c187b7faf48ebf38ac9efb0ed7b126f2a460
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Mar 9 20:05:48 2015 +0100
r300g: remove the broken SNORM->UNORM shader lowering pass
Not used anymore.
commit 74a757f92f7377f59c0feb7f84c7518f9a167631
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Mar 9 20:04:04 2015 +0100
r300g: fix RGTC1 and LATC1 SNORM formats
Cc: 10.5 10.4 <mesa-stable at lists.freedesktop.org>
commit f710b99071fe4e3c2ee88cdcb6bb5c10298e014e
Author: Stefan Dösinger <stefandoesinger at gmx.at>
Date: Mon Mar 9 16:15:13 2015 +0100
r300g: Fix the ATI1N swizzle (RGTC1 and LATC1)
This fixes the GL_COMPRESSED_RED_RGTC1 part of piglit's rgtc-teximage-01
test as well as the precision part of Wine's 3dc format test (fd.o bug
89156).
The Z component seems to contain a lower precision version of the
result, probably a temporary value from the decompression computation.
The Y and W component contain different data that depends on the input
values as well, but I could not make sense of them (Not that I tried
very hard).
GL_COMPRESSED_SIGNED_RED_RGTC1 still seems to have precision problems in
piglit, and both formats are affected by a compiler bug if they're
sampled by the shader with a swizzle other than .xyzw. Wine uses .xxxx,
which returns random garbage.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89156
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
Cc: 10.5 10.4 <mesa-stable at lists.freedesktop.org>
commit 51b43c559f40eed2d02a35014c86b6a3e232c6fa
Author: Tom Stellard <thomas.stellard at amd.com>
Date: Thu Feb 26 21:27:27 2015 -0500
radeonsi: Add additional information to shader dumps
This adds SGPR count, VGPR count, shader size, LDS size, and scratch
usage to shader dumps.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit bbfa1c323917cc54162a64e7882cecaaaa9a7b70
Author: Tom Stellard <thomas.stellard at amd.com>
Date: Fri Mar 6 14:53:00 2015 +0000
radeonsi/compute: Use value from compiler for COMPUTE_PGM_RSRC1.FLOAT_MODE
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit a646b00cfc42fecdf4f853a6fe3ddf12d7801881
Author: Tom Stellard <thomas.stellard at amd.com>
Date: Thu Mar 5 14:30:57 2015 +0000
clover: Return the minimum required value for CL_DEVICE_SINGLE_FP_CONFIG v2
This means dropping CL_FP_DENORM from the current return value.
v2:
- Add comments about minimum values for OpenCL 1.2.
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
Reviewed-by: Jan Vesely <jan.vesely at rutgers.edu>
commit cb3eb43ad690a7355429ba8dcd40120646c55b9c
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Mar 7 18:25:54 2015 -0500
freedreno/ir3: get the # of miplevels from getinfo
This fixes ARB_texture_query_levels to actually return the desired
value.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Rob Clark <robclark at freedesktop.org>
Cc: "10.4 10.5" <mesa-stable at lists.freedesktop.org>
commit 8ac957a51c67fc095db9539df6482b9533b1d05c
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Mar 7 17:41:47 2015 -0500
freedreno/ir3: fix array count returned by TXQ
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Rob Clark <robclark at freedesktop.org>
Cc: "10.4 10.5" <mesa-stable at lists.freedesktop.org>
commit f3dfe6513c26d1ce50b3b0fc830d4d8ff7f6b922
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Mar 2 21:22:27 2015 -0500
freedreno: move fb state copy after checking for size change
Fixes: 1f3ca56b ("freedreno: use util_copy_framebuffer_state()")
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Rob Clark <robclark at freedesktop.org>
Cc: "10.4 10.5" <mesa-stable at lists.freedesktop.org>
commit b9c2fa15e31c4904d4a2526b79ef3f70596c1074
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Feb 19 01:19:13 2015 -0800
nir: Make the printer include nir_variable::location too.
Being able to see both location and driver_location can be useful when
debugging IO mistakes.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit a72fb69604711d4f0e0fe49241d2da0311503f6a
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Thu Mar 5 09:43:38 2015 +0100
i965/fs: Implement SIMD16 dual source blending.
From the SNB PRM, volume 4, part 1, page 193:
"The dual source render target messages only have SIMD8 forms due to
maximum message length limitations. SIMD16 pixel shaders must send two of
these messages to cover all of the pixels. Each message contains two colors
(4 channels each) for each pixel in the message payload."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82831
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 8dcc1f2c10b3dc6ded38e7a6c302f60061ba587c
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Mar 6 01:24:30 2015 -0800
nir: Only do gl_FrontFacing workaround in glsl_to_nir for the FS.
Vertex shaders can have shader inputs where location happens to be
VARYING_SLOT_FACE. Without predicating this on the shader stage,
we suddenly end up with load_front_face intrinsics in vertex shaders,
which is nonsensical.
Fixes spec/arb_vertex_buffer_object/pos-array when using NIR for VS.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit c6f2abe67e38c52361a1d342dca6ec5ed7747913
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Mar 6 01:22:49 2015 -0800
nir: Plumb the shader stage into glsl_to_nir().
The next commit needs to know the shader stage in glsl_to_nir().
To facilitate that, we pass the gl_shader rather than the raw exec_list
of instructions. This has both the exec_list and the stage.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit b200cbb0a41aaebb007668f870a483f0b9ecd898
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Mar 6 01:17:22 2015 -0800
nir: Add native_integers to nir_shader_compiler_options.
glsl_to_nir, tgsi_to_nir, and prog_to_nir all want to know whether the
driver supports native integers. Presumably other passes may as well.
Adding this to nir_shader_compiler_options is an easy way to provide
that information, as it's accessible via nir_shader::options.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit a55da73be46b4576015417b2dff71a719bc8b797
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Mar 6 00:43:28 2015 -0800
nir: Try to make sense of the nir_shader_compiler_options code.
The code in glsl_to_nir is entirely dead, as we translate from GLSL to
NIR at link time, when there isn't a _mesa_glsl_parse_state to pass,
so every caller passes NULL.
glsl_to_nir seems like the wrong place to try and create the shader
compiler options structure anyway - tgsi_to_nir, prog_to_nir, and other
translators all would have to duplicate that code. The driver should
set this up once with whatever settings it wants, and pass it in.
Eric also added a NirOptions field to ctx->Const.ShaderCompilerOptions[]
and left a comment saying: "The memory for the options is expected to be
kept in a single static copy by the driver." This suggests the plan was
to do exactly that. That pointer was not marked const, however, and the
dead code used a mix of static structures and ralloced ones.
This patch deletes the dead code in glsl_to_nir, instead making it take
the shader compiler options as a mandatory argument. It creates an
(empty) options struct in the i965 driver, and makes NirOptions point
to that. It marks the pointer const so that we can actually do so
without generating "discards const qualifier" compiler warnings.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Acked-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 2561aea6b306c4438defeb4ec96be05f6aadd12e
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Mar 6 00:26:25 2015 -0800
nir: Delete nir_shader::user_structures and num_user_structures.
Nothing actually uses these, and the only caller of glsl_to_nir()
(brw_fs_nir.cpp) always passes NULL for the _mesa_glsl_parse_state
pointer, meaning they'll always be NULL and 0, respectively.
Just delete them.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 9f1e250e77ebd9255bbd9a83bd68c9e4068c2aab
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Mar 5 23:18:36 2015 -0800
glsl: Mark array access when copying to a temporary for the ?: operator.
Piglit's spec/glsl-1.20/compiler/structure-and-array-operations/
array-selection.vert test contains the following code:
gl_Position = (pick_from_a_or_b ? a : b)[i];
where "a" and "b" are uniform vec4[2] variables.
ast_to_hir creates a temporary vec4[2] variable, conditional_tmp, and
generates an if-block to copy one or the other:
(declare (temporary) (array vec4 2) conditional_tmp)
(if (var_ref pick_from_a_or_b)
((assign () (var_ref conditional_tmp) (var_ref a)))
((assign () (var_ref conditional_tmp) (var_ref b))))
However, we failed to update max_array_access for "a" and "b", so it
remained 0 - here, the whole array is being accessed. At link time,
update_array_sizes() used this bogus information to change the types
of "a" and "b" to vec4[1]. We then had assignments from a vec4[1] to
a vec4[2], which is highly illegal.
This tripped assertions in nir_split_var_copies with scalar VS.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Cc: mesa-stable at lists.freedesktop.org
commit a84f66a9b6cf46bb19ca71faca5b1d6d81209caf
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Mar 5 20:39:49 2015 -0800
i965/nir: Resolve source modifiers on Gen8+ logic operations.
On Gen8+, AND/OR/XOR/NOT don't support the abs() source modifier, and
negate changes meaning to bitwise-not (~, not -). This isn't what NIR
expects, so we should resolve the source modifers via a MOV.
+30 Piglits (fs-op-bit{and,or,xor}-not-abs-*).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
commit 7c25a4a84d01557945ff0273fb481c24cf509837
Author: Dave Airlie <airlied at gmail.com>
Date: Mon Mar 9 09:51:27 2015 +1000
st/mesa: drop unused texture function
This has no users.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit c5e69409d7f04312b5a928b952b4e97f6b78be1f
Author: Dave Airlie <airlied at gmail.com>
Date: Thu Mar 5 08:19:23 2015 +1000
mesa/st: remove unused TexData
this isn't hooked up to anything at all from what I can see.
Seems like a left over from commit 5d67d4fbebb(st/mesa: remove
st_TexImage(), use core Mesa code instead).
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit fd17db6fe51da8878472582329553cbae663f1db
Author: Rob Clark <robclark at freedesktop.org>
Date: Sun Mar 8 13:38:51 2015 -0400
freedreno: replace glsl130 debug flag with glsl120
Now that relative-dst works, we should never fall back to the old
compiler. (Which is almost true, other than a couple edge case sched
fails in piglit).
So replace glsl130 flag to force GLSL 130 and integers on a3xx/a4xx with
a glsl120 flag to force GLSL 120 and !integers.
If this commit breaks any game/app/etc use FD_MESA_DEBUG=glsl120 as a
workaround and please let me know.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 0e8d58b80a0799728bcb8b65a79ce2d27b32170a
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Jan 29 15:55:41 2015 -0500
gallium/docs: add some freedreno compiler docs
Enable the 'sphinx.ext.graphviz' extension, and add in a section for
driver specific docs, with freedreno compiler docs beneath. The
goal is for more complete compiler docs, and hopefully some docs about
other parts of the driver (such as how tiling works, etc).
Note that there is also a Distribution -> Drivers section. Although
that appears to be simply just a list of drivers. Not sure if that
should move under the 'Drivers' section or left alone. I did add a
one-line section for freedreno in the existing Distribution -> Drivers
section.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 060d3499202c339a27fbc366335f2122ed4ff7bc
Author: Rob Clark <robclark at freedesktop.org>
Date: Fri Jan 23 15:04:46 2015 -0500
freedreno/ir3: relative dst
To simplify RA, assign arrays that are written to first. Since enough
dependency information is in the graph to preserve order of reads and
writes of array, so all SSA names for the array collapse into one, just
assign the entire thing by array-id.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit b7703212d8dc2b38407565768ac45d1a307cd810
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Feb 4 13:41:42 2015 -0500
freedreno/ir3: split out array_fanin() helper
We'll need this too for relative dst..
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 17754b70d78649f29e25dfe938de91d64dbf5ebf
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Feb 4 16:07:44 2015 -0500
freedreno/ir3: drop deref nodes
The meta-deref instruction doesn't really do what we need for relative
destination. Instead, since each instruction can reference at most a
single address value, track the dependency on the address register via
instr->address. This lets us express the dependency regardless of
whether it is used for dst and/or src.
The foreach_ssa_src{_n} iterator macros now also iterates the address
register so, at least in SSA form, the address register behaves as an
additional virtual src to the instruction. Which is pretty much what
we want, as far as scheduling/etc.
TODO:
For now, the foreach_src{_n} iterators are unchanged. We could wrap
the address in an ir3_register and make the foreach_src_{_n} iterators
behave the same way. But that seems unnecessary at this point, since
we mainly care about the address dependency when in SSA form.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit f8f7548f466509bf881db1826ef6dd23ffe2acdf
Author: Rob Clark <robclark at freedesktop.org>
Date: Mon Feb 2 12:54:25 2015 -0500
freedreno/ir3: helpful iterator macros
I remembered that we are using c99.. which makes some sugary iterator
macros easier. So introduce iterator macros to iterate all src
registers and all SSA src instructions. The _n variants also return
the src #, since there are a handful of places that need this.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 26b79ac3e40624726bff5101dfe892d3ee2ba607
Author: Rob Clark <robclark at freedesktop.org>
Date: Sun Feb 1 13:04:09 2015 -0500
freedreno/ir3: fix register usage calculations
For cat1 instructions, use reg() as well for relative src, to ensure
proper accounting of register usage. Also, for relative instructions,
use reg->size rather than reg->wrmask to determine the number of
components read/written.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 3ecc834e752a452bfc445a46ea14d06dc24d7b9b
Author: Rob Clark <robclark at freedesktop.org>
Date: Tue Feb 3 15:53:35 2015 -0500
freedreno/ir3: couple tweaks for cmdline compiler
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 0f797f7b7dd84f0bbb6efc68f230ce99eea00488
Author: Rob Clark <robclark at freedesktop.org>
Date: Fri Jan 23 15:03:51 2015 -0500
freedreno/ir3: split up ssa_dst
And a couple other trivial renames, to prepare for relative dst.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 27648efa2070e8db111908314d8b924d3717dbb0
Author: Rob Clark <robclark at freedesktop.org>
Date: Tue Feb 10 04:42:32 2015 -0500
freedreno/ir3: fix failed assert in grouping
Turns out there are scenarios where we need to insert mov's in "front"
of an input. Triggered by shaders like:
VERT
DCL IN[0]
DCL IN[1]
DCL OUT[0], POSITION
DCL OUT[1], GENERIC[9]
DCL SAMP[0]
DCL TEMP[0], LOCAL
0: MOV TEMP[0].xy, IN[1].xyyy
1: MOV TEMP[0].w, IN[1].wwww
2: TXF TEMP[0], TEMP[0], SAMP[0], 1D_ARRAY
3: MOV OUT[1], TEMP[0]
4: MOV OUT[0], IN[0]
5: END
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 72d4f6c67f8a96956a1a8eeb90449231ba8e0940
Author: Jon TURNEY <jon.turney at dronecode.org.uk>
Date: Thu Mar 5 15:29:32 2015 +0000
c99_alloca.h: Also use <alloca.h> for cygwin
Signed-off-by: Jon TURNEY <jon.turney at dronecode.org.uk>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 1ca39ec03cfba9c032f6e3b8b6c1f24e69bf96ac
Author: Vinson Lee <vlee at freedesktop.org>
Date: Tue Mar 3 18:54:48 2015 -0800
i915: Fix GCC unused-variable warning in release build.
i915_debug_fp.c: In function ‘i915_disassemble_program’:
i915_debug_fp.c:302:11: warning: unused variable ‘size’ [-Wunused-variable]
GLuint size = program[0] & 0x1ff;
^
Signed-off-by: Vinson Lee <vlee at freedesktop.org>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
commit b28c037d64ac7cee7e2c7d9d33b128d62aa4df8a
Author: Mark Janes <mark.a.janes at intel.com>
Date: Fri Mar 6 13:36:55 2015 -0800
r300g: Fix build, invalid extern "C" around header inclusion.
A previous patch to fix header inclusion within extern "C" neglected
to fix the occurences of this pattern in r300 files.
When the helper to detect this issue was pushed to master, it broke
the build for the r300 driver. This patch fixes the r300 build.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89477
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit c4b91a1f5c7ef667708a6b8d734707bbba851437
Author: Mark Janes <mark.a.janes at intel.com>
Date: Fri Mar 6 13:36:54 2015 -0800
nouveau: Fix build, invalid extern "C" around header inclusion.
A previous patch to fix header inclusion within extern "C" neglected
to fix the occurences of this pattern in nouveau files.
When the helper to detect this issue was pushed to master, it broke
the build for the nouveau driver. This patch fixes the nouveau build.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89477
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 20346808cf4f1ee4f320afaf18f94043fb146f2e
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Mar 5 12:09:21 2015 -0500
nv50,nvc0: remove bogus 64_FLOAT formats
There is no HW support for these and the VBO pusher doesn't know about
them. No need to, either, since the st will be lowering them to 2x32.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 1e5f833a0d94943e0fe13be245261757e6c73a2e
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Mar 7 00:33:06 2015 +0000
docs: add news item and link release notes for mesa 10.4.6/10.5.0
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit ac9679b1c5ed533bbb419a4ea94d8cdd0c7a935f
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Mar 6 23:58:47 2015 +0000
docs: Add sha256 sums for the 10.5.0 release
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit 0d3e4ed1349565dea8e6c5139400d7441b8ffdca)
commit b48774e7d8b402497ffccf25b7372bdb7ff49350
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Mar 6 22:55:59 2015 +0000
docs: Update 10.5.0 release notes
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit 97357d475fc8cbb5dbe7bf17ca41f535827fb253)
commit 19c5bee10165d7918dcf4456ce0e546d554d7d21
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Mar 6 19:44:55 2015 +0000
docs: Add sha256 sums for the 10.4.6 release
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit fc9dd495b2adbd329d6b58cd611d2acd8ac3070a)
commit 9fe27c7b9987fd3fa353cc355dce1a9364dc27e6
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Mar 6 19:23:34 2015 +0000
Add release notes for the 10.4.6 release
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit 542a754524a2b149c178a2f70c05b292c7228fc2)
commit bca6c8572f68a21e43982ffec057b30f35465965
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Mar 6 12:41:55 2015 -0700
ilo: clarify valid and preferred tilings
We did it right until the switch to gen_surface_tiling, which has
GEN8_TILING_W. Generally, GEN8_TILING_W may be valid but not preferred.
commit bf061a3d2ec00aa486cda0fb4af04e50e8522868
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Sat Mar 7 01:55:15 2015 +0800
ilo: clean up Gen6 WAs
Add a help function for each WA and make PIPE_CONTROL flags match the WA
descriptions. Call gen6_wa_pre_pipe_contro() only before PIPE_CONTROLs.
Fix missing gen6_wa_pre_3dstate_vs_toggle() in the rectlist path.
commit ba5670fc500cce59a76e241ab384caaf5502e391
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Sat Mar 7 01:44:33 2015 +0800
ilo: add generic ilo_render_3dprimitive()
It replaces gen[6-8]_3dprimitive().
commit 8b2eecfbf8def8ef343529f7b0378dc1b8a36ff9
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Sat Mar 7 01:16:47 2015 +0800
ilo: add generic ilo_render_pipe_control()
It replaces gen[6-8]_pipe_control() and a direct gen6_PIPE_CONTROL() call in
ilo_render_emit_flush().
commit 35b713ad75c9d6be4ad357244b59b39d80dcc77f
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Mar 6 15:10:45 2015 +0800
ilo: fix padding of linear sampler views
Should use the temporary variable in the loop instead of layout->bo_height.
commit dda482384446dae9b48077a2e1bd51b3c1fce8fc
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Mar 6 15:04:47 2015 +0800
ilo: do not check for interleaved_samples
interleaved_samples is only zero-initialized when layout_want_mcs() is called.
We should not check for it. There is also no need to.
commit 56ede80940751bfcdaf26e9c23e439d37ef0e96b
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Mar 6 17:07:40 2015 +0000
Revert "egl/main: use c11/threads' mutex directly"
This reverts commit 6cee785c69a5c8d2d32b6807f9c502117f5a74b0.
Not meant to go in yet. Lacking review.
commit eb14d28e6db25eeecc89faf51837c92cc3dafbed
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Mar 6 17:07:34 2015 +0000
Revert "egl/main: convert thread management to use c11 threads"
This reverts commit 33eff853363d7eba5e61b00431b95f7aa0d7b0a5.
Not meant to go in yet. Lacking review.
commit 3b1d69910dcee3f53e827f1a10adb93992b10a05
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Mar 6 17:07:29 2015 +0000
Revert "configure: require pthreads for POSIX builds"
This reverts commit 50714cec2b50c7836841c09f04bfe875de00ae1d.
Not meant to go in yet. Lacking review.
commit 8f2eaae10c199ed8347e96a9057a580b768c62df
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Mar 6 17:07:23 2015 +0000
Revert "glx: remove final reference to THREADS"
This reverts commit 8b15a883e0ba72c9156d7192a798bb272e0bc528.
Not meant to go in yet. Lacking review.
commit 5e3276f5c7bf1a363de710709737624634389858
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Fri Mar 6 17:07:11 2015 +0000
Revert "glx: remove support for non-multithreaded platforms"
This reverts commit 38591295cd4b68f89f257b20f476f98de3772a47.
Not meant to go in yet. Lacking review.
commit 1c1fd82b4b50fae4644e442b0c2a017f1e428610
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Mar 5 23:48:29 2015 +0000
glx: remove unneeded ifdef _WIN32 guard
The C99 header exists on other platforms as well.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 3f167516399c8e20478bb0081a24ab7ac155b093
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Mar 5 23:40:10 2015 +0000
util: rework _MSC_VER >= 1200 checks
Replace the _MSC_VER >= 1200 with defined (_MSC_VER) and compact if/else
statements. We require MSVC 2008 or later with commit 46110c5d564.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 38591295cd4b68f89f257b20f476f98de3772a47
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Mar 5 23:06:42 2015 +0000
glx: remove support for non-multithreaded platforms
Implicitly required for a while, although commit 9385c592c68 (mapi:
remove u_thread.h) was the one that put the final nail on the
coffin.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 8b15a883e0ba72c9156d7192a798bb272e0bc528
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Mar 5 22:06:06 2015 +0000
glx: remove final reference to THREADS
Left over from commit 18db13f5865(mapi: THREADS was always defined,
remove it)
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 50714cec2b50c7836841c09f04bfe875de00ae1d
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Mar 5 22:36:41 2015 +0000
configure: require pthreads for POSIX builds
This has been an implicit rule for building mesa for a long time. Let's
make it official and just bail out at configure time. This way we can
cleaning up some of our glx code.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 33eff853363d7eba5e61b00431b95f7aa0d7b0a5
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Mar 5 15:30:12 2015 +0000
egl/main: convert thread management to use c11 threads
Convert the code to use the C11 threads implementation, and nuke the
Windows non-pthreads code-path. The c11/threads_win32.h abstraction
should be better than the current code.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 6cee785c69a5c8d2d32b6807f9c502117f5a74b0
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Mar 5 15:07:51 2015 +0000
egl/main: use c11/threads' mutex directly
Remove the inline wrappers/abstraction layer.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit bfb4db83b618d57fcc5f0c9e9fdb3a7ff33d07f3
Author: José Fonseca <jfonseca at vmware.com>
Date: Thu Dec 11 22:14:14 2014 +0000
include: Add helper header to help trap includes inside extern C.
This is just to help repro and fixing these issues with any C++ compiler --
Commiting this will of course wait until all issues are addressed.
$ scons src/glsl/
scons: Reading SConscript files ...
Checking for GCC ... yes
Checking for Clang ... no
Checking for X11 (x11 xext xdamage xfixes glproto >= 1.4.13)... yes
Checking for XCB (x11-xcb xcb-glx >= 1.8.1 xcb-dri2 >= 1.8)... yes
Checking for XF86VIDMODE (xxf86vm)... yes
Checking for DRM (libdrm >= 2.4.38)... yes
Checking for UDEV (libudev >= 151)... yes
warning: LLVM disabled: not building llvmpipe
scons: done reading SConscript files.
scons: Building targets ...
scons: building associated VariantDir targets: build/linux-x86_64-debug/glsl
Compiling src/glsl/ast_array_index.cpp ...
Compiling src/glsl/ast_expr.cpp ...
Compiling src/glsl/ast_function.cpp ...
Compiling src/glsl/ast_to_hir.cpp ...
Compiling src/glsl/ast_type.cpp ...
Compiling src/glsl/builtin_functions.cpp ...
In file included from include/c99_compat.h:28:0,
from src/mapi/u_compiler.h:4,
from src/mapi/u_thread.h:47,
from src/mapi/glapi/glapi.h:47,
from src/mesa/main/mtypes.h:42,
from src/mesa/main/errors.h:47,
from src/mesa/main/imports.h:41,
from src/mesa/main/core.h:44,
from src/glsl/builtin_functions.cpp:58:
include/no_extern_c.h:48:1: error: template with C linkage
template<class T> class _IncludeInsideExternCNotPortable;
^
In file included from include/c99_compat.h:28:0,
from include/c11/threads.h:38,
from src/mapi/u_thread.h:49,
from src/mapi/glapi/glapi.h:47,
from src/mesa/main/mtypes.h:42,
from src/mesa/main/errors.h:47,
from src/mesa/main/imports.h:41,
from src/mesa/main/core.h:44,
from src/glsl/builtin_functions.cpp:58:
include/no_extern_c.h:48:1: error: template with C linkage
template<class T> class _IncludeInsideExternCNotPortable;
^
Compiling src/glsl/builtin_types.cpp ...
Compiling src/glsl/builtin_variables.cpp ...
scons: *** [build/linux-x86_64-debug/glsl/builtin_functions.os] Error 1
scons: building terminated because of errors.
Reviewed-by: Mark Janes <mark.a.janes at intel.com>
commit 7f10e1678e4ff72791a544cbb9da669f373dc78d
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Wed Oct 1 13:55:32 2014 +0200
i965: free scratch buffers when destroying the context
If scratch space is needed for a shader stage we try to reuse the last scratch
buffer bound to that stage. If we can't, we free the old scratch buffer and
allocate a new one. This means we always keep the last scratch buffer for a
particular shader stage around for the entire life span of the context.
These buffers are being reported by Valgrind as definitely lost after
destroying the OpenGL context. For example, for the geometry shader stage:
==18350== 248 bytes in 1 blocks are definitely lost in loss record 85 of 150
==18350== at 0x4C2CC70: calloc (in /usr/lib/valgrind/vgpreload_memcheck-amd64-linux.so)
==18350== by 0xA1B35D6: drm_intel_gem_bo_alloc_internal (intel_bufmgr_gem.c:724)
==18350== by 0xA1B383F: drm_intel_gem_bo_alloc (intel_bufmgr_gem.c:794)
==18350== by 0xA1AEFA3: drm_intel_bo_alloc (intel_bufmgr.c:52)
==18350== by 0x9D08E31: brw_get_scratch_bo (brw_program.c:226)
==18350== by 0x9D2A0F2: do_gs_prog (brw_vec4_gs.c:280)
==18350== by 0x9D2A635: brw_gs_precompile (brw_vec4_gs.c:401)
==18350== by 0x9D14F68: brw_shader_precompile(gl_context*, gl_shader_program*) (brw_shader.cpp:76)
==18350== by 0x9D157B8: brw_link_shader (brw_shader.cpp:269)
==18350== by 0x9B0941E: _mesa_glsl_link_shader (ir_to_mesa.cpp:3038)
==18350== by 0x99AE4ED: link_program (shaderapi.c:917)
==18350== by 0x99AF365: _mesa_LinkProgram (shaderapi.c:1385)
So make sure that by the time we destroy the context we check if we have live
scratch buffers for the various stages and release them if that is the case.
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
commit 970dc2360372a7859691d690bd2f1976c3c97fb0
Author: Ville Syrjälä <ville.syrjala at linux.intel.com>
Date: Mon Jan 19 16:08:31 2015 +0200
i965: Fix URB size for CHV
Increase the device info .urb.size for CHV to match the default URB
size (192kB).
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
commit ced9425327be6cb557a4a1217a1dac29b18d1a09
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Mon Mar 2 10:49:31 2015 +0100
configure: Introduce new output variable to ax_check_python_mako_module.m4
This output variables gives more flexibility for future changes
in autoconf to detect if it is needed to auto-generate files and
check for the auto-generation dependencies.
It is still returning error when Python is not installed.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Kai Wasserbäch <kai at dev.carbon-project.org>
commit 0dfec59a2785cf7a87ee5128889ecebe810b611b
Author: Andrey Sudnik <andrey.sudnik at intel.com>
Date: Thu Mar 5 11:16:49 2015 -0800
i965/vec4: Don't lose the saturate modifier in copy propagation.
Cc: 10.4, 10.5 <mesa-stable at lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89224
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 78df9d5e30fbca8b0795594448a3bcae05d5f5f2
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu Mar 5 11:16:07 2015 -0800
i965/vec4: Handle saturate in dump_instruction().
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit ebad062e9abbc070645dbfd18cf57c24daf7da6c
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Mar 6 04:30:07 2015 +0800
ilo: enable L3 cache in MOCS
This enables L3 cache in MOCS almost everywhere.
commit c7d17f8a80e99014743c0efbdb434c0bb281eb6c
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Mar 6 04:24:34 2015 +0800
ilo: track if a ilo_view_surface is a scanout
Scanouts require a different cache type.
commit e7c74ef43d7dc9c8e6791e8a4083b0776abdcfc6
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Mar 6 04:27:16 2015 +0800
ilo: clean up SURFACE_STATE and BINDING_TABLE_STATE
Add ilo_builder_surface_pointer() to replace ilo_builder_surface_write().
Make Gen8+ take a different path in gen6_SURFACE_STATE().
commit 8b2c845ea0227cf51f51eec90ec51447ae642d5b
Author: Brian Paul <brianp at vmware.com>
Date: Thu Mar 5 07:22:40 2015 -0700
mapi: actually remove unused u_thread.h
I thought this was in the previous commit in the series.
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 60096ed906e5ebfdce41024c7af69f03b96dbe82
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Mar 5 15:27:27 2015 -0500
freedreno/ir3: fix silly typo for binning pass shaders
Was resulting in gl_PointSize write being optimized out, causing
particle system type shaders to hang if hw binning enabled.
Fixes neverball, OGLES2ParticleSystem, etc.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 1a96d9ef1c2821df7e49f6bf685d26c264167933
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Tue Feb 24 17:28:51 2015 +1100
glsl: let interface linking code validate its arrays
Currently intrastage arrays are validated twice for interface blocks.
Reviewed-by: Mark Janes <mark.a.janes at intel.com>
commit c5a56a63f9fe94eaddea358b2fd67a1b7abe9ab0
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Sun Feb 22 22:52:48 2015 +1100
glsl: use common intrastage array validation
Use common intrastage array validation for interface blocks.
This change also allows us to support interface blocks
that are arrays of arrays.
V2: Reinsert unsized array asserts in interstage_match()
Reviewed-by: Mark Janes <mark.a.janes at intel.com>
commit 50859c688c15bd0e98ce20fb1563e61e90aca169
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Sat Feb 21 21:47:14 2015 +1100
glsl: move array validation into its own function
V2: return true when var->type is unsized but max access is within valid range
Reviewed-by: Mark Janes <mark.a.janes at intel.com>
commit aa0705c06c03d2b882ac7b185ed123bc8a10d716
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Mar 4 18:14:31 2015 -0800
i965: Split Gen4-5 BlitFramebuffer code; prefer BLT over Meta.
A while back I switched intel_blit_framebuffer to prefer Meta over the
BLT. This meant that Gen8 platforms would start using the 3D engine
for blits, just like we do on Gen6-7.5.
However, I hadn't considered Gen4-5 when making that change. The BLT
engine appears to be substantially faster on 965GM than using Meta to
drive the 3D engine. This isn't too surprising: original Gen4 doesn't
support tile offsets (that came on G45), and the level/layer fields
don't work for cubemap rendering, so for inconvenient miplevel
alignments, we end up blitting or copying data to/from temporaries
in order to render to it. We may as well just use the blitter.
I chose to use the BLT on Gen4-5 because they use the same ring for
both 3D and BLT; Gen6+ splits it out.
Fixes regressions on 965GM due to botched tile offset code (we should
fix those properly as well, but they're longstanding bugs - for now,
put things back to the status quo).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89430
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Cc: "10.5" <mesa-stable at lists.freedesktop.org>
commit 4ddd981e407f9e97fcbb862c241f1ce165616fd4
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Mar 6 02:03:10 2015 +0800
ilo: add more convenient intel_bo_{ref,unref}()
They both check for NULL and intel_bo_ref() returns the referenced bo. They
replace intel_bo_{reference,unreference}().
commit 70ef171e91582f60a010a4f0ea9f7ff5ba971ab4
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Mar 6 01:36:01 2015 +0800
ilo: add intel_bo_set_tiling()
Make intel_winsys_alloc_bo() always allocate a linear bo, and add
intel_bo_set_tiling() to set the tiling. Document the purpose of tiling.
commit 0ac706535a07d003b9a40f8bad5445dd50f6c35b
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Thu Mar 5 23:53:16 2015 +0800
ilo: replace intel_tiling_mode by gen_surface_tiling
The former is used by the kernel driver to set up fence registers and to pass
tiling info across processes. It lacks INTEL_TILING_W, which made our code
less expressive.
commit eb32ac19569b5f05fc3fa2621b52f2c9fa85556a
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Thu Mar 5 15:25:43 2015 +0800
ilo: update genhw headers
The main change is non-inline <enum>s are now generated as C enums.
commit 237dcb4aa7c39c59bfd225ae3d73caf709be216d
Author: Mark Janes <mark.a.janes at intel.com>
Date: Wed Mar 4 16:37:29 2015 -0800
Fix invalid extern "C" around header inclusion.
System headers may contain C++ declarations, which cannot be given C
linkage. For this reason, include statements should never occur
inside extern "C".
This patch moves the C linkage statements to enclose only the
declarations within a single header.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 2e4c95dfe2cb205c327ceaa12b44a9273bdb20dc
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Mar 4 15:21:53 2015 -0800
i965: Tell intel_get_memcpy() which direction the memcpy() is going.
The SSSE3 swizzling code was written for fast uploads to the GPU and
assumed the destination was always 16-byte aligned. When we began using
this code for fast downloads as well we didn't do anything to account
for the fact that the destination pointer given by glReadPixels() or
glGetTexImage() is not guaranteed to be suitably aligned.
With SSSE3 enabled (at compile-time), some applications would crash when
an SSE aligned-store instruction tried to store to an unaligned
destination (or an assertion that the destination is aligned would
trigger).
To remedy this, tell intel_get_memcpy() whether we're uploading or
downloading so that it can select whether to assume the destination or
source is aligned, respectively.
Cc: 10.5 <mesa-stable at lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89416
Tested-by: Uriy Zhuravlev <stalkerg at gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 5f9ee6a02f54864df166e5dcc7303771d4eac9b3
Author: Mark Janes <mark.a.janes at intel.com>
Date: Thu Mar 5 10:14:16 2015 -0800
mesa/x86: missing stdio inclusions
Several patches added include statements where required by the m64
build. Some files are only compiled for m32, and require similar
changes.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit c97e902a1a69892147e7649581951747f03afaee
Author: Tom Stellard <thomas.stellard at amd.com>
Date: Wed Jul 2 15:42:43 2014 -0400
clover: Enable cl_khr_fp64 for devices that support doubles v4
v2:
- Report correct values for CL_DEVICE_NATIVE_VECTOR_WIDTH_DOUBLE
and CL_DEVICE_PREFERRED_VECTOR_WIDTH_DOUBLE.
- Only define cl_khr_fp64 if the extension is supported.
- Remove trailing space from extension string.
- Rename device query function from cl_khr_fp64() to
has_doubles().
v3:
- Return 0 for device::doubled_fp_confg() when doubles aren't
supported.
v4:
- Remove device query for double fp_config.
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 8d8ca64c28170ec7e9ffa01638bcf8fd30a96088
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Mar 2 15:58:21 2015 +0000
xmlpool: make sure we ship options.h
The header is included in ../xmlpool.h. With the latter of which used
directly in a number of places in mesa.
Note that we can also add it (alongside t_option.h) to noinst_HEADERS,
but neither solution fixes the issue that brough us here - namely:
Do not regenerate the headers, if it already exists.
Cc: "10.5" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit fe5fddd7e2df74233a2a02ae021418485f39d11c
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Mar 2 15:58:20 2015 +0000
mapi: fix *glapi dependency tracking
I.e. add {shared-,}glapi/glapi_mapi_tmp.h to the SOURCES list. Otherwise
there will be no knowledge that the file is required by others for the
build. Thus autotools won't pick it up for the distribution tarball.
v2: Don't forget about the static glapi. Spotted by Matt.
Cc: "10.5" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 2c0f72d5389a9838cc4fbf4cc4f4291aa56c7845
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Mar 2 15:58:19 2015 +0000
mesa: drop Makefile from get_hash.h dependency list
Not required. Additionally this had the side effect of generating the
file, despite it's existence.
Cc: "10.5" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit d22391cb165af4ed2f9a9e5d6233072a432cc969
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Mar 2 15:58:18 2015 +0000
mesa: fix dependency tracking of generated sources
Some of the files generated were not in the SOURCES variable, thus
although generated prior to compilation the dependency tracking was
incomplete. The latter of which resulted in the files missing from the
distribution tarball.
Cc: "10.5" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 3f6c28f2a976e35128b7a4a513cfa60af00301e1
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Mar 2 15:58:17 2015 +0000
mesa: rename format_info.c to format_info.h
The file is auto-generated, and #included by formats.c. Let's rename it
to reflect the latter. This will also help up fix the dependency
tracking by adding it to the _SOURCES variable, without the side effect
of it being compiled (twice).
v2: Update .gitignore to reflect the rename.
Cc: "10.4, 10.5" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit abae3434c42ce55d0aa26443e52fea98cc7cfe32
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Mar 2 15:58:16 2015 +0000
mesa/main: update .gitignore
Drop the no longer present get_es{1,2}.c from the list.
v2: Keep the format_info.c rename hunk out of this patch.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit d1fbea038b29579a578ff4e1babbce8c39365d36
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Feb 28 17:14:31 2015 +0000
egl/main: remove no-longer needed definition of stdint types
All the users directly include the header, plus we have a in-tree
replacements for non C99 compilers which we already use.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit bf0e4d219a8cf396402b46c265eb35afd22a676d
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Feb 28 17:12:40 2015 +0000
egl/drivers: include stdint.h where needed
Currently these files are including it indirectly via eglcompiler.h
The latter of which will be removed with follow up commits.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 74c40b9b5676c836b3d6ea2ff32e3d1913a0e559
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Feb 28 16:51:21 2015 +0000
egl/main: drop the declaration of PUBLIC keyword.
Should no longer be used. As many places indirectly include
eglcompiler.h keep this change separate, so that it can be easily
reverted, if needed.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit dd438ae34bdbaa6651cdd226d5fec15a892923bf
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Feb 28 17:20:01 2015 +0000
egl/main: no longer export internal function
With the split of the gallium egl module we had previously it required
access to some of the internal functions. As the only build (automake)
that did this no longer builds it we can now appropriately hide those
functions.
Cc: 10.5 <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit d780012cd75c24394b043b107d17eb8199ae2dc7
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Feb 28 16:39:10 2015 +0000
egl/main: replace __FUNCTION__ with __func__
The latter is a C99 standard, and our current wrapper c99_compat.h
should handle non-compliant compilers.
Drop the c99_compat.h inclusion from eglcompiler.h altogether, as it's
no longer required.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 7bd1693877e4de9aaf8f6776649fc48db54ec82b
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Feb 28 16:35:22 2015 +0000
egl/main: replace INLINE with inline
Drop the custom keyword in favour of the C99 one. All the places using
it now directly include c99_compat.h which should handle things on
platforms which lack it.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 9385c592c68e7304cd9084fe17f27ec17319cdcf
Author: Brian Paul <brianp at vmware.com>
Date: Wed Mar 4 19:17:57 2015 -0700
mapi: remove u_thread.h
Just use c11 threads directly.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: José Fonseca <jfonseca at vmware.com>
commit 262cd683e22ec64645a50b558f91001b75ea2000
Author: Brian Paul <brianp at vmware.com>
Date: Wed Mar 4 19:17:57 2015 -0700
mapi: use c11 call_once() instead of pthread_once()
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: José Fonseca <jfonseca at vmware.com>
commit 18db13f586509f4fc196839886efcfd0715d8db0
Author: Brian Paul <brianp at vmware.com>
Date: Wed Mar 4 19:17:57 2015 -0700
mapi: THREADS was always defined, remove it
THREADS was defined if HAVE_PTHREADS or _WIN32 was defined. That's
always the case. The build would die in c11/threads.h otherwise.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: José Fonseca <jfonseca at vmware.com>
commit fac77912b5faa2394e0c0a88f3862eae9d87967a
Author: Brian Paul <brianp at vmware.com>
Date: Wed Mar 4 19:17:57 2015 -0700
mesa: remove THREADS check, printf calls in debug.c
THREADS is going away in the next commit.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: José Fonseca <jfonseca at vmware.com>
commit 458c7490c29ef2960a33a089f65490e044da5d27
Author: Brian Paul <brianp at vmware.com>
Date: Wed Mar 4 19:17:57 2015 -0700
mapi: rewrite u_current_init() function without u_thread_self()
Remove u_thread_self() since u_thread.h is going away soon.
Create a simple thread ID abstraction which wraps WIN32 or c11 threads.
This also gets rid of the questionable casting of thrd_t to an unsigned
long.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: José Fonseca <jfonseca at vmware.com>
commit 6b5eb7bce6ac5351b0c96252a1c8738f51834e1d
Author: Brian Paul <brianp at vmware.com>
Date: Wed Mar 4 19:17:57 2015 -0700
mapi: fix preprocessor check in u_current_destroy()
So it matches the preprocessor check around the u_current_init_tsd() code.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: José Fonseca <jfonseca at vmware.com>
commit c3f352e8367f03cc416968d780f5dc6a6812a496
Author: Brian Paul <brianp at vmware.com>
Date: Wed Mar 4 19:17:57 2015 -0700
mapi: remove u_macros.h
Only U_STRINGIFY() is used in entry.c
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: José Fonseca <jfonseca at vmware.com>
commit 83926b8193cfbb3ad259760567babb4eab7c5fe7
Author: Brian Paul <brianp at vmware.com>
Date: Wed Mar 4 19:17:57 2015 -0700
osmesa: include stdio.h
Acked-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: José Fonseca <jfonseca at vmware.com>
commit 80524549f06cc98cb77d18715a79c0fc989c0bff
Author: Brian Paul <brianp at vmware.com>
Date: Wed Mar 4 19:17:57 2015 -0700
xlib: include stdio.h
Acked-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: José Fonseca <jfonseca at vmware.com>
commit 8f1a11bfc4a48abff77f80dd3c2b043efc9787d4
Author: Brian Paul <brianp at vmware.com>
Date: Wed Mar 4 19:17:57 2015 -0700
st/osmesa: include stdio.h
Acked-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: José Fonseca <jfonseca at vmware.com>
commit 8c68987d0962f0a6c0b5157ccc2d8ab074fbadfd
Author: Brian Paul <brianp at vmware.com>
Date: Wed Mar 4 19:17:57 2015 -0700
st/xlib: include stdio.h
Acked-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: José Fonseca <jfonseca at vmware.com>
commit 68579c4a5c43bf946b6a1301d360468761d46644
Author: Brian Paul <brianp at vmware.com>
Date: Wed Mar 4 19:17:57 2015 -0700
st/xlib: include stdio.h
Acked-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: José Fonseca <jfonseca at vmware.com>
commit fe976ceb76d71189eff866ede2538572af09c4bf
Author: Brian Paul <brianp at vmware.com>
Date: Wed Mar 4 19:17:57 2015 -0700
st/mesa: include stdio.h where needed
Acked-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: José Fonseca <jfonseca at vmware.com>
commit 2655afc7e68a0c7dacbd7cf653f11105790b50a6
Author: Brian Paul <brianp at vmware.com>
Date: Wed Mar 4 19:17:57 2015 -0700
swrast: include stdio.h where needed
Acked-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: José Fonseca <jfonseca at vmware.com>
commit 78ee6fdb2303a630925405bf12af2b61f20383d7
Author: Brian Paul <brianp at vmware.com>
Date: Wed Mar 4 19:17:57 2015 -0700
nouveau: include stdio.h where needed
Acked-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: José Fonseca <jfonseca at vmware.com>
commit f330ab93835c98e778dc22a50f8a018eb01d2ec3
Author: Brian Paul <brianp at vmware.com>
Date: Wed Mar 4 19:17:57 2015 -0700
dri/common: include stdio.h where needed
Acked-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: José Fonseca <jfonseca at vmware.com>
commit db9a088d329453bcdc770e5caf7578c1eaf67aa7
Author: Brian Paul <brianp at vmware.com>
Date: Wed Mar 4 19:17:57 2015 -0700
glsl: include stdio.h where needed
Acked-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: José Fonseca <jfonseca at vmware.com>
commit db29869205ecc2d7254698daac3e9027f6c92619
Author: Brian Paul <brianp at vmware.com>
Date: Wed Mar 4 19:17:57 2015 -0700
mesa: include stdio.h where needed
Instead of relying on glapi.h or some other header to provide it.
Acked-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: José Fonseca <jfonseca at vmware.com>
commit 028968a3ce317cead6aec29890308f8242d547dd
Author: Brian Paul <brianp at vmware.com>
Date: Wed Mar 4 19:17:56 2015 -0700
mesa: include c11/threads.h in mtypes.h
Let's directly include c11/threads.h instead of relying on glapi.h
to provide it.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: José Fonseca <jfonseca at vmware.com>
commit 7286a6899176a8b26aa794097288eff941f5178c
Author: Neil Roberts <neil at linux.intel.com>
Date: Wed Feb 25 15:33:08 2015 +0000
meta: Fix the y offset for 1D_ARRAY in _mesa_meta_pbo_TexSubImage
The yoffset needs to be interpreted as a slice offset for 1D array
textures. This patch implements that by moving the yoffset into
zoffset similar to how it moves the height into depth.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Cc: "10.5" <mesa-stable at lists.freedesktop.org>
commit a08bff1e98b8e630f8bdf341af1491cd99e7d104
Author: Neil Roberts <neil at linux.intel.com>
Date: Thu Feb 26 12:53:50 2015 +0000
meta: Allow GL_UN/PACK_IMAGE_HEIGHT in _mesa_meta_pbo_Get/TexSubImage
Now that a layered source PBO is interpreted as a single tall 2D image
it's quite easy to accept the image height packing option by just
creating an image that is tall enough to include the image padding.
I'm not sure whether the image height property should affect 1D_ARRAY
textures. My intuition and interpretation of the GL spec (which is a
bit vague) would be that it shouldn't. However the software fallback
path in Mesa uses the property for packing but not for unpacking. The
binary NVidia driver uses it for both. This patch doesn't use it for
either case so it is different from the software fallback. There is
some discussion about this here:
http://lists.freedesktop.org/archives/mesa-dev/2015-February/077925.html
This is tested by the texsubimage Piglit test with the array and pbo
arguments. Previously this test was skipping this code path because it
always sets the image height.
I've also tested it by modifying the getteximage-targets test. It
wasn't using this code path before because it was using the default
texture object so this code couldn't successfully create a frame
buffer. I also modified it to add some image padding with the image
height in the PBO.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Cc: "10.5" <mesa-stable at lists.freedesktop.org>
commit 7d10d2feee381739eef97f4720cbadbd65bb4fc6
Author: Neil Roberts <neil at linux.intel.com>
Date: Thu Feb 26 12:12:15 2015 +0000
Revert "common: Fix PBOs for 1D_ARRAY."
This reverts commit 546aba143d13ba3f993ead4cc30b2404abfc0202.
I think the changes to the calls to glBlitFramebuffer from this patch
are no different to what it was doing previously because it used to
set height to 1 before doing the blits. However it was introducing
some problems with the blit for layer 0 because this was no longer
special cased. It didn't fix problems with the yoffset which needs to
be interpreted as a slice offset. I think a better solution would be
to modify the original if statement to cope with the yoffset.
Conflicts:
src/mesa/drivers/common/meta_tex_subimage.c
Cc: "10.5" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 29c23644cc8cfe9a1cdd75f79a96a1c9b49d26fa
Author: Vinson Lee <vlee at freedesktop.org>
Date: Tue Mar 3 18:46:13 2015 -0800
glsl: Fix GCC unused-variable warning in release build.
CXX ast_array_index.lo
ast_array_index.cpp: In function ‘void update_max_array_access(ir_rvalue*, int, YYLTYPE*, _mesa_glsl_parse_state*)’:
ast_array_index.cpp:86:30: warning: unused variable ‘interface_type’ [-Wunused-variable]
const glsl_type *interface_type =
^
Signed-off-by: Vinson Lee <vlee at freedesktop.org>
Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
commit b5eb6f769db71557c86c72c3352db149379fdade
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Wed Mar 4 14:38:50 2015 -0700
ilo: improve WA handling in rectlist path
Add wrappers for 3DPRIMITIVE to make sure we clear current_pipe_control_dw1
and deferred_pipe_control_dw1 after it. Add missing
gen7_wa_post_ps_and_later().
commit 1424bdd61bce26f0853e974fc3b87c4c275e6ef0
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Wed Mar 4 14:09:26 2015 -0700
ilo: clean up Gen7.5 WAs
These WAs
gen7_wa_post_3dstate_push_constant_alloc_ps()
gen7_wa_pre_vs()
gen7_wa_pre_3dstate_sf_depth_bias()
first half of gen7_wa_pre_depth()
gen7_wa_post_ps_and_later()
are Gen7-specific. Update copy-and-pasted gen8_wa_pre_depth() also.
commit a398168f7238b42c2fbecf940e09fc5ebef71f62
Author: Tom Stellard <thomas.stellard at amd.com>
Date: Wed Mar 4 13:09:50 2015 -0800
clover: Fix build since llvm r231270
commit 68d2e395d9e18898ef74a635a93dfc4501c1c507
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Wed Mar 4 13:07:55 2015 -0700
ilo: add ILO_DEBUG=hang
When set, detect and dump the hanging batch bufffer.
commit af4cff5d6f74460d34bc10f9dc3a9f91e4e11f2d
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Wed Mar 4 12:02:12 2015 -0700
ilo: add some more winsys functions
Add intel_winsys_get_reset_stats(), intel_winsys_import_userptr(), and
intel_bo_map_async(). The latter two are stubs, but we are not going to use
them immediately either.
commit 1e128e9b69c6336762a2b6ee5d356c763b9ae3b0
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Feb 27 10:22:21 2015 -0800
i965/fs: Don't propagate cmod to inst with different type.
Cc: 10.5 <mesa-stable at lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89317
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit ade0b580e75bdea227eec5345f6681b678d0811b
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Mar 3 16:09:58 2015 -0800
r300g: Check return value of snprintf().
Would have at least prevented the crash the previous patch fixed.
Cc: 10.4, 10.5 <mesa-stable at lists.freedesktop.org>
Bugzilla: https://bugs.gentoo.org/show_bug.cgi?id=540970
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
commit f5e2aa1324dd6a9666bb21834097d2fbc3cb99b6
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Mar 3 16:02:40 2015 -0800
r300g: Use PATH_MAX instead of limiting ourselves to 100 chars.
When built with Gentoo's package manager, the Mesa source directory
exists seven directories deep. The path to the .test file is too long
and is silently truncated, leading to a crash. Just use PATH_MAX.
Cc: 10.4, 10.5 <mesa-stable at lists.freedesktop.org>
Bugzilla: https://bugs.gentoo.org/show_bug.cgi?id=540970
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
commit 67e0a4f6e8a6c6d03cf3f9d15797bc14c373711e
Author: Brian Paul <brianp at vmware.com>
Date: Wed Mar 4 10:03:09 2015 -0700
glx/tests: add -I src/ to fix make check
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 10c82c6c5fc415d323a5e9c6acdc6a4c85d6b712
Author: Kristian Høgsberg <krh at bitplanet.net>
Date: Mon Mar 2 16:19:52 2015 -0800
i965: Fix uint64_t overflow in intel_client_wait_sync()
DRM_IOCTL_I915_GEM_WAIT takes an int64_t for the timeout value but
GL_ARB_sync takes an uint64_t. Further, the ioctl used to wait
indefinitely when passed a negative timeout, but it's been broken and
now returns immediately in that case. Thus, if an application passes
UINT64_MAX to wait forever, we overflow to -1LL and return immediately.
Work around this mess by clamping the wait timeout to INT64_MAX.
Signed-off-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit 65c8965d033cf9ade5e6f3c88bda6d247d46af9d
Author: Daniel Stone <daniels at collabora.com>
Date: Mon Mar 2 13:52:59 2015 +0000
egl: Take alpha bits into account when selecting GBM formats
This fixes piglit when using PIGLIT_PLATFORM=gbm
Tom Stellard:
- Fix ARGB2101010 format
Cc: "10.4 10.5" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit b709adf7cca24412a6c1bb813856ca701e534ffd
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Mar 4 11:36:32 2015 -0500
freedreno/ir3: fix old compiler after f6b2e8af742
If first_driver_param is left as zero (calloc'd struct), the result is
c0 getting clobbered.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 34ff9bc6696f3bb84406850d9bc59dfda4bcf8d6
Author: Brian Paul <brianp at vmware.com>
Date: Tue Mar 3 13:20:56 2015 -0700
gallivm: init MM = NULL to silence warning
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 8aa9191878a5608fc6e4e8c72bea1d25cd821dec
Author: Brian Paul <brianp at vmware.com>
Date: Tue Mar 3 17:15:05 2015 -0700
mapi: remove u_compiler.h
Just include c99_compat.h or util/macros.h where needed.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 4ab713423ffbdb885910f0c0efcabb594e55d227
Author: Brian Paul <brianp at vmware.com>
Date: Tue Mar 3 09:11:35 2015 -0700
mapi: use util/macros.h instead of locally defined macros
The next step is to get rid of u_compiler.h completely.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 41c87cc5666de7ec5cfdea2c035c671048c06ca5
Author: Brian Paul <brianp at vmware.com>
Date: Tue Mar 3 09:08:22 2015 -0700
mapi: replace INLINE with inline
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 5bebd7099ab22c6f1498cd928170561718d6ff36
Author: Brian Paul <brianp at vmware.com>
Date: Tue Mar 3 09:01:03 2015 -0700
mesa: consolidate PUBLIC macro definition
Define the macro in src/util/macros.h rather than in two different
places. Note that USED isn't actually used anywhere at this time.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 25656753d765680ea4a592ff812deac132e2262d
Author: Brian Paul <brianp at vmware.com>
Date: Tue Mar 3 09:18:36 2015 -0700
st/xlib: include p_compiler.h to get PUBLIC definition
To prevent build break with following changes.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 25a847d9cc046584aa43894f70da1bf11ba48f09
Author: Brian Paul <brianp at vmware.com>
Date: Tue Mar 3 09:40:40 2015 -0700
mapi: remove unneeded ARRAY_SIZE #define
include util/macros.h instead.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 0339e7dbdab2ee3a4776e50461bc4697a23b57b6
Author: Brian Paul <brianp at vmware.com>
Date: Tue Mar 3 09:51:19 2015 -0700
glx: use ARRAY_SIZE from macros.h
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 6e836d2c8643dff127c0aef22dcabed763d7ea3e
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Wed Mar 4 13:56:35 2015 +0000
scons: Update for the fact that we require GCC 4.2
Reviewed-by: Brian Paul <brianp at vmware.com>
commit d0b1c74b73ddc7590e81bdfd837f540d75b172ce
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Wed Mar 4 14:25:54 2015 +0000
svga: Set MSVC2013 compat flags.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 2c25008e8e37a41fa61988b7fb65b524cbb7e64f
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Wed Mar 4 14:25:39 2015 +0000
softpipe,trace: Set MSVC 2008 compat flags.
Although we don't deploy these, we need to use them for debugging.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 00faf9f00059370bc20ebeaf00884c2d8ef15a74
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Wed Mar 4 14:23:52 2015 +0000
scons: Use -Werror MSVC compatibility flags per-directory.
Matching what we already do with autotools builds.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 3acd7a34ab05b87521b74f626ec637e7fdcc6595
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Tue Mar 3 16:58:21 2015 +0000
st/vega: Remove.
OpenVG API seems to have dwindled away. The code
would still be interesting if we wanted to implement NV_path_rendering
but given the trend of the next gen graphics APIs, it seems
unlikely that this becomes ARB or core.
v2: Remove a few "openvg" references left, per Emil Velikov.
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
v3: Update release notes.
commit 5564c361b5cc1f5ec4be3622d7f9be601e3c268a
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Tue Mar 3 16:01:22 2015 +0000
st/egl: Remove.
Largely superseeded by src/egl, and
WGL/GLX_EXT_create_context_es_profile extensions.
Note this will break Android.mk with gallium drivers -- somebody
familiar with that build infrastructure will need to update it to use
gallium drivers through egl_dri2.
v2: Remove the _EGL_BUILT_IN_DRIVER_GALLIUM define from
src/egl/main/Android.mk; and update the src/egl/main/Sconscript to
create a SharedLibrary, add versioning, create symlink - copy the bits
from egl-static, per Emil Velikov.
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
v3: Disallow undefined symbols in libEGL.so. Update release notes
commit 17b2825d760fb6a7b643e5f9c067d249a582cfdb
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Tue Mar 3 14:52:15 2015 +0000
windows/gdi: Remove.
This classic driver is so far behind Gallium softpipe/llvmpipe based
one, that's hard to imagine ever being useful.
v2: Drop drivers/windows from src/mesa/Makefile.am:EXTRA_DIST per Emil
Velikov.
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
v3: Update release notes.
commit 40a4797384d89c4ae225e1999ebe502cd50b2500
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Fri Feb 27 15:32:24 2015 +0000
nir: Use helper macros for dealing with VLAs.
v2:
- Single statement, by using memset return value as suggested by Ian
Romanick.
- No internal declaration, as suggested by Jason Ekstrand.
- Move macros to a header.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 073a5d2e84ac9d95f0d037aeb04889822e76aa4e
Author: Marc-Andre Lureau <marcandre.lureau at gmail.com>
Date: Fri Feb 27 19:40:19 2015 +0100
gallium/auxiliary/indices: fix start param
Since commit 28f3f8d, indices generator take a start parameter. However, some
index values have been left to start at 0.
This fixes the glean/fbo test with the virgl driver, and copytexsubimage
with freedreno.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.4 10.5" <mesa-stable at lists.freedesktop.org>
commit b77576edc1a8010e5457f82b41c335ae27cb066b
Author: Vinson Lee <vlee at freedesktop.org>
Date: Sun Mar 1 00:41:48 2015 -0800
scons: Define _DEFAULT_SOURCE.
Fix GCC cpp warnings with glibc >= 2.19.
/usr/include/features.h:148:3: warning: #warning "_BSD_SOURCE and _SVID_SOURCE are deprecated, use _DEFAULT_SOURCE" [-Wcpp]
# warning "_BSD_SOURCE and _SVID_SOURCE are deprecated, use _DEFAULT_SOURCE"
^
Signed-off-by: Vinson Lee <vlee at freedesktop.org>
Acked-by: Emil Velikov <emil.l.velikov at gmail.com>
commit e43729943e67972e547a19123fb3afca6b77202b
Author: Frank Henigman <fjhenigman at google.com>
Date: Thu Feb 19 15:09:20 2015 -0800
intel: fix EGLImage renderbuffer _BaseFormat
Correctly set _BaseFormat field when creating a gl_renderbuffer
with EGLImage storage.
Change-Id: I8c9f7302d18b617f54fa68304d8ffee087ed8a77
Signed-off-by: Frank Henigman <fjhenigman at google.com>
Reviewed-by: Stéphane Marchesin <marcheu at chromium.org>
Reviewed-by: Chad Versace <chad.versace at intel.com>
commit 8e67fd798e750fde213c6c401964e065e7dbe5e5
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Feb 26 19:37:31 2015 -0500
freedreno/a4xx: re-enable int (conditional on glsl130)
Re-enable integer, now that we can handle flat varyings. Still, ofc,
conditional on FD_MESA_DEBUG=glsl130, until we can deprecate _old
compiler..
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit e9f2abe349886ae5423c7c31d201e7d587a3695a
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Feb 25 13:54:25 2015 -0500
freedreno/ir3: handle flat bypass for a4xx
We may not need this for later a4xx patchlevels, but we do at least need
this for patchlevel 0. Bypass bary.f for fetching varyings when flat
shading is needed (rather than configure via cmdstream). This requires
a special dummy bary.f w/ (ei) flag to signal to scheduler when all
varyings are consumed. And requires shader variants based on rasterizer
flatshade state to handle TGSI_INTERPOLATE_COLOR.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 9d732d3125e1b39788a642a5723aeb54cb1983f3
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Feb 26 15:13:10 2015 -0500
freedreno/ir3: add support for memory (cat6) instructions
Scheduled basically the same as texture (cat5) instructions, using (sy)
flag for synchronization.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 20b50a071271e2caf8a4c3d4fd72f877af8a18d9
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Feb 26 13:35:31 2015 -0500
freedreno/ir3: fix up cat6 instruction encodings
I think there is at least one more sub-encoding, but these two should be
enough to cover the common load/store instructions.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 4abb789bca95e9c23b2339ea7732833203c94639
Author: Rob Clark <robclark at freedesktop.org>
Date: Fri Feb 27 09:02:48 2015 -0500
tgsi/lowering: don't forget interp for BCOLOR inputs
To lower two sided color, tgsi_lowering creates additional BCOLOR inputs
(matching up to the BCOLOR outputs on the vert shader). These inputs
should copy the interpolation state of their matching COLOR input.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 583a8a8f65c3086d21de864c602c6aa6283bcd45
Author: Rob Clark <robclark at freedesktop.org>
Date: Thu Feb 26 21:06:02 2015 -0500
freedreno/a3xx,a4xx: silence some warnings
fd3_emit.c: In function ‘fd3_emit_vertex_bufs’:
fd3_emit.c:377:11: warning: unused variable ‘semantic’ [-Wunused-variable]
uint8_t semantic = sem2name(vp->inputs[i].semantic);
and
fd4_emit.c: In function ‘fd4_emit_vertex_bufs’:
fd4_emit.c:304:11: warning: unused variable ‘semantic’ [-Wunused-variable]
uint8_t semantic = sem2name(vp->inputs[i].semantic);
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 5ece2888769c2886b181d228ad447a8bca2ddee0
Author: Brian Paul <brianp at vmware.com>
Date: Tue Mar 3 08:09:21 2015 -0700
c99_alloca.h: add case for __sun
Reviewed-by: Alan Coopersmith <alan.coopersmith at oracle.com>
commit 80c5bd7ef0319d14cd0362a763d9d15e9ba2c946
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Thu Feb 26 16:46:48 2015 +0000
configure: Leverage gcc warn options to enable safe use of C99 features where possible.
The main objective of this change is to enable Linux developers to use
more of C99 throughout Mesa, with confidence that the portions that need
to be built with MSVC -- and only those portions --, stay portable.
This is achieved by using the appropriate -Werror= options only on the
places they need to be used.
Unfortunately we still need MSVC 2008 on a few portions of the code
(namely llvmpipe and its dependencies). I hope to eventually eliminate
this so that we can use C99 everywhere, but there are technical/logistic
challenges (specifically, newer Windows SDKs no longer bundle MSVC,
instead require a full installation of Visual Studio, and that has
hindered adoption of newer MSVC versions on our build processes.)
Thankfully we have more directy control over our OpenGL driver, which is
why we're now able to migrate to MSVC 2013 for most of the tree.
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 3d4d77a5dc7bc9f60d7845ff1d8d5b23f988232a
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Fri Nov 28 14:28:19 2014 -0800
i965: Fix assertion in brw_reg_type_letters
While using various debugging features (optimization debug, instruction dumping,
etc) this function is called in order to get a readable letter for the type of
unit.
On GEN8, two new units were added, the Qword and the Unsigned Qword (Q, and UQ
respectively). The existing assertion tries to determine that the argument
passed in is within the correct boundary, however, it was using UQ as the upper
limit instead of Q.
To my knowledge you can only hit this case with the branch I am currently
working on, so it doesn't fix any known issues.
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 37c2687645bf44515dbd1bc1c066b02889ca46c4
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Thu Feb 26 23:01:33 2015 -0800
i965: Rename some PIPE_CONTROL flags
I'm not really sure of the origins of the existing flag names. Modern docs have
some slightly different names. Having the correct names makes it easier to
determine if existing PIPE_CONTROL flag settings are correct, as well as making
adding new PIPE_CONTROLs easier.
This originally came up while I was trying to implement workarounds and spotted
some things called, "flush" which should have been called "invalidate."
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit e214000f258ae564e64d839cccee9418526f226b
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Jan 13 15:35:57 2015 -0800
i965/fs: Don't use backend_visitor::instructions after creating the CFG.
This is a fix for a regression introduced in commit a9f8296d ("i965/fs:
Preserve the CFG in a few more places.").
The errata this code works around is described in a comment before the function:
"[DevBW, DevCL] Errata: A destination register from a send can not be
used as a destination register until after it has been sourced by an
instruction with a different destination register.
The framebuffer write's sources must be in message registers, which SEND
instructions cannot have as a destination. There's no way for this
errata to affect anything at the end of the program. Just remove the
code.
Cc: 10.4, 10.5 <mesa-stable at lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84613
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit c4925d7f3b66d63fbdd7b7607cd809db1e58bee9
Author: Jason Ekstrand <jason at jlekstrand.net>
Date: Fri Feb 27 18:53:11 2015 -0500
main/base_tex_format: Properly handle STENCIL_INDEX1/4/16
This takes "fbo-stencil blit GL_STENCIL_INDEX1/4/16" from crash to pass on
BDW.
Cc: 10.5 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit b1ab02d9c0cc11ba8ef4efaba9452d644b6a0811
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Feb 27 12:29:03 2015 -0800
meta/TexSubImage: Stash everything other than PIXEL_TRANSFER/store in meta_begin
Previously, there were bugs where if the app set a scissor it could affect
the area of the texture that was downloaded. There was also potential that
the framebuffer SRGB state could affect downloads. This ensures that those
will get saved/restored and can't affect the texture download.
Cc: 10.5 <mesa-stable at lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89292
Reviewed-by: Neil Roberts <neil at linux.intel.com>
commit 93a8c702a6582049d2f49c752fdaab1df625cc0c
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Feb 20 20:32:14 2015 -0800
i915: Remove hand-rolled memcpy implementation.
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 54d7925012c639e7ff93eb2ae65404df290a5f91
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Feb 20 20:28:52 2015 -0800
i965: Remove hand-rolled memcpy implementation.
Reviewed-by: Eric Anholt <eric at anholt.net>
commit da20bf068ef0f816968d9bc4dfea81facf0fd680
Author: Matt Turner <mattst88 at gmail.com>
Date: Sat Feb 28 13:36:21 2015 -0800
i965: Consider scratch writes to have side effects.
We could do better by tracking scratch reads and writes.
Cc: 10.5 <mesa-stable at lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88793
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 491d42135ad0e5670756216154f2ba9fc79d4ba7
Author: Matt Turner <mattst88 at gmail.com>
Date: Sat Feb 28 11:14:02 2015 -0800
mesa: Correct backwards NULL check.
Cc: "10.4, 10.5" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 87109acbed9c9b52f33d58ca06d9048d0ac7a215
Author: Matt Turner <mattst88 at gmail.com>
Date: Sat Feb 28 11:08:17 2015 -0800
mesa: Free memory allocated for luminance in readpixels.
Cc: "10.4, 10.5" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 2b2fa1865248c6e3b7baec81c4f92774759b201f
Author: Matt Turner <mattst88 at gmail.com>
Date: Sat Feb 28 11:00:51 2015 -0800
mesa: Indent break statements and add a missing one.
Always indenting break statements makes spotting missing ones easier.
Cc: "10.4, 10.5" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
commit 3de01d2fe46652471362bcb8a527f59e0bb81cfc
Author: Vinson Lee <vlee at freedesktop.org>
Date: Sun Mar 1 13:52:00 2015 -0700
c99_alloca.h: Include stdlib.h on all non-Windows.
Fix build on FreeBSD.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89364
Signed-off-by: Vinson Lee <vlee at freedesktop.org>
Tested-by: Brian Paul <brianp at vmware.com>
commit 6f0e9c2e393ba17829e1338dc035c25f22a2718c
Author: Brian Paul <brianp at vmware.com>
Date: Sat Feb 28 13:33:11 2015 -0700
mesa: remove extra definition of ARRAY_SIZE in src/mesa/main/macros.h
Already defined in src/util/macros.h
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit e1437d6c0a88906191b7531f4e941fc6b06e2e4a
Author: Brian Paul <brianp at vmware.com>
Date: Sat Feb 28 09:11:43 2015 -0700
mesa: remove the Elements() macro definition
No longer used.
Acked-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 692bd4a1ab9ae00a4771746626d4f33ceb8bcc9b
Author: Brian Paul <brianp at vmware.com>
Date: Sat Feb 28 13:28:06 2015 -0700
util: replace Elements() with ARRAY_SIZE()
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 6633271159f99bc86d29a86d7e3802f0b60c7a11
Author: Brian Paul <brianp at vmware.com>
Date: Sat Feb 28 09:05:54 2015 -0700
radeon: replace Elements() with ARRAY_SIZE()
Acked-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 9775dbc33505e486f9e6e11587a38bd09285a10c
Author: Brian Paul <brianp at vmware.com>
Date: Sat Feb 28 09:05:48 2015 -0700
r200: replace Elements() with ARRAY_SIZE()
Acked-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit ea760c20902b92f83e324e2dd601d5f8e254ae74
Author: Brian Paul <brianp at vmware.com>
Date: Sat Feb 28 09:05:40 2015 -0700
nouveau: replace Elements() with ARRAY_SIZE()
Acked-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 49a7f8c919d23fec977116f218780a35896cc1dd
Author: Brian Paul <brianp at vmware.com>
Date: Sat Feb 28 09:05:29 2015 -0700
i965: replace Elements() with ARRAY_SIZE()
Acked-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit b565771003fc416e6ccccda8b10efa2423ae7e5a
Author: Brian Paul <brianp at vmware.com>
Date: Sat Feb 28 09:05:24 2015 -0700
i915: replace Elements() with ARRAY_SIZE()
Acked-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 0a77ffcd5a22cffdbf3b70d5aa105b9b1019e704
Author: Brian Paul <brianp at vmware.com>
Date: Sat Feb 28 09:11:29 2015 -0700
mapi: replace Elements() with ARRAY_SIZE()
Acked-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit c16c719647664abf7531896770c31eda1dbe7a58
Author: Brian Paul <brianp at vmware.com>
Date: Sat Feb 28 09:11:23 2015 -0700
glsl: replace Elements() with ARRAY_SIZE()
Acked-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 70b401029cf800f22e6c4318cfd2ab9bf118bb6c
Author: Brian Paul <brianp at vmware.com>
Date: Sat Feb 28 09:11:13 2015 -0700
st/dri: replace Elements() with ARRAY_SIZE()
Acked-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 2f0143ca968d739e8b9cefb213ac61402a7f6587
Author: Brian Paul <brianp at vmware.com>
Date: Sat Feb 28 09:01:33 2015 -0700
st/mesa: replace Elements() with ARRAY_SIZE()
Acked-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit c7136ff64691efec1bf58b34019e5283a751f67b
Author: Brian Paul <brianp at vmware.com>
Date: Sat Feb 28 08:57:27 2015 -0700
mesa/program: replace Elements() with ARRAY_SIZE()
Acked-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 16f7b7727569758a4df9c2bae3ca3a0de683960d
Author: Brian Paul <brianp at vmware.com>
Date: Sat Feb 28 08:57:20 2015 -0700
mesa/swrast: replace Elements() with ARRAY_SIZE()
Acked-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 766f5cf8f88c08a7673beb492095ad8ca878bc22
Author: Brian Paul <brianp at vmware.com>
Date: Sat Feb 28 08:57:15 2015 -0700
mesa/vbo: replace Elements() with ARRAY_SIZE()
Acked-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit c2e130f8201239f836f429cab3beddb4d66a3357
Author: Brian Paul <brianp at vmware.com>
Date: Sat Feb 28 08:57:11 2015 -0700
mesa/main: replace Elements() with ARRAY_SIZE()
We've been using a mix of these two macros for a while now. Let's
just use the later everywhere. It seems to be the convention used
by other open-source projects.
Acked-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit cd6db1989ad98b3e848d3ab132de98dc06274385
Author: Brian Paul <brianp at vmware.com>
Date: Thu Feb 26 13:06:57 2015 -0700
mesa: trim down #includes in api_loopback.h
Acked-by: Matt Turner <mattst88 at gmail.com>
commit 775049b6adb3f83b7c00cfc06088c443aef0b514
Author: Brian Paul <brianp at vmware.com>
Date: Thu Feb 26 13:03:05 2015 -0700
mesa: trim down includes of compiler.h
In some cases, glheader.h is the right #include.
Also remove some instances of struct _glapi_table declarations.
Acked-by: Matt Turner <mattst88 at gmail.com>
commit fa5140bb18422da570958a58a4bd0cec718402e7
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Fri Feb 27 15:42:23 2015 +0000
scons: Fix HAVE___* definition.
These definitions must be moved before `cppdefines` is used to have effect.
Trivial.
commit 9a07435ff885277aba670eb59c039a748175c702
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Fri Feb 27 14:43:51 2015 +0000
identity: Remove.
It's unmaintained, and most likely broken: I use trace driver every now
and then, and everytime I do I need to fix it up.
It's also unused: identity_screen_create is never called.
Above all, it's dead weight: if identity driver had the infrastructure
for other pass-through drivers (like trace and rbug), then it would make
sense on its own right. But as it is implemmented, it's just another
driver to (forget) to update whenever there is a gallium interface
change.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 7bfbaf4a5ab580a8661ea99059cb48c64a016ab6
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue Feb 10 15:54:55 2015 +0200
i965: Remove the create_raw_surface vtbl hook.
It's a wrapper around emit_buffer_surface_state with format=RAW, pitch=1,
rw=true and the remaining arguments ordered differently. There's no point in
having a separate vtbl pointer for that.
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
commit 65f9b83e05d790ddb3846b7a0e2b02241c61ab02
Author: Francisco Jerez <currojerez at riseup.net>
Date: Fri Nov 22 16:18:43 2013 -0800
i965: Add missing defines for render cache messages.
And remove duplicated definition of OWORD_DUAL_BLOCK_WRITE.
Reviewed-by: Paul Berry <stereotype441 at gmail.com>
commit cf67ca9ffa92a6324ed4c3df0bffd18fd967bc8d
Author: Neil Roberts <neil at linux.intel.com>
Date: Thu Feb 12 14:39:07 2015 +0000
i965/skl: Lay out a 1D miptree horizontally
On Gen9+ the 1D miptree is laid out with all of the mipmap levels in a
horizontal line.
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit 0f1e86afd65952df00b82e55c4b7371645cf6fbc
Author: Neil Roberts <neil at linux.intel.com>
Date: Wed Feb 18 18:27:45 2015 +0000
i965/skl: Lay out 3D textures the same as array textures
On Gen9+ the 3D textures use the same mipmap layout as 2D array
textures.
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit aef8a4897937c0c06c7b01e39de23117a6e81d3e
Author: Neil Roberts <neil at linux.intel.com>
Date: Fri Feb 27 16:57:22 2015 +0000
i965/skl: Fix the maximum thread count format for the PS
According to the bspec for some reason the format of the maximum
number of threads field has changed from U8-2 to U8-1 for the PS.
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 27a34f62baa991eadd040302748c48b31ec21a0c
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Mar 1 11:18:42 2015 +0100
draw: fix division-by-zero for empty geometry shaders
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89372
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit b51ff50a767cc78d678ed3d2c25995f5c4194fea
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Sat Feb 28 19:57:20 2015 +1300
i965/gs: Check newly-generated GS-out VUE map against correct stage
Previously, we compared our new GS-out VUE map to the existing *VS*-out
VUE map, which is bogus.
This would mostly manifest as redundant dirty flagging where the GS is
in use but the VS and GS output layouts differ; but there is a scary
case where we would fail to flag a GS-out layout change if it happened
to match the VS-out layout.
Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
Cc: "10.5, 10.4" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88885
commit 213c41bf5d7911a0964c43ccc4192ab3672d0ea5
Author: Brian Paul <brianp at vmware.com>
Date: Sat Feb 28 08:43:16 2015 -0700
i965: add GLSL_TYPE_DOUBLE switch case to silence warning
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 7783131a519324604333f5b410107112436d5a7b
Author: Brian Paul <brianp at vmware.com>
Date: Thu Feb 26 13:06:31 2015 -0700
mesa: include macros.h in stencil.h
Since it uses the CLAMP macro.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 8a25e73df3a38bdbd9e880138edd3000ff54a609
Author: Brian Paul <brianp at vmware.com>
Date: Thu Feb 26 13:22:36 2015 -0700
mesa: move finite macro to imports.h
Move it to the only place it's used.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 977c56df09f8d6753df2618de5a25307b7e6df7d
Author: Brian Paul <brianp at vmware.com>
Date: Thu Feb 26 12:26:09 2015 -0700
mesa: remove _NORMAPI, _NORMAPIP macros
Was only used in one place. Use equivalent _XFORMAPIP there instead.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 61d344ebba65aa35fef9b0bec92be98469b71f71
Author: Brian Paul <brianp at vmware.com>
Date: Thu Feb 26 11:35:10 2015 -0700
mesa: move FLT_MAX_EXP to c99_math.h
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 20dc94ba3c7306f9e89cc8bf02fb2431418d48d4
Author: Brian Paul <brianp at vmware.com>
Date: Thu Feb 26 11:34:23 2015 -0700
mesa: move ONE_DIV_SQRT_LN2 to prog_statevars.c
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit cbf788a34835c9d41f27203d28f407ff469dd7aa
Author: Brian Paul <brianp at vmware.com>
Date: Sat Feb 28 13:38:11 2015 -0700
mesa: remove unused uninitialized_var() macro
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit e71a7f8013e540281d17a0aa1aaa3a3051592ac8
Author: Matt Turner <mattst88 at gmail.com>
Date: Sat Feb 28 10:06:26 2015 -0800
mesa: Check return value of __get_cpuid().
The use of the uninitialized_var() macro was to silence an uninitialized
variable warning that I assumed stemmed from gcc being unable to see
inside __get_cpuid() or understand its inline assembly.
In fact, it was because the __get_cpuid() function can fail, and not
initialize its arguments. Instead, check for failure and return early.
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 5666d9266fd43d552c76ce7b472abc0afde6c32b
Author: Matt Turner <mattst88 at gmail.com>
Date: Sat Feb 28 10:46:33 2015 -0800
i965/fs/nir: Mark fallthrough.
commit 54cd2f7c9655ccbb00209b1f49692196df2a33a1
Author: Matt Turner <mattst88 at gmail.com>
Date: Sat Feb 28 10:37:50 2015 -0800
i965/fs/nir: Mark fallthrough.
commit d528907fd2950c7bb968fff66dd79863cd128890
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Feb 27 10:59:17 2015 -0800
i965: Avoid applying negate to wrong MAD source.
For some given GLSL IR like (+ (neg x) (* 1.2 x)), the try_emit_mad
function would see that one of the +'s sources was a negate expression
and set mul_negate = true without confirming that it was actually a
multiply.
Cc: 10.5 <mesa-stable at lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89315
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89095
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 43ef2657a08f850c5756f28520f2cbe506807f24
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu Feb 26 22:49:47 2015 -0800
i965/vec4: Fix implementation of i2b.
I broke this in commit 2881b123d. I must have misread i2b as b2i.
Cc: 10.5 <mesa-stable at lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88246
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit b8a1637119249c1d5e76c27d0053360bbb7f4e77
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Fri Feb 27 14:17:50 2015 -0800
i965/fs/nir: Use emit_math for nir_op_fpow
It appears that all the other instructions that need it already use it.
This one just got missed.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Cc: "10.5" <mesa-stable at lists.freedesktop.org>
commit 76cd0f00f44c0935dc7d6a0e14e0515f08a8e1dc
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Feb 27 11:42:43 2015 -0800
mapi: Don't rely on GNU void pointer arithmetic.
Commit 79daa510c added -Werror=pointer-arith to CFLAGS, which makes
arithmetic on void pointers an error.
See https://gcc.gnu.org/onlinedocs/gcc/Pointer-Arith.html
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 982723dfa20386b40ab2876fb134217cba42a934
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Feb 27 15:48:06 2015 -0800
Revert "configure: Leverage gcc warn options to enable safe use of C99 features where possible."
This reverts commit 79daa510c7a871a33797308a2ccb4b83a067ffbe.
I apparently hadn't done a clean build when testing this; it broke the
build for Tom, Ben, and myself. We like the idea; let's try a v2.
commit 7983a3d2e06b0bc16c1a16bddccc7f14fe1f132c
Author: Jonathan Gray <jsg at jsg.id.au>
Date: Sun Feb 22 19:19:25 2015 +1100
auxilary/os: correct sysctl use in os_get_total_physical_memory()
The length argument passed to sysctl was the size of the pointer
not the type. The result of this is sysctl calls would fail on
32 bit BSD/Mac OS X.
Additionally the wrong pointer was passed as an argument to store
the result of the sysctl call.
Cc: "10.4, 10.5" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Jonathan Gray <jsg at jsg.id.au>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 667dac9d40760822e0e4be750c3a18fe56ec4b40
Author: Brian Paul <brianp at vmware.com>
Date: Fri Feb 27 13:06:06 2015 -0700
glsl: silence uninitialized var warning on MinGW
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit bf8d049488eb0a693712281f0ff5adb3d56d2340
Author: Brian Paul <brianp at vmware.com>
Date: Fri Feb 27 13:05:42 2015 -0700
mesa: silence unused var warning in get_tex_rgba_uncompressed()
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 48f229d759480cf6e42af1236b5889fe389e4dd8
Author: Brian Paul <brianp at vmware.com>
Date: Fri Feb 27 13:05:16 2015 -0700
mesa: move declaration before code
To fix MinGW warning.
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 5b089e5f15ca06be82ca36e21d678db17493b6b6
Author: Brian Paul <brianp at vmware.com>
Date: Fri Feb 27 13:04:38 2015 -0700
meta: silence declaration after code warning on MinGW
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 544f56b75a58baf4cfadb646b0a21939a67c0113
Author: Brian Paul <brianp at vmware.com>
Date: Fri Feb 27 13:04:18 2015 -0700
meta: silence uninitialized variable warnings for MinGW
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 098e5bf3b37431af2a9156789cbc9534f0b70235
Author: Brian Paul <brianp at vmware.com>
Date: Fri Feb 27 13:03:03 2015 -0700
c99_alloca.h: fix #include for MinGW
As with MSVC, include malloc.h but don't redefine alloca.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89364
Reviewed-by: José Fonseca <jfonseca at vmware.com>
commit 943784bbcd3e44254fd5e9b27b917b49c37206fb
Author: Brian Paul <brianp at vmware.com>
Date: Fri Feb 27 13:00:50 2015 -0700
gallium/util: add debug_print_usage_enum() debug helper
Signed-off-by: Brian Paul <brianp at vmware.com>
commit b14cec0b8e98195679eab5afbdba3bb47badccf2
Author: Brian Paul <brianp at vmware.com>
Date: Fri Feb 27 12:49:29 2015 -0700
gallium/util: fix 'statement with no effect' warning
Reviewed-by: José Fonseca <jfonseca at vmware.com>
commit 53295bebc883c5b90b4b3a2612d7cacabc94fd1b
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Feb 26 14:29:25 2015 -0800
i965: Fix I/L/LA SNORM formats.
_mesa_choose_tex_format (texformat.c) tries I8_SNORM, L8_SNORM, and
either L8A8_SNORM or A8L8_SNORM, none of which are supported by our
driver. Failing that, it falls back to RGBX for luminance, and RGBA
intensity and luminance alpha. So, we need to use swizzle overrrides
to obtain the correct values.
Fixes Piglit's EXT_texture_snorm/fbo-blending-formats and
fbo-clear-formats.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
commit ea696be5ac097af621f10858d925a343a838be7a
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Feb 25 16:08:14 2015 -0800
i965/fs: Patch the instruction generating discards; don't use CMP.Z.
CMP.Z doesn't work on Gen4-5 because the boolean isn't guaranteed to be
0 or 0xFFFFFFFF - only the low bit is defined.
We can call emit_bool_to_cond_code to generate the condition in f0.0;
the last instruction will generate the flag value. We can patch it to
use f0.1, and negate the condition.
Fixes discard tests on Gen4-5.
Haswell shader-db stats:
total instructions in shared programs: 5770279 -> 5769112 (-0.02%)
instructions in affected programs: 64342 -> 63175 (-1.81%)
helped: 1069
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 4ebacf8aa67b1bfba7820f25536be98c7452dcb1
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Feb 25 16:07:03 2015 -0800
i965/fs: Introduce brw_negate_cmod().
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 0fad07af9aa9855ebdff5eabeef6419449e2996c
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Mon Feb 9 15:39:53 2015 -0800
main: Fix whitespace in teximage.c.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit da85ab4b655a28cec33a81dae78ebe375fef9aa1
Author: Tom Stellard <thomas.stellard at amd.com>
Date: Thu Feb 26 23:25:14 2015 +0000
radeonsi/compute: Enable PIPE_SHADER_CAP_DOUBLES v2
v2:
- Simplify ifdef
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 75514555aa0061299034bf15b5df31ab6746c0e5
Author: Tom Stellard <thomas.stellard at amd.com>
Date: Thu Feb 26 18:20:06 2015 -0500
clover: Don't unconditionally define cl_khr_fp64
This should be done by the frontend for devices that support this
extension.
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit ed07255149d7cffac07615e946289b3d683faa4b
Author: Tom Stellard <thomas.stellard at amd.com>
Date: Tue Feb 24 19:43:43 2015 -0500
pipe-loader: Fix build with dri drivers enabled, and vl state trackers disabled
Configure arguments:
./configure --disable-dri3 --disable-xvmc --enable-opencl
--with-gallium-drivers=r300,r600,radeonsi
--with-egl-platforms=drm
Build error:
make[3]: *** No rule to make target
`../../../../src/gallium/auxiliary/libgalliumvlwinsys.la', needed by
`pipe_r300.la'. Stop.
Cc: "10.5" <mesa-stable at lists.freedestkop.org>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 79daa510c7a871a33797308a2ccb4b83a067ffbe
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Thu Feb 26 16:46:48 2015 +0000
configure: Leverage gcc warn options to enable safe use of C99 features where possible.
The main objective of this change is to enable Linux developers to use
more of C99 throughout Mesa, with confidence that the portions that need
to be built with MSVC -- and only those portions --, stay portable.
This is achieved by using the appropriate -Werror= options only on the
places they need to be used.
Unfortunately we still need MSVC 2008 on a few portions of the code
(namely llvmpipe and its dependencies). I hope to eventually eliminate
this so that we can use C99 everywhere, but there are technical/logistic
challenges (specifically, newer Windows SDKs no longer bundle MSVC,
instead require a full installation of Visual Studio, and that has
hindered adoption of newer MSVC versions on our build processes.)
Thankfully we have more directy control over our OpenGL driver, which is
why we're now able to migrate to MSVC 2013 for most of the tree.
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit f320ecf218ab24ef4883f918a9007b2a6cfdac5e
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Thu Feb 26 16:37:48 2015 +0000
nir: Use alloca instead of variable length arrays.
This is to enable the code to build with -Werror=vla in the short term,
and enable the code to build with MSVC2013 soon after.
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 84a1e3d61e6df449571e41426ec64b115fedc7c3
Author: Brian Paul <brianp at vmware.com>
Date: Thu Feb 26 13:33:54 2015 -0700
mesa: restore #include stdarg.h in imports.h
https://bugs.freedesktop.org/show_bug.cgi?id=89345
Signed-off-by: Brian Paul <brianp at vmware.com>
commit 06ed81044fc6b1dee90e67de314f81150746e104
Author: Brian Paul <brianp at vmware.com>
Date: Thu Feb 26 12:31:45 2015 -0700
c99_math.h: add defines for M_PI, M_E, M_LOG2E
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89342
Signed-off-by: Brian Paul <brianp at vmware.com>
commit 8170eba7e7c37235bd5fad2f9adfdd0eda8e3246
Author: Vinson Lee <vlee at freedesktop.org>
Date: Thu Feb 26 21:00:15 2015 -0800
r300g/tests: Include stdio.h.
Fix build error.
CC compiler/tests/r300_compiler_tests-radeon_compiler_regalloc_tests.o
compiler/tests/radeon_compiler_regalloc_tests.c: In function ‘test_runner_rc_regalloc’:
compiler/tests/radeon_compiler_regalloc_tests.c:57:3: error: implicit declaration of function ‘fprintf’ [-Werror=implicit-function-declaration]
fprintf(stderr, "Failed to load program\n");
^
Signed-off-by: Vinson Lee <vlee at freedesktop.org>
commit 40cfa0c347d60d4542128abecc5bd21c675f1131
Author: Brian Paul <brianp at vmware.com>
Date: Thu Feb 26 12:33:16 2015 -0700
radeon/compiler: include stdio.h
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89343
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
commit 549078cb5a95e0ee381d036b8c36bc41506f21bc
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Wed Feb 25 10:34:03 2015 -0800
main: Fix target checking for CompressedTexSubImage*D.
This fixes a dEQP test failure. In the test,
glCompressedTexSubImage2D was called with target = 0 and failed to throw
INVALID ENUM. This failure was caused by _mesa_get_current_tex_object(ctx,
target) being called before the target checking. To remedy this, target
checking was made into its own function and called prior to
_mesa_get_current_tex_object.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89311
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit ca65764d6042d2ea220a1e3952490f79c226f3e0
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Wed Feb 25 15:45:47 2015 -0800
main: Fix target checking for CopyTexSubImage*D.
This fixes a dEQP test failure. In the test,
glCopyTexSubImage2D was called with target = 0 and failed to throw
INVALID ENUM. This failure was caused by _mesa_get_current_tex_object(ctx,
target) being called before the target checking. To remedy this, target
checking was separated from the main error-checking function and
called prior to _mesa_get_current_tex_object.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89312
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 688d7656c58ea4775dbd55fe56193a27f4799c00
Author: Brian Paul <brianp at vmware.com>
Date: Thu Feb 26 10:19:37 2015 -0700
c99: in c99_math.h check that _USE_MATH_DEFINES is defined with MSVC
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit fb2ddef15793bf75bdc13c9de997100b4f1d7927
Author: Brian Paul <brianp at vmware.com>
Date: Thu Feb 26 09:52:20 2015 -0700
mesa: remove unused INLINE macro from compiler.h
We now use 'inline' everywhere in Mesa.
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
commit 164b3cd7577dc6c168eb59003306f241e501da7f
Author: Brian Paul <brianp at vmware.com>
Date: Thu Feb 26 10:03:22 2015 -0700
st/mesa: replace INLINE with inline
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
commit 0dc6b7245534ebe44470133945cbb747b92cf073
Author: Brian Paul <brianp at vmware.com>
Date: Thu Feb 26 09:48:50 2015 -0700
swrast: replace INLINE with inline
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
commit f51f2af76d5532a4f272f15ac28e1a23a4967fd0
Author: Brian Paul <brianp at vmware.com>
Date: Thu Feb 26 09:48:44 2015 -0700
radeon: replace INLINE with inline
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
commit bbedb85898fb53bee613510e1fe8d890aab4cfda
Author: Brian Paul <brianp at vmware.com>
Date: Thu Feb 26 09:48:34 2015 -0700
r200: replace INLINE with inline
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
commit 8e9fe53ce9f8b01ae66b19dc273594fa413e9ad5
Author: Brian Paul <brianp at vmware.com>
Date: Thu Feb 26 09:48:24 2015 -0700
i915: replace INLINE with inline
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
commit 46110c5d56eb7a2d3c69b2d8565c7631541511b1
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Thu Feb 26 11:47:46 2015 +0000
include,auxiliary: Remove support for MSVC older then 2008.
MSVC 2008 (shipped with Windows SDK 7.0.7600) is the oldest we
need to support. At least on llvmpipe, gallium/auxiliary, and util
modules. For the remaining modules (particular all OpenGL specific
code) can be built with MSVC 2013.
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit fd090fdadd6dd955e7663d83885d00678f60e133
Author: Brian Paul <brianp at vmware.com>
Date: Tue Feb 24 18:00:37 2015 -0700
mesa: don't include stdint.h in compiler.h
Not needed.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 95855dd32f4228d3c99e040b76f4357593b4b5a4
Author: Brian Paul <brianp at vmware.com>
Date: Tue Feb 24 17:56:45 2015 -0700
mesa: don't include math.h in compiler.h
Not needed by anything in that header. Include math.h or c99_math.h
where needed instead.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 4f25a180115d6f7a6149ba8285a394e10aa04ef2
Author: Brian Paul <brianp at vmware.com>
Date: Tue Feb 24 17:48:31 2015 -0700
mesa: trim down #includes in compiler.h
Don't include stuff we don't need. Fix a few #includes elsewhere to
keep thing building.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 538e13d4a13419add6bbcb5b14a69762ffad0818
Author: Brian Paul <brianp at vmware.com>
Date: Tue Feb 24 17:47:00 2015 -0700
r300g: remove dependency on compiler.h
It only needs typical stdio.h and stdlib.h functions.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 609cb60d4beb48db4f5641253d331947f7eae2da
Author: Brian Paul <brianp at vmware.com>
Date: Tue Feb 24 17:05:48 2015 -0700
mesa: don't include limits.h in compiler.h
Not needed.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 13730bcaf360e4b6b5bbc80eb5d0015baea2c194
Author: Brian Paul <brianp at vmware.com>
Date: Tue Feb 24 17:03:47 2015 -0700
mesa: don't include float.h in compiler.h
Not needed.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit ddf4b2e363653daf9342925e71122ba6670816a8
Author: Brian Paul <brianp at vmware.com>
Date: Tue Feb 24 16:56:54 2015 -0700
mesa: only include ctype.h where it's used
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 135b8c65305c05c1ea9145141bad670003270c41
Author: Brian Paul <brianp at vmware.com>
Date: Tue Feb 24 16:55:53 2015 -0700
mesa: include stdarg.h only where it's used
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 6b06697b0da6940b6c709f9e66b1739e076f09d0
Author: Brian Paul <brianp at vmware.com>
Date: Tue Feb 24 16:44:53 2015 -0700
mesa: remove M_PI, M_E, M_LOG2E macro definitions
Should be defined in math.h. If not, we can add them to c99_math.h
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 6cb431c19c03e0582dc9552159b308ff9a5d2294
Author: Brian Paul <brianp at vmware.com>
Date: Tue Feb 24 16:42:43 2015 -0700
glsl: #include c99_math.h instead of core.h
We only need the M_LOG2E definition.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 36ea81d0675b11c08c61fc3cd508dc273c9de542
Author: Brian Paul <brianp at vmware.com>
Date: Wed Feb 25 17:04:05 2015 -0700
gallium: whitespace, comment formatting fixes in p_defines.h
Just to keep things consistent.
Reviewed-by: José Fonseca <jfonseca at vmware.com>
commit e09fe389359285dc13abec51f1c61e67972f0235
Author: Brian Paul <brianp at vmware.com>
Date: Wed Feb 25 16:59:54 2015 -0700
util: add debug_print_bind_flags() debug helper
Reviewed-by: José Fonseca <jfonseca at vmware.com>
commit 2069f2c7fa9d3178d59da4f7e407a598f388477b
Author: Brian Paul <brianp at vmware.com>
Date: Wed Feb 25 16:58:43 2015 -0700
gallium: renumber PIPE_BIND_ flags
Note that PIPE_BIND_COMMAND_ARGS_BUFFER and PIPE_BIND_LINEAR were both
bit 21 before.
Reviewed-by: José Fonseca <jfonseca at vmware.com>
commit a44606eb8164be2aa37eb288fd90894d74bd0935
Author: Neil Roberts <neil at linux.intel.com>
Date: Wed Feb 25 15:10:01 2015 +0000
meta: In pbo_{Get,}TexSubImage don't repeatedly rebind the source tex
A layered PBO image is now interpreted as a single tall 2D image so
the z argument in _mesa_meta_bind_fbo_image is ignored. Therefore this
was just redundantly rebinding the same image repeatedly.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 1a93e7690dc90211164082d6a2d26d93da8127ef
Author: Marius Predut <marius.predut at intel.com>
Date: Wed Feb 25 09:49:45 2015 -0700
mesa: use fi_type in vertex attribute code
For 32-bit builds, floating point operations use x86 FPU registers,
not SSE registers. If we're actually storing an integer in a float
variable, the value might get modified when written to memory. This
patch changes the VBO code to use the fi_type (float/int union) to
store/copy vertex attributes.
Also, this can improve performance on x86 because moving floats with
integer registers instead of FP registers is faster.
Neil Roberts review:
- include changes on all places that are storing attribute values.
- check with and without -O3 compiler flag.
Brian Paul review:
- use fi_type type instead gl_constant_value type
- fix a bunch of nit-picks.
- fix compiler warnings
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82668
Signed-off-by: Marius Predut <marius.predut at intel.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 47053464630888f819ef8cc44278f1a1220159b9
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Fri Feb 13 11:21:21 2015 -0800
i965/gen8: Use HALIGN_16 if MCS is enabled for non-MSRT
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Neil Roberts <neil at linux.intel.com>
commit 84199fa64731c19a1527e68bd9d15e81ab05df3f
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Fri Feb 20 12:26:36 2015 -0800
i965: Pass pointer to miptree as function parameter in intel_horizontal_texture_alignment_unit
This will be used by next patch in the series.
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Neil Roberts <neil at linux.intel.com>
commit 94d88cb46870ad7da8ae9e98ace524319c45bb8b
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Thu Feb 5 12:24:57 2015 -0800
i965: Allocate texture buffer in intelTexImage
before calling _mesa_meta_pbo_TexSubImage(). This will be used in
later patches and will be required in Skylake to get the tile
resource mode of miptree before calling _mesa_meta_pbo_TexSubImage().
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Neil Roberts <neil at linux.intel.com>
commit 82f6d17300bcdf407bffddba03533c702fe262f3
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Thu Feb 12 18:49:13 2015 -0800
i965: Make a function to check the conditions to use the blitter
No functional changes in the patch. Just makes the code look cleaner.
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Neil Roberts <neil at linux.intel.com>
commit 6960a3962c3cbc2d6e0f19a0b630e1a21509b856
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Thu Feb 12 16:59:12 2015 -0800
i965: Move the comment to the right place
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Neil Roberts <neil at linux.intel.com>
commit 524a729f68c15da3fc6c42b3158a13e0b84c2728
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Tue Feb 17 10:40:58 2015 -0800
i965: Fix condition to use Y tiling in blitter in intel_miptree_create()
Y tiling is supported in blitter on SNB+.
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Neil Roberts <neil at linux.intel.com>
commit 688309374d6e2ec8af10907e36f30f0028f16d55
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Mon Feb 23 10:56:14 2015 -0800
meta: Pass null pointer for the pixel data to avoid unnecessary data upload
to a temporary pbo created in _mesa_meta_pbo_GetTexSubImage().
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Neil Roberts <neil at linux.intel.com>
commit 068ba4ac78a62d2d07300a54e6585e16a2c747d5
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Tue Feb 3 16:56:04 2015 -0800
meta: Fix buffer object assignment to account for both pack and unpack bo's
create_texture_for_pbo() is shared by _mesa_meta_pbo_GetTexSubImage()
and _mesa_meta_pbo_TexSubImage() functions. So, we need to account
for both pack and unpack buffer objects.
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Neil Roberts <neil at linux.intel.com>
commit 618c4c4b6ab82c606cd2c8f139372502baa06c5f
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Tue Feb 3 16:50:57 2015 -0800
meta: Use GL_STREAM_READ for pbo created with GL_PIXEL_PACK_BUFFER
create_texture_for_pbo() is used by both _mesa_meta_pbo_GetTexSubImage()
and _mesa_meta_pbo_TexSubImage() functions with different PBO targets.
Use GL_STREAM_READ with GL_PIXEL_PACK_BUFFER and GL_STREAM_DRAW with
GL_PIXEL_UNPACK_BUFFER.
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Neil Roberts <neil at linux.intel.com>
commit 8d6ae49a8b18ad8006ff8f22caf06bad83b96e6b
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Tue Feb 3 17:04:45 2015 -0800
meta: Add assertion check for ctx->Meta->SaveStackDepth
before using it for derefrencing.
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Neil Roberts <neil at linux.intel.com>
commit 0a4ea87344a1cbca4c50cfca1efe97202aa18be8
Author: Anuj Phogat <anuj.phogat at gmail.com>
Date: Sun Dec 31 16:05:42 2000 -0800
meta: Do power of two samples check only for samples > 0
otherwise samples=0 passes the check, which is invalid.
Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Neil Roberts <neil at linux.intel.com>
commit cb25087c7bd5f1ad2515647278b32d3f07803f77
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Feb 24 10:41:52 2015 -0800
glsl: Rewrite and fix min/max to saturate optimization.
There were some bugs, and the code was really difficult to follow. We
would optimize
min(max(x, b), 1.0) into max(sat(x), b)
but not pay attention to the order of min/max and also do
max(min(x, b), 1.0) into max(sat(x), b)
Corrects four shaders from Champions of Regnum that do
min(max(x, 1), 10)
and corrects rendering of Mass Effect under VMware Workstation.
Cc: "10.4 10.5" <mesa-stable at lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89180
Reviewed-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 864340219ba5aa90a19eb1336459d78a9b02cd16
Author: Rob Clark <robclark at freedesktop.org>
Date: Wed Feb 25 08:35:32 2015 -0500
freedreno: drop ARRAY_SIZE macro
Since now ARRAY_SIZE has been added to util/macros.h. Fixes a bunch of:
freedreno_util.h:79:0: warning: "ARRAY_SIZE" redefined
#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
^
In file included from ../../../../src/gallium/include/pipe/p_compiler.h:36:0,
from ../../../../src/gallium/include/pipe/p_context.h:31,
from freedreno_context.h:32,
from freedreno_context.c:29:
../../../../src/util/macros.h:29:0: note: this is the location of the previous definition
# define ARRAY_SIZE(x) (sizeof(x) / sizeof(*(x)))
^
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 67e3302497e90a4602921b4ac4621e97df60f850
Author: Neil Roberts <neil at linux.intel.com>
Date: Thu Feb 19 16:09:41 2015 +0000
i965: Don't force x-tiling for 16-bpp formats on Gen>7
Sandybridge doesn't support y-tiling for surface formats with 16 or
more bpp. There was previously an override to explicitly allow this
for Gen7. However, this restriction is also removed in Gen8+ so we
should use y-tiling there too.
This is important to do for Skylake which doesn't support x-tiling for
3D surfaces.
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit 6d164f65c5a794164d07bc66c1f8f87280514e8c
Author: Andreas Boll <andreas.boll.dev at gmail.com>
Date: Tue Feb 24 20:01:30 2015 +0100
glx: Fix returned values of GLX_RENDERER_PREFERRED_PROFILE_MESA
If the renderer supports the core profile the query returned incorrectly
0x8 as value, because it was using (1U << __DRI_API_OPENGL_CORE) for the
returned value.
The same happened with the compatibility profile. It returned 0x1
(1U << __DRI_API_OPENGL) instead of 0x2.
Internal DRI defines:
dri_interface.h: #define __DRI_API_OPENGL 0
dri_interface.h: #define __DRI_API_OPENGL_CORE 3
Those two bits are supposed for internal usage only and should be
translated to GLX_CONTEXT_CORE_PROFILE_BIT_ARB (0x1) for a preferred
core context profile and GLX_CONTEXT_COMPATIBILITY_PROFILE_BIT_ARB (0x2)
for a preferred compatibility context profile.
This patch implements the above translation in the glx module.
v2: Fix the incorrect behavior in the glx module
Cc: "10.3 10.4 10.5" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Andreas Boll <andreas.boll.dev at gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 06924972d5982f00e66335a66df0172a9d90cc29
Author: Andreas Boll <andreas.boll.dev at gmail.com>
Date: Mon Feb 9 11:18:04 2015 +0100
dri/common: Update comment about driQueryRendererIntegerCommon
Since 87d3ae0b45b6b6bb50b583dafa55eb109449a005
driQueryRendererIntegerCommon handles __DRI2_RENDERER_PREFFERED_PROFILE
too.
Signed-off-by: Andreas Boll <andreas.boll.dev at gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 720ba6ca9745f7b7dc0b5120f3a57d66e2bbe18b
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Feb 20 04:08:38 2015 -0500
glsl: add double support for packing varyings
Doubles are always packed, but a single double will never cross a slot
boundary -- single slots can still be wasted in some situations.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 546aba143d13ba3f993ead4cc30b2404abfc0202
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Wed Feb 18 17:17:38 2015 -0800
common: Fix PBOs for 1D_ARRAY.
Corrects the way that _mesa_meta_pbo_TexSubImage and
_mesa_meta_pbo_GetTexSubImage handle 1D_ARRAY textures. Fixes a failure in
the Piglit arb_direct_state_access/gettextureimage-targets test.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Tested-by: Laura Ekstrand <laura at jlekstrand.net>
Cc: "10.4, 10.5" <mesa-stable at lists.freedesktop.org>
commit ccc5ce6f72c1ec86be4dfcef96c0b51fba0faa6d
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Tue Feb 24 14:51:29 2015 -0800
common: Correct PBO 2D_ARRAY handling.
Changes PBO uploads and downloads to use a tall (height * depth) 2D texture
for blitting. This fixes the bug where 2D_ARRAY, 3D, and CUBE_MAP_ARRAY
textures are not properly uploaded and downloaded.
Removes the option to use a 2D ARRAY texture for the PBO during upload and
download. This option didn't work because the miptree couldn't be set up
reliably.
v2: Review from Jason Ekstrand and Neil Roberts:
-Delete the depth parameter from create_texture_for_pbo
-Abandon the option to create a 2D ARRAY texture in create_texture_for_pbo
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Cc: "10.4, 10.5" <mesa-stable at lists.freedesktop.org>
commit 06084652fefe49c3d6bf1b476ff74ff602fdc22a
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Tue Feb 24 13:29:11 2015 -0800
common: Correct texture init for meta pbo uploads and downloads.
This moves the line setting immutability for the texture to after
_mesa_initialize_texture_object so that the initializer function will not
cancel it out. Moreover, because of the ARB_texture_view extension, immutable
textures must have NumLayers > 0, or depth will equal (0-1)=0xFFFFFFFF during
SURFACE_STATE setup, which triggers assertions.
v2: Review from Kenneth Graunke:
- Include more explanation in the commit message.
- Make texture setup bug fixes into a separate patch.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Cc: "10.4, 10.5" <mesa-stable at lists.freedesktop.org>
commit 88ff8dee02d43a55d72a22a0172b92e7cd988bbf
Author: Brian Paul <brianp at vmware.com>
Date: Tue Feb 24 15:26:34 2015 -0700
mesa: remove DEG2RAD macro
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit ab68219a59c128e018ba68a287228c24890b8f4f
Author: Brian Paul <brianp at vmware.com>
Date: Tue Feb 24 15:23:22 2015 -0700
mesa: remove MAX_GLUSHORT, move MAX_GLUINT
The later is only used in one place in swrast.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit f847ddb64dfe7d0e84354b30b7551d83fe3463c9
Author: Brian Paul <brianp at vmware.com>
Date: Tue Feb 24 15:11:45 2015 -0700
mesa: move signbit() macro to c99_math.h
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 612143b2d0b7ec84d43049908f454d79bebeeb5f
Author: Brian Paul <brianp at vmware.com>
Date: Tue Feb 24 15:05:47 2015 -0700
mesa: remove unused isblank() function
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit e033d2c6422066a69a98f0a073e87a78587a292a
Author: Brian Paul <brianp at vmware.com>
Date: Tue Feb 24 15:05:05 2015 -0700
glcpp: remove unneeded #include of core.h
isblank() is not used in the code.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 9fd7e9d83197f90d008043446317ebe01432144b
Author: Brian Paul <brianp at vmware.com>
Date: Tue Feb 24 15:03:44 2015 -0700
mesa: remove sqrtf macro
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit ee3f6745723856419d7f5ecb17652e19855c4caa
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Jul 5 22:10:41 2014 -0700
i965: Remove redundant discard jumps.
With the previous optimization in place, some shaders wind up with
multiple discard jumps in a row, or jumps directly to the next
instruction. We can remove those.
Without NIR on Haswell:
total instructions in shared programs: 5777258 -> 5775872 (-0.02%)
instructions in affected programs: 20312 -> 18926 (-6.82%)
helped: 716
With NIR on Haswell:
total instructions in shared programs: 5773163 -> 5771785 (-0.02%)
instructions in affected programs: 21040 -> 19662 (-6.55%)
helped: 717
v2: Use the CFG rather than the old instructions list. Presumably
the placeholder halt will be in the last basic block.
v3: Make sure placeholder_halt->prev isn't the head sentinel (caught
twice by Eric Anholt).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 30f51f1a1a70bc838d5bed449daff0dd9f2e8ef2
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Oct 22 20:48:21 2014 -0700
glsl: Optimize "if (cond) discard;" to a conditional discard.
st_glsl_to_tgsi and ir_to_mesa have handled conditional discards for a
long time; the previous patch added that capability to i965.
i965 (Haswell) shader-db stats:
Without NIR:
total instructions in shared programs: 5792133 -> 5776360 (-0.27%)
instructions in affected programs: 737585 -> 721812 (-2.14%)
helped: 6300
HURT: 68
GAINED: 2
With NIR:
total instructions in shared programs: 5787538 -> 5769569 (-0.31%)
instructions in affected programs: 767843 -> 749874 (-2.34%)
helped: 6522
HURT: 35
GAINED: 6
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 8eb6c109994de2827b0a1340a2dc8d933edaf5e0
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Aug 19 15:22:43 2014 -0700
i965/fs: Handle conditional discards.
The discard condition tells us which channels we want killed. We want
to invert that condition to get the channels that should survive (remain
live) in f0.1. Emit a CMP to negate it.
Nothing generates these today, but that will change shortly.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 8e62bd52f8296a220bd4542abd6fdcdfc41a388c
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Feb 23 23:47:00 2015 -0800
nir: Introduce nir_intrinsic_discard_if.
This is a conditional discard, which takes a boolean source.
Note that we don't generate ir_discard::condition today, so this
shouldn't break drivers (since none implement this intrinsic yet).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 23d42b46e306d4104e534842f6dec3500d331cae
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Feb 24 01:00:22 2015 -0800
glsl: Delete dead discard conditions in constant folding.
opt_constant_folding() already detects conditional assignments where the
condition is constant, and either deletes the assignment or the
condition.
Make it handle discards in the same fashion.
Spotted happening in the wild in Tropico 5 shaders.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit d77b186871389be10a68546da0e3ada8134ae539
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Feb 23 23:12:39 2015 -0800
glsl: Handle conditional discards in lower_discard_flow().
This pass wasn't prepared to handle conditional discards.
Instead of initializing the "discarded" temporary to "true", set it to
the condition. Then, refer to the variable for the condition, to avoid
duplicating the expression tree.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 44b45da994c5d827eb123fb18b501d712822baae
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Feb 23 22:00:34 2015 -0800
glsl: Make ir_rvalue_visitor visit ir_discard::condition.
This was forgotten.
I omitted the NULL check since we don't check ir_assignment::condition
either.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 926d8b05107f4f5fecad41ad30833a306a566303
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Feb 23 22:56:47 2015 -0800
glsl: Make ir_validate check the type of ir_discard::condition.
Copy and pasted from the ir_if::condition handling, plus a NULL check.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 6f5604601cefb3c656e16a7b65102740861bee90
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Feb 24 12:11:21 2015 -0800
Revert "i965/fs: Remove force_writemask_all assertion for execsize < 8."
This reverts commit 0d8f27eab7b7e8b7a16e76aabd3f6a0ab4880497.
"This doesn't seem to be necessary." <- I was wrong!
Tested-by: Markus Wick <markus at selfnet.de>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 2c7a703b05a84aff89cd908b2a84e04d1ce8aed8
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Feb 24 12:03:37 2015 -0800
i965/fs: Emit MOV(1) instructions with force_writemask_all.
Fixes rendering with Dolphin.
Tested-by: Markus Wick <markus at selfnet.de>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 467077b834eff4a38eb7a298826baddc44a298b8
Author: Matt Turner <mattst88 at gmail.com>
Date: Sun Dec 21 19:50:03 2014 -0800
i965/fs: Optimize (gl_FrontFacing ? x : y) where x and y are ±1.0.
total instructions in shared programs: 5695356 -> 5689775 (-0.10%)
instructions in affected programs: 486231 -> 480650 (-1.15%)
helped: 2604
LOST: 1
commit b8582d18e6b0737c4a34777837c10898ed177e30
Author: Matt Turner <mattst88 at gmail.com>
Date: Sun Feb 15 14:03:09 2015 -0800
i965/fs/nir: Optimize integer multiply by a 16-bit constant.
Gen8+ support was just broken, since MUL now consumes 32-bits from both
sources. Fixes 986 piglit tests on my BDW.
total instructions in shared programs: 7753873 -> 7753522 (-0.00%)
instructions in affected programs: 28164 -> 27813 (-1.25%)
helped: 77
GAINED: 47
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 7a997a386375a98b70ae5e1d880c8d47f236de8d
Author: Matt Turner <mattst88 at gmail.com>
Date: Sun Feb 15 13:45:04 2015 -0800
i965/fs/nir: Optimize (gl_FrontFacing ? x : y) where x and y are ±1.0.
total instructions in shared programs: 7756214 -> 7753873 (-0.03%)
instructions in affected programs: 455452 -> 453111 (-0.51%)
helped: 2333
Reviewed-by: Eric Anholt <eric at anholt.net>
commit c750ecaa1265c3f77d52e69697006cc5ecc3d6dd
Author: Jason Ekstrand <jason at jlekstrand.net>
Date: Thu Jan 29 21:45:53 2015 -0800
nir/register: Add a parent_instr field
This adds a parent_instr field similar to the one for ssa_def. The
difference here is that the parent_instr field on a nir_register can be
NULL if the register does not have a unique definition or if that
definition does not dominate all its uses. We set this field in the
out-of-SSA pass so that backends can get SSA-like information even after
they have gone out of SSA.
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit fc59695b9272335651346bedd7dc8b902a9ccf54
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Feb 21 23:20:05 2015 +0100
st/mesa: remove unused/broken function st_print_shaders
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit a86054bac70f913880bd838d4565c1270b0c00aa
Author: Brian Paul <brianp at vmware.com>
Date: Tue Feb 24 09:59:30 2015 -0700
st/mesa: remove struct qualifier from st_src_reg parameter
It's a class. Silences MSVC warning.
commit a2b366b92cecc5045293528aa0bb8b1f0678bbcc
Author: Brian Paul <brianp at vmware.com>
Date: Tue Feb 24 09:39:51 2015 -0700
mesa: remove INV_SQRTF() macro
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit bbb2d8403256dd16fb55b4059f396c42cdc5008c
Author: Brian Paul <brianp at vmware.com>
Date: Tue Feb 24 09:33:41 2015 -0700
mesa: remove ceilf, floorf macros
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit bdd0402ca3400328b38a8cf02b501852a037b957
Author: Brian Paul <brianp at vmware.com>
Date: Tue Feb 24 09:32:27 2015 -0700
mesa: remove expf macro
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit cffedcf163f54ec4e2625bba07a63add722c7d55
Author: Brian Paul <brianp at vmware.com>
Date: Tue Feb 24 09:31:34 2015 -0700
mesa: remove logf macro
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit f5816d77e24850c53a9dbc4add0e87bf3031e00a
Author: Brian Paul <brianp at vmware.com>
Date: Tue Feb 24 09:26:41 2015 -0700
mesa: remove powf macro
Use the wrapper in c99_math.h if needed.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit bad154e677fb2ee3b2fb976ac3843dad08c87ea2
Author: Brian Paul <brianp at vmware.com>
Date: Tue Feb 24 09:24:27 2015 -0700
mesa: remove unused exp2f, log2f, truncf wrappers
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit aeabf4ede52f8952d62387e3062e2fc09db1c755
Author: Brian Paul <brianp at vmware.com>
Date: Tue Feb 24 09:20:12 2015 -0700
mesa: remove unused acosf, asinf, atan2f, etc. macros
Not used anywhere. If any of these are needed, they should be added
to c99_math.h
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit bd7f7aac56d3703f3d0fd55cd20f86f6c431b030
Author: Brian Paul <brianp at vmware.com>
Date: Tue Feb 24 09:08:50 2015 -0700
mesa: replace FABSF with fabsf
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 46ce78d4c659fcf9fb2b088424d4d16d13ab5d75
Author: Brian Paul <brianp at vmware.com>
Date: Tue Feb 24 09:04:54 2015 -0700
mesa: replace FLOORF with floorf
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit b2c13534f7b38eed1c5b15d73e8171d3038765c7
Author: Brian Paul <brianp at vmware.com>
Date: Tue Feb 24 09:03:25 2015 -0700
mesa: remove unused CEILF macro
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 79b480ccc069b92d4614ed7f61d810bdc816cb7c
Author: Brian Paul <brianp at vmware.com>
Date: Tue Feb 24 09:01:51 2015 -0700
mesa: replace LOGF, EXPF with logf, expf
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit e25f7772cacef8673318a7bfb33b151c5bc5d94c
Author: Brian Paul <brianp at vmware.com>
Date: Tue Feb 24 08:57:17 2015 -0700
mesa: replace FREXPF, LDEXPF with frexpf, ldexpf
Start getting rid of some imports.h macros. Use the c99 functions instead.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit e6eddbb96a9a690a865df8b0b9cfa2f644824b51
Author: Brian Paul <brianp at vmware.com>
Date: Tue Feb 24 08:47:57 2015 -0700
targets/libgl-xlib: add src/ include dir to fix build
commit a55831e8fabf3e53802a45d8bd74dbb1986f9754
Author: Brian Paul <brianp at vmware.com>
Date: Mon Feb 23 17:48:00 2015 -0700
swrast: fix a few release build warnings
commit 1180e61a1bb52d8fdf99185ca2c3042e7f686594
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Feb 23 18:03:02 2015 +0100
r600g,radeonsi: fix streamout after pipeline stats have been used
EVENT_TYPE_PIPELINESTAT_STOP disables streamout queries too.
Luckily, pipeline stats are enabled by default, so we don't even have to
emit EVENT_TYPE_PIPELINESTAT_START.
Tested on Hawaii, Bonaire, Redwood, RV730.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit fdf2c04737741c3bfaf2fc2167bcae4160dfeab3
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Feb 22 17:42:20 2015 +0100
radeonsi: small cleanup around current_rast_prim
- remove the last parameter of si_emit_rasterizer_prim_state
- remove the last unused parameter of si_emit_draw_registers
- use current_rast_prim in si_emit_draw_registers
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 0b1f31ab7fb323df14801dc3869c9de437c174d5
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Feb 22 19:14:42 2015 +0100
radeonsi: set current_rast_prim in the right place
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 4eb0ccf9e7902a0b1c9b691fa37852f31cb2befc
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Feb 22 15:36:20 2015 +0100
radeonsi: simplify obtaining a shader property in si_emit_clip_regs
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 53494371547392f3b9a836cdda66b5a1fdc9fda2
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Feb 22 15:11:49 2015 +0100
radeonsi: only preload VertexID for the GS copy shader
The copy shader doesn't use any other preloaded VGPRs.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit ffd701e677bf5df9315bd42a5f07585c7ad03d93
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Feb 22 14:58:30 2015 +0100
radeonsi: dump the shader key when dumping shaders
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 93daf5a2f6218ab086add878fce8e423899e1cc5
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Feb 20 12:22:00 2015 +0100
r600g,radeonsi: cleanup of hex literals
0x3F800000 -> fui(1.0)
0x00000000 -> 0
Reviewed-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit fa913a2dc6aefabdb9c6e927ad7095e89ffe0211
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Feb 20 12:14:37 2015 +0100
radeonsi: set PA_SU_HARDWARE_SCREEN_OFFSET to 0
It was probably 0 already, but it doesn't hurt to set it.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 558f51f1c5491d86c73769065c6df12a2b73dc4d
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Feb 22 13:22:07 2015 +0100
st/mesa: cleanup st_translate_geometry_program
Mostly dead code or code that didn't do anything.
Computing gs_num_outputs at the end was also useless. It's already set
correctly.
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit 94746cadc04c23add7750b446865b88297ff0a46
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Feb 21 22:41:39 2015 +0100
st/mesa: inline st_free_tokens
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit b039302fb7b6ae5041ae77e14c6b18f34e70f28b
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Feb 21 22:37:47 2015 +0100
st/mesa: cleanup st_geometry_program structure
It's full of unused variables and variables only used
in st_translate_geometry_program.
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit 002aa7502245805def2fd9bb1bc83284019757fe
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Feb 22 00:33:03 2015 +0100
mesa: add a missing GS support check in GetActiveUniformBlockiv
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit d80701df8af4a5d74c4f4eb09a4b3cef6970104b
Author: Glenn Kennard <glenn.kennard at gmail.com>
Date: Tue Feb 24 15:59:16 2015 +0100
r600g: Implement GL_ARB_draw_indirect for EG/CM
Requires Evergreen/Cayman and radeon kernel module
2.41.0 or newer.
Expected piglit fails due to hardware limitations:
* arb_draw_indirect-draw-arrays-prim-restart
Restarts not applied for DrawArrays commands
* arb_draw_indirect-vertexid
Base vertex offset is not included in vertex id
Marek: bump vgt_state num_dw by 3 (= space needed for one register write)
Signed-off-by: Glenn Kennard <glenn.kennard at gmail.com>
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
commit dd70e786747f7e4800f4bba245373c5ffa3baeee
Author: Rob Clark <robclark at freedesktop.org>
Date: Tue Feb 24 11:55:28 2015 -0500
freedreno/a4xx: aniso filtering
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit c70097ae8655d84a900cb27d165ca59d66411e29
Author: Rob Clark <robclark at freedesktop.org>
Date: Tue Feb 24 11:48:01 2015 -0500
freedreno: update generated headers
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit daccbd27ce2f838e855ade1216445c8dba7731f3
Author: Rob Clark <robclark at freedesktop.org>
Date: Sun Dec 21 11:52:44 2014 -0500
freedreno/a4xx: add ARB_instanced_arrays support
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit e13398714c29903577601df7cfb4cacfc35e73eb
Author: Rob Clark <robclark at freedesktop.org>
Date: Tue Feb 24 12:29:06 2015 -0500
freedreno/a4xx: handle index_bias (i.e. base_vertex)
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 283bb4848e0904d901e79d32883bf7dd546d6159
Author: Rob Clark <robclark at freedesktop.org>
Date: Sun Dec 21 11:38:34 2014 -0500
freedreno/a4xx: add support for vertexid and instanceid sysvals
ir3 bits of it already in place from a3xx patch..
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 4aef0d79ee2cebf3d11b803c5df016d87f3ba9fd
Author: Rob Clark <robclark at freedesktop.org>
Date: Sun Dec 21 11:14:24 2014 -0500
freedreno/a4xx: pass number of instances to draw
a4xx has it's own draw packet, so needs equivalent update to what a3xx
already got.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 86d88e2fbb509a85083725650f19442ad518f37e
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Tue Feb 24 16:09:12 2015 +0000
docs: add news item and link release notes for mesa 10.4.5
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit d60c628f2a6f8a87d2da9f998ec8eab3f80d4d37
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Feb 21 12:31:51 2015 +0000
docs: Add sha256 sums for the 10.4.5 release
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit 41bdeda10210b8f1d358c04b25af2fbfe3335531)
commit 1d761be43a694f24489ffea422c83737a731b8f2
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Feb 21 12:22:08 2015 +0000
Add release notes for the 10.4.5 release
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
(cherry picked from commit a5c608e951c7d41be99a1f84450a1d5aaf6ccadd)
commit 9c7b343bc0a6aa6065055cbc1c0a891ccc445984
Author: Leo Liu <leo.liu at amd.com>
Date: Mon Feb 23 13:50:06 2015 -0500
st/omx/dec/h264: fix picture out-of-order with poc type 0 v2
poc counter should be reset with IDR frame,
otherwise there would be a re-order issue with
frames before and after IDR
v2: add commit message
Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
Cc: "10.4 10.5" <mesa-stable at lists.freedesktop.org>
commit fece147be53880ac8e8e5e2863f91cdd01d98b5c
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Tue Feb 24 14:05:15 2015 +0000
install-lib-links: remove the .install-lib-links file
With earlier commit (install-lib-links: don't depend on .libs directory)
we moved the location of the file from .libs/ to the current dir.
Although we did not attribute that in the former case autotools was
doing us a favour and removing the file. Explicitly remove the file at
clean-local time, otherwise we'll end up with dangling files.
Cc: "10.3 10.4 10.5" <mesa-stable at lists.freedesktop.org>
Cc: Matt Turner <mattst88 at gmail.com>
Cc: Lucas Stach <l.stach at pengutronix.de>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit f8f3aa78d8846174d3b5a877b3c06ee7bdbb29c7
Author: Francisco Jerez <currojerez at riseup.net>
Date: Sun Feb 22 15:05:19 2015 +0200
clover: Set appropriate flag defaults on memory object creation.
According to the spec when no device access mode is specified
clCreateBuffer and clCreateImage* should default to read/write, and
clCreateSubBuffer should default to the parent's device access flags.
clCreateSubBuffer is also required to inherit the host access and
host pointer flags from the parent.
Reviewed-and-tested-by: EdB <edb+mesa at sigluy.net>
commit 0e8460a52882ec58743991fec431f85300bea209
Author: EdB <edb+mesa at sigluy.net>
Date: Sun Feb 22 15:00:06 2015 +0200
clover: Add CL_MEM_HOST_* flag checks.
Those flags have been introduced in OpenCL 1.2.
[ Francisco Jerez: Rebase. Throw CL_INVALID_VALUE from
clCreateSubBuffer if the subbuffer drops access flags from its
parent. Use single function taking the set of allowed host access
flags to validate memory transfer operands. ]
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 80d3c1e5372d56a55701b10b937173c27615e4b0
Author: Francisco Jerez <currojerez at riseup.net>
Date: Sun Feb 22 01:02:41 2015 +0200
clover: Factor out memory object flags validation to a helper function.
And define constants for commonly used subsets of flags to save some
typing.
Reviewed-and-tested-by: EdB <edb+mesa at sigluy.net>
commit 49d3c6a8e63ead43fafb7d52e2c770a1320eb2ee
Author: Eric Anholt <eric at anholt.net>
Date: Mon Feb 23 06:48:34 2015 +0000
vc4: Update to current kernel sources.
New BO create and mmap ioctls are added. The submit ABI gains a flags
argument, and the pointers are fixed at 64-bit. Shaders are now fixed at
the start of their BOs.
commit 1d1e820a6dce5e6fc8f67bd0f00e402645774e1b
Author: Eric Anholt <eric at anholt.net>
Date: Tue Feb 24 13:47:58 2015 +0000
r600: Fix build after 984f3069370cd4a347cb38269d430b428385affd
Same as for the CLAMP macro, undef it before including a header file that
tries to make fields with that name.
commit 98ae01c82294882b1fddcd03adf24101b4f24d4f
Author: Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de>
Date: Thu Feb 12 18:31:41 2015 +0100
st/nine: Mark end of non-void function unreachable
Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 984f3069370cd4a347cb38269d430b428385affd
Author: Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de>
Date: Thu Feb 12 18:31:40 2015 +0100
gallium: include util/macros.h
The most common macros are defined there, no use to duplicate these
Clean up the already redefinded macros
Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 9913ce14e7fc8d67fb58e175b7efac10ded152a9
Author: Alex Henrie <alexhenrie24 at gmail.com>
Date: Mon Feb 23 14:56:45 2015 -0700
driconf: Update Catalan translation
Signed-off-by: Alex Henrie <alexhenrie24 at gmail.com>
commit d28a4b523d252f47235d24fcda4db5a91a1af603
Author: Alex Henrie <alexhenrie24 at gmail.com>
Date: Mon Feb 23 14:56:44 2015 -0700
driconf: Update Spanish translation
Signed-off-by: Alex Henrie <alexhenrie24 at gmail.com>
commit 0c47e5492b2055848f88e41a14b0083674c5b18e
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Sat Feb 14 13:25:20 2015 +0100
mesa: Add missing error checks to GetProgramInfoLog, GetShaderInfoLog and GetProgramiv
Fixes 3 dEQP tests:
* dEQP-GLES3.functional.negative_api.state.get_program_info_log
* dEQP-GLES3.functional.negative_api.state.get_shader_info_log
* dEQP-GLES3.functional.negative_api.state.get_programiv
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit fe74fee8fa721a42448470e063870d24f9453dab
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Tue Feb 10 16:40:46 2015 +0100
i965: Fix non-AA wide line rendering with fractional line widths
"(...)Let w be the width rounded to the nearest integer (...). If the
line segment has endpoints given by (x0,y0) and (x1,y1) in window
coordinates, the segment with endpoints (x0,y0-(w-1)/2) and
(x1,y1-(w-1/2)) is rasterized, (...)"
The hardware it not rounding the line width, so we should do it.
Also, we should be careful not to go beyond the hardware limits
for the line width after it gets rounded. Gen6-7 define a maximum line
width slightly below 8.0, so we should advertise a maximum line
width lower than 7.5 to make sure that 7.0 is the maximum integer
line width that we can select. Since the line width granularity in these
platforms is 0.125, we choose 7.375. Other platforms advertise rounded
maximum line widths, so those are fine.
Fixes the following 3 dEQP tests:
dEQP-GLES3.functional.rasterization.primitives.lines_wide
dEQP-GLES3.functional.rasterization.fbo.texture_2d.primitives.lines_wide
dEQP-GLES3.functional.rasterization.fbo.rbo_singlesample.primitives.lines_wide
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 6148e3aae7e0d36b59759075bf7a4ce2248ce321
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Wed Feb 11 11:35:35 2015 +0100
mesa: Fix ctx->Texture.CubeMapSeamless
The intel driver code, and apparently all other Mesa drivers, call
_mesa_initialize_context early in the CreateContext hook. That
function will end up calling _mesa_init_texture which will do:
ctx->Texture.CubeMapSeamless = _mesa_is_gles3(ctx);
But this won't work at this point, since _mesa_is_gles3 requires
ctx->Version to be set and that will not happen until late
in the CreateContext hook, when _mesa_compute_version is called.
We can't just move the call to _mesa_compute_version before
_mesa_initialize_context since it needs that available extensions
have been computed, which again requires other things to be
initialized, etc. Instead, we enable seamless cube maps since
GLES2, which should work for most implementations, and expect
drivers that don't support this to disable it manually as part
of their context initialization setup.
Fixes the following 192 dEQP tests:
dEQP-GLES3.functional.texture.filtering.cube.formats.*
dEQP-GLES3.functional.texture.filtering.cube.sizes.*
dEQP-GLES3.functional.texture.filtering.cube.combinations.*
dEQP-GLES3.functional.texture.mipmap.cube.*
dEQP-GLES3.functional.texture.vertex.cube.filtering.*
dEQP-GLES3.functional.texture.vertex.cube.wrap.*
dEQP-GLES3.functional.shaders.texture_functions.texturelod.samplercube_fixed_*
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit dccdf1d687c3abb9a2fc6695c2090f01fdb65997
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Mon Feb 9 11:32:43 2015 +0100
mesa: Return error if BeginQuery is called with an existing object of different type
Section 2.14 Asynchronous Queries, page 84 of the OpenGL ES 3.0.4
spec states:
"BeginQuery generates an INVALID_OPERATION error if any of the
following conditions hold: [...] id is the name of an
existing query object whose type does not match target; [...]
Similar wording exists in the OpenGL 4.5 spec, section 4.2. QUERY
OBJECTS AND ASYNCHRONOUS QUERIES, page 43.
Fixes 1 dEQP test:
* dEQP-GLES3.functional.negative_api.fragment.begin_query
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 36998664630e1e846011fd8436fd02476e1b647e
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Mon Feb 9 11:07:42 2015 +0100
mesa: Return INVALID_OPERATION when querying a never bound Query obj
Section 2.14 Asynchronous Queries, page 84 of the OpenGL ES 3.0.4 states:
"The command void GenQueries( sizei n, uint *ids ); returns n previously unused
query object names in ids. These names are marked as used, for the purposes of
GenQueries only, but no object is associated with them until the first time they
are used by BeginQuery."
This means that any attempt to use or query a Query object id before it has ever
been bound by calling glBeginQuery, should be assume to be an invalid object.
Fixes 1 dEQP test:
* dEQP-GLES3.functional.negative_api.state.get_query_objectuiv
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 4db4a559adcad494cdd17d378602b4b97a51d2b8
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Tue Feb 10 16:40:43 2015 +0100
mesa: Add _mesa_is_array_texture helper
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 2aa71e9485a5a062b1bd2dd8bdc081a8fa4c873d
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Mon Feb 2 18:14:47 2015 +0100
mesa: Fix error validating args for TexSubImage3D
The zoffset and depth values were not being considered when calling
error_check_subtexture_dimensions().
Fixes 2 dEQP tests:
* dEQP-GLES3.functional.negative_api.texture.texsubimage3d_neg_offset
* dEQP-GLES3.functional.negative_api.texture.texsubimage3d_invalid_offset
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Cc: "10.4 10.5" <mesa-stable at lists.freedestkop.org>
commit fbd6eba72bd282297c5f49371e89a1c18cb24151
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Thu Jan 22 16:01:57 2015 +0100
i965/blorp: round to nearest when converting float into integer
Fixes:
dEQP-GLES3.functional.fbo.blit.rect.out_of_bounds_nearest
dEQP-GLES3.functional.fbo.blit.rect.out_of_bounds_linear
dEQP-GLES3.functional.fbo.blit.rect.out_of_bounds_reverse_src_y_nearest
dEQP-GLES3.functional.fbo.blit.rect.out_of_bounds_reverse_src_y_linear
dEQP-GLES3.functional.fbo.blit.rect.out_of_bounds_reverse_dst_y_nearest
dEQP-GLES3.functional.fbo.blit.rect.out_of_bounds_reverse_dst_y_linear
dEQP-GLES3.functional.fbo.blit.rect.out_of_bounds_reverse_src_dst_x_nearest
dEQP-GLES3.functional.fbo.blit.rect.out_of_bounds_reverse_src_dst_x_linear
dEQP-GLES3.functional.fbo.blit.rect.out_of_bounds_reverse_src_dst_y_nearest
dEQP-GLES3.functional.fbo.blit.rect.out_of_bounds_reverse_src_dst_y_linear
No piglit regressions.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 4a6c6c49a7236b1471df143a697195f0c11eb23c
Author: Carl Worth <cworth at cworth.org>
Date: Wed Feb 11 13:53:31 2015 -0800
i965: Perform program state upload outside of atom handling
Across the board of the various generations, the intial few atoms in
all of the atom lists are basically the same, (performing uploads for
the various programs). The only difference is that prior to gen6
there's an ff_gs upload in place of the later gs upload.
In this commit, instead of using the atom lists for this program state
upload, we add a new function brw_upload_programs that calls into the
per-stage upload functions which in turn check dirty bits and return
immediately if nothing needs to be done.
This commit is intended to have no functional change. The motivation
is that future code, (such as the shader cache), wants to have a
single function within which to perform various operations before and
after program upload, (with some local variables holding state across
the upload).
It may be worth looking at whether some of the other functionality
currently handled via atoms might also be more cleanly handled in a
similar fashion.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 1e96eece300bbd2dd621a4941a4418222bb4c8e5
Author: Vivek Kasireddy <vivek.kasireddy at intel.com>
Date: Tue Feb 10 19:15:31 2015 -0800
egl, wayland: RGB565 format support on Back-buffer
In current code, color format is always hardcoded to
__DRI_IMAGE_FORMAT_ARGB8888 when buffer or DRI image is
allocated in function calls, get_back_bo and dri2_get_buffers,
regardless of current target's color format. This problem
may leads to incorrect render pitch calculation, which
eventually ends up with wrong offset of pixels in
the frame buffer when the image is in different color format
from dri surf's, especially with different bpp. (e.g. RGB565-16bpp)
Attached code patch simply adds RGB565 and XRGB8888 cases to two
functions noted above to resolve the issue.
v2: added a case of XRGB8888, format and bpp selection is done
via switch-case (not "if-else" anymore)
Signed-off-by: Vivek Kasireddy <vivek.kasireddy at intel.com>
Signed-off-by: Dongwon Kim <dongwon.kim at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Cc: "10.5" <mesa-stable at lists.freedesktop.org>
commit cbd287f094b4bd7a6030edf97f5330b4c3fa9a5c
Author: Brian Paul <brianp at vmware.com>
Date: Mon Feb 23 13:33:50 2015 -0700
mesa: move math-related function into new c99_math.h file
The alternative would be to include math.h in c99_compat.h but that
seems heavy-handed.
This patch also replaces INLINE with inline in the c99 math function
wrappers.
Fixes MSVC build.
Acked-by: Matt Turner <mattst88 at gmail.com>
commit 9b9ef2aeeec07d011e9c51632914fa5e769ca0ad
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Sat Feb 21 22:29:01 2015 -0800
nir/gcm: Add some missing break statements
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit cb4b2ad44aad6bc5fcb2db594af38a6283bb7a4e
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Thu Feb 19 17:19:22 2015 -0800
nir: Copy-propagate vecN operations that are actually moves
We were already do this for ALU operations but we haven't for non-ALU
operations. This changes that.
total NIR instructions in shared programs: 2039883 -> 2022338 (-0.86%)
NIR instructions in affected programs: 1768850 -> 1751305 (-0.99%)
helped: 14244
HURT: 124
total FS instructions in shared programs: 4083960 -> 4084036 (0.00%)
FS instructions in affected programs: 7302 -> 7378 (1.04%)
helped: 12
HURT: 51
Signed-off-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit f80af89d48f2c9045c7e0438a1b35d09be3e84d5
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Feb 16 13:38:39 2015 +0200
ra: Disable round-robin strategy for optimistically colorable nodes.
The round-robin allocation strategy is expected to decrease the amount
of false dependencies created by the register allocator and give the
post-RA scheduling pass more freedom to move instructions around. On
the other hand it has the disadvantage of increasing fragmentation and
decreasing the number of equally-colored nearby nodes, what increases
the likelihood of failure in presence of optimistically colorable
nodes.
This patch disables the round-robin strategy for optimistically
colorable nodes. These typically arise in situations of high register
pressure or for registers with large live intervals, in both cases the
task of the instruction scheduler shouldn't be constrained excessively
by the dense packing of those nodes, and a spill (or on Intel hardware
a fall-back to SIMD8 mode) is invariably worse than a slightly less
optimal scheduling.
Shader-db results on the i965 driver:
total instructions in shared programs: 5488539 -> 5488489 (-0.00%)
instructions in affected programs: 1121 -> 1071 (-4.46%)
helped: 1
HURT: 0
GAINED: 49
LOST: 5
v2: Re-enable round-robin already for the lowest one of the nodes
pushed optimistically onto the sack (Connor).
v3: Use UINT_MAX instead of ~0, open-code MIN2 (Jason, Connor).
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 34c93fd7f119fa824062e05377de849b8a2da0e6
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Feb 5 12:20:03 2015 +0200
i965/fs: Fix lower_load_payload() not to use an incorrect half for immediates and uniforms.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit ea7b4d25c8da352f4ca0dcaefa4fadb9e202636e
Author: Francisco Jerez <currojerez at riseup.net>
Date: Fri Feb 6 15:06:05 2015 +0200
i965/fs: Fix lower_load_payload() to take into account non-zero reg_offset.
Fixes metadata guess when instructions in the program specify a
destination register with non-zero reg_offset and when the payload of
a LOAD_PAYLOAD spans several registers.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 08b4c8f7bf2cc2fe914a07a32bf4961894593e72
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Feb 4 19:49:32 2015 +0200
i965/fs: Remove logic to keep track of MRF metadata in lower_load_payload().
MRFs cannot be read from anyway so they cannot possibly be a valid
source of LOAD_PAYLOAD.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 8e47f51a5a7aba2bb56e7185988072431444d811
Author: Francisco Jerez <currojerez at riseup.net>
Date: Sat Jan 17 14:12:34 2015 +0200
i965/fs: Less broken handling of force_writemask_all in lower_load_payload().
It's perfectly fine to read the second half of a register written with
force_writemask_all from a first half MOV instruction or vice versa, and
lower_load_payload shouldn't mark the whole MOV as belonging to the second
half in that case. Replicate the same metadata to both halves of the
destination when writemasking is disabled.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 57d80d11b1ecc45dc38c1fbf3d92413fa847a513
Author: Matt Turner <mattst88 at gmail.com>
Date: Sun Feb 22 20:25:28 2015 -0800
mesa/vbo: Use unreachable to silence uninitialized var warning.
Reviewed-by: Eric Anholt <eric at anholt.net>
commit bb2a897dbc8064ccd38ecbf3f484abc0b900a862
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Feb 20 20:27:06 2015 -0800
mesa: Move START/END_FAST_MATH macros to their only use.
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 08bc7cf8f641812a48e9d9a416611795e2736489
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Feb 20 20:23:26 2015 -0800
mesa: Remove definition of NULL.
If your stdlib.h doesn't define this you should fix your stdlib.h.
Reviewed-by: Eric Anholt <eric at anholt.net>
commit bfcdb843830bba0190e00e35e3c5c18c4bdb5de1
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Feb 20 20:18:47 2015 -0800
mesa: Use assert() instead of ASSERT wrapper.
Acked-by: Eric Anholt <eric at anholt.net>
commit 52049f8fd83f2ef31c2a4d645cfb7d7b2ab518a6
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Feb 20 20:12:14 2015 -0800
mesa: Remove CHECK macro.
There's some commentary about how it's defined by other "modules", and
maybe that was true in 2000 when the code was added.
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 6a587a44617aed3638e324abd3bbdad8b499eb80
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Feb 20 20:08:51 2015 -0800
mesa: Remove dead CAPI define.
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 14ded5ee61b2dfc23878c4a6f38021b15bd0a2fc
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Feb 20 19:46:21 2015 -0800
gallium: Use util_cpu_to_le{16,32} in many more places.
... and util_le{16,32}_to_cpu. I think I've used the right ones for
describing the actual operation performed (even though they're both just
"byte-swap this if I'm on big-endian").
The Linux Kernel has typedefs __le32/__be32 and friends that static
analysis tools can use to check that byte-orderings are correct. It
might be interesting to apply that here as well.
Reviewed-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 3492e88090d2d0c0bfbc934963b8772b45fc8880
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Feb 20 18:46:43 2015 -0800
gallium/util: Use HAVE___BUILTIN_* macros.
Reviewed-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 5a191f49ad084e728122fed83bd7511817e66831
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Feb 20 18:32:05 2015 -0800
mesa: Move C99 MSVC compatibility code from u_math.h to c99_compat.h.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 0b6d43e329d194b01ab5cd554617f79a13f6669a
Author: Matt Turner <mattst88 at gmail.com>
Date: Sat Feb 21 22:41:24 2015 -0800
i965: Link test programs with gtest before pthreads.
Cc: "10.5" <mesa-stable at lists.freedesktop.org>
Bugzilla: https://bugs.gentoo.org/show_bug.cgi?id=540962
commit 5dc6c8c570a11a3e4bf3142b54cd618e9c66b51b
Author: Brian Paul <brianp at vmware.com>
Date: Mon Feb 23 08:39:11 2015 -0700
osmesa: add gallium include dirs to Makefile.am
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89260
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 44375a3b1362cf88cd5b00463a8ae91376c8a93b
Author: Brian Paul <brianp at vmware.com>
Date: Mon Feb 23 08:57:32 2015 -0700
util: move pipe_prim_names array into u_prim_name()
Also, wrapping the array in #ifdef DEBUG / #endif doesn't seem necessary.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit f1c67e37e66adfedb0ff944868d62918979349da
Author: Brian Paul <brianp at vmware.com>
Date: Mon Feb 23 08:57:32 2015 -0700
util: rewrite debug_print_transfer_flags() using debug_dump_flags()
Add add missing PIPE_TRANSFER_PERSISTENT, PIPE_TRANSFER_COHERENT flags.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 0bfe21e8e0bf6c80d46e82b7b8382e75881f2d64
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Mon Feb 23 13:03:56 2015 +0100
mesa: Adds missing error condition in _mesa_check_sample_count()
This corrects a trivial error introduced in commit
19252fee46b835cb4f6b1cce18d7737d62b64a2e. That patch was merged recently
and omits one condition (that 'samples' is greater than zero) in one of
the error checks. That error will definitely cause regressions.
Also corrects the reference to the specification above the error check,
which was wrongly quoting OpenGL instead of OpenGL-ES.
Reviewed-by: Martin Peres <martin.peres at linux.intel.com>
commit 050bf75c8bbaa7cad537aabaf8612129edfee3a4
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Feb 23 11:42:59 2015 +0100
radeonsi: fix a warning caused by previous commit
Cc: 10.5 10.4 <mesa-stable at lists.freedesktop.org>
commit 7820a11e3dea2aca8e2b9b4ed9faf94ff5696990
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Feb 23 11:39:53 2015 +0100
radeonsi: fix point sprites
Broken by a27b74819ad375e8c0bc88e13f42c951d2b5cd6a.
This fix is critical and should be ported to stable ASAP.
Cc: 10.5 10.4 <mesa-stable at lists.freedesktop.org>
commit 6e62a52865787362ae1deb9dee80140d3a66c519
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Thu Feb 19 15:49:34 2015 -0800
i965/skl: Use 1 register for uniform pull constant payload
When under dispatch_width=16 the previous code would allocate 2 registers for
the payload when only one is needed. This manifested itself through bugs on SKL
which needs to mess with this instruction.
Ken though this might impact shader-db, but apparently it doesn't
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89118
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88999
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Tested-by: Timo Aaltonen <timo.aaltonen at canonical.com>
commit 4359954d842caa2a9f8d4b50d70ecc789884b68b
Author: Eric Anholt <eric at anholt.net>
Date: Fri Feb 20 00:00:27 2015 -0800
nir: Generalize the optimization of subs of subs from 0.
I initially wrote this based on the "(('fneg', ('fneg', a)), a)" above,
but we can generalize it and make it more potentially useful. In the
specific original case of a 0 for our new 'a' argument, it'll get further
algebraic optimization once the 0 is an argument to the new add.
No shader-db effects.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 345c2b288a5f49b82d505eb098847b8e53dde91f
Author: Eric Anholt <eric at anholt.net>
Date: Fri Feb 20 01:20:34 2015 -0800
nir: Collapse repeated bcsels on the same argument.
vc4 results:
total instructions in shared programs: 39881 -> 39794 (-0.22%)
instructions in affected programs: 6302 -> 6215 (-1.38%)
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit a38038ca5e329c074f67399a993a653c8e439cae
Author: Eric Anholt <eric at anholt.net>
Date: Fri Feb 20 01:18:46 2015 -0800
nir: When faced with a csel on !condition, just flip the arguments.
total NIR instructions in shared programs: 39426 -> 39411 (-0.04%)
NIR instructions in affected programs: 3748 -> 3733 (-0.40%)
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 8e1152cb33e53a9d31a6c239dd77b0b4b7613ea8
Author: Eric Anholt <eric at anholt.net>
Date: Fri Feb 20 00:57:04 2015 -0800
nir: Allow nir_opt_algebraic to see booleanness through &&, ||, ^, !.
We have some useful optimizations to drop things like 'ine a, 0' on a
boolean argument, but if 'a' came from logical operations on bools, it
couldn't tell. These kinds of constructs appear as a result of TGSI->NIR
quite frequently (at least with if flattening), so being a little more
aggressive in detecting booleans can pay off.
v2: Add ixor as a booleanness-preserving op (Suggestion by Connor).
vc4 results:
total instructions in shared programs: 40207 -> 39881 (-0.81%)
instructions in affected programs: 6677 -> 6351 (-4.88%)
Reviewed-by: Matt Turner <mattst88 at gmail.com> (v1)
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit dc982f4a859d800ec3eba95d3c55bbe6af8d6518
Author: Eric Anholt <eric at anholt.net>
Date: Thu Jan 29 15:50:18 2015 -0800
nir: Add a couple of simplifications of csel operations.
vc4 was already cleaning these up, but it does shave 4 NIR instructions in
shader-db.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit c2ece77678c19f6aee1d9a3ef65a1251a59dd2ae
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Feb 21 12:53:43 2015 -0500
glsl: ensure that enter/leave record get a record type
May make life easier for tools like Coverity.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 1763494b315179495eabb97d50d025a04a6537e2
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Feb 21 12:44:05 2015 -0500
tgsi: avoid returning pointer to local var, make it static
Spotted by Coverity.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 51e335742e55d6725fd5c4558158769a32f70f22
Author: Rob Clark <robclark at freedesktop.org>
Date: Sat Feb 21 13:55:37 2015 -0500
freedreno/a4xx: set PC_PRIM_VTX_CNTL.VAROUT properly
Fixes xonotic, some webgl stuff, and really pretty much anything with
more than 4 varyings.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit fb1301e40abbac1de973563cacd2c7f31aa6bb4f
Author: Rob Clark <robclark at freedesktop.org>
Date: Sat Feb 21 13:50:52 2015 -0500
freedreno: update generated headers
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit bdf023482a6fd07adef090fb66a4aaaac22810fc
Author: Rob Clark <robclark at freedesktop.org>
Date: Sat Feb 21 13:39:06 2015 -0500
freedreno/a4xx: bit of cleanup
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 9153dd4b7eb95728aa9746a45a9dd136458d0213
Author: Rob Clark <robclark at freedesktop.org>
Date: Sun Feb 15 01:59:17 2015 -0500
loader: not having a pci-id should not be a warn
If there is no pci-id, which is valid for vc4 and freedreno, just emit
an info msg. Keep malformed but existing pci-id's as a warning.
Mostly just to clean up a warning that confuses users for the non-pci
devices.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit e17437386c1bf715b6b241bd9de3a583103f851b
Author: Rob Clark <robclark at freedesktop.org>
Date: Sun Feb 15 00:04:57 2015 -0500
freedreno: implement fence
I never actually implemented the stubbed out fence stuff back in the
early days. Fix that.
We'll need a few libdrm_freedreno changes to handle timeout properly,
so ignore that for now to avoid a libdrm_freedreno dependency bump.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 68552266535747bad1eff34d856c43158398b9bf
Author: Rob Clark <robclark at freedesktop.org>
Date: Tue Feb 3 15:52:53 2015 -0500
freedreno/a2xx: fix increment in assert
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88883
Signed-off-by: Rob Clark <robclark at freedesktop.org>
commit 49a938a265f5959c9b558995cc658f80acb6eb18
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Fri Feb 20 12:12:25 2015 -0800
i965/fs: Use fs_reg for CS/VS atomics pixel mask immediate data
The brw_imm_ud will yield a HW_REG which then will introduce a barrier
for certain optimization opportunities.
No piglit regressions seen with gen8 (simd8vs).
Suggested-by: Matt Turner <mattst88 at gmail.com>
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 17fbd854e03a569d71885e54a98dab45bfa6b897
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Sun Sep 21 18:31:45 2014 -0700
i965/fs: Set pixel/sample mask for compute shaders atomic ops
For fragment programs, we pull this mask from the payload header. The same
mask doesn't exist for compute shaders, so we set all bits to enabled.
Previously we were setting 0xff to support SIMD8 VS, but with CS we
support SIMD16, and therefore we change this to 0xffff.
Related commits for SIMD8 VS:
commit d9cd982d556be560af3bcbcdaf62b6b93eb934a5
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Sun Feb 15 20:06:59 2015 -0800
i965/simd8vs: Fix SIMD8 atomics
commit 4a95be9772a255776309f23180519a4a8560f2dd
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Tue Feb 17 09:57:35 2015 -0800
i965/simd8vs: Fix SIMD8 atomics (read-only)
Note: this mask is ANDed with the execution mask, so some channels may not end
up issuing the atomic operation.
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit 9fe81879c54562a4abbfba3eb5f6081f152c83db
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Sat Feb 21 00:35:49 2015 +0800
ilo: R32G32B32_FLOAT need no special care on Gen8+
Gen8+ must use VALIGN_4. Unlike prior Gens, R32G32B32_FLOAT should supposedly
support VALIGN_4.
commit 226109436fd7e0fe67bad024629496b4f4d75633
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Feb 20 15:27:14 2015 +0800
ilo: 128 BPP formats can use TiledY on Gen7.5+
The restriction is lifted.
commit f8e4792b227544aefd45eb716091adb7409fa843
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Jul 23 22:32:55 2014 -0400
nvc0: enable double support
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 5491458843998e8083baf9b62c14895946de1a3f
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Jul 7 01:53:52 2014 -0400
nvc0/ir: remove merge/split pairs to allow normal propagation to occur
Because the TGSI interface creates merges for each instruction source
and then splits them back out, there are a lot of unnecessary
merge/split pairs which do essentially nothing. The various modifier/etc
propagation doesn't know how to walk though those, so just remove them
when they're unnecessary.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 93812dc10aebf805568926583b0f289ebb5ccbf6
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Jul 6 23:39:59 2014 -0400
nvc0/ir: add support for new TGSI double opcodes
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit ef8f09be3375231481373a5c49a5cef3db3d2141
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Jul 7 02:32:45 2014 -0400
nvc0/ir: handle zero and negative sqrt arguments
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 88127874a3eacd379f3c721bbdacdbdad4d03125
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Jul 6 23:39:38 2014 -0400
nvc0/ir: no instruction can load a double immediate
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit b87b498b88c51fb8c80901b8f581331d3fbcd972
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Jul 7 00:04:19 2014 -0400
nvc0/ir: fix lowering of RSQ/RCP/SQRT/MOD to work with F64
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 93ebe91baed86a63f81fa852c5e7cc0ea52ff562
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Sep 26 02:38:53 2014 -0400
gm107/ir: fix F2F flipped stype/dtype flags
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit dbf4a674b94fc8fca21997f8145b96bcf2f7a260
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Sep 26 02:35:51 2014 -0400
gm107/ir: fix DSET boolean float flag
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 727018bb0c4fb7ca6e047937af5a58e17a1b4f7c
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Sep 26 02:21:55 2014 -0400
gm107/ir: fix DMUL opcode encoding
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 493ad88e1b6598e3827546854b0c8336b42b36a2
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Jul 18 22:20:42 2014 -0400
gk110/ir: add emission of dadd/dmul/dmad opcodes
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit fd0b1a4cbf65e2fc4eaaf90fea6df786530ab9a7
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Jul 6 23:36:32 2014 -0400
nvc0/ir: add emission of dadd/dmul/dmad opcodes, fix minmax
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 88305dfd0b79ad5980d293e86712496f134347b4
Author: Roland Scheidegger <sroland at vmware.com>
Date: Sat Feb 14 16:34:04 2015 +0100
mesa: don't enable NV_fragment_program_option with swrast
Since dropping some NV_fragment_program opcodes (commits
868f95f1da74cf6dd7468cba1b56664aad585ccb, a3688d686f147f4252d19b298ae26d4ac72c2e08)
we can no longer parse all opcodes necessary for this extension, leading
to bugs (https://bugs.freedesktop.org/show_bug.cgi?id=86980).
Hence don't announce support for it in swrast (no other driver enabled it).
(Note that remnants of some NV_fp/vp extensions remain, they could be
dropped but are required as hacks for getting viewperf11 catia to run.)
commit 9dbe5e1dca8da8e129706ed88e41e142172617fe
Author: Brian Paul <brianp at vmware.com>
Date: Fri Feb 20 13:19:50 2015 -0700
drivers/x11: add gallium include dirs to Makefile.am
Fixes xlib driver build after e8c5cbfd921680c.
Acked-by: Matt Turner <mattst88 at gmail.com>
commit 0feb0b73731cebd1513dd7f4e6cdf6de81edb802
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Feb 20 20:17:39 2015 +0100
vbo: fix an unitialized-variable warning
It looks like a bug to me.
Cc: 10.5 10.4 10.3 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 41f49a2fd422f698c2edaf71c016f38a925d02fd
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Feb 20 20:17:20 2015 +0100
gallium/sw/kms: fix a type-mismatch warning
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 1a44566132e9ba9bae39cac24887c83ef6d0787d
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Feb 20 20:15:59 2015 +0100
gallium/sw/kms: don't redefine DEBUG
Reviewed-by: Brian Paul <brianp at vmware.com>
commit f9002339284e137e6ce80389744d0e56ec265006
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Feb 20 20:15:35 2015 +0100
targets/d3dadapter9: remove an unused variable
Reviewed-by: Brian Paul <brianp at vmware.com>
commit ab947d2dd8219038ff6a71e5794a243cf1d1e314
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Feb 20 20:15:05 2015 +0100
tgsi: fix type-mismatch warning
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 6f273ec408b794d1d8969ec52a5952c9babc1c52
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Feb 20 20:14:33 2015 +0100
gallivm: fix uninitialized-variable warnings
Reviewed-by: Brian Paul <brianp at vmware.com>
commit b21ad12485d24565fd7f21addb5c86c77cf64580
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Feb 20 12:41:46 2015 -0800
mesa: Have configure define NDEBUG, not mtypes.h.
mtypes.h had been defining NDEBUG (used by assert) if DEBUG was not
defined. Confusing and bizarre that you don't get NDEBUG if you don't
include mtypes.h.
... which is just what happened in commit bef38f62e.
Let's let configure define this for us if not using --enable-debug.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit b6393d70402a60c124c1884d8d0cc1dc6a9b4ca5
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Feb 20 12:31:31 2015 -0800
nir: Fix the Mesa build without -DDEBUG.
With -DDEBUG -UNDEBUG, this assert uses reg_state::stack_size, which
doesn't exist, breaking the build:
assert(state->states[index].index < state->states[index].stack_size);
Switch it to ifndef NDEBUG, so the field will exist if the assertion
actually generates code.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit bef38f62e026c5bce5073f82f2797151f941b586
Author: Eric Anholt <eric at anholt.net>
Date: Wed Feb 11 15:08:02 2015 -0800
nir: Drop dependency on mtypes.h for core NIR.
One less new directory necessary for gallium code that wants to interact
with NIR.
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 90b4bf2e6e1289442331f0368221fde69b60915f
Author: Eric Anholt <eric at anholt.net>
Date: Wed Feb 11 15:21:37 2015 -0800
glsl: Only include mtypes from glsl_types.h for the C++ code that needs it.
It's used in one of the methods, not in the structure definitions.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit b53d035825ef3ad680470aa5c4f9dc51f8f5676b
Author: Eric Anholt <eric at anholt.net>
Date: Wed Feb 11 15:05:06 2015 -0800
util: Move Mesa's bitset.h to util/.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 8aa381e3cd848f051931f86af5fdcd59921916ee
Author: Eric Anholt <eric at anholt.net>
Date: Wed Feb 11 14:57:55 2015 -0800
mesa: Make bitset.h not rely on Mesa-specific types and functions.
Note that we can't use u_math.h's align() because it's a function instead
of a macro, while BITSET_DECLARE needs a constant expression for nouveau's
usage in global declarations.
v2: Stick some parens around the bits macro argument usage (review by Jose).
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 41b1882ed45f0fcb827a178cb3f7143fcaa8c4d9
Author: Eric Anholt <eric at anholt.net>
Date: Wed Feb 11 14:24:33 2015 -0800
mesa: Use u_math.h from macros.h
This avoids duplication of some macros and other definitions across the
tree.
Note that COPY_4FV switches from a memcpy-based implementation to an
assignment of 4 floats.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit 5ca019358f7a598174bd4adb6746fedc0ca78943
Author: Eric Anholt <eric at anholt.net>
Date: Wed Feb 11 14:28:44 2015 -0800
gallium/util: Don't include unused debug functions from u_math.h
It introduces references to gallium util/ symbols which means we don't get
to include it from outside-of-gallium code.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit e8c5cbfd921680c4a68755b66889338a6268debb
Author: Eric Anholt <eric at anholt.net>
Date: Wed Feb 11 14:18:50 2015 -0800
mesa: Add gallium include dirs to more parts of the tree.
v2: Try to patch up the scons bits.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
commit f5ac5e20b16d17b0adda6d856829dd0cf997f7dc
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Feb 20 20:13:44 2015 +0100
gallium/radeon: fix an uninitialized-variable warning
commit c85a686d028a6e90f7487ac4319dae2edd40c9a0
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Feb 19 23:30:36 2015 -0500
gallium: add new double-related shader caps to all the getters
Missed a few drivers in the earlier changes, this should fix up all the
ones that print unknown caps or don't have a default statement.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit 71b155a2cb10037584462f4f182f017a9898e810
Author: Brian Paul <brianp at vmware.com>
Date: Fri Feb 20 08:09:36 2015 -0700
svga: add missing _DROUND,DFRACEXP_DLDEXP_SUPPORTED switch cases
To silence unhandled switch case warnings.
commit 7692704b144b2aa9a57767a43212ceb5aad6638a
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Feb 19 13:03:54 2015 +0100
radeonsi: don't use SQC_CACHES to flush ICACHE and KCACHE on SI
This reverts 73c2b0d18c51459697d8ec194ecfc4438c98c139.
It doesn't seem to be reliable. It's probably missing a wait packet or
something, because it's just a register write and doesn't wait for anything.
SURFACE_SYNC at least seems to wait until the flush is done. Just guessing.
Let's not complicate things and revert this.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88561
Cc: 10.5 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
commit 2a06728ba0da5e4175843b1b53919d6167ca0aea
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Fri Feb 20 08:21:25 2015 +0100
i965/gen6: Fix GL_GEOMETRY_SHADER_PRIMITIVES_EMITTED_ARB
In gen6 we need to compute the primitive count in the generated GS program.
The current implementation only counts full primitives, that is, if the
output primitive type is a triangle strip, it won't count individual
triangles in the strip, only complete strips.
If we want to count basic primitives instead we have two options: rework
the assembly code we generate for strip primitives or simply use
CL_INVOCATION_COUNT to resolve the query and let the hardware do that work
for us. This patch implements the latter approach.
Fixes the following piglit test:
bin/arb_pipeline_statistics_query-geom -auto
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89210
Tested-by: Mark Janes <mark.a.janes at intel.com>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit 097b933b55eea6181678b34ede94bbc588dc94ff
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Fri Feb 20 09:32:42 2015 +0100
mesa: Check that draw buffers are valid for glDrawBuffers on GLES3
Section 4.2 (Whole Framebuffer Operations) of the OpenGL 3.0 specification
says:
"Each buffer listed in bufs must be BACK, NONE, or one of the values from
table 4.3 (NONE, COLOR_ATTACHMENTi)".
Fixes 1 dEQP test:
* dEQP-GLES3.functional.negative_api.buffer.draw_buffers
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit fe1e89a026fb85cc7dffbd3f967687186796631e
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Tue Nov 25 14:03:05 2014 +0100
glsl: don't allow invariant qualifiers for interface blocks
GLSL 1.50 and GLSL 4.40 specs, they both say the same in
"Interface Blocks" section:
"If optional qualifiers are used, they can include interpolation qualifiers,
auxiliary storage qualifiers, and storage qualifiers and they must declare
an input, output, or uniform member consistent with the interface qualifier
of the block"
From GLSL ES 3.0, chapter 4.3.7 "Interface Blocks", page 38:
"GLSL ES 3.0 does not support interface blocks for shader inputs or outputs."
and from GLSL ES 3.0, chapter 4.6.1 "The invariant qualifier", page 52.
"Only variables output from a shader can be candidates for invariance."
This patch fixes the following dEQP tests:
dEQP-GLES3.functional.shaders.declarations.invalid_declarations.invariant_uniform_block_2_vertex
dEQP-GLES3.functional.shaders.declarations.invalid_declarations.invariant_uniform_block_2_fragment
No piglit regressions.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
v2:
- Enable this check for GLSL.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 85316d059c899ac096331251de6b233229aa0b4f
Author: Eric Anholt <eric at anholt.net>
Date: Thu Feb 19 13:22:31 2015 -0800
vc4: Keep an array of pointers to instructions defining the temps around.
The optimization passes are always regenerating it and throwing it away,
but it's not hard to keep track of.
commit 877b48a531adc397493e508e509aba2918915349
Author: Eric Anholt <eric at anholt.net>
Date: Thu Feb 19 12:19:44 2015 -0800
vc4: Move qir_uniform() and the constant-value versions to vc4_qir.c/h.
I may want them in optimization passes, and they're not really particular
to the program translation stage.
commit 14dc281c1332518b6144718e1fb3845abbe23ff7
Author: Eric Anholt <eric at anholt.net>
Date: Thu Feb 19 12:58:53 2015 -0800
vc4: Enforce one-uniform-per-instruction after optimization.
This lets us more intelligently decide which uniform values should be put
into temporaries, by choosing the most reused values to push to temps
first.
total uniforms in shared programs: 13457 -> 13433 (-0.18%)
uniforms in affected programs: 1524 -> 1500 (-1.57%)
total instructions in shared programs: 40198 -> 40019 (-0.45%)
instructions in affected programs: 6027 -> 5848 (-2.97%)
I noticed this opportunity because with the NIR work, some programs were
happening to make different uniform copy propagation choices that
significantly increased instruction counts.
commit 09c844fcd9c0dc81da4f914e6b88892ea76fe8e9
Author: Eric Anholt <eric at anholt.net>
Date: Thu Feb 19 12:16:25 2015 -0800
vc4: Rename add_uniform() to qir_uniform().
commit 96f6efc561dff8a6a1d57c784239b7cb8ecf1d3e
Author: Eric Anholt <eric at anholt.net>
Date: Thu Feb 19 23:34:37 2015 -0800
vc4: Shut up runtime warnings about new pipe caps.
commit e0137fd6f720e4977466b1760ac02a72c5abceb8
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu Feb 12 01:42:43 2015 +0000
i965/vec4: Add and use byte-MOV instruction for unpack 4x8.
Previously we were using a B/UB source in an Align16 instruction, which
is illegal. It for some reason works on all platforms, except Broadwell.
Cc: "10.5" <mesa-stable at lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86811
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit dada30462b8469509ef16fbc351764d42320b236
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Feb 9 22:54:51 2015 -0800
i965/blorp: Emit MADs.
Low hanging fruit: cuts a couple of instructions.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 30ec53f30ee5813db30777b45dbe456a02c8382e
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Feb 9 21:26:14 2015 -0800
i965/blorp: Optimize clamping tex coords.
Each emit_cond_mov() emits a CMP of its first to arguments using the
specified conditional mod, followed by a predicated MOV of the fifth
argument into the fourth. In all four cases here, it was just
implementing MIN/MAX which we can do in a single SEL instruction.
Also reorder the instructions for a slightly better schedule.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 3b7f683f3bbbd93e417a6f42ec7c609465be49de
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Feb 9 21:11:46 2015 -0800
i965: Use greater-equal cmod to implement maximum.
The docs specifically call out SEL with .l and .ge as the
implementations of MIN and MAX respectively. Among other things, SEL
with these conditional mods are commutative.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit f8b435ae6a27fa2274ff166639b22d0b36d68c49
Author: Matt Turner <mattst88 at gmail.com>
Date: Mon Feb 9 22:21:21 2015 -0800
i965: Don't emit saturates for instructions without destinations.
We were special casing OPCODE_END but no other instructions that have no
destination, like OPCODE_KIL, leading us to emitting MOVs with null
destinations.
total instructions in shared programs: 5705243 -> 5701539 (-0.06%)
instructions in affected programs: 124104 -> 120400 (-2.98%)
helped: 904
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 7f8dd91d166e49d7da98f90d6428dc2705fb96d0
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Feb 10 16:25:47 2015 -0800
i965/fs: Consider MOV.SAT to interfere if it has a source modifier.
The saturate propagation pass recognizes that the second instruction
below does not interfere with an attempt to propagate the saturate
modifier from instruction 3 to 1.
1: add(8) dst0 src0 src1
2: mov.sat(8) dst1 dst0
3: mov.sat(8) dst2 dst0
Unfortunately, we did not consider the case of instruction 2 having a
source modifier on dst0. Take for instance:
1: add(8) dst0 src0 src1
2: mov.sat(8) dst1 -dst0
3: mov.sat(8) dst2 dst0
Consider such an instruction to interfere. Increase instruction counts
in Anomaly 2, which could be a bug fix depending on the values the first
instruction produces.
instructions in affected programs: 53228 -> 53934 (1.33%)
HURT: 360
Cc: <mesa-stable at lists.freedesktop.org>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 871ad3f08bc34e16fdd728e9a4821b9a83e509f0
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Jan 27 22:43:28 2015 -0800
i965/fs: Use fs_inst::overwrites_reg() in saturate propagation.
This is safer and matches the conditional_mod propagation pass.
Cc: <mesa-stable at lists.freedesktop.org>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit bf3389ec49a158e0b66db8e038d801eacabd20f1
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Feb 10 13:38:07 2015 -0800
i965/fs: Add unit tests for saturate propagation pass.
Cc: <mesa-stable at lists.freedesktop.org>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 9acb011a3e73676ada04df01832c930acf51a9a2
Author: Timothy Arceri <t_arceri at yahoo.com.au>
Date: Thu Feb 19 21:32:21 2015 +1100
glsl: Use the without_array predicate
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 5000a5f67b556096b6ba1e9bdac3a6e5cd5a1f68
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Feb 18 03:35:23 2015 -0500
nv50: add PIPELINE_STATISTICS query support, based on nvc0
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Tested-by: Nick Tenney <nick.tenney at gmail.com>
commit f883df74e0f1824607435eb43456263fc48085b8
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Feb 19 20:15:28 2015 -0500
svga: add missing :
Fixes: 924ee3f408 ("gallium: add shader cap for dldexp/dfracexp support")
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit c7002fad9062f54f7dfabe25dc14b7fb217e6adc
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Feb 9 20:18:44 2015 -0800
nir/GCM: Pull unpinned instructions out of blocks while pinning
This lets us be slightly more efficient by not walking the CFG extra times.
Also, it may make it easier to ensure that GVN happens on only unpinned
instructions.
Reviewed-by: Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 8dfe6f672f4f3e226089c6cc8d392fcd39dff5cb
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Feb 9 14:58:12 2015 -0800
nir/GCM: Use pass_flags instead of bitsets for tracking visited/pinned
Reviewed-by: Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 190073c737a2a525be836179ab3a15e1119986fb
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Feb 3 10:11:23 2015 -0800
nir: Add a global code motion (GCM) pass
v2 Jason Ekstrand <jason.ekstrand at intel.com>:
- Use nir_dominance_lca for computing least common anscestors
- Use the block index for comparing dominance tree depths
- Pin things that do partial derivatives
Reviewed-by: Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit a52a4b5223ec007d74e8a0277181929d3ba89c06
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Feb 9 14:41:10 2015 -0800
nir/instr: Change "live" to a more generic "pass_flags" field
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 3d25afc51c1d56fe8c29147825e53ba272780360
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Feb 4 21:22:45 2015 -0800
nir: Make nir_[cf_node/instr]_[prev/next] return null if at the end
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 902b0ccc9a5266955d104dc7652ac00e66081f95
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Feb 4 21:38:28 2015 -0800
nir/from_ssa: Don't try to read an invalid instruction
Right now, the nir_instr_prev function function blindly looks up the
previous element in the exec list and casts it to an instruction even if
it's the tail sentinel. The next commit will change this to return null if
it's the first instruction. Making this change first avoids getting a
segfault between commits. The only reason we never noticed is that, thanks
to the way things are laid out in nir_block, the casted instruction's type
was never parallal_copy.
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 0281fd07865e6ff5c85032b403a073b50659c1ac
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Feb 4 14:01:51 2015 -0800
nir/validate: Validate SSA defs the same way we do for registers
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 34952b56716a0f97812d68cd69540ab6bcc54c82
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Wed Feb 4 13:58:12 2015 -0800
nir/validate: Validate if_uses on registers
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 98ecb25f89c59da2d1bd4b02e12a5e39fac8a9e5
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Feb 3 21:39:56 2015 -0800
nir: Properly clean up CF nodes when we remove them
Previously, if you remved a CF node that still had instructions in it, none
of the use/def information from those instructions would get cleaned up.
Also, we weren't removing if statements from the if_uses of the
corresponding register or SSA def. This commit fixes both of these
problems
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit e025943134ada9dad02926e8191dd1bd2e7fc95e
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Tue Feb 3 21:04:57 2015 -0800
nir: use nir_foreach_ssa_def for indexing ssa defs
This is both simpler and more correct. The old code didn't properly index
load_const instructions.
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 0167c38cacc00eef77d7f83d3929cdbc99378d11
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Feb 6 12:49:08 2015 -0800
nir/from_ssa: Use the nir_block_dominance function instead of our own
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit f481a9425cb8d70bc61c6303268a465f5a05896b
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Feb 6 12:45:43 2015 -0800
nir/dominance: Add a constant-time mechanism for comparing blocks
This is mostly thanks to Connor. The idea is to do a depth-first search
that computes pre and post indices for all the blocks. We can then figure
out if one block dominates another in constant time by two simple
comparison operations.
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit b4c5489c8ac12eb2c9881ba2d8bb745203affb7b
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Feb 6 12:06:04 2015 -0800
nir/dominance: Expose the dominance intersection function
Being able to find the least common anscestor in the dominance tree is a
useful thing that we may want to do in other passes. In particular, we
need it for GCM.
v2: Handle NULL inputs by returning the other block
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 6316c90cc0daa9e9476b00e3c52c51190e782c3f
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Jul 18 00:38:59 2014 -0400
st/mesa: lower DFRACEXP/DLDEXP when they are not supported
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit e4a3f48a45fdbb85e842aa9aeac1ed4e68048f3a
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Jul 25 17:19:57 2014 -0400
st/mesa: disable lowering of dops to dfrac when dround is available
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit e556bfc8ff7abd51eacb5a1810964e3d28123b8c
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Jul 25 17:12:42 2014 -0400
st/mesa: add support for new double opcodes
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit 924ee3f408cd2aef87d868b229e3e0b93ca0e086
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Jul 25 17:48:01 2014 -0400
gallium: add shader cap for dldexp/dfracexp support
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit 899d779cb719f8401dc479a4f5b61dbe418b1a40
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Jul 25 17:03:33 2014 -0400
gallium: add a cap to enable double rounding opcodes
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit 12dedca52303cf32ac06b8e40ff3cf07b58ed0bc
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Jul 25 16:46:42 2014 -0400
gallium: add some more double opcodes to avoid unnecessary lowering
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit 1759689d189b9cb4449eb349c20eccffd6318b9f
Author: Dave Airlie <airlied at redhat.com>
Date: Fri Feb 20 09:14:44 2015 +1000
docs/GL3.txt: softpipe now supports GL_ARB_gpu_shader_fp64
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 8c6a0ebaad7224c40e55645b9c34aefe9b16542e
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Feb 17 10:48:04 2015 +1000
st/mesa: add st fp64 support (v7.1)
This adds support to the state tracker for
ARB_gpu_shader_fp64.
The details are explained in comments
within the code.
v2 : add double to int/unsigned conversion
v3: handle fp64 consts better
v4: use DRSQ
v4.1: add d2b
v4.2: drop DDIV
v5: split out some prep patches.
v5.1: add some comments.
v5.2: more comments
v6: simplify down the double instruction
generation loop.
v7: Merge Ilia's two cleanup patches.
v7.1: minor fixups for Ilia patch + cleanups
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 0178358a2d015a5fc8e3c7dfdd8ec4b1cfc64ea1
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Feb 17 09:44:50 2015 +1000
mesa/st_tgsi_to_glsl: prepare add_constant for fp64
This just moves stuff around a little to make the next patch
cleaner.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 12150a5beedf13eef236be8d59f696970c0d6972
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Feb 17 09:39:05 2015 +1000
st/glsl_to_tgsi: convert dst to an array
This is just prep work for fp64 support where we need
an array of 2 dst values.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit c442d0961e4ec6dcc304d652b637bb60687ce3cb
Author: Dave Airlie <airlied at gmail.com>
Date: Thu Aug 14 18:49:20 2014 +1000
i965: just avoid warnings with fp64
This just fills in some blanks to avoid warnings in the i965 driver.
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 75f6ed617fcdf0b28381c59e4d4a3030678d7faa
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Feb 19 13:36:07 2015 -0800
glsl: Add compute to _mesa_shader_stage_to_string(); use unreachable.
This is basically Ian's review feedback for my patch that added
_mesa_shader_stage_to_abbrev() - it just makes both consistent again.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 5cdfa839c26332dc5fc034966fe107d4779a64d7
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Feb 18 17:52:28 2015 -0800
i965/vec4: Print "VS" or "GS" when compiles fail, not "vec4".
This is now trivial to do right.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit e60318fbcdec139227e427f8ec4d17f07f0d3798
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Feb 18 17:50:42 2015 -0800
i965/vec4: Replace debug_flag with debug_enabled.
backend_visitor now handles this, so we can delete the vec4_visitor
specific code.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit eeacbc1a02ba2d8b9049d1108abcbd2b3dfe2712
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Feb 18 17:45:51 2015 -0800
i965: Make scheduler cycle estimates use the proper stage name.
Previously, the vec4 backend labeled shaders as "vec4" - now it uses the
specific names "VS" and "GS".
The FS backend now correctly prints "VS" for vertex shaders (rather than
"fs"). It also prints "FS" instead of "fs" for fragment shaders;
preserving that behavior didn't seem essential.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 2bd139e18c941e7ea0870ba43314a5c10fd5bb12
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Feb 18 17:43:07 2015 -0800
i965/fs: Un-hardcode DEBUG_WM, "FS", and "fragment".
These code paths can (or will) be used for other shader stages.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 7e35a812643982bef5d90f4998a4f240b2edfd26
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Feb 18 17:38:45 2015 -0800
i965: Create backend_visitor fields for debugging messages.
We introduce three new fields in backend_visitor:
- debug_enabled: whether or not INTEL_DEBUG & DEBUG_<stage flag>
- stage_name: "vertex", "fragment", etc. for use in messages
- stage_abbrev: "VS", "FS", etc. for use in messages
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 7c891e8ddd41a77ccdc804ce938f2a1ed46e97e8
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Feb 18 17:31:29 2015 -0800
i965: Add a function to translate MESA_SHADER_* into DEBUG_* enums.
When compiling, we have a gl_shader_stage (MESA_SHADER_*) enum, and want
to know whether debugging is enabled for that stage. This allows us to
easily translate it into the corresponding debug flag.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 7555d1bafb089bc5130f86602a23725e184c490e
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Feb 18 17:35:41 2015 -0800
glsl: Create a _mesa_shader_stage_to_abbrev() function.
This is similar to _mesa_shader_stage_to_string(), but returns "VS"
instead of "vertex".
v2: Use unreachable() and add MESA_SHADER_COMPUTE (requested by Ian).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 231267bf011e1fa6edb52ffad27fcbca8e0e28e1
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Jan 31 04:31:16 2015 -0800
i965/fs: Use VARYING_SLOT checks rather than strcmp().
Comparing the location field is equivalent and more efficient.
We'll also need this when we start using NIR for ARB programs, as our
NIR converter will set the location field correctly, but probably won't
use the GLSL names for these concepts.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit a07cd42f1e4739000adbbcf5613ba163cf73b666
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Feb 4 01:40:09 2015 -0800
i965/fs: Remove type parameter from emit_vs_system_value().
Every VS system value has type D. We can always add this back if that
changes, but for now, it's extra typing.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
commit 2e9f4eadfbe8e1eae657c268cb31515a872eceb4
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Feb 9 16:53:10 2015 +1000
glsl: add lowering for double divide to rcp/mul
It looks like no hw does div anyways, so we should just
lower at the GLSL level.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 0e82817247810d2aff29d8e3e9c633520924fd4a
Author: Dave Airlie <airlied at gmail.com>
Date: Thu Aug 14 18:40:41 2014 +1000
softpipe/tgsi: expose doubles for softpipe.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit fa43e0443e206740e219d45abefee65bdb2c3ecb
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Aug 27 09:56:14 2014 +1000
tgsi: add support for flt64 constants
These act like flt32 except they take up two slots, and you
can only add 2 x flt64 constants in one slot.
The main reason they are different is we don't want to match half a flt64
constants against a flt32 constant in the matching code, we need to make
sure we treat both parts of the flt64 as an single structure.
Cleaned up printing/parsing by Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 3cd1338534374c8ed13651548dcbf3949857dbcd
Author: Dave Airlie <airlied at gmail.com>
Date: Thu Aug 14 18:38:51 2014 +1000
gallium: add double opcodes and TGSI execution (v4.2)
This patch adds support for a set of double opcodes
to TGSI. It is an update of work done originally
by Michal Krol on the gallium-double-opcodes branch.
The opcodes have a hint where they came from in the
header file.
v2: add unsigned/int <-> double
v2.1: update docs.
v3: add DRSQ (Glenn), fix review comments (Glenn).
v4: drop DDIV
v4.1: cleanups, fix some docs bugs, (Ilia)
rework store_dest and fetch_source fns. (Ilia)
4.2: fixup float comparisons (Ilia)
This is based on code by Michael Krol <michal at vmware.com>
Roland and Glenn also reviewed earlier versions.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 14b9bf630c23ad060ea8bd12da2f7b18cb4f4101
Author: Brian Paul <brianp at vmware.com>
Date: Thu Feb 19 09:29:18 2015 -0700
gallium/util: indentation fix
commit 21c57a697f170872ad8ae19bc2fe7a27082f51a9
Author: Brian Paul <brianp at vmware.com>
Date: Thu Feb 19 09:26:51 2015 -0700
st/mesa: add GSL_TYPE_DOUBLE, new ir_unop_* switch cases
To silence compiler warnings about unhandled switch cases.
v2: move GSL_TYPE_DOUBLE case to the "Invalid type in type_size" section,
per Ilia.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 2f5597787c83aab069e53b3c7cad8acf8c91626c
Author: Brian Paul <brianp at vmware.com>
Date: Thu Feb 19 09:25:42 2015 -0700
nir: add missing GLSL_TYPE_DOUBLE case in type_size()
To silence compiler warning about unhandled switch case.
v2: move GLSL_TYPE_DOUBLE to the "not reached" section, per Ilia.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 62a8883f32f8a4c8c7d85390d4b17986e4018edf
Author: Brian Paul <brianp at vmware.com>
Date: Wed Feb 18 11:16:55 2015 -0700
st/mesa: fix sampler view reference counting bug in glDraw/CopyPixels
Use pipe_sampler_view_reference() instead of ordinary assignment.
Also add a new sanity check assertion.
Fixes piglit gl-1.0-drawpixels-color-index test crash. But note
that the test still fails.
Cc: "10.4, 10.5" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 89c96afe3c0acf8f2fccaf02da02945afe8ba5f3
Author: Brian Paul <brianp at vmware.com>
Date: Mon Feb 16 11:23:06 2015 -0700
swrast: fix multiple color buffer writing
If a fragment program wrote to more than one color buffer, the
first fragment color got replicated to all dest buffers. This
fixes 5 piglit FBO tests, including fbo-drawbuffers-arbfp.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=45348
Cc: "10.4, 10.5" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit fbac86ad2a735776a483cf1bb3827c4459f82e65
Author: Brian Paul <brianp at vmware.com>
Date: Mon Feb 16 11:12:40 2015 -0700
mesa: remove unused _math_trans_4chan()
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
commit 5c1aac17adffeef9bb6171d83cc7ddd94c61c5f2
Author: Lucas Stach <l.stach at pengutronix.de>
Date: Thu Feb 19 14:52:49 2015 +0100
install-lib-links: don't depend on .libs directory
This snippet can be included in Makefiles that may, depending on the
project configuration, not actually build any installable libraries.
In that case we don't have anything to depend on and this part of
the makefile may be executed before the .libs directory is created,
so do not depend on it being there.
Cc: "10.3 10.4 10.5" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Signed-off-by: Lucas Stach <l.stach at pengutronix.de>
commit 6c34fd20beb74e009778870a8e30811b393f745c
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Feb 11 18:15:44 2015 +0200
i965/vec4: Calculate register allocation q values manually.
This fixes a regression in the running time of Piglit introduced by
commit 78e9043475d4bed8b50f7e413963c960fa0935bb, which increased the
number of register allocation classes set up by the VEC4 back-end
from 2 to 16. The algorithm used by ra_set_finalize() to calculate
them is unnecessarily expensive, do it manually like the FS back-end
does.
Reported-by: Mark Janes <mark.a.janes at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 35a77a148f8b7ef03fe3b31d63719e0bfdf4b783
Author: Francisco Jerez <currojerez at riseup.net>
Date: Fri Jan 30 17:50:35 2015 +0200
i965: Don't compact instructions with unmapped bits.
Some instruction bits don't have a mapping defined to any compacted
instruction field. If they're ever set and we end up compacting the
instruction they will be forced to zero. Avoid using compaction in such
cases.
v2: Align multiple lines of an expression to the same column. Change
conditional compaction of 3-source instructions to an
assertion. (Matt)
v3: The 3-source instruction bit 105 is part of SourceIndex on CHV.
Add assertion that reserved bit 7 is not set. (Matt)
Document overlap with UIP and 64-bit immediate fields.
v4: Make some more unmapped bit checks assertions. (Matt)
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 6c07279e5ad67d925b99ff9e0345dcaeffc37283
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Feb 4 18:24:47 2015 +0200
i965: Handle F16TO32/F32TO16 with dword src/dst consistently on both back-ends.
Due to the way it's implemented in hardware, the F16TO32/F32TO16
instructions require the source/destination register to be of some
16-bit type in Align1 mode, while they require it to be some 32-bit
type in Align16 mode (and as an undocumented feature the high 16 bits
of the destination register are zeroed out in the case of the F32TO16
instruction on Gen7). Make their behaviour consistent so you can
specify a 32 bit register type as source or destination and get
predictable results in the most significant bits no matter what access
mode is being used.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 437d401e6398eebc2ecd061650d16d1ad2d947f1
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Feb 4 18:08:47 2015 +0200
i965/gen8: Fix F32TO16 in vec4 mode if the source and destination registers alias.
We cannot zero out the destination register if it overlaps with the
source. Use an Align1 instruction instead to zero out the high 16
bits after the conversion to half float.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 509f58740c721e1a8cc8ec4e556af3ed993f927e
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Feb 4 17:58:49 2015 +0200
i965/fs: Replace ud_reg_to_w() with a more general helper function.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 63d6d09a3b3790c5ec00f2cbc06f58c82ae40b0c
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue Feb 3 20:34:17 2015 +0200
i965/vec4: Don't attempt to reduce swizzles of send from GRF instructions.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit bda7698fce21daa1b94bc79c0a0ed3da8d385997
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue Feb 3 22:48:27 2015 +0200
i965/vec4: Fix constant propagation across different types.
If the source type differs from the original type of the constant we
need to bit-cast it before propagating, otherwise the original type
information will be lost. If the constant was a vector float there
isn't much we can do, because the result of bit-casting the component
values of a vector float cannot itself be represented as an immediate.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 187ace73a93d87122a977e4afade237be159ab04
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Tue Nov 25 16:36:53 2014 +0100
glsl: A shader cannot redefine or overload built-in functions in GLSL ES 3.00
Create a new search function to look for matching built-in functions by name
and use it for built-in function redefinition or overload in GLSL ES 3.00.
GLSL ES 3.0 spec, chapter 6.1 "Function Definitions", page 71
"A shader cannot redefine or overload built-in functions."
While in GLSL ES 1.0 specification, chapter 8 "Built-in Functions"
"User code can overload the built-in functions but cannot redefine them."
So this check is specific to GLSL ES 3.00.
This patch fixes the following dEQP tests:
dEQP-GLES3.functional.shaders.functions.invalid.overload_builtin_function_vertex
dEQP-GLES3.functional.shaders.functions.invalid.overload_builtin_function_fragment
dEQP-GLES3.functional.shaders.functions.invalid.redefine_builtin_function_vertex
dEQP-GLES3.functional.shaders.functions.invalid.redefine_builtin_function_fragment
No piglit regressions.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 19252fee46b835cb4f6b1cce18d7737d62b64a2e
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Mon Dec 15 11:30:21 2014 +0100
mesa: Adds check for integer internal format and num samples in glRenderbufferStorageMultisample
Per GLES3 specification, section 4.4 Framebuffer objects page 198, "If
internalformat is a signed or unsigned integer format and samples is greater
than zero, then the error INVALID_OPERATION is generated.".
Fixes 1 dEQP test:
* dEQP-GLES3.functional.negative_api.buffer.renderbuffer_storage_multisample
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit dbc160a3f8a6be26110656a15c0d6048391f4fc7
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Tue Dec 16 09:15:07 2014 +0100
mesa: Returns correct error values from gl(Get)SamplerParameter*() on GL-ES 3.0+
'3.8.2 Sampler Objects' section of the GL-ES 3.0 specification states:
"An INVALID_OPERATION error is generated if sampler is not the name
of a sampler object previously returned from a call to GenSamplers."
In desktop GL, an GL_INVALID_VALUE is returned instead.
Fixes 6 dEQP failing tests:
* dEQP-GLES3.functional.negative_api.shader.get_sampler_parameteriv
* dEQP-GLES3.functional.negative_api.shader.get_sampler_parameterfv
* dEQP-GLES3.functional.negative_api.shader.sampler_parameteri
* dEQP-GLES3.functional.negative_api.shader.sampler_parameteriv
* dEQP-GLES3.functional.negative_api.shader.sampler_parameterf
* dEQP-GLES3.functional.negative_api.shader.sampler_parameterfv
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit e8e22cf65fc8b9b0c0355540985b073a03c69a51
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Feb 19 01:44:44 2015 -0500
glsl: remove bogus 'd' constant qualifiers
0.0 is a double anyways. Apparently my version of gcc was happy with
0.0d as well, but this is not true of all compilers.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89218
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 0cade4ea2b114238206055eb256d0eb000bdfac9
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Feb 19 01:38:58 2015 -0500
st/mesa: don't die for ETC2 formats when no driver support
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 2a135c470e3db165a6417ffcccab4a9f4500f526
Author: Eric Anholt <eric at anholt.net>
Date: Mon Nov 10 11:16:30 2014 -0800
nir: Add an ALU op builder kind of like ir_builder.h
v2: Rebase on the nir_opcodes.h python code generation support.
v3: Use SSA values, and set an appropriate writemask on dot products.
v4: Make the arguments be SSA references as well. This lets you stack up
expressions in the arguments of other expressions, at the cost of
having to insert a fmov/imov if you want to swizzle. Also, add
the generated file to NIR_GENERATED_FILES.
v5: Use more pythonish style for iterating the list.
v6: Infer the size of the dest from the size of the srcs, and auto-swizzle
a single small src out to the appropriate size.
v7: Add little helpers for initializing the struct, add a typedef for the
struct like other nir types have.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org> (v6)
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com> (v7)
commit de798bb93708cebdedecefebdc96a82d9481f2aa
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Feb 18 14:53:26 2015 -0500
docs: mark ARB_gpu_shader_fp64 as done in core
No driver support... yet. But core is ready.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit e790a3c9105a54455eb634dbaffab8060805044c
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Feb 8 03:42:51 2015 -0500
glsl/tests: add DOUBLE types
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit 2e7e7b8af6cb9055204e196db9902ec9991cd538
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Jul 17 17:59:32 2014 -0400
glsl: add a lowering pass for frexp/ldexp with double arguments
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit fffbf371242b07ff157b88792ab65d82c785de78
Author: Dave Airlie <airlied at gmail.com>
Date: Thu Aug 14 20:21:46 2014 +1000
glsl: lower double optional passes (v2)
These lowering passes are optional for the backend to request, currently
the TGSI softpipe backend most likely the r600g backend would want to use
these passes as is. They aim to hit the gallium opcodes from the standard
rounding/truncation functions.
v2: also lower floor in mod_to_floor
Signed-off-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit e6354a2850d6735b857298ad206a97db0de47fd6
Author: Dave Airlie <airlied at gmail.com>
Date: Thu Aug 14 18:48:57 2014 +1000
glsl: implement double builtin functions
This implements the bulk of the builtin functions for fp64 support.
Signed-off-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 2e626318e0c3ac08b8f9a6ef53325e05177b131b
Author: Dave Airlie <airlied at gmail.com>
Date: Thu Aug 14 18:44:35 2014 +1000
glsl/lower_instructions: add double lowering passes
This lowers double dot product and lrp to fma.
Signed-off-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 8be5ee23de774a1101b808ff081cc3316d358933
Author: Dave Airlie <airlied at gmail.com>
Date: Thu Aug 14 18:44:50 2014 +1000
glsl: enable/disable certain lowering passes for doubles
We want to restrict some lowering passes to floats only,
and enable other for doubles.
Signed-off-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 3bbaf719940447045b4f1faae77953e15908cfec
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Mon Aug 11 12:03:54 2014 +0300
glsl: validate output types for shader stages
Patch fixes Piglit test:
arb_gpu_shader_fp64/preprocessor/fs-output-double.frag
and adds additional validation for shader outputs.
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 94f9ed701abe33b854f22577adffc4c7ad45cf18
Author: Dave Airlie <airlied at gmail.com>
Date: Thu Aug 14 18:48:09 2014 +1000
glsl: add double support to lower_mat_op_to_vec
Signed-off-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 37730721696a0644242af1a96112381052501b18
Author: Dave Airlie <airlied at gmail.com>
Date: Thu Feb 5 12:11:58 2015 +0200
glsl: Linking support for doubles
Signed-off-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 7aa3ffe2c5411d3cb2eee9f03ad1a92cb3629527
Author: Dave Airlie <airlied at gmail.com>
Date: Thu Feb 5 12:10:26 2015 +0200
glsl: Support double loop control
Signed-off-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 53383476d1ba2d863ac58087fd320a45d5c7a9a5
Author: Dave Airlie <airlied at gmail.com>
Date: Thu Feb 5 12:09:04 2015 +0200
glsl: Support double inouts
Signed-off-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit a10275f7620722f91a8c6811d2ede16f3a274b66
Author: Dave Airlie <airlied at gmail.com>
Date: Thu Feb 5 12:07:34 2015 +0200
glsl/lexer: Support double floats
Signed-off-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 942574bb244a77be61896d57f79dad7f5a086db8
Author: Dave Airlie <airlied at gmail.com>
Date: Thu Feb 5 12:06:20 2015 +0200
glsl/parser: Support double floats
Signed-off-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit ba3bab264d039926be391dcd6020dbf1c6313c41
Author: Dave Airlie <airlied at gmail.com>
Date: Thu Feb 5 12:04:58 2015 +0200
glsl/ast: Support double floats
Signed-off-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 24626444c3a21b984d023feba1843776c7f5c7ea
Author: Dave Airlie <airlied at gmail.com>
Date: Thu Feb 5 12:00:11 2015 +0200
glsl: Add ubo lowering support for doubles
Signed-off-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 8609b5371641b303fac0a928376b344dbd7096fa
Author: Dave Airlie <airlied at gmail.com>
Date: Thu Feb 5 11:58:05 2015 +0200
glsl: Add support doubles in optimization passes
Signed-off-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 41e9adfd83a35d3c147768b80b6b4c0b10c3a379
Author: Dave Airlie <airlied at gmail.com>
Date: Thu Feb 5 11:54:39 2015 +0200
glsl/ir: Add builder support for functions with double floats
Signed-off-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit eeae6251be7bddf3040f14a2782ee8d5d17f7914
Author: Dave Airlie <airlied at gmail.com>
Date: Thu Feb 5 11:53:10 2015 +0200
glsl/ir: Add builtin constant function support for doubles
Signed-off-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 753ba6b9995ad6a2d2e43faa7df8033dcd003f87
Author: Dave Airlie <airlied at gmail.com>
Date: Thu Feb 5 12:53:26 2015 +0200
glsl/ir: Add cloning support for doubles
Signed-off-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 57c6c3d3bdc36a59937bdb8ca686e0e416ff11d2
Author: Dave Airlie <airlied at gmail.com>
Date: Thu Feb 5 12:52:19 2015 +0200
glsl/ir: Add printing support for doubles
Signed-off-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 5a69bdb599ee4eb422cba6a47517c376e9dc5faf
Author: Dave Airlie <airlied at gmail.com>
Date: Thu Feb 5 11:50:43 2015 +0200
glsl/ir: Add builtin function support for doubles
v2: add d2b, more ir_constant stuff (Ilia)
Signed-off-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 53bf7c8fd2e11a6c64d6ff3a98b56d64d2242505
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Tue Feb 10 03:02:09 2015 -0500
glsl: fix uniform linking logic in the presence of structs
Add a enter/leave record callback so that the offset may be aligned to
the proper value. Otherwise only leaf fields are called, and the first
field needs to be aligned to the outer struct's base alignment while the
last field needs to be aligned to the inner struct's base alignment.
This removes most usage of the last field/record type values passed into
visit_field.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit 1ec715ce8b126da3cfe3b383054f9a176960c218
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Feb 13 22:03:47 2015 -0500
glsl: teach std140_base_alignment about samplers
These functions are about to be used more aggressively for determining
uniform layout. Samplers may be inside of structs, and it's easier to
reuse the existing base alignment logic.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Dave Airlie <airlied at redhat.com>
commit fe23bb85baa22dc06638c3ea8cbe5e6ee17bfa4a
Author: Dave Airlie <airlied at gmail.com>
Date: Thu Feb 5 11:44:02 2015 +0200
glsl: Uniform linking support for doubles
Signed-off-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 3af8db94cd315314ae8db096ba67f6655a005c23
Author: Dave Airlie <airlied at gmail.com>
Date: Thu Feb 5 11:38:44 2015 +0200
glsl: Add double builtin type generation
Signed-off-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 277f4d75a74b7b3e3af295e102be8bb5343d85dc
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Jun 11 13:36:12 2014 +1000
glsl: add ARB_gpu_shader_fp64 to the glsl extensions. (v2)
v2: add define bit (Tapani Pälli)
Patch makes following Piglit tests pass:
arb_gpu_shader_fp64/preprocessor/define.vert
arb_gpu_shader_fp64/preprocessor/define.frag
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 5cc486b4e3a169fd2d82c463ca793e48343daef3
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Jun 11 13:28:32 2014 +1000
mesa: add double uniform support. (v5)
This adds support for the new uniform interfaces
from ARB_gpu_shader_fp64.
v2:
support ARB_separate_shader_objects ProgramUniform*d* (Ian)
don't allow boolean uniforms to be updated (issue 15) (Ian)
v3: fix size_mul
v4: Teach uniform update to take into account double precision (Topi)
v5: add transpose for double case (Ilia)
Signed-off-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit bf257d2c909681139f6880555d896745289152e7
Author: Dave Airlie <airlied at redhat.com>
Date: Sat Feb 7 19:24:48 2015 -0500
glsl: Add double builtin type
This causes a lot of warnings about unchecked type in
switch statements - fix them later.
Signed-off-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 6227af26908251601b6a8ba6297ef6ce4fb34786
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Jun 11 13:27:22 2014 +1000
mesa: add ARB_gpu_shader_fp64 extension info (v2)
This just adds the entries to extensions.c and mtypes.h
v2: use core profile only (Ian)
Signed-off-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 3c915e5c1662f2d9d32bec04033967a5cceeca8f
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Jun 11 13:17:36 2014 +1000
glapi: add ARB_gpu_shader_fp64 (v2)
Just add the xml file covering this extension,
and dummy interface files in mesa, and fix up
sanity tests.
v2:
Enable ProgramUniform*d* from ARB_separate_shader_objects (Ian)
use 40 instead of 43 for dispatch_sanity.cpp (Chris)
uncomment PU sanity tests.
Signed-off-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 069dab75765a7ea8b995eea80167ffb34cdb0034
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Feb 18 22:36:13 2015 -0500
freedreno: add missing PIPE_CAP_RESOURCE_FROM_USER_MEMORY to switch
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 92fc8f04d63bae969d47d79fde2c9d48f5e90488
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Tue Dec 2 00:32:57 2014 -0500
freedreno/a3xx: add ARB_instanced_arrays support
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit f6b2e8af7425c67f8def9dfba92f6f0ad9585b40
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Oct 1 23:13:22 2014 -0400
freedreno/a3xx: add support for vertexid and instanceid sysvals
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 2c6e3d822ba6f03fe208da3c6228d796895b3008
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Oct 22 00:42:04 2014 -0400
freedreno: pass number of instances to draw
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit e4ddfeea65725a44446f4febe8718d7e378f50fe
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Feb 16 02:28:50 2015 -0500
freedreno/a3xx: add ETC2 decoding support
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 33edda7d975f2cbf7ba86ba0f300dcadf087fb9b
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Feb 16 02:27:37 2015 -0500
st/mesa: pass etc2 textures to driver if supported
If the driver actually supports ETC2, don't decode it in software.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit 845b9e4294b7b89a33d77ef6713543f96eba0686
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Feb 18 22:23:12 2015 -0500
llvmpipe,softpipe: only support ETC1, not the upcoming ETC2
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 0821efcb333ed2af639561f0ae77220ed4710559
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Feb 16 02:25:52 2015 -0500
gallium: add ETC2 format support
No actual decoding is added, similar faking mechanism to bptc.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit d622afdbc3999a4675cf0c343d5ee7863736c40a
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Mon Feb 16 01:33:11 2015 -0500
freedreno/a3xx: add hardware ETC1 support
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
commit 935ee6b652a97c1db08d999aa48eba0574e0b23e
Author: Eric Anholt <eric at anholt.net>
Date: Wed Feb 11 14:40:47 2015 -0800
gallium/dri: Shut up a compiler warning.
The compiler doesn't see that buffers is set in the !image case and used
in the !image case.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 6eadde51bba26bc57da7b26cbb40d783259d4a5f
Author: Eric Anholt <eric at anholt.net>
Date: Fri Jan 30 14:10:58 2015 -0800
nir: Recognize and reduce duplicated fsats.
No effect on vc4 shader-db.
v2: Rebase to master (no TGSI->NIR present)
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org> (v1)
commit 1907a3a7ee4d756b12b6fef32a6e5ea7656436d1
Author: Eric Anholt <eric at anholt.net>
Date: Fri Jan 30 13:53:39 2015 -0800
nir: Add a flag for lowering fsat.
vc4 cse/algebraic-disabled stats:
total instructions in shared programs: 44356 -> 44354 (-0.00%)
instructions in affected programs: 55 -> 53 (-3.64%)
v2: Rebase to master (no TGSI->NIR present)
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org> (v1)
commit e5ecf8e4272522e1950d1d4318df19377bf49ae1
Author: Eric Anholt <eric at anholt.net>
Date: Fri Jan 30 13:49:48 2015 -0800
nir: Add a flag for lowering ffma.
vc4 cse/algebraic-disabled stats:
total uniforms in shared programs: 13966 -> 13791 (-1.25%)
uniforms in affected programs: 435 -> 260 (-40.23%)
total instructions in shared programs: 44732 -> 44356 (-0.84%)
instructions in affected programs: 9599 -> 9223 (-3.92%)
v2: Rebase to master (no TGSI->NIR present)
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org> (v1)
commit 42a8ace66e539957b31ea96fe9a2aaacdb90f30e
Author: Eric Anholt <eric at anholt.net>
Date: Wed Jan 28 10:52:53 2015 -0800
nir: Add a flag for lowering fneg/ineg.
vc4 cse/algebraic-disabled stats:
total instructions in shared programs: 44911 -> 44732 (-0.40%)
instructions in affected programs: 11371 -> 11192 (-1.57%)
v2: Fix broken iabs(isub(0, a)) transformation.
v3: Rebase to master (no TGSI->NIR present)
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org> (v1)
commit cb95a228e81a963d77f50058c7406db0ad3bccac
Author: Eric Anholt <eric at anholt.net>
Date: Wed Jan 28 10:39:29 2015 -0800
nir: Add a flag for lowering fsqrt(x) to frcp(frsqrt(x)).
vc4 cse/algebraic-disabled stats:
total uniforms in shared programs: 13972 -> 13966 (-0.04%)
uniforms in affected programs: 408 -> 402 (-1.47%)
total instructions in shared programs: 44973 -> 44911 (-0.14%)
instructions in affected programs: 1551 -> 1489 (-4.00%)
v2: Rebase to master (no TGSI->NIR present)
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org> (v1)
commit ccf14bca4b892a0dffa1d8c244bfabe384d70f98
Author: Eric Anholt <eric at anholt.net>
Date: Wed Jan 28 10:32:57 2015 -0800
nir: Add lowering of POW instructions if the lower flag is set.
This could be done in a separate pass like we do in GLSL IR, but it seems
to me like having the definitions of the transformations in the two
directions next to each other makes a lot of sense.
v2: Reorder the comment about the transformation.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 8e9dbfff17f29533ad03f3afd25ada8cb6bf1e2b
Author: Eric Anholt <eric at anholt.net>
Date: Tue Jan 27 16:22:54 2015 -0800
nir: Conditionalize the POW reconstruction on shader compiler options.
Mesa has a shader compiler struct flagging whether GLSL IR's opt_algebraic
and other passes should try and generate certain types of opcodes or
patterns. Extend that to NIR by defining our own struct, which is
automatically generated from the Mesa struct in glsl_to_nir and provided
directly by the driver in TGSI-to-NIR.
v2: Split out the previous two prep patches.
v3: Rebase to master (no TGSI->NIR present)
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org> (v2)
commit 955a6bb57d6ca5a679021bcfe43c7cae1863f299
Author: Eric Anholt <eric at anholt.net>
Date: Mon Feb 2 16:20:06 2015 -0800
nir: Add an optional expression controlling nir_algebraic xforms.
This will be used so that we can customize the transforms for the target
GPU, so we don't un-lower expressions that had already been lowered (or
introduce new lowering transformations that not all GPUs want)
v2: Drop the complication of having the condition->index dictionary, since
we don't actually expect there to be many different conditions (change
by Kenneth).
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit f90bb54734bf03be6c736812226e3f65f2e11519
Author: Eric Anholt <eric at anholt.net>
Date: Mon Feb 2 16:13:49 2015 -0800
nir: Add a nir_shader_compiler_options struct pointed to by the shaders.
This will be used to give the optimization passes a chance to customize
behavior for the particular target device.
v2: Rebase to master (no TGSI->NIR present)
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org> (v1)
commit 4a95be9772a255776309f23180519a4a8560f2dd
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Tue Feb 17 09:57:35 2015 -0800
i965/simd8vs: Fix SIMD8 atomics (read-only)
An update for d9cd982d556be560af3bcbcdaf62b6b93eb934a5.
A similar change was needed for CS to allow the piglit test
tests/spec/arb_compute_shader/execution/simple-barrier-atomics.shader_test
to pass.
The previous change (d9cd982d) should fix cases that write atomics,
such as atomicCounterIncrement, and this change will fix cases than
only read atomics, such as atomicCounter.
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
commit b0e26173b26b60bb3892de9e4b764f608e0e13c7
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Wed Feb 18 13:26:29 2015 -0700
ilo: fix PCB alloc asserts on Gen7.5 GT3
GT3 has two slices and all limits are doubled.
commit 68573f57eeba1229a7963440428c3229c7ad7ff6
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Tue Feb 17 16:10:10 2015 -0700
ilo: fix compiler warnings
Fix -Wmaybe-uninitialized warnings. The change to
ilo_blit_resolve_slices_for_hiz() is a potential bug fix.
commit b290330e3b78405424a907cf6e82cef531c71c50
Author: Adam Jackson <ajax at redhat.com>
Date: Wed Jan 28 16:28:12 2015 -0500
i915: For the love of all that is holy, stop saying "IGD"
a001 and a011 are pineview chips. Say so.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Signed-off-by: Adam Jackson <ajax at redhat.com>
commit 8a71fd8d49c6a086f9b7697bca3b1f3ae035121a
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Feb 16 19:11:33 2015 +0000
auxiliary/vl: honour the DRI2PROTO_CFLAGS
Otherwise for non-default installations the build will fail to find the
headers and error out.
Cc: "10.5" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit dd7b6670a29ff3ed48ba44a9fecd1890363d914f
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Mon Feb 16 18:22:16 2015 +0000
auxiliary/vl: Build vl_winsys_dri.c only when needed.
With commit c39dbfdd0f7(auxiliary/vl: bring back the VL code for the dri
targets) we did not fully consider users of dri-swrast alone. Thus we
ended up trying to compile the dri2 specific code on platform which lack
it - Cygwin for example.
Cc: "10.5" <mesa-stable at lists.freedesktop.org>
Reported-by: Jon TURNEY <jon.turney at dronecode.org.uk>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Jon TURNEY <jon.turney at dronecode.org.uk>
commit 3018c4a56aab2ac1d8d5b228e6cbf13eea68b790
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Feb 12 15:27:28 2015 +0000
automake: Use AM_DISTCHECK_CONFIGURE_FLAGS
Currently we use DISTCHECK_CONFIGURE_FLAGS, which is reserved for
the user. As with other variables, one should use the AM_ variable
within the makefile.
Cc: "10.5" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit b0eada1707f0b7b4346663b98a7fb1a803580327
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Thu Jan 22 17:35:40 2015 +0000
glx: do not leak the dri2 extension information
The XExtensionInfo is allocated dynamically (if the pointer is NULL)
in the XEXT_GENERATE_FIND_DISPLAY macro. On the other hand the
macro XEXT_GENERATE_CLOSE_DISPLAY does not check/free the memory.
Follow the example set by dri1 and appledri, and use a static variable.
Spotted while hunting "still reachable" leaks in Waffle.
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
commit 4db985a5fa9ea985616a726b1770727309502d81
Author: Michel Dänzer <michel.daenzer at amd.com>
Date: Tue Feb 17 17:03:35 2015 +0900
Revert "radeon/llvm: enable unsafe math for graphics shaders"
This reverts commit 0e9cdedd2e3943bdb7f3543a3508b883b167e427.
It caused the grass to disappear in The Talos Principle.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89069
Cc: "10.5 10.4" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit b7a85bee833b47f48445abb0a6523ed7338bb995
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Wed Feb 11 00:36:47 2015 -0500
st/mesa: add ARB_pipeline_statistics_query support
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit e206785b5790c97743b7d3929563c21ad87aa765
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Tue Dec 2 18:33:12 2014 -0800
i965: implement ARB_pipeline_statistics_query
NOTE: The implementation was initially one patch, this. All the history is kept
here, even though all the core mesa changes were moved to the parent of this
patch.
This patch implements ARB_pipeline_statistics_query. This addition to GL does
not add a new API. Instead, it adds new tokens to the existing query APIs. The
work to hook up the new tokens is trivial due to it's similarity to the previous
work done for the query APIs. I've implemented all the new tokens to some
degree, but have stubbed out the untested ones at the entry point for Begin().
Doing this should allow the remainder of the code to be left in.
The new tokens give GL clients a way to obtain stats about the GL pipeline.
Generally, you get the number of things going in, invocations, and number of
things coming out, primitives, of the various stages. There are two immediate
uses for this, performance information, and debugging various types of
misrendering. I doubt one can use these for debugging very complex applications,
but for piglit tests, it should be quite useful.
Tessellation shaders, and compute shaders are not addressed in this patch
because there is no upstream implementation. I've implemented how I believe
tessellation shader stats will work for Intel hardware (though there is a bit of
ambiguity). Compute shaders are a bit more interesting though, and I don't yet
know what we'll do there.
For the lazy, here is a link to the relevant part of the spec:
https://www.opengl.org/registry/specs/ARB/pipeline_statistics_query.txt
Running the piglit tests
http://lists.freedesktop.org/archives/piglit/2014-November/013321.html
(http://cgit.freedesktop.org/~bwidawsk/piglit/log/?h=pipe_stats)
yield the following results:
> piglit-run.py -t stats tests/all.py output/pipeline_stats
> [5/5] pass: 5 Running Test(s): 5
v2:
- Don't allow pipeline_stats to be per stream (Ilia). This may (not sure) be
needed for AMD_transform_feedback4, which we do not support.
> If AMD_transform_feedback4 is supported then GEOMETRY_SHADER_PRIMITIVES_-
> EMITTED_ARB counts primitives emitted to any of the vertex streams for
> which STREAM_RASTERIZATION_AMD is enabled.
- Remove comment from GL3.txt because it is only used for extensions that are
part of required versions (Ilia)
- Move the new tokens to a new XML doc instead of using the main GL4x.xml (Ilia)
- Add a fallthrough comment (Ilia)
- Only divide PS invocations by 4 on HSW+ (Ben)
v3:
- Add ARB_pipeline_statistics_query to relnotes.html
- Add ARB_pipeline_statistics_query.xml to the Makefile.am, and master XML (Ilia)
- Correct extension number (Ilia)
- Add link to xml in the main GL API xml (Ilia)
- remove special GS case from gen6_end_query (Ian)
- Make lookup table static so gcc doesn't initialized it on every call (Ian)
- Use if (_mesa_has_geometry_shaders(ctx)) instead of explicit checks (Ian)
- Core mesa parts moved into a prep patch (Ilia)
v4:
- Change to 10.6 relnotes since we missed 10.5 window
- Moved compute shader stuff into the switch statement (Jordan)
- Jordan: Add compute shader support
v5:
- Fixed relnote style (Ilia)
v6:
- Rebased on master which beat me to adding the first relnotes - essentially
this undoes v5 (which had a typo anyway)
- Some code style fixes (Ken)
- Remove some excess comments (Ken)
- Unify tessellation failure style - unreachable (Ken)
- Fix workaround comment for PS invocations (Ken)
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 86ffc36d3c971417e1c38b29c3b7863368b5c6d9
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Fri Jan 2 12:13:53 2015 -0800
mesa: Add support for the ARB_pipeline_statistics_query extension
This was originally part of a single patch which added the extension, and
implemented it for i965 classic. For information about the evolution of the
patch, please see the subsequent commit.
One difference here as compared to the original mega patch is this does build
support for the compute shader query. Since it cannot be tested on any platform,
it will always return NULL for now. Jordan has already written a patch to
address this, and when that patch lands, this logic can be modified.
v2: Fix typo in subject (Brian Paul)
Add checks for desktop gl (Ilia)
Fail for any callers for now (Ilia)
Update QueryCounterBits for new tokens (Ilia)
Jordan: Use _mesa_has_compute_shaders
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
v3: Rebased on patch which adds the proper information to unstub tessellation
shaders.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 2cd2831500443dc9ff4ea0bf645713c1f9da57d0
Author: Jordan Justen <jordan.l.justen at intel.com>
Date: Sat Feb 14 12:53:42 2015 -0800
mesa: Add _mesa_has_compute_shaders
v2 (Ben): Change GLboolean to bool as requested by Ian
Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
commit 599cbe5508ccb246fe06b64116c84ce976165fed
Author: Fabian Bieler <fabianbieler at fastmail.fm>
Date: Sun Sep 21 13:40:42 2014 +1200
mesa: Add ARB_tessellation_shader to extension table.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit d523fefa756eef9c7a2c0d91cf4c2df10b89ed2a
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Jan 15 01:41:14 2015 -0800
i965: Prefer Meta over the BLT for BlitFramebuffer.
There's some debate about whether we should use Meta or BLORP,
but either should run circles around the BLT engine.
In particular, this means that Gen8+ will use the 3D engine for blits,
like we do on Gen6-7.
Improves performance in "copypixrate -blit -back" (from Mesa demos)
by 232.037% +/- 3.15795% (n=10) on Broadwell GT3e.
v2: Rebase on Laura's changes.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Cc: "10.5" <mesa-stable at lists.freedesktop.org>
commit bb33a31c3830945ae768ebdaeb686291bdf897fa
Author: Matt Turner <mattst88 at gmail.com>
Date: Sun Nov 9 17:27:52 2014 -0800
i965/fs: Add algebraic optimizations for MAD.
total instructions in shared programs: 5764176 -> 5763808 (-0.01%)
instructions in affected programs: 25121 -> 24753 (-1.46%)
helped: 164
HURT: 2
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 8cfd1e2ac6b0d509d34c7d155a95016cd80338ed
Author: Matt Turner <mattst88 at gmail.com>
Date: Sun Oct 26 22:08:15 2014 -0700
i965/fs: Emit MAD instructions when possible.
Previously we didn't emit MAD instructions since they cannot take
immediate arguments, but with the opt_combine_constants() pass we can
handle this properly.
total instructions in shared programs: 5920017 -> 5733278 (-3.15%)
instructions in affected programs: 3625153 -> 3438414 (-5.15%)
helped: 22017
HURT: 870
GAINED: 91
LOST: 49
Without constant pooling, this patch is a complete loss:
total instructions in shared programs: 5912589 -> 5987888 (1.27%)
instructions in affected programs: 3190050 -> 3265349 (2.36%)
helped: 1564
HURT: 17827
GAINED: 27
LOST: 101
And since the constant pooling patch by itself hurt a bunch of things,
from before constant pooling to this patch the results are:
total instructions in shared programs: 5895414 -> 5747946 (-2.50%)
instructions in affected programs: 3617993 -> 3470525 (-4.08%)
helped: 20478
HURT: 4469
GAINED: 54
LOST: 146
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 36bc5f06dd22cde0ba572c00ae7548fe8cb7c731
Author: Matt Turner <mattst88 at gmail.com>
Date: Sun Oct 26 22:07:06 2014 -0700
i965/fs: Allow immediates in MAD and LRP instructions.
And then the opt_combine_constants() pass will pull them out into
registers. This will allow us to do some algebraic optimizations on MAD
and LRP.
total instructions in shared programs: 5946656 -> 5931320 (-0.26%)
instructions in affected programs: 778247 -> 762911 (-1.97%)
helped: 3780
HURT: 6
GAINED: 12
LOST: 12
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 2dad1e3abdb1ad153289455f3e273101e5bac1a8
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Feb 12 11:00:46 2014 -0800
i965/fs: Add pass to combine immediates.
total instructions in shared programs: 5885407 -> 5940958 (0.94%)
instructions in affected programs: 3617311 -> 3672862 (1.54%)
helped: 3
HURT: 23556
GAINED: 31
LOST: 165
... but will allow us to always emit MAD instructions.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 0d8f27eab7b7e8b7a16e76aabd3f6a0ab4880497
Author: Matt Turner <mattst88 at gmail.com>
Date: Sun Oct 26 22:10:53 2014 -0700
i965/fs: Remove force_writemask_all assertion for execsize < 8.
This doesn't seem to be necessary.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86974
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 662c645318849164526d1a79f86db9dcb6711ad9
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Feb 26 16:15:52 2014 -0800
i965/cfg: Add function to generate a dot file of the dominator tree.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit b06eef05d040ffcfe5a203387b1c4b5b0b32848a
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Feb 26 16:07:52 2014 -0800
i965/cfg: Add function to generate a dot file of the CFG.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 0e3dbc0248340bebd1a3012f18db5383ec90b077
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Feb 18 16:35:56 2014 -0800
i965/cfg: Calculate the immediate dominators.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 08f304bb3bfd4cc93bcc9108063afb7a8b2dd806
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Feb 18 16:38:07 2014 -0800
i965/cfg: Allow cfg::dump to be called without a visitor.
The fs_visitor's dump_instruction() implementation calls cfg_t()
indirectly through calculate_live_intervals, so if you have an infinite
loop in the CFG code, you can't call cfg::dump(fs_visitor *) to debug
it.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 1af5c4a526ab27ee2e4c5be96148af231f217c25
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Feb 17 18:01:41 2015 -0800
i965: Allow exec_list sentinels as arguments to insert functions.
To insert an instruction at the end of a basic block, we typically do
something like
inst = block->last_non_control_flow_inst();
inst->insert_after(block, new_inst);
But blocks can consist of a single control flow instruction, so inst
will actually be the exec_list's head sentinel. We shouldn't use it as
if it were a regular instruction, but it is safe to insert something after
it.
This patch avoids assert-failing because an exec_list sentinel wasn't in
the basic block's instruction list.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit b7ce7c00e35ceb3518d932359ed52cacd6679acb
Author: Alan Coopersmith <alan.coopersmith at oracle.com>
Date: Sun Feb 15 16:20:25 2015 -0800
Make _mesa_swizzle_and_convert argument types in .c match those in .h
Caused Solaris Studio compilers to fail to build with errors about
incompatible function redefinitions.
Signed-off-by: Alan Coopersmith <alan.coopersmith at oracle.com>
Cc: "10.5" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 4671dca0eecf7dbf3e0d0a13111813756722d57d
Author: Alan Coopersmith <alan.coopersmith at oracle.com>
Date: Sun Feb 15 16:19:06 2015 -0800
Use __typeof instead of typeof with Solaris Studio compilers
While the C compiler accepts typeof, C++ requires __typeof.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86944
Signed-off-by: Alan Coopersmith <alan.coopersmith at oracle.com>
Cc: "10.5" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit d602fbd861e2c3c5570b55f0839361a6f8bd32c7
Author: Alan Coopersmith <alan.coopersmith at oracle.com>
Date: Sun Feb 15 16:16:15 2015 -0800
Avoid fighting with Solaris headers over isnormal()
When compiling in C99 or C++11 modes, Solaris defines isnormal() as
a macro via <math.h>, which causes the function definition to become
too mangled to compile.
Signed-off-by: Alan Coopersmith <alan.coopersmith at oracle.com>
Cc: "10.5" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 815b3bd096a3eab9f00f9270d45a6885d73180e9
Author: Alan Coopersmith <alan.coopersmith at oracle.com>
Date: Sun Feb 15 14:46:29 2015 -0800
Remove extraneous ; after DECL_TYPE usage
The macro is defined to provide a trailing ; so this caused the expansion
to end in ";;" which made the Solaris Studio compilers issue warnings for
every line of:
"builtin_type_macros.h", line 113: Warning: extra ";" ignored.
for every file that included the header, filling build logs with thousands
of useless warnings.
Signed-off-by: Alan Coopersmith <alan.coopersmith at oracle.com>
Cc: "10.5" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 60ad5103b9c85cbb0921082fba9401f117424f25
Author: Alan Coopersmith <alan.coopersmith at oracle.com>
Date: Thu Jan 1 12:55:27 2015 -0800
Bracket arguments to tr so they work with Solaris tr
https://www.gnu.org/savannah-checkouts/gnu/autoconf/manual/autoconf-2.69/html_node/Limitations-of-Usual-Tools.html#index-g_t_0040command_007btr_007d-1842
Without this fix, egl fails to build on Solaris, with the error:
<command-line>:0:22: error: '_EGL_PLATFORM_x11' undeclared (first use in this function)
egldisplay.c:207:31: note: in expansion of macro '_EGL_NATIVE_PLATFORM'
native_platform = _EGL_NATIVE_PLATFORM;
^
Signed-off-by: Alan Coopersmith <alan.coopersmith at oracle.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
Cc: "10.5" <mesa-stable at lists.freedesktop.org>
commit 76960a55e6656bb0022e9c31ae7542010da130e3
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Dec 16 18:33:39 2014 -0800
glsl: Reduce memory consumption of copy propagation passes.
opt_copy_propagation and opt_copy_propagation_elements create new ACP
and Kill sets each time they enter a new control flow block. For if
blocks, they also copy the entire existing ACP set contents into the
new set.
When we exit the control flow block, we discard the new sets. However,
we weren't freeing them - so they lived on until the pass finished.
This can waste a lot of memory (57MB on one pessimal shader).
This patch makes the pass allocate ACP entries using this->acp as the
memory context, and Kill entries out of this->kill. It also steals
kill entries when moving them from the inner kill list to the parent.
It then frees the lists, including their contents.
v2: Move ralloc_free(this->acp) just before this->acp = orig_acp
(suggested by Eric Anholt).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Cc: "10.5 10.4" <mesa-stable at lists.freedesktop.org>
commit eda3dd00760039493fa2afc00193aa47b6ce8c58
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Tue Sep 9 21:28:46 2014 +1200
i965: Add device limits for tess threads & URB entries
This should cover all platforms prior to Skylake.
Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Acked-by: Ben Widawsky <ben at bwidawsk.net>
commit e8e4437ed0660b3f1d1912f53d997cf5e25f486d
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Feb 18 10:13:20 2015 +1000
r600g/sb: treat undefined values like constants
When we schedule an instructions with undefined value, we
eventually will use 0, which is a constant, however sb wasn't
taking this into account and creating ops with illegal scalar
swizzles.
this replaces my fix for op3 in t slots.
Reviewed-by: Glenn Kennard <glenn.kennard at gmail.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit 598d144cef412f114bddccc5d3c428682b41a7c2
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Feb 10 03:36:48 2015 -0800
i915c: Use the actual MIN instruction.
Matt Turner noticed that the hardware has always had a MIN
instruction, but the driver always used MAX+MOV for no
apparent reason.
This should cut an instruction, and a temporary, allowing
more programs to run in hardware.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 7bf774034a20e6864d63caf8c65cc424454b1bed
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Feb 10 03:36:47 2015 -0800
i915g: Use the actual MIN instruction.
Matt Turner noticed that the hardware has always had a MIN
instruction, but the driver always used MAX+MOV for no
apparent reason.
This should cut an instruction, and a temporary, allowing
more programs to run in hardware.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 27b6ef7ecaa60ce192ec74eef2245c25ed4e703b
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Feb 6 00:36:26 2015 -0800
i965: Add a function to disassemble an instruction from the 4 dwords.
I used this a while back when debugging GPU hangs, and it seems like it
could be useful, so I figured I'd add it so people can use it in the
debugger.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 0b499abb51c80867ad034f2a6d9fcb1e86d021cc
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Jan 9 23:07:56 2015 -0800
i965: Do Sandybridge workaround flushes before each primitive.
Sandybridge requires the post-sync non-zero workaround in a ton of
places, and if you ever miss one, the GPU usually hangs.
Currently, we try to track exactly when a workaround flush is
necessary (via the brw->batch.need_workaround_flush flag). This is
tricky to get right, and we've botched it several times in the past.
This patch unconditionally performs the post-sync non-zero flush at the
start of each primitive's state upload (including BLORP). We drop the
needs_workaround_flush flag, and drop all the other callers, as the
flush has already been performed.
We have no data to indicate that simply flushing all the time will
hurt performance, and it has the potential to help stability.
v2: Add post-sync workaround to initial GPU state upload to be extra
cautious (suggested by Chad Versace).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chad Versace <chad.versace at linux.intel.com>
commit 92163482bda87216764edc0beca3ca090678038d
Author: Laura Ekstrand <laura at jlekstrand.net>
Date: Mon Feb 16 14:29:57 2015 -0800
main: Fixed _mesa_GetCompressedTexImage_sw to copy slices correctly.
Previously array textures were not working with GetCompressedTextureImage,
leading to failures in the test
arb_direct_state_access/getcompressedtextureimage.c.
Tested-by: Laura Ekstrand <laura at jlekstrand.net>
Reviewed-by: Brian Paul <brianp at vmware.com>
Cc: "10.4, 10.5" <mesa-stable at lists.freedesktop.org>
commit 4470bf1f494ce313bda4f1627c775569d886f93f
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Feb 11 09:23:41 2015 -0800
i965/vec4: Silence unused parameter warnings
brw_vec4_copy_propagation.cpp:243:59: warning: unused parameter 'reg' [-Wunused-parameter]
int arg, struct copy_entry *entry, int reg)
^
brw_vec4_generator.cpp:869:57: warning: unused parameter 'inst' [-Wunused-parameter]
vec4_generator::generate_unpack_flags(vec4_instruction *inst,
^
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 2524f9b80d5763377600e15e584152253420ad25
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Feb 10 08:58:01 2015 -0800
mesa/main: Silence unused parameter warning
Just remove the _mesa_free_lighting_data function. The body has been
empty since the shine table was moved into the tnl module (commit
ba1d921).
main/light.c:1216:46: warning: unused parameter 'ctx' [-Wunused-parameter]
_mesa_free_lighting_data( struct gl_context *ctx )
^
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 1424bbfb572e6165e57554c6a591282743920b5c
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Feb 10 08:05:12 2015 -0800
util/hash: Silence comparison between signed and unsigned integer warnings in tests
delete_management.c:56:18: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (i = 0; i < size; i++) {
^
delete_management.c:69:27: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (i = size - 100; i < size; i++) {
^
delete_management.c:79:31: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
assert(key_value(entry->key) >= size - 100 &&
^
delete_management.c:79:70: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
assert(key_value(entry->key) >= size - 100 &&
^
insert_many.c:56:18: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (i = 0; i < size; i++) {
^
insert_many.c:62:18: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (i = 0; i < size; i++) {
^
insert_many.c:67:18: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
assert(ht->entries == size);
^
random_entry.c:62:18: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
for (i = 0; i < size; i++) {
^
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 3d8f9570cdd8a467d76cfffb5f998977dbab8682
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Feb 10 08:02:28 2015 -0800
util/hash: Silence unused parameter warnings in tests
delete_and_lookup.c:37:21: warning: unused parameter ‘key’ [-Wunused-parameter]
badhash(const void *key)
^
delete_and_lookup.c:43:10: warning: unused parameter ‘argc’ [-Wunused-parameter]
main(int argc, char **argv)
^
delete_and_lookup.c:43:23: warning: unused parameter ‘argv’ [-Wunused-parameter]
main(int argc, char **argv)
^
collision.c:34:10: warning: unused parameter ‘argc’ [-Wunused-parameter]
main(int argc, char **argv)
^
collision.c:34:23: warning: unused parameter ‘argv’ [-Wunused-parameter]
main(int argc, char **argv)
^
destroy_callback.c:50:10: warning: unused parameter ‘argc’ [-Wunused-parameter]
main(int argc, char **argv)
^
destroy_callback.c:50:23: warning: unused parameter ‘argv’ [-Wunused-parameter]
main(int argc, char **argv)
^
insert_many.c:46:10: warning: unused parameter ‘argc’ [-Wunused-parameter]
main(int argc, char **argv)
^
insert_many.c:46:23: warning: unused parameter ‘argv’ [-Wunused-parameter]
main(int argc, char **argv)
^
insert_and_lookup.c:34:10: warning: unused parameter ‘argc’ [-Wunused-parameter]
main(int argc, char **argv)
^
insert_and_lookup.c:34:23: warning: unused parameter ‘argv’ [-Wunused-parameter]
main(int argc, char **argv)
^
null_destroy.c:32:10: warning: unused parameter ‘argc’ [-Wunused-parameter]
main(int argc, char **argv)
^
null_destroy.c:32:23: warning: unused parameter ‘argv’ [-Wunused-parameter]
main(int argc, char **argv)
^
random_entry.c:52:10: warning: unused parameter ‘argc’ [-Wunused-parameter]
main(int argc, char **argv)
^
random_entry.c:52:23: warning: unused parameter ‘argv’ [-Wunused-parameter]
main(int argc, char **argv)
^
remove_null.c:34:10: warning: unused parameter ‘argc’ [-Wunused-parameter]
main(int argc, char **argv)
^
remove_null.c:34:23: warning: unused parameter ‘argv’ [-Wunused-parameter]
main(int argc, char **argv)
^
replacement.c:34:10: warning: unused parameter ‘argc’ [-Wunused-parameter]
main(int argc, char **argv)
^
replacement.c:34:23: warning: unused parameter ‘argv’ [-Wunused-parameter]
main(int argc, char **argv)
^
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 147afac80cb00d34a787314ce5645a4688c88129
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Tue Feb 10 07:57:08 2015 -0800
glcpp: Silence GCC warning
glcpp/glcpp.c:124:1: warning: ‘static’ is not at beginning of declaration [-Wold-style-declaration]
const static struct option
^
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 2ead74888a70481aa40b5b6ede42279e1917e66c
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun Feb 15 18:12:06 2015 +0100
radeonsi: fix a crash if a stencil ref state is set before a DSA state
+ minor indentation fixes
Discovered by Axel Davy.
This can't be reproduced with any app, because all state trackers set a DSA
state first.
Cc: 10.5 10.4 10.3 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Axel Davy <axel.davy at ens.fr>
commit 7713d594e4fbb9afb1ac67417b7871d436590548
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Feb 10 16:02:54 2015 +0100
r600g,radeonsi: implement GL_AMD_pinned_memory
v2: update release notes
Reviewed-by: Christian König <christian.koenig at amd.com>
commit c688988b0d68ffee2d8f1d64b0d402e23e8ce49e
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Feb 11 20:25:16 2015 +0100
winsys/radeon: test the userptr ioctl to see if it's present
There is no other way to check for support.
Reviewed-by: Christian König <christian.koenig at amd.com>
commit 064847122a4c6dae6fdee41a4862948352cd929f
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Feb 10 22:27:21 2015 +0100
winsys/radeon: allow unaligned size for user-memory buffers
This is not required, but being user-friendly doesn't hurt.
Reviewed-by: Christian König <christian.koenig at amd.com>
commit e8d727a2b6b89f6c6c205fbe87acf30659a0bd39
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Feb 10 16:41:53 2015 +0100
winsys/radeon: allow mapping a user buffer
OpenGL requires this.
Reviewed-by: Christian König <christian.koenig at amd.com>
commit 8b587ee7011aee900fd84f6203467ba899f2ed01
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Feb 10 14:00:57 2015 +0100
gallium: add interface and state tracker support for GL_AMD_pinned_memory
v2: add alignment restrictions to docs, fix indentation in headers
Reviewed-by: Christian König <christian.koenig at amd.com>
commit 11ebb03c26a7af4e975f5611303f6caf98f8a315
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Feb 10 01:39:41 2015 +0100
mesa: implement GL_AMD_pinned_memory
It's not possible to query the current buffer binding, because the extension
doesn't define GL_..._BUFFER__BINDING_AMD.
Drivers should check the target parameter of Drivers.BufferData. If it's
equal to GL_EXTERNAL_VIRTUAL_MEMORY_BUFFER_AMD, the memory should be pinned.
That's all there is to it.
A piglit test is on the piglit mailing list.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
commit 4fa61b1a23ab0128d3791541403ee020fbef3d4c
Author: Christian König <christian.koenig at amd.com>
Date: Thu Feb 5 18:34:51 2015 +0100
winsys/radeon: add user pointer support
Signed-off-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
commit e8625a29fe0942af2876f0684b06c6ed01939227
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Feb 10 01:35:23 2015 +0100
mesa: fix AtomicBuffer typo in _mesa_DeleteBuffers
Cc: 10.5 10.4 10.3 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Brian Paul <brianp at vmware.com>
commit 218b15715ec6a9e987ae78d904683801e5ccdf4b
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Feb 10 14:16:56 2015 +0100
radeonsi: initialize TC_L2_dirty to false after buffer allocation
I forgot to do this, though "true" should have no effect on correctness.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit a27b74819ad375e8c0bc88e13f42c951d2b5cd6a
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Feb 6 18:00:50 2015 +0100
radeonsi: small fix in SPI state
Cc: 10.5 10.4 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 5f1cef76f9bbaae772120dcb38e0b98d68a93f26
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Feb 7 13:19:38 2015 +0100
r600g,radeonsi: use fences to implement PIPE_QUERY_GPU_FINISHED
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89014
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit f1103f6a1e5f35a0fa9db388ff352b4e8d4c9828
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Feb 6 17:18:11 2015 +0100
r600g,radeonsi: demote TIMESTAMP_DISJOINT query to be a software query
The query result is always constant.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
commit 59292b38eb0173dfdf42a8ae24322e46d51d759d
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Feb 17 10:05:45 2015 +1000
st/glsl_to_tgsi: fix whitespace
everytime I open this file in emacs with show trailing whitespace
or git add from it my screen flares with red.
Just do a general cleanup, makes working on fp64 support not as
jarring.
I'm not saying this is perfect, its just better than before.
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit b53fbec01d8c76de0dff78c8fbceac08b2d02d3a
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Tue Feb 17 11:25:16 2015 +1000
glsl/tests: add IMAGE type.
This fixes a warning when running make check.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Dave Airlie <airlied at redhat.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
commit faaf13f6bf0ff826727af442beebc530ac1b74ac
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Tue Feb 17 04:45:03 2015 +0800
ilo: always set up BLEND_STATE on Gen8
There is now an DW0 that seems to be always referenced.
commit 6d4475d7bf24aae77b862994e303ebf02de141db
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Tue Feb 17 04:54:17 2015 +0800
ilo: fix alpha test on Gen8
Shoudl use GEN8_BLEND_DW0_ALPHA_TEST_ENABLE instead of
GEN6_RT_DW1_ALPHA_TEST_ENABLE (and others).
commit d9cd982d556be560af3bcbcdaf62b6b93eb934a5
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Sun Feb 15 20:06:59 2015 -0800
i965/simd8vs: Fix SIMD8 atomics
The short version: we need to set bits in R0.7 which provide a mask to be used
for PS kill samples/pixels. Since the VS has no such concept, we just need to
set all 1.
The longer version...
Execution for SIMD8 atomics is defined as follows:
SIMD8: The low 8 bits of the execution mask are ANDed with 8 bits of the
Pixel/Sample Mask from the message header. For the typed messages, the Slot
Group in the message descriptor selects either the low or high 8 bits. For the
untyped messages, the low 8 bits are always selected. The resulting mask is used
to determine which slots are read into the destination GRF register (for read),
or which slots are written to the surface (for write). If the header is not
present, only the low 8 bits of the execution mask are used.
The message header for untyped messages is defined in R0.7 "This field contains
the 16-bit pixel/sample mask to be used for SIMD16 and SIMD8 messages. All 16
bits are used for SIMD16 messages. For typed SIMD8 messages, Slot Group selects
which 8 bits of this field are used. For untyped SIMD8 messages, the low 8 bits
of this field are used." Furthermore, "The message header for the untyped
messages only needs to be delivered for pixel shader threads, where the
execution mask may indicate pixels/samples that are enabled only due to
derivative (LOD) calculations, but the corresponding slot on the surface must
not be accessed." We're not using a pixel shader here, but AFAICT, this mask is
used for all stages.
This leaves two options, Remove the header, or make the VS code emit the correct
thing for the header. I believe one of the goals of using SIMD8 VS was to get as
much code reuse as possible, and so I chose the latter. Since the VS has no such
thing as kill instructions, the mask is derived simple as all 1's.
v2:
Add a comment to the code (stolen from Curro on the mailing list)
Change the control flow style (Curro + Jason)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=87258
Cc: Kristian Høgsberg <krh at bitplanet.net>
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
commit 9ac370014698fda062b41e86a6c20306d6573292
Author: Brian Paul <brianp at vmware.com>
Date: Mon Feb 16 08:38:56 2015 -0700
mesa: move assertion after declarations in texstore.c
To fix MSVC build.
commit 4d2cee4d5e53a96b6badeb60a24a2c05a21eef5a
Author: Brian Paul <brianp at vmware.com>
Date: Tue Feb 10 12:17:18 2015 -0700
mesa: silence uninitialized var warning in get_tex_rgba_uncompressed()
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit bb77745681e179b53ea64da7bc1987b57643b7b0
Author: Neil Roberts <neil at linux.intel.com>
Date: Tue Nov 25 17:52:27 2014 +0000
meta: Fix saving the results of the current occlusion query
When restoring the current state in _mesa_meta_end it was previously trying to
copy the on-going sample count of the current occlusion query into the new
query after restarting it so that the driver will continue adding to the
previous value. This wouldn't work for two reasons. Firstly, the query might
not be ready yet so the Result member will usually be zero. Secondly the saved
query is stored as a pointer to the query object, not a copy of the struct, so
it is actually restarting the exact same object. Copying the result value is
just copying between identical addresses with no effect. The call to
_mesa_BeginQuery will have always reset it back to zero.
This patch fixes it by making it actually wait for the query object to be
ready before grabbing the previous result. The downside of doing this is that
it could introduce a stall but I think this situation is unlikely so it might
not matter too much. A better solution might be to introduce a real
suspend/resume mechanism to the driver interface. This could be implemented in
the i965 driver by saving the depth count multiple times like it does in the
i945 driver.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88248
Reviewed-by: Carl Worth <cworth at cworth.org>
Cc: "10.5" <mesa-stable at lists.freedesktop.org>
commit 946e29847bb6bca18244192bad8058922ae0a948
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Feb 12 10:20:49 2015 +0200
i965/vec4: Override destination register writemask in sampler message send.
This line was removed by accident in commit
16b911257440afbd77a6eb762e28df62e3c19bc7 causing a regression in the
ES3-CTS.gtf.GL3Tests.shadow.shadow_execution_vert Khronos conformance
test. It's necessary because the swizzle_result() code below expects
all four components of the vector to be valid.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89094
Tested-by: Lu Hua <huax.lu at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 0a811e1d1e5b23ecefda3f4569f68198e2612f3f
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Fri Feb 13 08:29:32 2015 +0100
i965: Fix a crash in the texture gradient lowering pass with cube samplers
We need to swizzle the rhs to match the number of components in the writemask,
otherwise we'll hit an assertion in ir_assignment.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit ba426522dddf0860f59dedfe9953dbd509160c7d
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Fri Feb 13 12:56:26 2015 +0100
mesa: Fix element count for byte-swaps in texstore, readpix and texgetimage
Some old format conversion code in pack.c implemented byte-swapping like this:
GLint comps = _mesa_components_in_format(dstFormat);
GLint swapSize = _mesa_sizeof_packed_type(dstType);
if (swapSize == 2)
_mesa_swap2((GLushort *) dstAddr, n * comps);
else if (swapSize == 4)
_mesa_swap4((GLuint *) dstAddr, n * comps);
where n is the pixel count. But this is incorrect for packed formats,
where _mesa_sizeof_packed_type is already returning the size of a pixel
instead of the size of a single component, so multiplying this by the
number of components in the format results in a larger element count
for _mesa_swap than we want.
Unfortunately, we followed the same implementation for byte-swapping
in the rewrite of the format conversion code for texstore, readpixels
and texgetimage.
This patch computes the correct element counts for _mesa_swap calls
by computing the bytes per pixel in the image and dividing that by the
swap size to obtain the number of swaps required per pixel. Then multiplies
that by the number of pixels in the image to obtain the swap count that
we need to use.
Also, when handling byte-swapping in texstore_rgba, we were ignoring
the image's depth. This patch fixes this too.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Cc: "10.5" <mesa-stable at lists.freedesktop.org>
commit 4b249d2eed686384d6d7c36f3232360891d5eeda
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Fri Feb 13 10:23:26 2015 +0100
mesa: Handle transferOps in texstore_rgba
In the recent rewrite of the format conversion code we did not handle this.
This patch adds the missing support.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89068
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Cc: "10.5" <mesa-stable at lists.freedesktop.org>
commit a2299bfbbd6ed96ea4b529f90005d0242dbfeac0
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu Jan 8 22:56:44 2015 -0800
i965/fs: Handle U/UW-type immediates in the generator.
commit 7a83f7d4814c9216316a742e97c33259f7b3ae76
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu Jan 8 22:55:16 2015 -0800
i965/fs: Handle W/UW-type immediates in dump_instructions().
commit 74ef90acd751fc91ba9e20c2f16871fa9bf140e0
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Feb 13 10:46:32 2015 -0800
i965: Let dump_instructions() work before calculate_cfg().
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit fa124a337ca10d2c5d2d81a89dc8c21a7ba2f58b
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Feb 13 10:34:39 2015 -0800
i965/fs: Call calculate_cfg() before optimize().
The CFG is fundamental to the FS IR, not merely a piece of optimization.
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
commit eb47d0efd39d73d4388389d6c0ebe458160f79fa
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Feb 4 18:08:30 2015 -0800
i965: Optimize multiplication by -1 into a negated MOV.
instructions in affected programs: 968 -> 942 (-2.69%)
helped: 4
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit e8a6f2ad65b03eac7c030b2cd4955a162739870b
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Feb 4 18:08:21 2015 -0800
i965: Add an is_negative_one() method.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 72b9f8db2a035b52dbd59af0d2a6441cbde11a4c
Author: Matt Turner <mattst88 at gmail.com>
Date: Thu Feb 12 02:01:49 2015 +0000
i965/vec4/vp: Use vec4_visitor::CMP.
... instead of emit(BRW_OPCODE_CMP, ...). In commit 6b3a301f I changed
vec4_visitor::CMP to set the destination's type to that of src0. In the
following commit (2335153f) I removed an apparently now unnecessary work
around for Gen8 that did the same thing.
But there was a single place that emitted a CMP instruction without
using the vec4_visitor::CMP function. Use it there.
And change dst_null_d to dst_null_f for good measure, since ARB vp
doesn't have integers.
Cc: "10.5" <mesa-stable at lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89032
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 69b1693ef3e5f6be872ae131ea01de435a8e9337
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Sun Feb 15 13:21:51 2015 +0800
ilo: fix some state pointer commands on Gen8
3DSTATE_CC_STATE_POINTERS seems to be ignored when bit 0 of DW1 is not set.
Follow i965 and set the bit for 3DSTATE_CC_STATE_POINTERS and
3DSTATE_BLEND_STATE_POINTERS. Add gen checks for all state pointer commands.
commit 854eb06bee7d266fc739f984c1b4ebb54dac3b87
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Feb 14 01:43:31 2015 -0500
nvc0: allow holes in xfb target lists
Tested with a modified xfb-streams test which outputs to streams 0, 2,
and 3.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.4 10.5" <mesa-stable at lists.freedesktop.org>
commit 80d373ed5b1d90a5e71747ee5b8951baac62f750
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sat Feb 14 01:27:19 2015 -0500
st/mesa: treat resource-less xfb buffers as if they weren't there
If a transform feedback buffer's size is 0, st_bufferobj_data doesn't
end up creating a buffer for it. There's no point in trying to write to
such a buffer, so just pretend as if it's not really there.
This fixes arb_gpu_shader5-xfb-streams-without-invocations on nvc0.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Cc: "10.4 10.5" <mesa-stable at lists.freedesktop.org>
commit 68e4f3f572b1e629f32a73ae618dc0b016f631b1
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Fri Feb 13 23:21:36 2015 -0500
nvc0: bail out of 2d blits with non-A8_UNORM alpha formats
This fixes the teximage-colors uploads with GL_ALPHA format and
non-GL_UNSIGNED_BYTE type.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: "10.4 10.5" <mesa-stable at lists.freedesktop.org>
commit 3c57a595276d0614940d70315e78de0d83bf74ac
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Sat Feb 14 12:16:03 2015 -0800
i965/nir: Don't support gl_FrontFacing as an input variable
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit dd110cdfd878a261ad7f2114f83f86deb35aa0fb
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Sat Feb 14 12:10:32 2015 -0800
nir: Make gl_FrontFacing a system_value
GLSL IR labels gl_FrontFacing as an input variable and not a system value.
This commit makes NIR silently translate gl_FrontFacing to a system value
so that it properly gets translated into a load_system_value intrinsic.
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 785b22caee28892d9d995a743de1dee5434c9ce1
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Sat Feb 14 12:09:31 2015 -0800
i965/nir: Add support for nir_intrinsic_load_front_face
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 929f43851e669742081a17f85025efcb91189fbe
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Mon Feb 9 14:22:14 2015 -0800
nir/lower_phis_to_scalar: Fix some logic in is_phi_scalarizable
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 7df256add2ae9fb916c3e0f80c879e42d1c8a7a0
Author: Shawn Starr <shawn.starr at rogers.com>
Date: Fri Feb 13 21:16:17 2015 -0500
clover: Use Legacy PassManager for LLVM trunk (3.7)
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
Signed-off-by: Shawn Starr <shawn.starr at rogers.com>
commit 8323796840a343ee39687cc8e8b424ee43d6fee7
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Sat Feb 14 06:28:12 2015 +0800
ilo: fix JIP/UIP on Gen8
UIP is in DW2 and JIP is in DW3 on Gen8. Also, the units are in bytes.
commit c62507f42cf7ea8ce3c3b843f488c6efd26f17dc
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Sat Feb 14 06:25:27 2015 +0800
ilo: do not set GEN6_THREADCTRL_SWITCH
It is not needed on Gen6+, and it appears to be broken on Gen8.
commit 7504b357d45d5c814bd8d4511bf42a8c04c8af63
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Sat Feb 14 03:07:51 2015 +0800
ilo: correct ISA UIP/JIP decoding for Gen8
JIP is int32_t and UIP is in DW2 on Gen8.
commit f8126fed954977604697f3c6485a6701618458cb
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Sat Feb 14 03:05:47 2015 +0800
ilo: prepare for 64-bit immediates decoding
Replace imm32 by imm64. Add more ways (UD, D, etc) to access the immediate.
commit 9ed376a76c37755f4408aa5cdb754178143f804f
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Sat Feb 14 02:23:53 2015 +0800
ilo: cleanup ISA DW1 decoding
Decode the higher and lower 16 bits separately.
commit db362983d17ea1403e6121ce80f05df141a11aa5
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Sat Feb 14 02:18:55 2015 +0800
ilo: cleanup ISA DW0 decoding
Add disasm_inst_decode_dw0_opcode_gen6() to decode the opcode. Simplify
branch_ctrl/acc_wr_ctrl decoding.
commit 5fc0dd8953012c5f4864b40d89983f6d44985dc1
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Feb 13 04:04:18 2015 +0800
ilo: update some outdated gen checks
Update gen checks for 3DSTATE_POLY_STIPPLE_OFFSET,
3DSTATE_POLY_STIPPLE_PATTERN, 3DSTATE_LINE_STIPPLE, and
3DSTATE_AA_LINE_PARAMETERS.
commit 8b9446dbeb6bc146b92a17b8d44e39fcf2f96e97
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Feb 13 03:59:45 2015 +0800
ilo: fix rectlist length on Gen8
5 PIPE_CONTROLs, 2 3DSTATE_WM_HZ_OP, and depth buffer setup require 65 DWords.
commit baba8b2745e0036dbac0350a344bb86278fdb673
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Feb 13 03:54:32 2015 +0800
ilo: fix 3DSTATE_VF_TOPOLOGY
The pipe primitive type was wrongly translated twice.
commit c944b91190048e370d2adc362f0860d9f58e58f2
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Fri Feb 13 13:51:28 2015 +0000
os,llvmpipe: Set rasterizer thread names on Linux.
To help identify llvmpipe rasterizer threads -- especially when there
can be so many.
We can eventually generalize this to other OSes, but for that we must
restrict the function to be called from the current thread. See also
http://stackoverflow.com/a/7989973
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit b09f25428ff5e908aefc03b8f9931599c3afd6d2
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Fri Feb 13 09:46:44 2015 +0000
uti/u_atomic: Don't test p_atomic_add with booleans.
Add another class of tests.
Fixes https://bugs.freedesktop.org/show_bug.cgi?id=89112
I failed to spot this in my previous change, because bool was a typedef
for char on the system I tested.
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit e333035c47a6a4cc88f0f9ca2bced500538bebae
Author: Tapani Pälli <tapani.palli at intel.com>
Date: Thu Feb 12 14:33:53 2015 +0200
mesa: fix OES_texture_float texture render target behavior
Current implementation allowed usage of unsized type texture GL_FLOAT
and GL_HALF_FLOAT as a render target as this was 'expected behavior' by
WEBGL_oes_texture_float and is also allowed by the oes-texture-float
WebGL test. However this broke some ES3 conformance tests that do not
accept such behavior. Patch sets such an fbo incomplete as expected by
the ES3 conformance tests. Textures with sized types like RGBA32F will
still continue to work as render targets.
v2: code style cleanups (Ian Romanick, Matt Turner)
Signed-off-by: Tapani Pälli <tapani.palli at intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88905
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Cc: "10.5" <mesa-stable at lists.freedesktop.org>
commit 3f1e1287fd960966eee8b12a75c8a8f62e11cdd2
Author: Eric Anholt <eric at anholt.net>
Date: Thu Feb 12 14:17:21 2015 -0800
vc4: Make SF be a flag on the QIR instructions.
Right now the places that used to emit a mov.sf just put the SF on the
previous instruction when it generated the source of the SF value. Even
without optimization to push the sf up further (and kill thus potentially
kill more MOVs), this gets us:
total uniforms in shared programs: 13455 -> 13457 (0.01%)
uniforms in affected programs: 3 -> 5 (66.67%)
total instructions in shared programs: 40296 -> 40198 (-0.24%)
instructions in affected programs: 12595 -> 12497 (-0.78%)
commit 4413861dd835cf8b9143f3032b670635bd217bf6
Author: Eric Anholt <eric at anholt.net>
Date: Wed Feb 11 14:55:42 2015 -0800
r200: Drop unused variable.
Quiets compiler warning since e7f2f2dea5acdbd1a12ed88914e64a38a97432f0.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
commit 55de910f909ac668ec7ea8fd94ec4f235b0d0335
Author: Eric Anholt <eric at anholt.net>
Date: Wed Feb 11 14:54:33 2015 -0800
i965: Quiet another compiler warning about uninitialized values.
The compiler can't tell that we're always going to hit the first if block
on the first time through the loop.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit f65e26478ba5e20c9cf4ee5d0fcf879ccb4e3c0d
Author: Eric Anholt <eric at anholt.net>
Date: Wed Feb 11 14:53:08 2015 -0800
i965: Move some asserts to unreachable.
If execution was supposed to be supported in this case, we'd run into
trouble from completely uninitialized sat_imm values.
v2: Drop the '!' before the string.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 6489cb1ae6f3cb999b1a9c60d941ef4c388febd1
Author: Eric Anholt <eric at anholt.net>
Date: Wed Feb 11 14:50:35 2015 -0800
i965: Shut up a compiler warning about uninitialized var.
We always pass this argument, even if it won't be used by the particular
texture op.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 55a57834bf912916a5e07486b32f1778b35657f6
Author: Carl Worth <cworth at cworth.org>
Date: Thu Feb 12 10:14:24 2015 -0800
Revert use of Mesa IR optimizer for ARB_fragment_programs
Commit f82f2fb3dc770902f1657ab1c22e6004faa3afab added use of the Mesa
IR optimizer for both ARB_fragment_program and ARB_vertex_program, but
only justified the vertex-program portions with measured performance
improvements.
Meanwhile, the optimizer was seen to generate hundreds of unused
immediates without discarding them, causing failures.
Discard the use of the optimizer for now to fix the regression. (In
the future, we anticpate things moving from Mesa IR to NIR for better
optimization anyway.)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82477
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
CC: "10.3 10.4 10.5" <mesa-stable at lists.freedesktop.org>
commit 1ba9f9e62c1e83a2a9a48435cce5128be3d3ea66
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Thu Feb 12 19:31:20 2015 +0000
util/u_atomic: Use lower-case variables in _Interlocked* helpers.
commit 531d47baa8f755a688c77aec488742ee7d491014
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Wed Feb 11 15:30:39 2015 +0000
util/u_atomic: Add _InterlockedExchangeAdd8/16 for older MSVC.
We need to build certain parts of Mesa (namely gallium, llvmpipe, and
therefore util) with Windows SDK 7.0.7600, which includes MSVC 2008.
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit d2438f5920b95a880e9146882a58bf37ec57bad5
Author: Jose Fonseca <jfonseca at vmware.com>
Date: Wed Feb 11 15:21:25 2015 +0000
util/u_atomic: Test p_atomic_add() for 8bit integers.
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
commit b1e70f2423749bda11953a8aa84a11aec00825b3
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Feb 12 06:16:27 2015 -0500
docs: add ARB_draw_indirect to ES 3.1 list
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
commit 63986f958097288a29ae001e15df3dea076486d1
Author: Axel Davy <axel.davy at ens.fr>
Date: Wed Jan 14 20:36:04 2015 +0100
egl: Soften several HAVE_DRM_PLATFORM to HAVE_LIBDRM
To fix build when libdrm is not found,
commit a594cec7e3ef275c386054127a357110a19dd823 did put several
parts of egl code under #ifdef HAVE_DRM_PLATFORM.
HAVE_DRM_PLATFORM means the egl drm platform is being built.
What should have been used instead is HAVE_LIBDRM.
At a few locations, the HAVE_DRM_PLATFORM introduced
have already been replaced by HAVE_LIBDRM, this patch
replaces the remaining occurences.
This patch makes for example EGL_EXT_image_dma_buf_import
be advertised by egl under x11 when the drm egl platform
is not built, whereas previously it required the drm egl
platform to be built.
Signed-off-by: Axel Davy <axel.davy at ens.fr>
Reviewed-by: Emil Velikov <emil.l.velikov at gmail.com>
commit c39dbfdd0f764b1aaa7319b4694e7335692993dd
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Tue Feb 10 15:11:09 2015 +0000
auxiliary/vl: bring back the VL code for the dri targets
With commit c642e87d9f4(auxiliary/vl: rework the build of the VL code)
we split out the VL code into a separate static library that was meant
to be used by the VL targets alone - va, vdpau, xvmc.
The commit failed to consider the way we handle vdpau-gl interop and
broke it. Bring back the functionality by keeping the vl <> vl_stub
separation as requrested by Christian.
v2: Update the omx target as well. Update mesa-stable email address.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86837
Cc: "10.5" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Tested-by: Andy Furniss <adf.lists at gmail.com>
commit 153539bd9d4445b504110958306f00632222f840
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Tue Feb 10 14:14:16 2015 +0000
configure: rework wayland_scanner handling(fix make distcheck)
Currently having the wayland-scanner is optional, which causes problems
when autotools parses through the makefiles, and tries to generate all
the BUILT_SOURCES.
As the config option --with-egl-platform=wayland is not the default, we
won't end up setting the WAYLAND_SCANNER variable, which in turn will
cause some files to not get generated.
There has been a wayland-scanner package as of wayland 1.2 which
provides a variable for the scanner binary, so let's use that one and
fall back to manually searching via AC_PATH_PROG when needed.
Cc: "10.5" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 72e602905dd9d86450a936d5a22bf21758844b38
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Tue Feb 10 13:10:18 2015 +0000
nir: add missing header to the sources list
Cc: "10.5" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 556fc4b84df99a1cd4b18c11fb16f7854a948b2a
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date: Sat Feb 7 19:20:16 2015 +0000
nir: resolve nir.h dependency list (fix make distcheck)
Use nir/nir_opcodes.h as is (w/o the absolute path), as it is the target
name used to generate the actual file. Otherwise the target is missing,
the file won't get generated and the build will fail.
Cc: "10.5" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
commit 9f7efa78a8912505dcebdb587edc504663538e3c
Author: Martin Peres <martin.peres at linux.intel.com>
Date: Thu Feb 12 11:24:37 2015 +0200
docs: update GL3.txt to state my current work on the dsa extension
Signed-off-by: Martin Peres <martin.peres at linux.intel.com>
commit e93566a15c61c33faa2e694aa18d18e544e857ff
Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date: Tue Feb 10 17:22:45 2015 -0800
i965/vs/skl: Use vec4 datatypes for message header
We're using a SIMD4x2 sampler message, which has execsize 4, and so the
register width must be <= 4. Use <4,4,1> regioning instead of <8,8,1>
regioning to access the same data but avoid tripping the assert.
Fixes the following piglit tests:
spec/glsl-1.20/compiler/structure-and-array-operations/array-selection.vert
spec/glsl-es-3.00/compiler/uniform_block/interface-name-basic.vert
spec/glsl-es-3.00/compiler/uniform_block/interface-name-field-clashes-with-struct.vert
spec/glsl-es-3.00/compiler/uniform_block/interface-name-field-clashes-with-function.vert
spec/glsl-es-3.00/compiler/uniform_block/interface-name-array.vert
glslparsertest/glsl2/condition-07.vert
spec/glsl-es-3.00/compiler/uniform_block/interface-name-field-clashes-with-variable.vert
v2: Better commit message courtesy of Ken.
I had a discussion with Ken, and we both question how we end up with a mov and
execsize 4. For now though, this fixes the piglit tests, so we can worry about
it later.
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit cba6a4a12943d635e8dd3d38d94e21cbcab8be34
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Tue Jan 27 19:48:39 2015 +0800
ilo: update screen init for Gen8
This is very preliminary and is only tested with glxgears. All information
about Gen8 is derived from i965 and beignet.
commit cb1cdecf64126363370e58fc46bdd47796344ef0
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Wed Feb 11 14:31:54 2015 +0800
ilo: update outdated render command emissions for Gen8
commit 9ab4fc4e632c6ff67d44879b39bb52f231b618e9
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Wed Feb 11 14:21:42 2015 +0800
ilo: update rectlist command emission for Gen8
commit 4caf8d9761d10792489fa519138eb01d6c72c0e6
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Tue Jan 27 20:11:27 2015 +0800
ilo: update draw command emission for Gen8
commit d8927ab02f8527cbf489823c76768308829720c8
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Tue Jan 27 20:10:46 2015 +0800
ilo: update surface state emission for Gen8
commit 7832a3013b1869364b5b39a3d1db49d0b880adde
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Tue Jan 27 20:10:19 2015 +0800
ilo: update dynamic state emission for Gen8
commit 8682cbab3e30f8d3c089f1f7113fcd7e9e184718
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Tue Jan 27 20:00:48 2015 +0800
ilo: update outdated gen assertions for Gen8
commit c173a5288fa80a1461d99d6e5f010c5969cb3166
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Jan 26 17:12:33 2015 +0800
ilo: add new WM related helpers for Gen8
commit 8c2cbc8955f8512820a32aae2fa38ed5b97c2e95
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Tue Feb 10 07:13:11 2015 +0800
ilo: update VS related functions for Gen8
commit 0e3381154cfcc265495344c1c7b3e98dbbbe6183
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Tue Feb 10 07:10:20 2015 +0800
ilo: update VF related functions for Gen8
commit a57805cb750c4b2aa57a387e4145bba6c1a0b86e
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Sun Jan 25 18:05:04 2015 +0800
ilo: update SAMPLER_STATE for Gen8
commit 7e7e45db65968df7a56c8c5aabed0a700633c72b
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Jan 26 15:52:06 2015 +0800
ilo: update SAMPLER_BORDER_COLOR_STATE for Gen8
commit 8976a190b2c4049598afa23b7a277e9f571306ba
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Jan 26 15:35:14 2015 +0800
ilo: update depth clear value for Gen8
commit 0b7fdce4f5f507bac86211a6e5356c86e15d8379
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Tue Jan 27 16:34:45 2015 +0800
ilo: update ilo_zs_surface for Gen8
commit aa7109f0591e2306ea8c9c7fd61cff30860ac8b3
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Tue Jan 27 14:58:32 2015 +0800
ilo: update ilo_view_surface for Gen8
commit 7922982d4f192475f102fe6fc308c063ab654d00
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Sun Jan 25 15:12:52 2015 +0800
ilo: update texture layout for Gen8
commit 47dc2ae6e283423bad6286287b870dff63c7954c
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Sun Jan 25 18:20:43 2015 +0800
ilo: update ilo_blend_state and related functions for Gen8
commit e8455128aacb470bef1c5b18c88eac556dffb3ba
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Jan 26 15:28:15 2015 +0800
ilo: update ilo_dsa_state and related functions for Gen8
commit 9aeee99e4da1488922c47e66709b5a3e82fcbf06
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Jan 26 13:34:51 2015 +0800
ilo: update multisample related states for Gen8
commit 6366fbc1a8055b437a97acf160596514885df6e7
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Jan 26 18:06:00 2015 +0800
ilo: update WM and PS related functions for Gen8
commit 584d3369b6552d0d34dd783031d25dd472a4d6b0
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Tue Jan 27 00:08:48 2015 +0800
ilo: update SBE related functions for Gen8
commit 4cb592ec172f7892a4551cbd37272131dd172207
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Jan 26 23:12:55 2015 +0800
ilo: update SF related functions for Gen8
commit 05e2eb57cdb2ce185625038e7424ca2ef733a9aa
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Tue Jan 27 19:57:40 2015 +0800
ilo: update CLIP related functions for Gen8
commit 9ab0165375ea3e32a02b488ba9f78c460e700cd7
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Jan 26 16:23:29 2015 +0800
ilo: update SF_CLIP_VIEWPORT for Gen8
commit b64aeebbcce996ab7057a9af39a97e32689df13f
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Jan 26 16:37:38 2015 +0800
ilo: update streamout related functions for Gen8
commit 6f77bd3bdc3bfb004d3e4d0b17b641786e16cde9
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Jan 26 16:08:23 2015 +0800
ilo: update 3DSTATE_{DS,HS,GS} for Gen8
commit 3be0504399d7710d9cefcfcfe0b75cffc8cd7ad5
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Jan 26 15:51:41 2015 +0800
ilo: update 3DSTATE_CONSTANT_x for Gen8
commit 49306afe7bc5333df710dc071419111ed4d4a6fb
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Wed Jan 28 00:20:09 2015 +0800
ilo: update 3DSTATE_URB_x for Gen8
commit d43ae05d76b1f14b713b70a84e87e443ab20979e
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Wed Jan 28 00:07:15 2015 +0800
ilo: update 3DSTATE_PUSH_CONSTANT_ALLOC_x for Gen8
commit f43332ca2ffbbaf009994c6e1fdac5c52e25b3b2
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Jan 26 15:34:34 2015 +0800
ilo: update render engine common helpers for Gen8
commit 8d9f69bef28a41e8655ed351bf81523dfa70137d
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Sun Jan 25 16:19:14 2015 +0800
ilo: update BLT helpers for Gen8
commit 574f8d0229c2b94f1e408da06ea82f9a4c50a590
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Sun Jan 25 15:25:33 2015 +0800
ilo: update MI helpers for Gen8
commit bfc8a726096c752f15b1e2f1043fe284f0effb18
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Sun Jan 25 18:04:25 2015 +0800
ilo: add functions for Gen8 relocs
Extend ilo_builder_writer_reloc() for Gen8 memory addressing. Add new
wrappers, ilo_builder_surface_reloc64(() and ilo_builder_batch_reloc64().
commit a7911620f61a10f6297155d58445ed146bbcb056
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Sat Jan 24 01:12:04 2015 +0800
ilo: update the toy compiler for Gen8
Based on what we know from the classic driver.
commit 0066c22c40f9cca572e34ec618f7a7ae4e723d2e
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Fri Jan 23 15:44:53 2015 +0800
ilo: update genhw headers
Accumulated changes for various renames and additions, including Gen8
definitions. Some of the dynamic state __SIZE no longer means the size of an
element, but the size of an array of elements. The changes can be seen in
ilo_render_dynamic.c.
commit 5933d84ad6e0815438dcd55ca802fa70d4401e19
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Jan 26 14:58:16 2015 +0800
ilo: clean up ilo_gpe_init_dsa()
Add dsa_get_stencil_enable_gen6(), dsa_get_depth_enable_gen6(), and
dsa_get_alpha_enable_gen6() to be called from ilo_gpe_init_dsa().
commit aa354b92d259d9fc5e85c49c76719ebc8e3c1b4a
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Jan 26 01:08:31 2015 +0800
ilo: clean up ilo_gpe_init_blend()
Make ilo_blend_state more space efficient and forward-looking.
commit 1d07055b5087bf7c0cca50b7b5a5635bfdd85885
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Mon Jan 26 14:00:25 2015 +0800
ilo: clean up sample patterns
Use signed int for sample positions and add helpers to access them. Call them
patterns instead of positions.
commit 69ad5fd4ce33aeab73d9eb546072d77e73e3a730
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Jan 30 13:42:19 2015 -0800
glsl: Optimize (f2i(trunc x)) into (f2i x).
total instructions in shared programs: 5950326 -> 5949286 (-0.02%)
instructions in affected programs: 88264 -> 87224 (-1.18%)
helped: 692
commit c262b2b582798f389601b8198b1dbf3c7ba7a187
Author: Matt Turner <mattst88 at gmail.com>
Date: Wed Jan 28 10:09:14 2015 -0800
glsl: Optimize round-half-up pattern.
Hurts some Psychonauts shaders, but after the next patch (which this
enables) they're fewer instructions than before this patch.
commit a5455ab1cae85dbe40c12ada9030bc4b4537ced7
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Jan 30 13:50:28 2015 -0800
glsl: Add trunc() to ir_builder.
commit d91390634ff8c50b217d55372db186d03996e9f7
Author: Matt Turner <mattst88 at gmail.com>
Date: Fri Jan 23 21:58:51 2015 -0800
i965: Add LINTERP/CINTERP to can_do_cmod().
LINTERP is implemented as a PLN instruction or a LINE+MAC. PLN and MAC
can do conditional mod. CINTERP is just a MOV.
total instructions in shared programs: 5952103 -> 5950284 (-0.03%)
instructions in affected programs: 324573 -> 322754 (-0.56%)
helped: 1819
We lose the SIMD16 in one Unigine Heaven shader which appears six times
in shader-db.
commit 245c7848fc8e010a2b139a0eacd5cb652cef4ce3
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Feb 10 18:45:18 2015 -0800
program: Remove _mesa_nop_vertex_program/_mesa_nop_fragment_program.
Dead since
commit 284ce20901b0c2cfab1d952cc129b8f3cd068f12
Author: Eric Anholt <eric at anholt.net>
Date: Fri Aug 20 10:52:14 2010 -0700
Remove remnants of the old glsl compiler.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 4c42e1116b552cca1ed667c20ae9ba966b580983
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Feb 10 21:43:32 2015 -0800
nir: Recognize open-coded fmin/fmax.
And unfortunately other shaders do the same thing but with >=/<= which
we can't apply this optimization to because of NaNs.
instructions in affected programs: 23309 -> 22938 (-1.59%)
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
commit 56e21647e20db8e3708001a8600c3d8e7d12d841
Author: Eric Anholt <eric at anholt.net>
Date: Fri Feb 6 17:12:59 2015 -0800
nir: Add algebraic opt for int comparisons with identical operands.
No change on shader-db on i965.
v2: Reword the comment due to feedback from Erik Faye-Lund
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com> (v1)
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com> (v1)
commit 2919bdf466295bc3fbf6f6e796ef8d301404d3d9
Author: Eric Anholt <eric at anholt.net>
Date: Fri Feb 6 17:16:29 2015 -0800
nir: Fix load_const comparisons for CSE.
We want the size of a float per component, not the size of a whole vec4.
NIR instructions on i965:
total instructions in shared programs: 1261937 -> 1261929 (-0.00%)
instructions in affected programs: 114 -> 106 (-7.02%)
Looking at one of these examples (tesseract), it's from vec4 load_consts
for a MRT solid fill, which do get CSEed now that we don't memcmp off the
end of the const value and into the SSA def. For the 1-component loads
that are common in i965, we were only memcmping off into the rest of the
usually zero-filled const_value.
Reviewed-by: Connor Abbott <cwabbott0 at gmail.com>
commit 09d6ea9ae3c487be20fb3157368003d30856d3bc
Author: Matt Turner <mattst88 at gmail.com>
Date: Tue Feb 10 21:36:26 2015 -0800
i965/fs: Remove conditional mod when optimizing a SEL into a MOV.
Missed in commit ca675b73, but got right in the companion commit 3c28b2c0.
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